2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
26 * Screen related driver hooks and capability lists.
28 * A program may use multiple rendering contexts (iris_context), but
29 * they all share a common screen (iris_screen). Global driver state
30 * can be stored in the screen; it may be accessed by multiple threads.
35 #include <sys/ioctl.h>
36 #include "pipe/p_defines.h"
37 #include "pipe/p_state.h"
38 #include "pipe/p_context.h"
39 #include "pipe/p_screen.h"
40 #include "util/debug.h"
41 #include "util/u_inlines.h"
42 #include "util/format/u_format.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "util/xmlconfig.h"
47 #include "drm-uapi/i915_drm.h"
48 #include "iris_context.h"
49 #include "iris_defines.h"
50 #include "iris_fence.h"
51 #include "iris_pipe.h"
52 #include "iris_resource.h"
53 #include "iris_screen.h"
54 #include "compiler/glsl_types.h"
55 #include "intel/compiler/brw_compiler.h"
56 #include "intel/common/gen_gem.h"
57 #include "intel/common/gen_l3_config.h"
58 #include "iris_monitor.h"
61 iris_flush_frontbuffer(struct pipe_screen
*_screen
,
62 struct pipe_resource
*resource
,
63 unsigned level
, unsigned layer
,
64 void *context_private
, struct pipe_box
*box
)
69 iris_get_vendor(struct pipe_screen
*pscreen
)
75 iris_get_device_vendor(struct pipe_screen
*pscreen
)
81 iris_get_name(struct pipe_screen
*pscreen
)
83 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
85 const char *name
= gen_get_device_name(screen
->pci_id
);
88 name
= "Intel Unknown";
90 snprintf(buf
, sizeof(buf
), "Mesa %s", name
);
95 iris_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
97 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
98 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
101 case PIPE_CAP_NPOT_TEXTURES
:
102 case PIPE_CAP_ANISOTROPIC_FILTER
:
103 case PIPE_CAP_POINT_SPRITE
:
104 case PIPE_CAP_OCCLUSION_QUERY
:
105 case PIPE_CAP_QUERY_TIME_ELAPSED
:
106 case PIPE_CAP_TEXTURE_SWIZZLE
:
107 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
108 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
109 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
110 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
111 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
112 case PIPE_CAP_PRIMITIVE_RESTART
:
113 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
114 case PIPE_CAP_INDEP_BLEND_ENABLE
:
115 case PIPE_CAP_INDEP_BLEND_FUNC
:
116 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
:
117 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
118 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
119 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
120 case PIPE_CAP_TGSI_INSTANCEID
:
121 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
122 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
123 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
124 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
125 case PIPE_CAP_CONDITIONAL_RENDER
:
126 case PIPE_CAP_TEXTURE_BARRIER
:
127 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
128 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
129 case PIPE_CAP_COMPUTE
:
130 case PIPE_CAP_START_INSTANCE
:
131 case PIPE_CAP_QUERY_TIMESTAMP
:
132 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
133 case PIPE_CAP_CUBE_MAP_ARRAY
:
134 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
135 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE
:
136 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
137 case PIPE_CAP_TEXTURE_QUERY_LOD
:
138 case PIPE_CAP_SAMPLE_SHADING
:
139 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
140 case PIPE_CAP_DRAW_INDIRECT
:
141 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
142 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
143 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
144 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
145 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
146 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
147 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
148 case PIPE_CAP_ACCELERATED
:
150 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
151 case PIPE_CAP_CLIP_HALFZ
:
152 case PIPE_CAP_TGSI_TEXCOORD
:
153 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
154 case PIPE_CAP_DOUBLES
:
156 case PIPE_CAP_INT64_DIVMOD
:
157 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
158 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
159 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
160 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
161 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
162 case PIPE_CAP_CULL_DISTANCE
:
163 case PIPE_CAP_PACKED_UNIFORMS
:
164 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
165 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
166 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
167 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
168 case PIPE_CAP_QUERY_SO_OVERFLOW
:
169 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
170 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
171 case PIPE_CAP_TGSI_TXQS
:
172 case PIPE_CAP_TGSI_CLOCK
:
173 case PIPE_CAP_TGSI_BALLOT
:
174 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
175 case PIPE_CAP_CLEAR_TEXTURE
:
176 case PIPE_CAP_CLEAR_SCISSORED
:
177 case PIPE_CAP_TGSI_VOTE
:
178 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
179 case PIPE_CAP_TEXTURE_GATHER_SM5
:
180 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
181 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
:
182 case PIPE_CAP_LOAD_CONSTBUF
:
183 case PIPE_CAP_NIR_COMPACT_ARRAYS
:
184 case PIPE_CAP_DRAW_PARAMETERS
:
185 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
186 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
187 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES
:
188 case PIPE_CAP_INVALIDATE_BUFFER
:
189 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
190 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED
:
191 case PIPE_CAP_TEXTURE_SHADOW_LOD
:
192 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL
:
193 case PIPE_CAP_GL_SPIRV
:
194 case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS
:
195 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION
:
196 case PIPE_CAP_NATIVE_FENCE_FD
:
197 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
199 case PIPE_CAP_FBFETCH
:
200 return BRW_MAX_DRAW_BUFFERS
;
201 case PIPE_CAP_FBFETCH_COHERENT
:
202 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE
:
203 case PIPE_CAP_POST_DEPTH_COVERAGE
:
204 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
205 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
206 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK
:
207 case PIPE_CAP_ATOMIC_FLOAT_MINMAX
:
208 return devinfo
->gen
>= 9;
209 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
210 return devinfo
->gen
>= 12;
211 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
213 case PIPE_CAP_MAX_RENDER_TARGETS
:
214 return BRW_MAX_DRAW_BUFFERS
;
215 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
217 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
218 return IRIS_MAX_MIPLEVELS
; /* 16384x16384 */
219 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
220 return 12; /* 2048x2048 */
221 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
223 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
225 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
226 return BRW_MAX_SOL_BINDINGS
/ IRIS_MAX_SOL_BUFFERS
;
227 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
228 return BRW_MAX_SOL_BINDINGS
;
229 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
230 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
232 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
233 /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
235 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
236 return IRIS_MAP_BUFFER_ALIGNMENT
;
237 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
238 /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
239 * GPU writing the same SSBO on non-coherent systems (Atom CPUs). With
240 * UBOs, the GPU never writes, so there's no problem. For an SSBO, the
241 * GPU and the CPU can be updating disjoint regions of the buffer
242 * simultaneously and that will break if the regions overlap the same
246 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
248 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
249 return 16; // XXX: u_screen says 256 is the minimum value...
250 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
252 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
253 return IRIS_MAX_TEXTURE_BUFFER_SIZE
;
254 case PIPE_CAP_MAX_VIEWPORTS
:
256 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
258 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
260 case PIPE_CAP_MAX_GS_INVOCATIONS
:
262 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
264 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
266 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
268 case PIPE_CAP_MAX_VERTEX_STREAMS
:
270 case PIPE_CAP_VENDOR_ID
:
272 case PIPE_CAP_DEVICE_ID
:
273 return screen
->pci_id
;
274 case PIPE_CAP_VIDEO_MEMORY
: {
275 /* Once a batch uses more than 75% of the maximum mappable size, we
276 * assume that there's some fragmentation, and we start doing extra
277 * flushing, etc. That's the big cliff apps will care about.
279 const unsigned gpu_mappable_megabytes
=
280 (devinfo
->aperture_bytes
* 3 / 4) / (1024 * 1024);
282 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
283 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
285 if (system_memory_pages
<= 0 || system_page_size
<= 0)
288 const uint64_t system_memory_bytes
=
289 (uint64_t) system_memory_pages
* (uint64_t) system_page_size
;
291 const unsigned system_memory_megabytes
=
292 (unsigned) (system_memory_bytes
/ (1024 * 1024));
294 return MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
296 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
297 case PIPE_CAP_MAX_VARYINGS
:
299 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
300 /* AMD_pinned_memory assumes the flexibility of using client memory
301 * for any buffer (incl. vertex buffers) which rules out the prospect
302 * of using snooped buffers, as using snooped buffers without
303 * cogniscience is likely to be detrimental to performance and require
304 * extensive checking in the driver for correctness, e.g. to prevent
305 * illegal snoop <-> snoop transfers.
307 return devinfo
->has_llc
;
308 case PIPE_CAP_THROTTLE
:
309 return screen
->driconf
.disable_throttling
? 0 : 1;
311 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
312 return PIPE_CONTEXT_PRIORITY_LOW
|
313 PIPE_CONTEXT_PRIORITY_MEDIUM
|
314 PIPE_CONTEXT_PRIORITY_HIGH
;
316 case PIPE_CAP_FRONTEND_NOOP
:
319 // XXX: don't hardcode 00:00:02.0 PCI here
320 case PIPE_CAP_PCI_GROUP
:
322 case PIPE_CAP_PCI_BUS
:
324 case PIPE_CAP_PCI_DEVICE
:
326 case PIPE_CAP_PCI_FUNCTION
:
329 case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS
:
330 case PIPE_CAP_INTEGER_MULTIPLY_32X16
:
334 return u_pipe_screen_get_param_defaults(pscreen
, param
);
340 iris_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
343 case PIPE_CAPF_MAX_LINE_WIDTH
:
344 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
347 case PIPE_CAPF_MAX_POINT_WIDTH
:
348 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
351 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
353 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
355 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
356 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
357 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
360 unreachable("unknown param");
365 iris_get_shader_param(struct pipe_screen
*pscreen
,
366 enum pipe_shader_type p_stage
,
367 enum pipe_shader_cap param
)
369 gl_shader_stage stage
= stage_from_pipe(p_stage
);
371 /* this is probably not totally correct.. but it's a start: */
373 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
374 return stage
== MESA_SHADER_FRAGMENT
? 1024 : 16384;
375 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
376 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
377 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
378 return stage
== MESA_SHADER_FRAGMENT
? 1024 : 0;
380 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
383 case PIPE_SHADER_CAP_MAX_INPUTS
:
384 return stage
== MESA_SHADER_VERTEX
? 16 : 32;
385 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
387 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
388 return 16 * 1024 * sizeof(float);
389 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
391 case PIPE_SHADER_CAP_MAX_TEMPS
:
392 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
393 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
395 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
396 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
397 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
398 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
399 /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
400 * which we don't want. Our compiler backend will check brw_compiler's
401 * options and call nir_lower_indirect_derefs appropriately anyway.
404 case PIPE_SHADER_CAP_SUBROUTINES
:
406 case PIPE_SHADER_CAP_INTEGERS
:
408 case PIPE_SHADER_CAP_INT64_ATOMICS
:
409 case PIPE_SHADER_CAP_FP16
:
410 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
411 case PIPE_SHADER_CAP_INT16
:
412 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS
:
414 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
415 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
416 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
417 return IRIS_MAX_TEXTURE_SAMPLERS
;
418 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
419 return IRIS_MAX_ABOS
+ IRIS_MAX_SSBOS
;
420 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
421 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
423 case PIPE_SHADER_CAP_PREFERRED_IR
:
424 return PIPE_SHADER_IR_NIR
;
425 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
426 return (1 << PIPE_SHADER_IR_NIR
);
427 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
428 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
430 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
431 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
432 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
433 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
434 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
435 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
436 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
439 unreachable("unknown shader param");
444 iris_get_compute_param(struct pipe_screen
*pscreen
,
445 enum pipe_shader_ir ir_type
,
446 enum pipe_compute_cap param
,
449 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
450 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
452 /* Limit max_threads to 64 for the GPGPU_WALKER command. */
453 const unsigned max_threads
= MIN2(64, devinfo
->max_cs_threads
);
454 const uint32_t max_invocations
= 32 * max_threads
;
456 #define RET(x) do { \
458 memcpy(ret, x, sizeof(x)); \
463 case PIPE_COMPUTE_CAP_IR_TARGET
:
468 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
469 RET((uint64_t []) { 3 });
471 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
472 RET(((uint64_t []) { 65535, 65535, 65535 }));
474 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
475 /* MaxComputeWorkGroupSize[0..2] */
476 RET(((uint64_t []) {max_invocations
, max_invocations
, max_invocations
}));
478 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
479 /* MaxComputeWorkGroupInvocations */
480 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
481 /* MaxComputeVariableGroupInvocations */
482 RET((uint64_t []) { max_invocations
});
484 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
485 /* MaxComputeSharedMemorySize */
486 RET((uint64_t []) { 64 * 1024 });
488 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
489 RET((uint32_t []) { BRW_SUBGROUP_SIZE
});
491 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
492 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
493 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
494 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
495 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
496 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
497 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
498 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
499 // XXX: I think these are for Clover...
503 unreachable("unknown compute param");
508 iris_get_timestamp(struct pipe_screen
*pscreen
)
510 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
511 const unsigned TIMESTAMP
= 0x2358;
514 iris_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &result
);
516 result
= gen_device_info_timebase_scale(&screen
->devinfo
, result
);
517 result
&= (1ull << TIMESTAMP_BITS
) - 1;
523 iris_screen_destroy(struct iris_screen
*screen
)
525 glsl_type_singleton_decref();
526 iris_bo_unreference(screen
->workaround_bo
);
527 u_transfer_helper_destroy(screen
->base
.transfer_helper
);
528 iris_bufmgr_unref(screen
->bufmgr
);
529 disk_cache_destroy(screen
->disk_cache
);
530 close(screen
->winsys_fd
);
535 iris_screen_unref(struct pipe_screen
*pscreen
)
537 iris_pscreen_unref(pscreen
);
541 iris_query_memory_info(struct pipe_screen
*pscreen
,
542 struct pipe_memory_info
*info
)
547 iris_get_compiler_options(struct pipe_screen
*pscreen
,
548 enum pipe_shader_ir ir
,
549 enum pipe_shader_type pstage
)
551 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
552 gl_shader_stage stage
= stage_from_pipe(pstage
);
553 assert(ir
== PIPE_SHADER_IR_NIR
);
555 return screen
->compiler
->glsl_compiler_options
[stage
].NirOptions
;
558 static struct disk_cache
*
559 iris_get_disk_shader_cache(struct pipe_screen
*pscreen
)
561 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
562 return screen
->disk_cache
;
566 iris_getparam(int fd
, int param
, int *value
)
568 struct drm_i915_getparam gp
= { .param
= param
, .value
= value
};
570 if (ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1)
577 iris_getparam_integer(int fd
, int param
)
581 if (iris_getparam(fd
, param
, &value
) == 0)
587 static const struct gen_l3_config
*
588 iris_get_default_l3_config(const struct gen_device_info
*devinfo
,
591 bool wants_dc_cache
= true;
592 bool has_slm
= compute
;
593 const struct gen_l3_weights w
=
594 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
595 return gen_get_l3_config(devinfo
, w
);
599 iris_shader_debug_log(void *data
, const char *fmt
, ...)
601 struct pipe_debug_callback
*dbg
= data
;
605 if (!dbg
->debug_message
)
609 dbg
->debug_message(dbg
->data
, &id
, PIPE_DEBUG_TYPE_SHADER_INFO
, fmt
, args
);
614 iris_shader_perf_log(void *data
, const char *fmt
, ...)
616 struct pipe_debug_callback
*dbg
= data
;
621 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
623 va_copy(args_copy
, args
);
624 vfprintf(stderr
, fmt
, args_copy
);
628 if (dbg
->debug_message
) {
629 dbg
->debug_message(dbg
->data
, &id
, PIPE_DEBUG_TYPE_PERF_INFO
, fmt
, args
);
636 iris_detect_kernel_features(struct iris_screen
*screen
)
639 if (gen_gem_supports_syncobj_wait(screen
->fd
))
640 screen
->kernel_features
|= KERNEL_HAS_WAIT_FOR_SUBMIT
;
644 iris_init_identifier_bo(struct iris_screen
*screen
)
648 bo_map
= iris_bo_map(NULL
, screen
->workaround_bo
, MAP_READ
| MAP_WRITE
);
652 screen
->workaround_bo
->kflags
|= EXEC_OBJECT_CAPTURE
;
653 screen
->workaround_address
= (struct iris_address
) {
654 .bo
= screen
->workaround_bo
,
656 intel_debug_write_identifiers(bo_map
, 4096, "Iris") + 8, 8),
659 iris_bo_unmap(screen
->workaround_bo
);
665 iris_screen_create(int fd
, const struct pipe_screen_config
*config
)
667 /* Here are the i915 features we need for Iris (in chronoligical order) :
668 * - I915_PARAM_HAS_EXEC_NO_RELOC (3.10)
669 * - I915_PARAM_HAS_EXEC_HANDLE_LUT (3.10)
670 * - I915_PARAM_HAS_EXEC_BATCH_FIRST (4.13)
671 * - I915_PARAM_HAS_EXEC_FENCE_ARRAY (4.14)
672 * - I915_PARAM_HAS_CONTEXT_ISOLATION (4.16)
674 * Checking the last feature availability will include all previous ones.
676 if (iris_getparam_integer(fd
, I915_PARAM_HAS_CONTEXT_ISOLATION
) <= 0) {
677 debug_error("Kernel is too old for Iris. Consider upgrading to kernel v4.16.\n");
681 struct iris_screen
*screen
= rzalloc(NULL
, struct iris_screen
);
685 if (!gen_get_device_info_from_fd(fd
, &screen
->devinfo
))
687 screen
->pci_id
= screen
->devinfo
.chipset_id
;
688 screen
->no_hw
= screen
->devinfo
.no_hw
;
690 p_atomic_set(&screen
->refcount
, 1);
692 if (screen
->devinfo
.gen
< 8 || screen
->devinfo
.is_cherryview
)
695 bool bo_reuse
= false;
696 int bo_reuse_mode
= driQueryOptioni(config
->options
, "bo_reuse");
697 switch (bo_reuse_mode
) {
698 case DRI_CONF_BO_REUSE_DISABLED
:
700 case DRI_CONF_BO_REUSE_ALL
:
705 screen
->bufmgr
= iris_bufmgr_get_for_fd(&screen
->devinfo
, fd
, bo_reuse
);
709 screen
->fd
= iris_bufmgr_get_fd(screen
->bufmgr
);
710 screen
->winsys_fd
= fd
;
712 if (getenv("INTEL_NO_HW") != NULL
)
713 screen
->no_hw
= true;
715 screen
->workaround_bo
=
716 iris_bo_alloc(screen
->bufmgr
, "workaround", 4096, IRIS_MEMZONE_OTHER
);
717 if (!screen
->workaround_bo
)
720 if (!iris_init_identifier_bo(screen
))
723 brw_process_intel_debug_variable();
725 screen
->driconf
.dual_color_blend_by_location
=
726 driQueryOptionb(config
->options
, "dual_color_blend_by_location");
727 screen
->driconf
.disable_throttling
=
728 driQueryOptionb(config
->options
, "disable_throttling");
729 screen
->driconf
.always_flush_cache
=
730 driQueryOptionb(config
->options
, "always_flush_cache");
732 screen
->precompile
= env_var_as_boolean("shader_precompile", true);
734 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
, false);
736 screen
->compiler
= brw_compiler_create(screen
, &screen
->devinfo
);
737 screen
->compiler
->shader_debug_log
= iris_shader_debug_log
;
738 screen
->compiler
->shader_perf_log
= iris_shader_perf_log
;
739 screen
->compiler
->supports_pull_constants
= false;
740 screen
->compiler
->supports_shader_constants
= true;
741 screen
->compiler
->compact_params
= false;
743 screen
->l3_config_3d
= iris_get_default_l3_config(&screen
->devinfo
, false);
744 screen
->l3_config_cs
= iris_get_default_l3_config(&screen
->devinfo
, true);
746 iris_disk_cache_init(screen
);
748 slab_create_parent(&screen
->transfer_pool
,
749 sizeof(struct iris_transfer
), 64);
751 screen
->subslice_total
=
752 iris_getparam_integer(screen
->fd
, I915_PARAM_SUBSLICE_TOTAL
);
753 assert(screen
->subslice_total
>= 1);
755 iris_detect_kernel_features(screen
);
757 struct pipe_screen
*pscreen
= &screen
->base
;
759 iris_init_screen_fence_functions(pscreen
);
760 iris_init_screen_resource_functions(pscreen
);
762 pscreen
->destroy
= iris_screen_unref
;
763 pscreen
->get_name
= iris_get_name
;
764 pscreen
->get_vendor
= iris_get_vendor
;
765 pscreen
->get_device_vendor
= iris_get_device_vendor
;
766 pscreen
->get_param
= iris_get_param
;
767 pscreen
->get_shader_param
= iris_get_shader_param
;
768 pscreen
->get_compute_param
= iris_get_compute_param
;
769 pscreen
->get_paramf
= iris_get_paramf
;
770 pscreen
->get_compiler_options
= iris_get_compiler_options
;
771 pscreen
->get_disk_shader_cache
= iris_get_disk_shader_cache
;
772 pscreen
->is_format_supported
= iris_is_format_supported
;
773 pscreen
->context_create
= iris_create_context
;
774 pscreen
->flush_frontbuffer
= iris_flush_frontbuffer
;
775 pscreen
->get_timestamp
= iris_get_timestamp
;
776 pscreen
->query_memory_info
= iris_query_memory_info
;
777 pscreen
->get_driver_query_group_info
= iris_get_monitor_group_info
;
778 pscreen
->get_driver_query_info
= iris_get_monitor_info
;
780 glsl_type_singleton_init_or_ref();