src/gallium/drivers/iris/iris_screen.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_SCREEN_H
  24 #define IRIS_SCREEN_H
  25
  26 #include "pipe/p_screen.h"
  27 #include "frontend/drm_driver.h"
  28 #include "util/disk_cache.h"
  29 #include "util/slab.h"
  30 #include "util/u_screen.h"
  31 #include "intel/dev/gen_device_info.h"
  32 #include "intel/isl/isl.h"
  33 #include "iris_bufmgr.h"
  34 #include "iris_binder.h"
  35 #include "iris_resource.h"
  36
  37 struct gen_l3_config;
  38 struct brw_vue_map;
  39 struct iris_vs_prog_key;
  40 struct iris_tcs_prog_key;
  41 struct iris_tes_prog_key;
  42 struct iris_gs_prog_key;
  43 struct iris_fs_prog_key;
  44 struct iris_cs_prog_key;
  45 enum iris_program_cache_id;
  46
  47 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
  48 #define WRITE_ONCE(x, v) *(volatile __typeof__(x) *)&(x) = (v)
  49
  50 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  51 #define IRIS_MAX_SOL_BUFFERS 4
  52 #define IRIS_MAP_BUFFER_ALIGNMENT 64
  53
  54 /**
  55  * Virtual table for generation-specific (genxml) function calls.
  56  */
  57 struct iris_vtable {
  58    void (*destroy_state)(struct iris_context *ice);
  59    void (*init_render_context)(struct iris_batch *batch);
  60    void (*init_compute_context)(struct iris_batch *batch);
  61    void (*upload_render_state)(struct iris_context *ice,
  62                                struct iris_batch *batch,
  63                                const struct pipe_draw_info *draw);
  64    void (*update_surface_base_address)(struct iris_batch *batch,
  65                                        struct iris_binder *binder);
  66    void (*upload_compute_state)(struct iris_context *ice,
  67                                 struct iris_batch *batch,
  68                                 const struct pipe_grid_info *grid);
  69    void (*rebind_buffer)(struct iris_context *ice,
  70                          struct iris_resource *res);
  71    void (*resolve_conditional_render)(struct iris_context *ice);
  72    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
  73                                uint32_t src);
  74    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
  75                                uint32_t src);
  76    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
  77                                uint32_t val);
  78    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
  79                                uint64_t val);
  80    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
  81                                struct iris_bo *bo, uint32_t offset);
  82    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
  83                                struct iris_bo *bo, uint32_t offset);
  84    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
  85                                 struct iris_bo *bo, uint32_t offset,
  86                                 bool predicated);
  87    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
  88                                 struct iris_bo *bo, uint32_t offset,
  89                                 bool predicated);
  90    void (*store_data_imm32)(struct iris_batch *batch,
  91                             struct iris_bo *bo, uint32_t offset,
  92                             uint32_t value);
  93    void (*store_data_imm64)(struct iris_batch *batch,
  94                             struct iris_bo *bo, uint32_t offset,
  95                             uint64_t value);
  96    void (*copy_mem_mem)(struct iris_batch *batch,
  97                         struct iris_bo *dst_bo, uint32_t dst_offset,
  98                         struct iris_bo *src_bo, uint32_t src_offset,
  99                         unsigned bytes);
 100    void (*emit_raw_pipe_control)(struct iris_batch *batch,
 101                                  const char *reason, uint32_t flags,
 102                                  struct iris_bo *bo, uint32_t offset,
 103                                  uint64_t imm);
 104
 105    void (*emit_mi_report_perf_count)(struct iris_batch *batch,
 106                                      struct iris_bo *bo,
 107                                      uint32_t offset_in_bytes,
 108                                      uint32_t report_id);
 109
 110    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 111    void (*store_derived_program_state)(struct iris_context *ice,
 112                                        enum iris_program_cache_id cache_id,
 113                                        struct iris_compiled_shader *shader);
 114    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 115                                     const struct brw_vue_map *vue_map);
 116    void (*populate_vs_key)(const struct iris_context *ice,
 117                            const struct shader_info *info,
 118                            gl_shader_stage last_stage,
 119                            struct iris_vs_prog_key *key);
 120    void (*populate_tcs_key)(const struct iris_context *ice,
 121                             struct iris_tcs_prog_key *key);
 122    void (*populate_tes_key)(const struct iris_context *ice,
 123                             const struct shader_info *info,
 124                             gl_shader_stage last_stage,
 125                             struct iris_tes_prog_key *key);
 126    void (*populate_gs_key)(const struct iris_context *ice,
 127                            const struct shader_info *info,
 128                            gl_shader_stage last_stage,
 129                            struct iris_gs_prog_key *key);
 130    void (*populate_fs_key)(const struct iris_context *ice,
 131                            const struct shader_info *info,
 132                            struct iris_fs_prog_key *key);
 133    void (*populate_cs_key)(const struct iris_context *ice,
 134                            struct iris_cs_prog_key *key);
 135    void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
 136 };
 137
 138 struct iris_address {
 139    struct iris_bo *bo;
 140    uint64_t offset;
 141    enum iris_domain access;
 142 };
 143
 144 struct iris_screen {
 145    struct pipe_screen base;
 146
 147    uint32_t refcount;
 148
 149    /** Global slab allocator for iris_transfer_map objects */
 150    struct slab_parent_pool transfer_pool;
 151
 152    /** drm device file descriptor, shared with bufmgr, do not close. */
 153    int fd;
 154
 155    /**
 156     * drm device file descriptor to used for window system integration, owned
 157     * by iris_screen, can be a different DRM instance than fd.
 158     */
 159    int winsys_fd;
 160
 161    /** PCI ID for our GPU device */
 162    int pci_id;
 163
 164    bool no_hw;
 165
 166    struct iris_vtable vtbl;
 167
 168    /** Global program_string_id counter (see get_program_string_id()) */
 169    unsigned program_id;
 170
 171    /** Precompile shaders at link time?  (Can be disabled for debugging.) */
 172    bool precompile;
 173
 174    /** driconf options and application workarounds */
 175    struct {
 176       /** Dual color blend by location instead of index (for broken apps) */
 177       bool dual_color_blend_by_location;
 178       bool disable_throttling;
 179       bool always_flush_cache;
 180    } driconf;
 181
 182    /** Does the kernel support various features (KERNEL_HAS_* bitfield)? */
 183    unsigned kernel_features;
 184 #define KERNEL_HAS_WAIT_FOR_SUBMIT (1<<0)
 185
 186    unsigned subslice_total;
 187
 188    uint64_t aperture_bytes;
 189
 190    /**
 191     * Last sequence number allocated by the cache tracking mechanism.
 192     *
 193     * These are used for synchronization and are expected to identify a single
 194     * section of a batch, so they should be monotonically increasing and
 195     * unique across a single pipe_screen.
 196     */
 197    uint64_t last_seqno;
 198
 199    struct gen_device_info devinfo;
 200    struct isl_device isl_dev;
 201    struct iris_bufmgr *bufmgr;
 202    struct brw_compiler *compiler;
 203    struct gen_perf_config *perf_cfg;
 204
 205    const struct gen_l3_config *l3_config_3d;
 206    const struct gen_l3_config *l3_config_cs;
 207
 208    /**
 209     * A buffer containing a marker + description of the driver. This buffer is
 210     * added to all execbufs syscalls so that we can identify the driver that
 211     * generated a hang by looking at the content of the buffer in the error
 212     * state. It is also used for hardware workarounds that require scratch
 213     * writes or reads from some unimportant memory. To avoid overriding the
 214     * debug data, use the workaround_address field for workarounds.
 215     */
 216    struct iris_bo *workaround_bo;
 217    struct iris_address workaround_address;
 218
 219    struct disk_cache *disk_cache;
 220 };
 221
 222 struct pipe_screen *
 223 iris_screen_create(int fd, const struct pipe_screen_config *config);
 224
 225 void iris_screen_destroy(struct iris_screen *screen);
 226
 227 UNUSED static inline struct pipe_screen *
 228 iris_pscreen_ref(struct pipe_screen *pscreen)
 229 {
 230    struct iris_screen *screen = (struct iris_screen *) pscreen;
 231
 232    p_atomic_inc(&screen->refcount);
 233    return pscreen;
 234 }
 235
 236 UNUSED static inline void
 237 iris_pscreen_unref(struct pipe_screen *pscreen)
 238 {
 239    struct iris_screen *screen = (struct iris_screen *) pscreen;
 240
 241    if (p_atomic_dec_zero(&screen->refcount))
 242       iris_screen_destroy(screen);
 243 }
 244
 245 bool
 246 iris_is_format_supported(struct pipe_screen *pscreen,
 247                          enum pipe_format format,
 248                          enum pipe_texture_target target,
 249                          unsigned sample_count,
 250                          unsigned storage_sample_count,
 251                          unsigned usage);
 252
 253 void iris_disk_cache_init(struct iris_screen *screen);
 254
 255 #endif