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9 * Software is furnished to do so, subject to the following conditions:
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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/format/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "util/u_memory.h"
99 #include "drm-uapi/i915_drm.h"
101 #include "intel/compiler/brw_compiler.h"
102 #include "intel/common/gen_aux_map.h"
103 #include "intel/common/gen_l3_config.h"
104 #include "intel/common/gen_sample_positions.h"
105 #include "iris_batch.h"
106 #include "iris_context.h"
107 #include "iris_defines.h"
108 #include "iris_pipe.h"
109 #include "iris_resource.h"
111 #include "iris_genx_macros.h"
112 #include "intel/common/gen_guardband.h"
115 * Statically assert that PIPE_* enums match the hardware packets.
116 * (As long as they match, we don't need to translate them.)
118 UNUSED
static void pipe_asserts()
120 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
122 /* pipe_logicop happens to match the hardware. */
123 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
124 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
125 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
126 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
127 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
128 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
129 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
130 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
131 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
132 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
133 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
134 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
135 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
136 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
137 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
138 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
140 /* pipe_blend_func happens to match the hardware. */
141 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
161 /* pipe_blend_func happens to match the hardware. */
162 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
163 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
164 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
165 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
166 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
168 /* pipe_stencil_op happens to match the hardware. */
169 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
170 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
171 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
172 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
173 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
174 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
175 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
176 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
178 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
179 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
180 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
185 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
187 static const unsigned map
[] = {
188 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
189 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
190 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
191 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
192 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
193 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
194 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
195 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
196 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
197 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
198 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
199 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
200 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
201 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
202 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
205 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
209 translate_compare_func(enum pipe_compare_func pipe_func
)
211 static const unsigned map
[] = {
212 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
213 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
214 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
215 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
216 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
217 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
218 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
219 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
221 return map
[pipe_func
];
225 translate_shadow_func(enum pipe_compare_func pipe_func
)
227 /* Gallium specifies the result of shadow comparisons as:
229 * 1 if ref <op> texel,
234 * 0 if texel <op> ref,
237 * So we need to flip the operator and also negate.
239 static const unsigned map
[] = {
240 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
241 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
242 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
243 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
244 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
245 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
246 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
247 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
249 return map
[pipe_func
];
253 translate_cull_mode(unsigned pipe_face
)
255 static const unsigned map
[4] = {
256 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
257 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
258 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
259 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
261 return map
[pipe_face
];
265 translate_fill_mode(unsigned pipe_polymode
)
267 static const unsigned map
[4] = {
268 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
269 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
270 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
271 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
273 return map
[pipe_polymode
];
277 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
279 static const unsigned map
[] = {
280 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
281 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
282 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
284 return map
[pipe_mip
];
288 translate_wrap(unsigned pipe_wrap
)
290 static const unsigned map
[] = {
291 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
292 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
293 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
294 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
295 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
296 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
298 /* These are unsupported. */
299 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
300 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
302 return map
[pipe_wrap
];
306 * Allocate space for some indirect state.
308 * Return a pointer to the map (to fill it out) and a state ref (for
309 * referring to the state in GPU commands).
312 upload_state(struct u_upload_mgr
*uploader
,
313 struct iris_state_ref
*ref
,
318 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
323 * Stream out temporary/short-lived state.
325 * This allocates space, pins the BO, and includes the BO address in the
326 * returned offset (which works because all state lives in 32-bit memory
330 stream_state(struct iris_batch
*batch
,
331 struct u_upload_mgr
*uploader
,
332 struct pipe_resource
**out_res
,
335 uint32_t *out_offset
)
339 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
341 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
342 iris_use_pinned_bo(batch
, bo
, false, IRIS_DOMAIN_NONE
);
344 iris_record_state_size(batch
->state_sizes
,
345 bo
->gtt_offset
+ *out_offset
, size
);
347 *out_offset
+= iris_bo_offset_from_base_address(bo
);
353 * stream_state() + memcpy.
356 emit_state(struct iris_batch
*batch
,
357 struct u_upload_mgr
*uploader
,
358 struct pipe_resource
**out_res
,
365 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
368 memcpy(map
, data
, size
);
374 * Did field 'x' change between 'old_cso' and 'new_cso'?
376 * (If so, we may want to set some dirty flags.)
378 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
379 #define cso_changed_memcmp(x) \
380 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
383 flush_before_state_base_change(struct iris_batch
*batch
)
385 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
387 /* Flush before emitting STATE_BASE_ADDRESS.
389 * This isn't documented anywhere in the PRM. However, it seems to be
390 * necessary prior to changing the surface state base adress. We've
391 * seen issues in Vulkan where we get GPU hangs when using multi-level
392 * command buffers which clear depth, reset state base address, and then
395 * Normally, in GL, we would trust the kernel to do sufficient stalls
396 * and flushes prior to executing our batch. However, it doesn't seem
397 * as if the kernel's flushing is always sufficient and we don't want to
400 * We make this an end-of-pipe sync instead of a normal flush because we
401 * do not know the current status of the GPU. On Haswell at least,
402 * having a fast-clear operation in flight at the same time as a normal
403 * rendering operation can cause hangs. Since the kernel's flushing is
404 * insufficient, we need to ensure that any rendering operations from
405 * other processes are definitely complete before we try to do our own
406 * rendering. It's a bit of a big hammer but it appears to work.
408 iris_emit_end_of_pipe_sync(batch
,
409 "change STATE_BASE_ADDRESS (flushes)",
410 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
411 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
412 PIPE_CONTROL_DATA_CACHE_FLUSH
|
413 /* GEN:BUG:1606662791:
415 * Software must program PIPE_CONTROL command
416 * with "HDC Pipeline Flush" prior to
417 * programming of the below two non-pipeline
419 * * STATE_BASE_ADDRESS
420 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
422 ((GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */ ?
423 PIPE_CONTROL_FLUSH_HDC
: 0)));
427 flush_after_state_base_change(struct iris_batch
*batch
)
429 /* After re-setting the surface state base address, we have to do some
430 * cache flusing so that the sampler engine will pick up the new
431 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
432 * Shared Function > 3D Sampler > State > State Caching (page 96):
434 * Coherency with system memory in the state cache, like the texture
435 * cache is handled partially by software. It is expected that the
436 * command stream or shader will issue Cache Flush operation or
437 * Cache_Flush sampler message to ensure that the L1 cache remains
438 * coherent with system memory.
442 * Whenever the value of the Dynamic_State_Base_Addr,
443 * Surface_State_Base_Addr are altered, the L1 state cache must be
444 * invalidated to ensure the new surface or sampler state is fetched
445 * from system memory.
447 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
448 * which, according the PIPE_CONTROL instruction documentation in the
451 * Setting this bit is independent of any other bit in this packet.
452 * This bit controls the invalidation of the L1 and L2 state caches
453 * at the top of the pipe i.e. at the parsing time.
455 * Unfortunately, experimentation seems to indicate that state cache
456 * invalidation through a PIPE_CONTROL does nothing whatsoever in
457 * regards to surface state and binding tables. In stead, it seems that
458 * invalidating the texture cache is what is actually needed.
460 * XXX: As far as we have been able to determine through
461 * experimentation, shows that flush the texture cache appears to be
462 * sufficient. The theory here is that all of the sampling/rendering
463 * units cache the binding table in the texture cache. However, we have
464 * yet to be able to actually confirm this.
466 iris_emit_end_of_pipe_sync(batch
,
467 "change STATE_BASE_ADDRESS (invalidates)",
468 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
469 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
470 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
474 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
476 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
477 lri
.RegisterOffset
= reg
;
481 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
484 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
486 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
487 lrr
.SourceRegisterAddress
= src
;
488 lrr
.DestinationRegisterAddress
= dst
;
493 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
496 _iris_emit_lrr(batch
, dst
, src
);
500 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
503 _iris_emit_lrr(batch
, dst
, src
);
504 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
508 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
511 _iris_emit_lri(batch
, reg
, val
);
515 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
518 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
519 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
523 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
526 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
527 struct iris_bo
*bo
, uint32_t offset
)
529 iris_batch_sync_region_start(batch
);
530 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
531 lrm
.RegisterAddress
= reg
;
532 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
534 iris_batch_sync_region_end(batch
);
538 * Load a 64-bit value from a buffer into a MMIO register via
539 * two MI_LOAD_REGISTER_MEM commands.
542 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
543 struct iris_bo
*bo
, uint32_t offset
)
545 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
546 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
550 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
551 struct iris_bo
*bo
, uint32_t offset
,
554 iris_batch_sync_region_start(batch
);
555 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
556 srm
.RegisterAddress
= reg
;
557 srm
.MemoryAddress
= rw_bo(bo
, offset
, IRIS_DOMAIN_OTHER_WRITE
);
558 srm
.PredicateEnable
= predicated
;
560 iris_batch_sync_region_end(batch
);
564 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
565 struct iris_bo
*bo
, uint32_t offset
,
568 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
569 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
573 iris_store_data_imm32(struct iris_batch
*batch
,
574 struct iris_bo
*bo
, uint32_t offset
,
577 iris_batch_sync_region_start(batch
);
578 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
579 sdi
.Address
= rw_bo(bo
, offset
, IRIS_DOMAIN_OTHER_WRITE
);
580 sdi
.ImmediateData
= imm
;
582 iris_batch_sync_region_end(batch
);
586 iris_store_data_imm64(struct iris_batch
*batch
,
587 struct iris_bo
*bo
, uint32_t offset
,
590 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
591 * 2 in genxml but it's actually variable length and we need 5 DWords.
593 void *map
= iris_get_command_space(batch
, 4 * 5);
594 iris_batch_sync_region_start(batch
);
595 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
596 sdi
.DWordLength
= 5 - 2;
597 sdi
.Address
= rw_bo(bo
, offset
, IRIS_DOMAIN_OTHER_WRITE
);
598 sdi
.ImmediateData
= imm
;
600 iris_batch_sync_region_end(batch
);
604 iris_copy_mem_mem(struct iris_batch
*batch
,
605 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
606 struct iris_bo
*src_bo
, uint32_t src_offset
,
609 /* MI_COPY_MEM_MEM operates on DWords. */
610 assert(bytes
% 4 == 0);
611 assert(dst_offset
% 4 == 0);
612 assert(src_offset
% 4 == 0);
613 iris_batch_sync_region_start(batch
);
615 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
616 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
617 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
,
618 IRIS_DOMAIN_OTHER_WRITE
);
619 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
623 iris_batch_sync_region_end(batch
);
627 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
629 #if GEN_GEN >= 8 && GEN_GEN < 10
630 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
632 * Software must clear the COLOR_CALC_STATE Valid field in
633 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
634 * with Pipeline Select set to GPGPU.
636 * The internal hardware docs recommend the same workaround for Gen9
639 if (pipeline
== GPGPU
)
640 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
644 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
645 * PIPELINE_SELECT [DevBWR+]":
649 * Software must ensure all the write caches are flushed through a
650 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
651 * command to invalidate read only caches prior to programming
652 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
654 iris_emit_pipe_control_flush(batch
,
655 "workaround: PIPELINE_SELECT flushes (1/2)",
656 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
657 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
658 PIPE_CONTROL_DATA_CACHE_FLUSH
|
659 PIPE_CONTROL_CS_STALL
);
661 iris_emit_pipe_control_flush(batch
,
662 "workaround: PIPELINE_SELECT flushes (2/2)",
663 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
664 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
665 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
666 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
668 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
672 sel
.PipelineSelection
= pipeline
;
677 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
682 * "This chicken bit works around a hardware issue with barrier
683 * logic encountered when switching between GPGPU and 3D pipelines.
684 * To workaround the issue, this mode bit should be set after a
685 * pipeline is selected."
688 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
689 reg
.GLKBarrierMode
= value
;
690 reg
.GLKBarrierModeMask
= 1;
692 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
697 init_state_base_address(struct iris_batch
*batch
)
699 uint32_t mocs
= batch
->screen
->isl_dev
.mocs
.internal
;
700 flush_before_state_base_change(batch
);
702 /* We program most base addresses once at context initialization time.
703 * Each base address points at a 4GB memory zone, and never needs to
704 * change. See iris_bufmgr.h for a description of the memory zones.
706 * The one exception is Surface State Base Address, which needs to be
707 * updated occasionally. See iris_binder.c for the details there.
709 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
710 sba
.GeneralStateMOCS
= mocs
;
711 sba
.StatelessDataPortAccessMOCS
= mocs
;
712 sba
.DynamicStateMOCS
= mocs
;
713 sba
.IndirectObjectMOCS
= mocs
;
714 sba
.InstructionMOCS
= mocs
;
715 sba
.SurfaceStateMOCS
= mocs
;
717 sba
.GeneralStateBaseAddressModifyEnable
= true;
718 sba
.DynamicStateBaseAddressModifyEnable
= true;
719 sba
.IndirectObjectBaseAddressModifyEnable
= true;
720 sba
.InstructionBaseAddressModifyEnable
= true;
721 sba
.GeneralStateBufferSizeModifyEnable
= true;
722 sba
.DynamicStateBufferSizeModifyEnable
= true;
724 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
725 sba
.BindlessSurfaceStateMOCS
= mocs
;
727 sba
.IndirectObjectBufferSizeModifyEnable
= true;
728 sba
.InstructionBuffersizeModifyEnable
= true;
730 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
731 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
733 sba
.GeneralStateBufferSize
= 0xfffff;
734 sba
.IndirectObjectBufferSize
= 0xfffff;
735 sba
.InstructionBufferSize
= 0xfffff;
736 sba
.DynamicStateBufferSize
= 0xfffff;
739 flush_after_state_base_change(batch
);
743 iris_emit_l3_config(struct iris_batch
*batch
,
744 const struct gen_l3_config
*cfg
)
747 assert(cfg
|| GEN_GEN
>= 12);
750 #define L3_ALLOCATION_REG GENX(L3ALLOC)
751 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
753 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
754 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
757 iris_pack_state(L3_ALLOCATION_REG
, ®_val
, reg
) {
759 reg
.SLMEnable
= cfg
->n
[GEN_L3P_SLM
] > 0;
762 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
763 * in L3CNTLREG register. The default setting of the bit is not the
764 * desirable behavior.
766 reg
.ErrorDetectionBehaviorControl
= true;
767 reg
.UseFullWays
= true;
769 if (GEN_GEN
< 12 || cfg
) {
770 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
771 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
772 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
773 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
776 reg
.L3FullWayAllocationEnable
= true;
780 _iris_emit_lri(batch
, L3_ALLOCATION_REG_num
, reg_val
);
785 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
789 /* A fixed function pipe flush is required before modifying this field */
790 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
791 : "disable preemption",
792 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
794 /* enable object level preemption */
795 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
796 reg
.ReplayMode
= enable
;
797 reg
.ReplayModeMask
= true;
799 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
805 iris_upload_slice_hashing_state(struct iris_batch
*batch
)
807 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
808 int subslices_delta
=
809 devinfo
->ppipe_subslices
[0] - devinfo
->ppipe_subslices
[1];
810 if (subslices_delta
== 0)
813 struct iris_context
*ice
= NULL
;
814 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_RENDER
]);
815 assert(&ice
->batches
[IRIS_BATCH_RENDER
] == batch
);
817 unsigned size
= GENX(SLICE_HASH_TABLE_length
) * 4;
818 uint32_t hash_address
;
819 struct pipe_resource
*tmp
= NULL
;
821 stream_state(batch
, ice
->state
.dynamic_uploader
, &tmp
,
822 size
, 64, &hash_address
);
823 pipe_resource_reference(&tmp
, NULL
);
825 struct GENX(SLICE_HASH_TABLE
) table0
= {
827 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
828 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
829 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
830 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
831 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
832 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
833 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
834 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
835 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
836 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
837 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
838 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
839 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
840 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
841 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
842 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
846 struct GENX(SLICE_HASH_TABLE
) table1
= {
848 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
849 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
850 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
851 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
852 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
853 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
854 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
855 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
856 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
857 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
858 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
859 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
860 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
861 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
862 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
863 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
867 const struct GENX(SLICE_HASH_TABLE
) *table
=
868 subslices_delta
< 0 ? &table0
: &table1
;
869 GENX(SLICE_HASH_TABLE_pack
)(NULL
, map
, table
);
871 iris_emit_cmd(batch
, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS
), ptr
) {
872 ptr
.SliceHashStatePointerValid
= true;
873 ptr
.SliceHashTableStatePointer
= hash_address
;
876 iris_emit_cmd(batch
, GENX(3DSTATE_3D_MODE
), mode
) {
877 mode
.SliceHashingTableEnable
= true;
883 iris_alloc_push_constants(struct iris_batch
*batch
)
885 /* For now, we set a static partitioning of the push constant area,
886 * assuming that all stages could be in use.
888 * TODO: Try lazily allocating the HS/DS/GS sections as needed, and
889 * see if that improves performance by offering more space to
890 * the VS/FS when those aren't in use. Also, try dynamically
891 * enabling/disabling it like i965 does. This would be more
892 * stalls and may not actually help; we don't know yet.
894 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
895 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
896 alloc
._3DCommandSubOpcode
= 18 + i
;
897 alloc
.ConstantBufferOffset
= 6 * i
;
898 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
905 init_aux_map_state(struct iris_batch
*batch
);
909 * Upload the initial GPU state for a render context.
911 * This sets some invariant state that needs to be programmed a particular
912 * way, but we never actually change.
915 iris_init_render_context(struct iris_batch
*batch
)
917 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
920 iris_batch_sync_region_start(batch
);
922 emit_pipeline_select(batch
, _3D
);
924 iris_emit_l3_config(batch
, batch
->screen
->l3_config_3d
);
926 init_state_base_address(batch
);
929 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
930 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
931 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
933 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
935 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
936 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
937 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
939 iris_emit_lri(batch
, INSTPM
, reg_val
);
943 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
944 reg
.FloatBlendOptimizationEnable
= true;
945 reg
.FloatBlendOptimizationEnableMask
= true;
946 reg
.PartialResolveDisableInVC
= true;
947 reg
.PartialResolveDisableInVCMask
= true;
949 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
951 if (devinfo
->is_geminilake
)
952 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
956 iris_pack_state(GENX(TCCNTLREG
), ®_val
, reg
) {
957 reg
.L3DataPartialWriteMergingEnable
= true;
958 reg
.ColorZPartialWriteMergingEnable
= true;
959 reg
.URBPartialWriteMergingEnable
= true;
960 reg
.TCDisable
= true;
962 iris_emit_lri(batch
, TCCNTLREG
, reg_val
);
964 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
965 reg
.HeaderlessMessageforPreemptableContexts
= 1;
966 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
968 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
970 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
971 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
972 reg
.EnabledTexelOffsetPrecisionFix
= 1;
973 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
975 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
977 /* Hardware specification recommends disabling repacking for the
978 * compatibility with decompression mechanism in display controller.
980 if (devinfo
->disable_ccs_repack
) {
981 iris_pack_state(GENX(CACHE_MODE_0
), ®_val
, reg
) {
982 reg
.DisableRepackingforCompression
= true;
983 reg
.DisableRepackingforCompressionMask
= true;
985 iris_emit_lri(batch
, CACHE_MODE_0
, reg_val
);
988 iris_upload_slice_hashing_state(batch
);
991 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
992 * changing it dynamically. We set it to the maximum size here, and
993 * instead include the render target dimensions in the viewport, so
994 * viewport extents clipping takes care of pruning stray geometry.
996 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
997 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
998 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
1001 /* Set the initial MSAA sample positions. */
1002 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
1003 GEN_SAMPLE_POS_1X(pat
._1xSample
);
1004 GEN_SAMPLE_POS_2X(pat
._2xSample
);
1005 GEN_SAMPLE_POS_4X(pat
._4xSample
);
1006 GEN_SAMPLE_POS_8X(pat
._8xSample
);
1008 GEN_SAMPLE_POS_16X(pat
._16xSample
);
1012 /* Use the legacy AA line coverage computation. */
1013 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
1015 /* Disable chromakeying (it's for media) */
1016 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
1018 /* We want regular rendering, not special HiZ operations. */
1019 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
1021 /* No polygon stippling offsets are necessary. */
1022 /* TODO: may need to set an offset for origin-UL framebuffers */
1023 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
1025 iris_alloc_push_constants(batch
);
1029 init_aux_map_state(batch
);
1032 iris_batch_sync_region_end(batch
);
1036 iris_init_compute_context(struct iris_batch
*batch
)
1038 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
1040 iris_batch_sync_region_start(batch
);
1042 /* GEN:BUG:1607854226:
1044 * Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS.
1047 emit_pipeline_select(batch
, _3D
);
1049 emit_pipeline_select(batch
, GPGPU
);
1052 iris_emit_l3_config(batch
, batch
->screen
->l3_config_cs
);
1054 init_state_base_address(batch
);
1057 emit_pipeline_select(batch
, GPGPU
);
1061 if (devinfo
->is_geminilake
)
1062 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
1066 init_aux_map_state(batch
);
1069 iris_batch_sync_region_end(batch
);
1072 struct iris_vertex_buffer_state
{
1073 /** The VERTEX_BUFFER_STATE hardware structure. */
1074 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
1076 /** The resource to source vertex data from. */
1077 struct pipe_resource
*resource
;
1082 struct iris_depth_buffer_state
{
1083 /* Depth/HiZ/Stencil related hardware packets. */
1084 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
1085 GENX(3DSTATE_STENCIL_BUFFER_length
) +
1086 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
1087 GENX(3DSTATE_CLEAR_PARAMS_length
) +
1088 GENX(MI_LOAD_REGISTER_IMM_length
) * 2];
1092 * Generation-specific context state (ice->state.genx->...).
1094 * Most state can go in iris_context directly, but these encode hardware
1095 * packets which vary by generation.
1097 struct iris_genx_state
{
1098 struct iris_vertex_buffer_state vertex_buffers
[33];
1099 uint32_t last_index_buffer
[GENX(3DSTATE_INDEX_BUFFER_length
)];
1101 struct iris_depth_buffer_state depth_buffer
;
1103 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
1106 bool pma_fix_enabled
;
1110 /* Is object level preemption enabled? */
1111 bool object_preemption
;
1116 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
1118 } shaders
[MESA_SHADER_STAGES
];
1122 * The pipe->set_blend_color() driver hook.
1124 * This corresponds to our COLOR_CALC_STATE.
1127 iris_set_blend_color(struct pipe_context
*ctx
,
1128 const struct pipe_blend_color
*state
)
1130 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1132 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
1133 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
1134 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1138 * Gallium CSO for blend state (see pipe_blend_state).
1140 struct iris_blend_state
{
1141 /** Partial 3DSTATE_PS_BLEND */
1142 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
1144 /** Partial BLEND_STATE */
1145 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
1146 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
1148 bool alpha_to_coverage
; /* for shader key */
1150 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
1151 uint8_t blend_enables
;
1153 /** Bitfield of whether color writes are enabled for RT[i] */
1154 uint8_t color_write_enables
;
1156 /** Does RT[0] use dual color blending? */
1157 bool dual_color_blending
;
1160 static enum pipe_blendfactor
1161 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
1164 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
1165 return PIPE_BLENDFACTOR_ONE
;
1167 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
1168 return PIPE_BLENDFACTOR_ZERO
;
1175 * The pipe->create_blend_state() driver hook.
1177 * Translates a pipe_blend_state into iris_blend_state.
1180 iris_create_blend_state(struct pipe_context
*ctx
,
1181 const struct pipe_blend_state
*state
)
1183 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
1184 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
1186 cso
->blend_enables
= 0;
1187 cso
->color_write_enables
= 0;
1188 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
1190 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
1192 bool indep_alpha_blend
= false;
1194 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
1195 const struct pipe_rt_blend_state
*rt
=
1196 &state
->rt
[state
->independent_blend_enable
? i
: 0];
1198 enum pipe_blendfactor src_rgb
=
1199 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
1200 enum pipe_blendfactor src_alpha
=
1201 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
1202 enum pipe_blendfactor dst_rgb
=
1203 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
1204 enum pipe_blendfactor dst_alpha
=
1205 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
1207 if (rt
->rgb_func
!= rt
->alpha_func
||
1208 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
1209 indep_alpha_blend
= true;
1211 if (rt
->blend_enable
)
1212 cso
->blend_enables
|= 1u << i
;
1215 cso
->color_write_enables
|= 1u << i
;
1217 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
1218 be
.LogicOpEnable
= state
->logicop_enable
;
1219 be
.LogicOpFunction
= state
->logicop_func
;
1221 be
.PreBlendSourceOnlyClampEnable
= false;
1222 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
1223 be
.PreBlendColorClampEnable
= true;
1224 be
.PostBlendColorClampEnable
= true;
1226 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
1228 be
.ColorBlendFunction
= rt
->rgb_func
;
1229 be
.AlphaBlendFunction
= rt
->alpha_func
;
1230 be
.SourceBlendFactor
= src_rgb
;
1231 be
.SourceAlphaBlendFactor
= src_alpha
;
1232 be
.DestinationBlendFactor
= dst_rgb
;
1233 be
.DestinationAlphaBlendFactor
= dst_alpha
;
1235 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
1236 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
1237 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
1238 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
1240 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
1243 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
1244 /* pb.HasWriteableRT is filled in at draw time.
1245 * pb.AlphaTestEnable is filled in at draw time.
1247 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
1248 * setting it when dual color blending without an appropriate shader.
1251 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1252 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1254 pb
.SourceBlendFactor
=
1255 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1256 pb
.SourceAlphaBlendFactor
=
1257 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1258 pb
.DestinationBlendFactor
=
1259 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1260 pb
.DestinationAlphaBlendFactor
=
1261 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1264 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1265 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1266 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1267 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1268 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1269 bs
.ColorDitherEnable
= state
->dither
;
1270 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1273 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1279 * The pipe->bind_blend_state() driver hook.
1281 * Bind a blending CSO and flag related dirty bits.
1284 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1286 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1287 struct iris_blend_state
*cso
= state
;
1289 ice
->state
.cso_blend
= cso
;
1291 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1292 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1293 ice
->state
.stage_dirty
|= ice
->state
.stage_dirty_for_nos
[IRIS_NOS_BLEND
];
1296 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
1300 * Return true if the FS writes to any color outputs which are not disabled
1301 * via color masking.
1304 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1305 const struct shader_info
*fs_info
)
1310 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1312 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1313 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1315 return cso_blend
->color_write_enables
& rt_outputs
;
1319 * Gallium CSO for depth, stencil, and alpha testing state.
1321 struct iris_depth_stencil_alpha_state
{
1322 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1323 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1326 uint32_t depth_bounds
[GENX(3DSTATE_DEPTH_BOUNDS_length
)];
1329 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1330 struct pipe_alpha_state alpha
;
1332 /** Outbound to resolve and cache set tracking. */
1333 bool depth_writes_enabled
;
1334 bool stencil_writes_enabled
;
1336 /** Outbound to Gen8-9 PMA stall equations */
1337 bool depth_test_enabled
;
1341 * The pipe->create_depth_stencil_alpha_state() driver hook.
1343 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1344 * testing state since we need pieces of it in a variety of places.
1347 iris_create_zsa_state(struct pipe_context
*ctx
,
1348 const struct pipe_depth_stencil_alpha_state
*state
)
1350 struct iris_depth_stencil_alpha_state
*cso
=
1351 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1353 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1355 cso
->alpha
= state
->alpha
;
1356 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1357 cso
->depth_test_enabled
= state
->depth
.enabled
;
1358 cso
->stencil_writes_enabled
=
1359 state
->stencil
[0].writemask
!= 0 ||
1360 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1362 /* gallium frontends need to optimize away EQUAL writes for us. */
1363 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1365 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1366 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1367 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1368 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1369 wmds
.StencilTestFunction
=
1370 translate_compare_func(state
->stencil
[0].func
);
1371 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1372 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1373 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1374 wmds
.BackfaceStencilTestFunction
=
1375 translate_compare_func(state
->stencil
[1].func
);
1376 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1377 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1378 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1379 wmds
.StencilBufferWriteEnable
=
1380 state
->stencil
[0].writemask
!= 0 ||
1381 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1382 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1383 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1384 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1385 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1386 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1387 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1388 /* wmds.[Backface]StencilReferenceValue are merged later */
1390 wmds
.StencilReferenceValueModifyDisable
= true;
1395 iris_pack_command(GENX(3DSTATE_DEPTH_BOUNDS
), cso
->depth_bounds
, depth_bounds
) {
1396 depth_bounds
.DepthBoundsTestValueModifyDisable
= false;
1397 depth_bounds
.DepthBoundsTestEnableModifyDisable
= false;
1398 depth_bounds
.DepthBoundsTestEnable
= state
->depth
.bounds_test
;
1399 depth_bounds
.DepthBoundsTestMinValue
= state
->depth
.bounds_min
;
1400 depth_bounds
.DepthBoundsTestMaxValue
= state
->depth
.bounds_max
;
1408 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1410 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1413 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1415 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1416 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1417 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1420 if (cso_changed(alpha
.ref_value
))
1421 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1423 if (cso_changed(alpha
.enabled
))
1424 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1426 if (cso_changed(alpha
.func
))
1427 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1429 if (cso_changed(depth_writes_enabled
))
1430 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1432 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1433 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1436 if (cso_changed(depth_bounds
))
1437 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BOUNDS
;
1441 ice
->state
.cso_zsa
= new_cso
;
1442 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1443 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1444 ice
->state
.stage_dirty
|=
1445 ice
->state
.stage_dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1448 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
1453 want_pma_fix(struct iris_context
*ice
)
1455 UNUSED
struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1456 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1457 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1458 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1459 const struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
1460 const struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
1461 const struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
1463 /* In very specific combinations of state, we can instruct Gen8-9 hardware
1464 * to avoid stalling at the pixel mask array. The state equations are
1465 * documented in these places:
1467 * - Gen8 Depth PMA Fix: CACHE_MODE_1::NP_PMA_FIX_ENABLE
1468 * - Gen9 Stencil PMA Fix: CACHE_MODE_0::STC PMA Optimization Enable
1470 * Both equations share some common elements:
1473 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
1474 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
1475 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
1476 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
1479 * 3DSTATE_WM::ForceKillPix != ForceOff &&
1480 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1481 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1482 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1483 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1484 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1486 * (Technically the stencil PMA treats ForceKillPix differently,
1487 * but I think this is a documentation oversight, and we don't
1488 * ever use it in this way, so it doesn't matter).
1491 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
1492 * 3DSTATE_RASTER::ForceSampleCount == NUMRASTSAMPLES_0 &&
1493 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
1494 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
1495 * 3DSTATE_WM::EDSC_Mode != EDSC_PREPS &&
1496 * 3DSTATE_PS_EXTRA::PixelShaderValid &&
1499 * These are always true:
1501 * 3DSTATE_RASTER::ForceSampleCount == NUMRASTSAMPLES_0
1502 * 3DSTATE_PS_EXTRA::PixelShaderValid
1504 * Also, we never use the normal drawing path for HiZ ops; these are true:
1506 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
1507 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
1508 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
1509 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
1511 * This happens sometimes:
1513 * 3DSTATE_WM::ForceThreadDispatch != 1
1515 * However, we choose to ignore it as it either agrees with the signal
1516 * (dispatch was already enabled, so nothing out of the ordinary), or
1517 * there are no framebuffer attachments (so no depth or HiZ anyway,
1518 * meaning the PMA signal will already be disabled).
1524 struct iris_resource
*zres
, *sres
;
1525 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
, &zres
, &sres
);
1527 /* 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
1528 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
1530 if (!zres
|| !iris_resource_level_has_hiz(zres
, cso_fb
->zsbuf
->u
.tex
.level
))
1533 /* 3DSTATE_WM::EDSC_Mode != EDSC_PREPS */
1534 if (wm_prog_data
->early_fragment_tests
)
1537 /* 3DSTATE_WM::ForceKillPix != ForceOff &&
1538 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1539 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1540 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1541 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1542 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1544 bool killpixels
= wm_prog_data
->uses_kill
|| wm_prog_data
->uses_omask
||
1545 cso_blend
->alpha_to_coverage
|| cso_zsa
->alpha
.enabled
;
1547 /* The Gen8 depth PMA equation becomes:
1550 * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
1551 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE
1554 * 3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
1555 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
1556 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE
1560 * 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable &&
1561 * ((killpixels && (depth_writes || stencil_writes)) ||
1562 * 3DSTATE_PS_EXTRA::PixelShaderComputedDepthMode != PSCDEPTH_OFF)
1565 if (!cso_zsa
->depth_test_enabled
)
1568 return wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
||
1569 (killpixels
&& (cso_zsa
->depth_writes_enabled
||
1570 (sres
&& cso_zsa
->stencil_writes_enabled
)));
1575 genX(update_pma_fix
)(struct iris_context
*ice
,
1576 struct iris_batch
*batch
,
1580 struct iris_genx_state
*genx
= ice
->state
.genx
;
1582 if (genx
->pma_fix_enabled
== enable
)
1585 genx
->pma_fix_enabled
= enable
;
1587 /* According to the Broadwell PIPE_CONTROL documentation, software should
1588 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
1589 * prior to the LRI. If stencil buffer writes are enabled, then a Render * Cache Flush is also necessary.
1591 * The Gen9 docs say to use a depth stall rather than a command streamer
1592 * stall. However, the hardware seems to violently disagree. A full
1593 * command streamer stall seems to be needed in both cases.
1595 iris_emit_pipe_control_flush(batch
, "PMA fix change (1/2)",
1596 PIPE_CONTROL_CS_STALL
|
1597 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1598 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1601 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
1602 reg
.NPPMAFixEnable
= enable
;
1603 reg
.NPEarlyZFailsDisable
= enable
;
1604 reg
.NPPMAFixEnableMask
= true;
1605 reg
.NPEarlyZFailsDisableMask
= true;
1607 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
1609 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
1610 * Flush bits is often necessary. We do it regardless because it's easier.
1611 * The render cache flush is also necessary if stencil writes are enabled.
1613 * Again, the Gen9 docs give a different set of flushes but the Broadwell
1614 * flushes seem to work just as well.
1616 iris_emit_pipe_control_flush(batch
, "PMA fix change (1/2)",
1617 PIPE_CONTROL_DEPTH_STALL
|
1618 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
1619 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
1624 * Gallium CSO for rasterizer state.
1626 struct iris_rasterizer_state
{
1627 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1628 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1629 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1630 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1631 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1633 uint8_t num_clip_plane_consts
;
1634 bool clip_halfz
; /* for CC_VIEWPORT */
1635 bool depth_clip_near
; /* for CC_VIEWPORT */
1636 bool depth_clip_far
; /* for CC_VIEWPORT */
1637 bool flatshade
; /* for shader state */
1638 bool flatshade_first
; /* for stream output */
1639 bool clamp_fragment_color
; /* for shader state */
1640 bool light_twoside
; /* for shader state */
1641 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1642 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1643 bool line_stipple_enable
;
1644 bool poly_stipple_enable
;
1646 bool force_persample_interp
;
1647 bool conservative_rasterization
;
1648 bool fill_mode_point_or_line
;
1649 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1650 uint16_t sprite_coord_enable
;
1654 get_line_width(const struct pipe_rasterizer_state
*state
)
1656 float line_width
= state
->line_width
;
1658 /* From the OpenGL 4.4 spec:
1660 * "The actual width of non-antialiased lines is determined by rounding
1661 * the supplied width to the nearest integer, then clamping it to the
1662 * implementation-dependent maximum non-antialiased line width."
1664 if (!state
->multisample
&& !state
->line_smooth
)
1665 line_width
= roundf(state
->line_width
);
1667 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1668 /* For 1 pixel line thickness or less, the general anti-aliasing
1669 * algorithm gives up, and a garbage line is generated. Setting a
1670 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1671 * (one-pixel-wide), non-antialiased lines.
1673 * Lines rendered with zero Line Width are rasterized using the
1674 * "Grid Intersection Quantization" rules as specified by the
1675 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1684 * The pipe->create_rasterizer_state() driver hook.
1687 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1688 const struct pipe_rasterizer_state
*state
)
1690 struct iris_rasterizer_state
*cso
=
1691 malloc(sizeof(struct iris_rasterizer_state
));
1693 cso
->multisample
= state
->multisample
;
1694 cso
->force_persample_interp
= state
->force_persample_interp
;
1695 cso
->clip_halfz
= state
->clip_halfz
;
1696 cso
->depth_clip_near
= state
->depth_clip_near
;
1697 cso
->depth_clip_far
= state
->depth_clip_far
;
1698 cso
->flatshade
= state
->flatshade
;
1699 cso
->flatshade_first
= state
->flatshade_first
;
1700 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1701 cso
->light_twoside
= state
->light_twoside
;
1702 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1703 cso
->half_pixel_center
= state
->half_pixel_center
;
1704 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1705 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1706 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1707 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1708 cso
->conservative_rasterization
=
1709 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1711 cso
->fill_mode_point_or_line
=
1712 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1713 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1714 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1715 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1717 if (state
->clip_plane_enable
!= 0)
1718 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1720 cso
->num_clip_plane_consts
= 0;
1722 float line_width
= get_line_width(state
);
1724 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1725 sf
.StatisticsEnable
= true;
1726 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1727 sf
.LineEndCapAntialiasingRegionWidth
=
1728 state
->line_smooth
? _10pixels
: _05pixels
;
1729 sf
.LastPixelEnable
= state
->line_last_pixel
;
1730 sf
.LineWidth
= line_width
;
1731 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1732 !state
->point_quad_rasterization
;
1733 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1734 sf
.PointWidth
= state
->point_size
;
1736 if (state
->flatshade_first
) {
1737 sf
.TriangleFanProvokingVertexSelect
= 1;
1739 sf
.TriangleStripListProvokingVertexSelect
= 2;
1740 sf
.TriangleFanProvokingVertexSelect
= 2;
1741 sf
.LineStripListProvokingVertexSelect
= 1;
1745 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1746 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1747 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1748 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1749 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1750 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1751 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1752 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1753 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1754 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1755 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1756 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1757 rr
.SmoothPointEnable
= state
->point_smooth
;
1758 rr
.AntialiasingEnable
= state
->line_smooth
;
1759 rr
.ScissorRectangleEnable
= state
->scissor
;
1761 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1762 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1763 rr
.ConservativeRasterizationEnable
=
1764 cso
->conservative_rasterization
;
1766 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1770 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1771 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1772 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1774 cl
.EarlyCullEnable
= true;
1775 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1776 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1777 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1778 cl
.GuardbandClipTestEnable
= true;
1779 cl
.ClipEnable
= true;
1780 cl
.MinimumPointWidth
= 0.125;
1781 cl
.MaximumPointWidth
= 255.875;
1783 if (state
->flatshade_first
) {
1784 cl
.TriangleFanProvokingVertexSelect
= 1;
1786 cl
.TriangleStripListProvokingVertexSelect
= 2;
1787 cl
.TriangleFanProvokingVertexSelect
= 2;
1788 cl
.LineStripListProvokingVertexSelect
= 1;
1792 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1793 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1794 * filled in at draw time from the FS program.
1796 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1797 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1798 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1799 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1800 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1803 /* Remap from 0..255 back to 1..256 */
1804 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1806 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1807 if (state
->line_stipple_enable
) {
1808 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1809 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1810 line
.LineStippleRepeatCount
= line_stipple_factor
;
1818 * The pipe->bind_rasterizer_state() driver hook.
1820 * Bind a rasterizer CSO and flag related dirty bits.
1823 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1825 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1826 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1827 struct iris_rasterizer_state
*new_cso
= state
;
1830 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1831 if (cso_changed_memcmp(line_stipple
))
1832 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1834 if (cso_changed(half_pixel_center
))
1835 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1837 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1838 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1840 if (cso_changed(rasterizer_discard
))
1841 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1843 if (cso_changed(flatshade_first
))
1844 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1846 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1847 cso_changed(clip_halfz
))
1848 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1850 if (cso_changed(sprite_coord_enable
) ||
1851 cso_changed(sprite_coord_mode
) ||
1852 cso_changed(light_twoside
))
1853 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1855 if (cso_changed(conservative_rasterization
))
1856 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_FS
;
1859 ice
->state
.cso_rast
= new_cso
;
1860 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1861 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1862 ice
->state
.stage_dirty
|=
1863 ice
->state
.stage_dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1867 * Return true if the given wrap mode requires the border color to exist.
1869 * (We can skip uploading it if the sampler isn't going to use it.)
1872 wrap_mode_needs_border_color(unsigned wrap_mode
)
1874 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1878 * Gallium CSO for sampler state.
1880 struct iris_sampler_state
{
1881 union pipe_color_union border_color
;
1882 bool needs_border_color
;
1884 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1888 * The pipe->create_sampler_state() driver hook.
1890 * We fill out SAMPLER_STATE (except for the border color pointer), and
1891 * store that on the CPU. It doesn't make sense to upload it to a GPU
1892 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1893 * all bound sampler states to be in contiguous memor.
1896 iris_create_sampler_state(struct pipe_context
*ctx
,
1897 const struct pipe_sampler_state
*state
)
1899 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1904 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1905 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1907 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1908 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1909 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1911 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1913 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1914 wrap_mode_needs_border_color(wrap_t
) ||
1915 wrap_mode_needs_border_color(wrap_r
);
1917 float min_lod
= state
->min_lod
;
1918 unsigned mag_img_filter
= state
->mag_img_filter
;
1920 // XXX: explain this code ported from ilo...I don't get it at all...
1921 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1922 state
->min_lod
> 0.0f
) {
1924 mag_img_filter
= state
->min_img_filter
;
1927 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1928 samp
.TCXAddressControlMode
= wrap_s
;
1929 samp
.TCYAddressControlMode
= wrap_t
;
1930 samp
.TCZAddressControlMode
= wrap_r
;
1931 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1932 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1933 samp
.MinModeFilter
= state
->min_img_filter
;
1934 samp
.MagModeFilter
= mag_img_filter
;
1935 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1936 samp
.MaximumAnisotropy
= RATIO21
;
1938 if (state
->max_anisotropy
>= 2) {
1939 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1940 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1941 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1944 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1945 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1947 samp
.MaximumAnisotropy
=
1948 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1951 /* Set address rounding bits if not using nearest filtering. */
1952 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1953 samp
.UAddressMinFilterRoundingEnable
= true;
1954 samp
.VAddressMinFilterRoundingEnable
= true;
1955 samp
.RAddressMinFilterRoundingEnable
= true;
1958 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1959 samp
.UAddressMagFilterRoundingEnable
= true;
1960 samp
.VAddressMagFilterRoundingEnable
= true;
1961 samp
.RAddressMagFilterRoundingEnable
= true;
1964 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1965 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1967 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1969 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1970 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1971 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1972 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1974 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1981 * The pipe->bind_sampler_states() driver hook.
1984 iris_bind_sampler_states(struct pipe_context
*ctx
,
1985 enum pipe_shader_type p_stage
,
1986 unsigned start
, unsigned count
,
1989 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1990 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1991 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1993 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1997 for (int i
= 0; i
< count
; i
++) {
1998 if (shs
->samplers
[start
+ i
] != states
[i
]) {
1999 shs
->samplers
[start
+ i
] = states
[i
];
2005 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_SAMPLER_STATES_VS
<< stage
;
2009 * Upload the sampler states into a contiguous area of GPU memory, for
2010 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
2012 * Also fill out the border color state pointers.
2015 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
2017 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2018 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
2020 /* We assume gallium frontends will call pipe->bind_sampler_states()
2021 * if the program's number of textures changes.
2023 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
2028 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
2029 * in the dynamic state memory zone, so we can point to it via the
2030 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
2032 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
2034 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
2038 struct pipe_resource
*res
= shs
->sampler_table
.res
;
2039 struct iris_bo
*bo
= iris_resource_bo(res
);
2041 iris_record_state_size(ice
->state
.sizes
,
2042 bo
->gtt_offset
+ shs
->sampler_table
.offset
, size
);
2044 shs
->sampler_table
.offset
+= iris_bo_offset_from_base_address(bo
);
2046 /* Make sure all land in the same BO */
2047 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
2049 ice
->state
.need_border_colors
&= ~(1 << stage
);
2051 for (int i
= 0; i
< count
; i
++) {
2052 struct iris_sampler_state
*state
= shs
->samplers
[i
];
2053 struct iris_sampler_view
*tex
= shs
->textures
[i
];
2056 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
2057 } else if (!state
->needs_border_color
) {
2058 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
2060 ice
->state
.need_border_colors
|= 1 << stage
;
2062 /* We may need to swizzle the border color for format faking.
2063 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
2064 * This means we need to move the border color's A channel into
2065 * the R or G channels so that those read swizzles will move it
2068 union pipe_color_union
*color
= &state
->border_color
;
2069 union pipe_color_union tmp
;
2071 enum pipe_format internal_format
= tex
->res
->internal_format
;
2073 if (util_format_is_alpha(internal_format
)) {
2074 unsigned char swz
[4] = {
2075 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
2076 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
2078 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
2080 } else if (util_format_is_luminance_alpha(internal_format
) &&
2081 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
2082 unsigned char swz
[4] = {
2083 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
2084 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
2086 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
2091 /* Stream out the border color and merge the pointer. */
2092 uint32_t offset
= iris_upload_border_color(ice
, color
);
2094 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
2095 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
2096 dyns
.BorderColorPointer
= offset
;
2099 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
2100 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
2103 map
+= GENX(SAMPLER_STATE_length
);
2107 static enum isl_channel_select
2108 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
2111 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
2112 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
2113 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
2114 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
2115 case PIPE_SWIZZLE_1
: return SCS_ONE
;
2116 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
2117 default: unreachable("invalid swizzle");
2122 fill_buffer_surface_state(struct isl_device
*isl_dev
,
2123 struct iris_resource
*res
,
2125 enum isl_format format
,
2126 struct isl_swizzle swizzle
,
2130 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
2131 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
2133 /* The ARB_texture_buffer_specification says:
2135 * "The number of texels in the buffer texture's texel array is given by
2137 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
2139 * where <buffer_size> is the size of the buffer object, in basic
2140 * machine units and <components> and <base_type> are the element count
2141 * and base data type for elements, as specified in Table X.1. The
2142 * number of texels in the texel array is then clamped to the
2143 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
2145 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
2146 * so that when ISL divides by stride to obtain the number of texels, that
2147 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
2149 unsigned final_size
=
2150 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
2151 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
2153 isl_buffer_fill_state(isl_dev
, map
,
2154 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
2155 .size_B
= final_size
,
2159 .mocs
= iris_mocs(res
->bo
, isl_dev
));
2162 #define SURFACE_STATE_ALIGNMENT 64
2165 * Allocate several contiguous SURFACE_STATE structures, one for each
2166 * supported auxiliary surface mode. This only allocates the CPU-side
2167 * copy, they will need to be uploaded later after they're filled in.
2170 alloc_surface_states(struct iris_surface_state
*surf_state
,
2171 unsigned aux_usages
)
2173 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
2175 /* If this changes, update this to explicitly align pointers */
2176 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
2178 assert(aux_usages
!= 0);
2180 /* In case we're re-allocating them... */
2181 free(surf_state
->cpu
);
2183 surf_state
->num_states
= util_bitcount(aux_usages
);
2184 surf_state
->cpu
= calloc(surf_state
->num_states
, surf_size
);
2185 surf_state
->ref
.offset
= 0;
2186 pipe_resource_reference(&surf_state
->ref
.res
, NULL
);
2188 assert(surf_state
->cpu
);
2192 * Upload the CPU side SURFACE_STATEs into a GPU buffer.
2195 upload_surface_states(struct u_upload_mgr
*mgr
,
2196 struct iris_surface_state
*surf_state
)
2198 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
2199 const unsigned bytes
= surf_state
->num_states
* surf_size
;
2202 upload_state(mgr
, &surf_state
->ref
, bytes
, SURFACE_STATE_ALIGNMENT
);
2204 surf_state
->ref
.offset
+=
2205 iris_bo_offset_from_base_address(iris_resource_bo(surf_state
->ref
.res
));
2208 memcpy(map
, surf_state
->cpu
, bytes
);
2212 * Update resource addresses in a set of SURFACE_STATE descriptors,
2213 * and re-upload them if necessary.
2216 update_surface_state_addrs(struct u_upload_mgr
*mgr
,
2217 struct iris_surface_state
*surf_state
,
2220 if (surf_state
->bo_address
== bo
->gtt_offset
)
2223 STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start
) % 64 == 0);
2224 STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_bits
) == 64);
2226 uint64_t *ss_addr
= (uint64_t *) &surf_state
->cpu
[GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start
) / 32];
2228 /* First, update the CPU copies. We assume no other fields exist in
2229 * the QWord containing Surface Base Address.
2231 for (unsigned i
= 0; i
< surf_state
->num_states
; i
++) {
2232 *ss_addr
= *ss_addr
- surf_state
->bo_address
+ bo
->gtt_offset
;
2233 ss_addr
= ((void *) ss_addr
) + SURFACE_STATE_ALIGNMENT
;
2236 /* Next, upload the updated copies to a GPU buffer. */
2237 upload_surface_states(mgr
, surf_state
);
2239 surf_state
->bo_address
= bo
->gtt_offset
;
2246 * Return an ISL surface for use with non-coherent render target reads.
2248 * In a few complex cases, we can't use the SURFACE_STATE for normal render
2249 * target writes. We need to make a separate one for sampling which refers
2250 * to the single slice of the texture being read.
2253 get_rt_read_isl_surf(const struct gen_device_info
*devinfo
,
2254 struct iris_resource
*res
,
2255 enum pipe_texture_target target
,
2256 struct isl_view
*view
,
2257 uint32_t *offset_to_tile
,
2258 uint32_t *tile_x_sa
,
2259 uint32_t *tile_y_sa
,
2260 struct isl_surf
*surf
)
2264 const enum isl_dim_layout dim_layout
=
2265 iris_get_isl_dim_layout(devinfo
, res
->surf
.tiling
, target
);
2267 surf
->dim
= target_to_isl_surf_dim(target
);
2269 if (surf
->dim_layout
== dim_layout
)
2272 /* The layout of the specified texture target is not compatible with the
2273 * actual layout of the miptree structure in memory -- You're entering
2274 * dangerous territory, this can only possibly work if you only intended
2275 * to access a single level and slice of the texture, and the hardware
2276 * supports the tile offset feature in order to allow non-tile-aligned
2277 * base offsets, since we'll have to point the hardware to the first
2278 * texel of the level instead of relying on the usual base level/layer
2281 assert(view
->levels
== 1 && view
->array_len
== 1);
2282 assert(*tile_x_sa
== 0 && *tile_y_sa
== 0);
2284 *offset_to_tile
= iris_resource_get_tile_offsets(res
, view
->base_level
,
2285 view
->base_array_layer
,
2286 tile_x_sa
, tile_y_sa
);
2287 const unsigned l
= view
->base_level
;
2289 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
2290 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
2291 minify(surf
->logical_level0_px
.height
, l
);
2292 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
2293 minify(surf
->logical_level0_px
.depth
, l
);
2295 surf
->logical_level0_px
.array_len
= 1;
2297 surf
->dim_layout
= dim_layout
;
2299 view
->base_level
= 0;
2300 view
->base_array_layer
= 0;
2305 fill_surface_state(struct isl_device
*isl_dev
,
2307 struct iris_resource
*res
,
2308 struct isl_surf
*surf
,
2309 struct isl_view
*view
,
2311 uint32_t extra_main_offset
,
2315 struct isl_surf_fill_state_info f
= {
2318 .mocs
= iris_mocs(res
->bo
, isl_dev
),
2319 .address
= res
->bo
->gtt_offset
+ res
->offset
+ extra_main_offset
,
2320 .x_offset_sa
= tile_x_sa
,
2321 .y_offset_sa
= tile_y_sa
,
2324 assert(!iris_resource_unfinished_aux_import(res
));
2326 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
2327 f
.aux_surf
= &res
->aux
.surf
;
2328 f
.aux_usage
= aux_usage
;
2329 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
2331 struct iris_bo
*clear_bo
= NULL
;
2332 uint64_t clear_offset
= 0;
2334 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
2336 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
2337 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
2341 isl_surf_fill_state_s(isl_dev
, map
, &f
);
2345 * The pipe->create_sampler_view() driver hook.
2347 static struct pipe_sampler_view
*
2348 iris_create_sampler_view(struct pipe_context
*ctx
,
2349 struct pipe_resource
*tex
,
2350 const struct pipe_sampler_view
*tmpl
)
2352 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2353 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2354 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2355 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
2360 /* initialize base object */
2362 isv
->base
.context
= ctx
;
2363 isv
->base
.texture
= NULL
;
2364 pipe_reference_init(&isv
->base
.reference
, 1);
2365 pipe_resource_reference(&isv
->base
.texture
, tex
);
2367 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
2368 struct iris_resource
*zres
, *sres
;
2369 const struct util_format_description
*desc
=
2370 util_format_description(tmpl
->format
);
2372 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
2374 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
2377 isv
->res
= (struct iris_resource
*) tex
;
2379 alloc_surface_states(&isv
->surface_state
, isv
->res
->aux
.sampler_usages
);
2381 isv
->surface_state
.bo_address
= isv
->res
->bo
->gtt_offset
;
2383 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
2385 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
2386 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
2387 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
2389 const struct iris_format_info fmt
=
2390 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2392 isv
->clear_color
= isv
->res
->aux
.clear_color
;
2394 isv
->view
= (struct isl_view
) {
2396 .swizzle
= (struct isl_swizzle
) {
2397 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
2398 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
2399 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
2400 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
2405 void *map
= isv
->surface_state
.cpu
;
2407 /* Fill out SURFACE_STATE for this view. */
2408 if (tmpl
->target
!= PIPE_BUFFER
) {
2409 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
2410 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
2411 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
2412 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
2413 isv
->view
.array_len
=
2414 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2416 if (iris_resource_unfinished_aux_import(isv
->res
))
2417 iris_resource_finish_aux_import(&screen
->base
, isv
->res
);
2419 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
2421 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2423 /* If we have a multisampled depth buffer, do not create a sampler
2424 * surface state with HiZ.
2426 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->res
->surf
,
2427 &isv
->view
, aux_usage
, 0, 0, 0);
2429 map
+= SURFACE_STATE_ALIGNMENT
;
2432 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
2433 isv
->view
.format
, isv
->view
.swizzle
,
2434 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
2437 upload_surface_states(ice
->state
.surface_uploader
, &isv
->surface_state
);
2443 iris_sampler_view_destroy(struct pipe_context
*ctx
,
2444 struct pipe_sampler_view
*state
)
2446 struct iris_sampler_view
*isv
= (void *) state
;
2447 pipe_resource_reference(&state
->texture
, NULL
);
2448 pipe_resource_reference(&isv
->surface_state
.ref
.res
, NULL
);
2449 free(isv
->surface_state
.cpu
);
2454 * The pipe->create_surface() driver hook.
2456 * In Gallium nomenclature, "surfaces" are a view of a resource that
2457 * can be bound as a render target or depth/stencil buffer.
2459 static struct pipe_surface
*
2460 iris_create_surface(struct pipe_context
*ctx
,
2461 struct pipe_resource
*tex
,
2462 const struct pipe_surface
*tmpl
)
2464 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2465 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2466 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2468 isl_surf_usage_flags_t usage
= 0;
2470 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2471 else if (util_format_is_depth_or_stencil(tmpl
->format
))
2472 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
2474 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
2476 const struct iris_format_info fmt
=
2477 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2479 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
2480 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
2481 /* Framebuffer validation will reject this invalid case, but it
2482 * hasn't had the opportunity yet. In the meantime, we need to
2483 * avoid hitting ISL asserts about unsupported formats below.
2488 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
2489 struct pipe_surface
*psurf
= &surf
->base
;
2490 struct iris_resource
*res
= (struct iris_resource
*) tex
;
2495 pipe_reference_init(&psurf
->reference
, 1);
2496 pipe_resource_reference(&psurf
->texture
, tex
);
2497 psurf
->context
= ctx
;
2498 psurf
->format
= tmpl
->format
;
2499 psurf
->width
= tex
->width0
;
2500 psurf
->height
= tex
->height0
;
2501 psurf
->texture
= tex
;
2502 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
2503 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
2504 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
2506 uint32_t array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2508 struct isl_view
*view
= &surf
->view
;
2509 *view
= (struct isl_view
) {
2511 .base_level
= tmpl
->u
.tex
.level
,
2513 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2514 .array_len
= array_len
,
2515 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2520 enum pipe_texture_target target
= (tex
->target
== PIPE_TEXTURE_3D
&&
2521 array_len
== 1) ? PIPE_TEXTURE_2D
:
2522 tex
->target
== PIPE_TEXTURE_1D_ARRAY
?
2523 PIPE_TEXTURE_2D_ARRAY
: tex
->target
;
2525 struct isl_view
*read_view
= &surf
->read_view
;
2526 *read_view
= (struct isl_view
) {
2528 .base_level
= tmpl
->u
.tex
.level
,
2530 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2531 .array_len
= array_len
,
2532 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2533 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
2537 surf
->clear_color
= res
->aux
.clear_color
;
2539 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
2540 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
2541 ISL_SURF_USAGE_STENCIL_BIT
))
2545 alloc_surface_states(&surf
->surface_state
, res
->aux
.possible_usages
);
2546 surf
->surface_state
.bo_address
= res
->bo
->gtt_offset
;
2549 alloc_surface_states(&surf
->surface_state_read
, res
->aux
.possible_usages
);
2550 surf
->surface_state_read
.bo_address
= res
->bo
->gtt_offset
;
2553 if (!isl_format_is_compressed(res
->surf
.format
)) {
2554 if (iris_resource_unfinished_aux_import(res
))
2555 iris_resource_finish_aux_import(&screen
->base
, res
);
2557 void *map
= surf
->surface_state
.cpu
;
2558 UNUSED
void *map_read
= surf
->surface_state_read
.cpu
;
2560 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
2561 * auxiliary surface mode and return the pipe_surface.
2563 unsigned aux_modes
= res
->aux
.possible_usages
;
2565 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2566 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2567 view
, aux_usage
, 0, 0, 0);
2568 map
+= SURFACE_STATE_ALIGNMENT
;
2571 struct isl_surf surf
;
2572 uint32_t offset_to_tile
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2573 get_rt_read_isl_surf(devinfo
, res
, target
, read_view
,
2574 &offset_to_tile
, &tile_x_sa
, &tile_y_sa
, &surf
);
2575 fill_surface_state(&screen
->isl_dev
, map_read
, res
, &surf
, read_view
,
2576 aux_usage
, offset_to_tile
, tile_x_sa
, tile_y_sa
);
2577 map_read
+= SURFACE_STATE_ALIGNMENT
;
2581 upload_surface_states(ice
->state
.surface_uploader
, &surf
->surface_state
);
2584 upload_surface_states(ice
->state
.surface_uploader
,
2585 &surf
->surface_state_read
);
2591 /* The resource has a compressed format, which is not renderable, but we
2592 * have a renderable view format. We must be attempting to upload blocks
2593 * of compressed data via an uncompressed view.
2595 * In this case, we can assume there are no auxiliary buffers, a single
2596 * miplevel, and that the resource is single-sampled. Gallium may try
2597 * and create an uncompressed view with multiple layers, however.
2599 assert(!isl_format_is_compressed(fmt
.fmt
));
2600 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
2601 assert(res
->surf
.samples
== 1);
2602 assert(view
->levels
== 1);
2604 struct isl_surf isl_surf
;
2605 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2607 if (view
->base_level
> 0) {
2608 /* We can't rely on the hardware's miplevel selection with such
2609 * a substantial lie about the format, so we select a single image
2610 * using the Tile X/Y Offset fields. In this case, we can't handle
2611 * multiple array slices.
2613 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
2614 * hard-coded to align to exactly the block size of the compressed
2615 * texture. This means that, when reinterpreted as a non-compressed
2616 * texture, the tile offsets may be anything and we can't rely on
2619 * Return NULL to force gallium frontends to take fallback paths.
2621 if (view
->array_len
> 1 || GEN_GEN
== 8)
2624 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
2625 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
2627 is_3d
? 0 : view
->base_array_layer
,
2628 is_3d
? view
->base_array_layer
: 0,
2630 &offset_B
, &tile_x_sa
, &tile_y_sa
);
2632 /* We use address and tile offsets to access a single level/layer
2633 * as a subimage, so reset level/layer so it doesn't offset again.
2635 view
->base_array_layer
= 0;
2636 view
->base_level
= 0;
2638 /* Level 0 doesn't require tile offsets, and the hardware can find
2639 * array slices using QPitch even with the format override, so we
2640 * can allow layers in this case. Copy the original ISL surface.
2642 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2645 /* Scale down the image dimensions by the block size. */
2646 const struct isl_format_layout
*fmtl
=
2647 isl_format_get_layout(res
->surf
.format
);
2648 isl_surf
.format
= fmt
.fmt
;
2649 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
2650 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
2651 tile_x_sa
/= fmtl
->bw
;
2652 tile_y_sa
/= fmtl
->bh
;
2654 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2655 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2657 struct isl_surf_fill_state_info f
= {
2660 .mocs
= iris_mocs(res
->bo
, &screen
->isl_dev
),
2661 .address
= res
->bo
->gtt_offset
+ offset_B
,
2662 .x_offset_sa
= tile_x_sa
,
2663 .y_offset_sa
= tile_y_sa
,
2666 isl_surf_fill_state_s(&screen
->isl_dev
, surf
->surface_state
.cpu
, &f
);
2668 upload_surface_states(ice
->state
.surface_uploader
, &surf
->surface_state
);
2675 fill_default_image_param(struct brw_image_param
*param
)
2677 memset(param
, 0, sizeof(*param
));
2678 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2679 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2680 * detailed explanation of these parameters.
2682 param
->swizzling
[0] = 0xff;
2683 param
->swizzling
[1] = 0xff;
2687 fill_buffer_image_param(struct brw_image_param
*param
,
2688 enum pipe_format pfmt
,
2691 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2693 fill_default_image_param(param
);
2694 param
->size
[0] = size
/ cpp
;
2695 param
->stride
[0] = cpp
;
2698 #define isl_surf_fill_image_param(x, ...)
2699 #define fill_default_image_param(x, ...)
2700 #define fill_buffer_image_param(x, ...)
2704 * The pipe->set_shader_images() driver hook.
2707 iris_set_shader_images(struct pipe_context
*ctx
,
2708 enum pipe_shader_type p_stage
,
2709 unsigned start_slot
, unsigned count
,
2710 const struct pipe_image_view
*p_images
)
2712 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2713 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2714 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2715 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2717 struct iris_genx_state
*genx
= ice
->state
.genx
;
2718 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2721 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2723 for (unsigned i
= 0; i
< count
; i
++) {
2724 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2726 if (p_images
&& p_images
[i
].resource
) {
2727 const struct pipe_image_view
*img
= &p_images
[i
];
2728 struct iris_resource
*res
= (void *) img
->resource
;
2730 util_copy_image_view(&iv
->base
, img
);
2732 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2734 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2735 res
->bind_stages
|= 1 << stage
;
2737 enum isl_format isl_fmt
= iris_image_view_get_format(ice
, img
);
2739 /* Render compression with images supported on gen12+ only. */
2740 unsigned aux_usages
= GEN_GEN
>= 12 ? res
->aux
.possible_usages
:
2741 1 << ISL_AUX_USAGE_NONE
;
2743 alloc_surface_states(&iv
->surface_state
, aux_usages
);
2744 iv
->surface_state
.bo_address
= res
->bo
->gtt_offset
;
2746 void *map
= iv
->surface_state
.cpu
;
2748 if (res
->base
.target
!= PIPE_BUFFER
) {
2749 struct isl_view view
= {
2751 .base_level
= img
->u
.tex
.level
,
2753 .base_array_layer
= img
->u
.tex
.first_layer
,
2754 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2755 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2756 .usage
= ISL_SURF_USAGE_STORAGE_BIT
,
2759 /* If using untyped fallback. */
2760 if (isl_fmt
== ISL_FORMAT_RAW
) {
2761 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2762 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2765 unsigned aux_modes
= aux_usages
;
2767 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2769 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2770 &view
, usage
, 0, 0, 0);
2772 map
+= SURFACE_STATE_ALIGNMENT
;
2776 isl_surf_fill_image_param(&screen
->isl_dev
,
2777 &image_params
[start_slot
+ i
],
2780 util_range_add(&res
->base
, &res
->valid_buffer_range
, img
->u
.buf
.offset
,
2781 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2783 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2784 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2785 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2786 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2787 img
->format
, img
->u
.buf
.size
);
2790 upload_surface_states(ice
->state
.surface_uploader
, &iv
->surface_state
);
2792 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2793 pipe_resource_reference(&iv
->surface_state
.ref
.res
, NULL
);
2794 fill_default_image_param(&image_params
[start_slot
+ i
]);
2798 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_BINDINGS_VS
<< stage
;
2800 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2801 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2803 /* Broadwell also needs brw_image_params re-uploaded */
2805 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_CONSTANTS_VS
<< stage
;
2806 shs
->sysvals_need_upload
= true;
2812 * The pipe->set_sampler_views() driver hook.
2815 iris_set_sampler_views(struct pipe_context
*ctx
,
2816 enum pipe_shader_type p_stage
,
2817 unsigned start
, unsigned count
,
2818 struct pipe_sampler_view
**views
)
2820 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2821 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2822 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2824 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2826 for (unsigned i
= 0; i
< count
; i
++) {
2827 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2828 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2829 &shs
->textures
[start
+ i
], pview
);
2830 struct iris_sampler_view
*view
= (void *) pview
;
2832 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2833 view
->res
->bind_stages
|= 1 << stage
;
2835 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2837 update_surface_state_addrs(ice
->state
.surface_uploader
,
2838 &view
->surface_state
, view
->res
->bo
);
2842 ice
->state
.stage_dirty
|= (IRIS_STAGE_DIRTY_BINDINGS_VS
<< stage
);
2844 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2845 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2849 iris_set_compute_resources(struct pipe_context
*ctx
,
2850 unsigned start
, unsigned count
,
2851 struct pipe_surface
**resources
)
2857 * The pipe->set_tess_state() driver hook.
2860 iris_set_tess_state(struct pipe_context
*ctx
,
2861 const float default_outer_level
[4],
2862 const float default_inner_level
[2])
2864 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2865 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2867 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2868 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2870 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_CONSTANTS_TCS
;
2871 shs
->sysvals_need_upload
= true;
2875 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2877 struct iris_surface
*surf
= (void *) p_surf
;
2878 pipe_resource_reference(&p_surf
->texture
, NULL
);
2879 pipe_resource_reference(&surf
->surface_state
.ref
.res
, NULL
);
2880 pipe_resource_reference(&surf
->surface_state_read
.ref
.res
, NULL
);
2881 free(surf
->surface_state
.cpu
);
2886 iris_set_clip_state(struct pipe_context
*ctx
,
2887 const struct pipe_clip_state
*state
)
2889 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2890 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2891 struct iris_shader_state
*gshs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
2892 struct iris_shader_state
*tshs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
2894 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2896 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_CONSTANTS_VS
|
2897 IRIS_STAGE_DIRTY_CONSTANTS_GS
|
2898 IRIS_STAGE_DIRTY_CONSTANTS_TES
;
2899 shs
->sysvals_need_upload
= true;
2900 gshs
->sysvals_need_upload
= true;
2901 tshs
->sysvals_need_upload
= true;
2905 * The pipe->set_polygon_stipple() driver hook.
2908 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2909 const struct pipe_poly_stipple
*state
)
2911 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2912 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2913 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2917 * The pipe->set_sample_mask() driver hook.
2920 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2922 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2924 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2925 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2927 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2928 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2932 * The pipe->set_scissor_states() driver hook.
2934 * This corresponds to our SCISSOR_RECT state structures. It's an
2935 * exact match, so we just store them, and memcpy them out later.
2938 iris_set_scissor_states(struct pipe_context
*ctx
,
2939 unsigned start_slot
,
2940 unsigned num_scissors
,
2941 const struct pipe_scissor_state
*rects
)
2943 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2945 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2946 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2947 /* If the scissor was out of bounds and got clamped to 0 width/height
2948 * at the bounds, the subtraction of 1 from maximums could produce a
2949 * negative number and thus not clip anything. Instead, just provide
2950 * a min > max scissor inside the bounds, which produces the expected
2953 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2954 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2957 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2958 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2959 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2964 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2968 * The pipe->set_stencil_ref() driver hook.
2970 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2973 iris_set_stencil_ref(struct pipe_context
*ctx
,
2974 const struct pipe_stencil_ref
*state
)
2976 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2977 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2979 ice
->state
.dirty
|= IRIS_DIRTY_STENCIL_REF
;
2980 else if (GEN_GEN
>= 9)
2981 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2983 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2987 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2989 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2993 * The pipe->set_viewport_states() driver hook.
2995 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2996 * the guardband yet, as we need the framebuffer dimensions, but we can
2997 * at least fill out the rest.
3000 iris_set_viewport_states(struct pipe_context
*ctx
,
3001 unsigned start_slot
,
3003 const struct pipe_viewport_state
*states
)
3005 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3007 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
3009 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
3011 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
3012 !ice
->state
.cso_rast
->depth_clip_far
))
3013 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
3017 * The pipe->set_framebuffer_state() driver hook.
3019 * Sets the current draw FBO, including color render targets, depth,
3020 * and stencil buffers.
3023 iris_set_framebuffer_state(struct pipe_context
*ctx
,
3024 const struct pipe_framebuffer_state
*state
)
3026 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3027 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3028 struct isl_device
*isl_dev
= &screen
->isl_dev
;
3029 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
3030 struct iris_resource
*zres
;
3031 struct iris_resource
*stencil_res
;
3033 unsigned samples
= util_framebuffer_get_num_samples(state
);
3034 unsigned layers
= util_framebuffer_get_num_layers(state
);
3036 if (cso
->samples
!= samples
) {
3037 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
3039 /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
3040 if (GEN_GEN
>= 9 && (cso
->samples
== 16 || samples
== 16))
3041 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_FS
;
3044 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
3045 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
3048 if ((cso
->layers
== 0) != (layers
== 0)) {
3049 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
3052 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
3053 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
3056 if (cso
->zsbuf
|| state
->zsbuf
) {
3057 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
3060 util_copy_framebuffer_state(cso
, state
);
3061 cso
->samples
= samples
;
3062 cso
->layers
= layers
;
3064 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
3066 struct isl_view view
= {
3069 .base_array_layer
= 0,
3071 .swizzle
= ISL_SWIZZLE_IDENTITY
,
3074 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
3077 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
3080 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
3081 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
3083 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
3086 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
3088 info
.depth_surf
= &zres
->surf
;
3089 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
3090 info
.mocs
= iris_mocs(zres
->bo
, isl_dev
);
3092 view
.format
= zres
->surf
.format
;
3094 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
3095 info
.hiz_usage
= zres
->aux
.usage
;
3096 info
.hiz_surf
= &zres
->aux
.surf
;
3097 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
+ zres
->aux
.offset
;
3102 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
3103 info
.stencil_aux_usage
= stencil_res
->aux
.usage
;
3104 info
.stencil_surf
= &stencil_res
->surf
;
3105 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
3107 view
.format
= stencil_res
->surf
.format
;
3108 info
.mocs
= iris_mocs(stencil_res
->bo
, isl_dev
);
3113 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
3115 /* Make a null surface for unbound buffers */
3116 void *null_surf_map
=
3117 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
3118 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
3119 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
3120 isl_extent3d(MAX2(cso
->width
, 1),
3121 MAX2(cso
->height
, 1),
3122 cso
->layers
? cso
->layers
: 1));
3123 ice
->state
.null_fb
.offset
+=
3124 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
3126 /* Render target change */
3127 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_BINDINGS_FS
;
3129 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
3131 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
3133 ice
->state
.stage_dirty
|=
3134 ice
->state
.stage_dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
3137 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
3141 * The pipe->set_constant_buffer() driver hook.
3143 * This uploads any constant data in user buffers, and references
3144 * any UBO resources containing constant data.
3147 iris_set_constant_buffer(struct pipe_context
*ctx
,
3148 enum pipe_shader_type p_stage
, unsigned index
,
3149 const struct pipe_constant_buffer
*input
)
3151 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3152 gl_shader_stage stage
= stage_from_pipe(p_stage
);
3153 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3154 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
3156 /* TODO: Only do this if the buffer changes? */
3157 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
3159 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
3160 shs
->bound_cbufs
|= 1u << index
;
3162 if (input
->user_buffer
) {
3164 pipe_resource_reference(&cbuf
->buffer
, NULL
);
3165 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
3166 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
3168 if (!cbuf
->buffer
) {
3169 /* Allocation was unsuccessful - just unbind */
3170 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
3175 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
3176 } else if (input
->buffer
) {
3177 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
3179 cbuf
->buffer_offset
= input
->buffer_offset
;
3183 MIN2(input
->buffer_size
,
3184 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
3186 struct iris_resource
*res
= (void *) cbuf
->buffer
;
3187 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
3188 res
->bind_stages
|= 1 << stage
;
3190 shs
->bound_cbufs
&= ~(1u << index
);
3191 pipe_resource_reference(&cbuf
->buffer
, NULL
);
3194 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_CONSTANTS_VS
<< stage
;
3198 upload_sysvals(struct iris_context
*ice
,
3199 gl_shader_stage stage
)
3201 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
3202 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3204 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3205 if (!shader
|| shader
->num_system_values
== 0)
3208 assert(shader
->num_cbufs
> 0);
3210 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
3211 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
3212 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
3213 uint32_t *map
= NULL
;
3215 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
3216 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
3217 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
3219 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
3220 uint32_t sysval
= shader
->system_values
[i
];
3223 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
3225 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
3226 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
3227 struct brw_image_param
*param
=
3228 &genx
->shaders
[stage
].image_param
[img
];
3230 assert(offset
< sizeof(struct brw_image_param
));
3231 value
= ((uint32_t *) param
)[offset
];
3233 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
3235 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
3236 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
3237 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
3238 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
3239 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
3240 if (stage
== MESA_SHADER_TESS_CTRL
) {
3241 value
= ice
->state
.vertices_per_patch
;
3243 assert(stage
== MESA_SHADER_TESS_EVAL
);
3244 const struct shader_info
*tcs_info
=
3245 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
3247 value
= tcs_info
->tess
.tcs_vertices_out
;
3249 value
= ice
->state
.vertices_per_patch
;
3251 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
3252 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
3253 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
3254 value
= fui(ice
->state
.default_outer_level
[i
]);
3255 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
3256 value
= fui(ice
->state
.default_inner_level
[0]);
3257 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
3258 value
= fui(ice
->state
.default_inner_level
[1]);
3259 } else if (sysval
>= BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
&&
3260 sysval
<= BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z
) {
3261 unsigned i
= sysval
- BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
;
3262 value
= ice
->state
.last_block
[i
];
3264 assert(!"unhandled system value");
3270 cbuf
->buffer_size
= upload_size
;
3271 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
3272 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
3274 shs
->sysvals_need_upload
= false;
3278 * The pipe->set_shader_buffers() driver hook.
3280 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
3281 * SURFACE_STATE here, as the buffer offset may change each time.
3284 iris_set_shader_buffers(struct pipe_context
*ctx
,
3285 enum pipe_shader_type p_stage
,
3286 unsigned start_slot
, unsigned count
,
3287 const struct pipe_shader_buffer
*buffers
,
3288 unsigned writable_bitmask
)
3290 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3291 gl_shader_stage stage
= stage_from_pipe(p_stage
);
3292 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3294 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
3296 shs
->bound_ssbos
&= ~modified_bits
;
3297 shs
->writable_ssbos
&= ~modified_bits
;
3298 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
3300 for (unsigned i
= 0; i
< count
; i
++) {
3301 if (buffers
&& buffers
[i
].buffer
) {
3302 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
3303 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
3304 struct iris_state_ref
*surf_state
=
3305 &shs
->ssbo_surf_state
[start_slot
+ i
];
3306 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
3307 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
3309 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
3311 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
3313 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
3315 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
3316 res
->bind_stages
|= 1 << stage
;
3318 util_range_add(&res
->base
, &res
->valid_buffer_range
, ssbo
->buffer_offset
,
3319 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
3321 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
3322 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
3327 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_BINDINGS_VS
<< stage
;
3331 iris_delete_state(struct pipe_context
*ctx
, void *state
)
3337 * The pipe->set_vertex_buffers() driver hook.
3339 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
3342 iris_set_vertex_buffers(struct pipe_context
*ctx
,
3343 unsigned start_slot
, unsigned count
,
3344 const struct pipe_vertex_buffer
*buffers
)
3346 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3347 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3348 struct iris_genx_state
*genx
= ice
->state
.genx
;
3350 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
3352 for (unsigned i
= 0; i
< count
; i
++) {
3353 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
3354 struct iris_vertex_buffer_state
*state
=
3355 &genx
->vertex_buffers
[start_slot
+ i
];
3358 pipe_resource_reference(&state
->resource
, NULL
);
3362 /* We may see user buffers that are NULL bindings. */
3363 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
3365 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
3366 struct iris_resource
*res
= (void *) state
->resource
;
3368 state
->offset
= (int) buffer
->buffer_offset
;
3371 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
3372 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
3375 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
3376 vb
.VertexBufferIndex
= start_slot
+ i
;
3377 vb
.AddressModifyEnable
= true;
3378 vb
.BufferPitch
= buffer
->stride
;
3380 vb
.BufferSize
= res
->base
.width0
- (int) buffer
->buffer_offset
;
3381 vb
.BufferStartingAddress
=
3382 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
3383 vb
.MOCS
= iris_mocs(res
->bo
, &screen
->isl_dev
);
3385 vb
.NullVertexBuffer
= true;
3390 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
3394 * Gallium CSO for vertex elements.
3396 struct iris_vertex_element_state
{
3397 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
3398 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
3399 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
3400 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
3405 * The pipe->create_vertex_elements() driver hook.
3407 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
3408 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
3409 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
3410 * needed. In these cases we will need information available at draw time.
3411 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
3412 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
3413 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
3416 iris_create_vertex_elements(struct pipe_context
*ctx
,
3418 const struct pipe_vertex_element
*state
)
3420 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3421 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3422 struct iris_vertex_element_state
*cso
=
3423 malloc(sizeof(struct iris_vertex_element_state
));
3427 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
3429 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
3432 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
3433 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
3436 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3438 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
3439 ve
.Component0Control
= VFCOMP_STORE_0
;
3440 ve
.Component1Control
= VFCOMP_STORE_0
;
3441 ve
.Component2Control
= VFCOMP_STORE_0
;
3442 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
3445 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3449 for (int i
= 0; i
< count
; i
++) {
3450 const struct iris_format_info fmt
=
3451 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
3452 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
3453 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
3455 switch (isl_format_get_num_channels(fmt
.fmt
)) {
3456 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
3457 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
3458 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
3460 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
3461 : VFCOMP_STORE_1_FP
;
3464 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3465 ve
.EdgeFlagEnable
= false;
3466 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
3468 ve
.SourceElementOffset
= state
[i
].src_offset
;
3469 ve
.SourceElementFormat
= fmt
.fmt
;
3470 ve
.Component0Control
= comp
[0];
3471 ve
.Component1Control
= comp
[1];
3472 ve
.Component2Control
= comp
[2];
3473 ve
.Component3Control
= comp
[3];
3476 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3477 vi
.VertexElementIndex
= i
;
3478 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
3479 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
3482 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
3483 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
3486 /* An alternative version of the last VE and VFI is stored so it
3487 * can be used at draw time in case Vertex Shader uses EdgeFlag
3490 const unsigned edgeflag_index
= count
- 1;
3491 const struct iris_format_info fmt
=
3492 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
3493 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
3494 ve
.EdgeFlagEnable
= true ;
3495 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
3497 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
3498 ve
.SourceElementFormat
= fmt
.fmt
;
3499 ve
.Component0Control
= VFCOMP_STORE_SRC
;
3500 ve
.Component1Control
= VFCOMP_STORE_0
;
3501 ve
.Component2Control
= VFCOMP_STORE_0
;
3502 ve
.Component3Control
= VFCOMP_STORE_0
;
3504 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
3505 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
3506 * at draw time, as it should change if SGVs are emitted.
3508 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
3509 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
3517 * The pipe->bind_vertex_elements_state() driver hook.
3520 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
3522 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3523 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
3524 struct iris_vertex_element_state
*new_cso
= state
;
3526 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
3527 * we need to re-emit it to ensure we're overriding the right one.
3529 if (new_cso
&& cso_changed(count
))
3530 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
3532 ice
->state
.cso_vertex_elements
= state
;
3533 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
3537 * The pipe->create_stream_output_target() driver hook.
3539 * "Target" here refers to a destination buffer. We translate this into
3540 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
3541 * know which buffer this represents, or whether we ought to zero the
3542 * write-offsets, or append. Those are handled in the set() hook.
3544 static struct pipe_stream_output_target
*
3545 iris_create_stream_output_target(struct pipe_context
*ctx
,
3546 struct pipe_resource
*p_res
,
3547 unsigned buffer_offset
,
3548 unsigned buffer_size
)
3550 struct iris_resource
*res
= (void *) p_res
;
3551 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
3555 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
3557 pipe_reference_init(&cso
->base
.reference
, 1);
3558 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
3559 cso
->base
.buffer_offset
= buffer_offset
;
3560 cso
->base
.buffer_size
= buffer_size
;
3561 cso
->base
.context
= ctx
;
3563 util_range_add(&res
->base
, &res
->valid_buffer_range
, buffer_offset
,
3564 buffer_offset
+ buffer_size
);
3566 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
3572 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
3573 struct pipe_stream_output_target
*state
)
3575 struct iris_stream_output_target
*cso
= (void *) state
;
3577 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
3578 pipe_resource_reference(&cso
->offset
.res
, NULL
);
3584 * The pipe->set_stream_output_targets() driver hook.
3586 * At this point, we know which targets are bound to a particular index,
3587 * and also whether we want to append or start over. We can finish the
3588 * 3DSTATE_SO_BUFFER packets we started earlier.
3591 iris_set_stream_output_targets(struct pipe_context
*ctx
,
3592 unsigned num_targets
,
3593 struct pipe_stream_output_target
**targets
,
3594 const unsigned *offsets
)
3596 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3597 struct iris_genx_state
*genx
= ice
->state
.genx
;
3598 uint32_t *so_buffers
= genx
->so_buffers
;
3599 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
3601 const bool active
= num_targets
> 0;
3602 if (ice
->state
.streamout_active
!= active
) {
3603 ice
->state
.streamout_active
= active
;
3604 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
3606 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
3607 * it's a non-pipelined command. If we're switching streamout on, we
3608 * may have missed emitting it earlier, so do so now. (We're already
3609 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
3612 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
3615 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3616 struct iris_stream_output_target
*tgt
=
3617 (void *) ice
->state
.so_target
[i
];
3619 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3621 flush
|= iris_flush_bits_for_history(res
);
3622 iris_dirty_for_history(ice
, res
);
3625 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
3626 "make streamout results visible", flush
);
3630 for (int i
= 0; i
< 4; i
++) {
3631 pipe_so_target_reference(&ice
->state
.so_target
[i
],
3632 i
< num_targets
? targets
[i
] : NULL
);
3635 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
3639 for (unsigned i
= 0; i
< 4; i
++,
3640 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
3642 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
3643 unsigned offset
= offsets
[i
];
3646 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3648 sob
.SOBufferIndex
= i
;
3650 sob
._3DCommandOpcode
= 0;
3651 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ i
;
3657 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3659 /* Note that offsets[i] will either be 0, causing us to zero
3660 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3661 * "continue appending at the existing offset."
3663 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3665 /* We might be called by Begin (offset = 0), Pause, then Resume
3666 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3667 * will actually be sent to the GPU). In this case, we don't want
3668 * to append - we still want to do our initial zeroing.
3673 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3675 sob
.SOBufferIndex
= i
;
3677 sob
._3DCommandOpcode
= 0;
3678 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ i
;
3680 sob
.SurfaceBaseAddress
=
3681 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
,
3682 IRIS_DOMAIN_OTHER_WRITE
);
3683 sob
.SOBufferEnable
= true;
3684 sob
.StreamOffsetWriteEnable
= true;
3685 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3686 sob
.MOCS
= iris_mocs(res
->bo
, &screen
->isl_dev
);
3688 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3689 sob
.StreamOffset
= offset
;
3690 sob
.StreamOutputBufferOffsetAddress
=
3691 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3692 tgt
->offset
.offset
, IRIS_DOMAIN_OTHER_WRITE
);
3696 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3700 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3701 * 3DSTATE_STREAMOUT packets.
3703 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3704 * hardware to record. We can create it entirely based on the shader, with
3705 * no dynamic state dependencies.
3707 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3708 * state-based settings. We capture the shader-related ones here, and merge
3709 * the rest in at draw time.
3712 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3713 const struct brw_vue_map
*vue_map
)
3715 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3716 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3717 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3718 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3720 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3722 memset(so_decl
, 0, sizeof(so_decl
));
3724 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3725 * command feels strange -- each dword pair contains a SO_DECL per stream.
3727 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3728 const struct pipe_stream_output
*output
= &info
->output
[i
];
3729 const int buffer
= output
->output_buffer
;
3730 const int varying
= output
->register_index
;
3731 const unsigned stream_id
= output
->stream
;
3732 assert(stream_id
< MAX_VERTEX_STREAMS
);
3734 buffer_mask
[stream_id
] |= 1 << buffer
;
3736 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3738 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3739 * array. Instead, it simply increments DstOffset for the following
3740 * input by the number of components that should be skipped.
3742 * Our hardware is unusual in that it requires us to program SO_DECLs
3743 * for fake "hole" components, rather than simply taking the offset
3744 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3745 * program as many size = 4 holes as we can, then a final hole to
3746 * accommodate the final 1, 2, or 3 remaining.
3748 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3750 while (skip_components
> 0) {
3751 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3753 .OutputBufferSlot
= output
->output_buffer
,
3754 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3756 skip_components
-= 4;
3759 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3761 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3762 .OutputBufferSlot
= output
->output_buffer
,
3763 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3765 ((1 << output
->num_components
) - 1) << output
->start_component
,
3768 if (decls
[stream_id
] > max_decls
)
3769 max_decls
= decls
[stream_id
];
3772 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3773 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3774 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3776 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3777 int urb_entry_read_offset
= 0;
3778 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3779 urb_entry_read_offset
;
3781 /* We always read the whole vertex. This could be reduced at some
3782 * point by reading less and offsetting the register index in the
3785 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3786 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3787 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3788 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3789 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3790 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3791 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3792 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3794 /* Set buffer pitches; 0 means unbound. */
3795 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3796 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3797 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3798 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3801 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3802 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3803 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3804 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3805 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3806 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3807 list
.NumEntries0
= decls
[0];
3808 list
.NumEntries1
= decls
[1];
3809 list
.NumEntries2
= decls
[2];
3810 list
.NumEntries3
= decls
[3];
3813 for (int i
= 0; i
< max_decls
; i
++) {
3814 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3815 entry
.Stream0Decl
= so_decl
[0][i
];
3816 entry
.Stream1Decl
= so_decl
[1][i
];
3817 entry
.Stream2Decl
= so_decl
[2][i
];
3818 entry
.Stream3Decl
= so_decl
[3][i
];
3826 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3827 const struct brw_vue_map
*last_vue_map
,
3828 bool two_sided_color
,
3829 unsigned *out_offset
,
3830 unsigned *out_length
)
3832 /* The compiler computes the first URB slot without considering COL/BFC
3833 * swizzling (because it doesn't know whether it's enabled), so we need
3834 * to do that here too. This may result in a smaller offset, which
3837 const unsigned first_slot
=
3838 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3840 /* This becomes the URB read offset (counted in pairs of slots). */
3841 assert(first_slot
% 2 == 0);
3842 *out_offset
= first_slot
/ 2;
3844 /* We need to adjust the inputs read to account for front/back color
3845 * swizzling, as it can make the URB length longer.
3847 for (int c
= 0; c
<= 1; c
++) {
3848 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3849 /* If two sided color is enabled, the fragment shader's gl_Color
3850 * (COL0) input comes from either the gl_FrontColor (COL0) or
3851 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3853 if (two_sided_color
)
3854 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3856 /* If front color isn't written, we opt to give them back color
3857 * instead of an undefined value. Switch from COL to BFC.
3859 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3860 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3861 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3866 /* Compute the minimum URB Read Length necessary for the FS inputs.
3868 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3869 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3871 * "This field should be set to the minimum length required to read the
3872 * maximum source attribute. The maximum source attribute is indicated
3873 * by the maximum value of the enabled Attribute # Source Attribute if
3874 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3875 * enable is not set.
3876 * read_length = ceiling((max_source_attr + 1) / 2)
3878 * [errata] Corruption/Hang possible if length programmed larger than
3881 * Similar text exists for Ivy Bridge.
3883 * We find the last URB slot that's actually read by the FS.
3885 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3886 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3887 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3890 /* The URB read length is the difference of the two, counted in pairs. */
3891 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3895 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3896 const struct iris_context
*ice
,
3897 unsigned urb_read_offset
,
3898 unsigned sprite_coord_enables
)
3900 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3901 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3902 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3903 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3904 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3906 /* XXX: this should be generated when putting programs in place */
3908 for (uint8_t idx
= 0; idx
< wm_prog_data
->urb_setup_attribs_count
; idx
++) {
3909 const uint8_t fs_attr
= wm_prog_data
->urb_setup_attribs
[idx
];
3910 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3911 if (input_index
< 0 || input_index
>= 16)
3914 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3915 &attr_overrides
[input_index
];
3916 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3918 /* Viewport and Layer are stored in the VUE header. We need to override
3919 * them to zero if earlier stages didn't write them, as GL requires that
3920 * they read back as zero when not explicitly set.
3923 case VARYING_SLOT_VIEWPORT
:
3924 case VARYING_SLOT_LAYER
:
3925 attr
->ComponentOverrideX
= true;
3926 attr
->ComponentOverrideW
= true;
3927 attr
->ConstantSource
= CONST_0000
;
3929 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3930 attr
->ComponentOverrideY
= true;
3931 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3932 attr
->ComponentOverrideZ
= true;
3935 case VARYING_SLOT_PRIMITIVE_ID
:
3936 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3938 attr
->ComponentOverrideX
= true;
3939 attr
->ComponentOverrideY
= true;
3940 attr
->ComponentOverrideZ
= true;
3941 attr
->ComponentOverrideW
= true;
3942 attr
->ConstantSource
= PRIM_ID
;
3950 if (sprite_coord_enables
& (1 << input_index
))
3953 /* If there was only a back color written but not front, use back
3954 * as the color instead of undefined.
3956 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3957 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3958 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3959 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3961 /* Not written by the previous stage - undefined. */
3963 attr
->ComponentOverrideX
= true;
3964 attr
->ComponentOverrideY
= true;
3965 attr
->ComponentOverrideZ
= true;
3966 attr
->ComponentOverrideW
= true;
3967 attr
->ConstantSource
= CONST_0001_FLOAT
;
3971 /* Compute the location of the attribute relative to the read offset,
3972 * which is counted in 256-bit increments (two 128-bit VUE slots).
3974 const int source_attr
= slot
- 2 * urb_read_offset
;
3975 assert(source_attr
>= 0 && source_attr
<= 32);
3976 attr
->SourceAttribute
= source_attr
;
3978 /* If we are doing two-sided color, and the VUE slot following this one
3979 * represents a back-facing color, then we need to instruct the SF unit
3980 * to do back-facing swizzling.
3982 if (cso_rast
->light_twoside
&&
3983 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3984 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3985 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3986 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3987 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3990 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3991 for (int i
= 0; i
< 16; i
++)
3992 sbes
.Attribute
[i
] = attr_overrides
[i
];
3997 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3998 const struct iris_rasterizer_state
*cso
)
4000 unsigned overrides
= 0;
4002 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
4003 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
4005 for (int i
= 0; i
< 8; i
++) {
4006 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
4007 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
4008 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
4015 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
4017 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4018 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
4019 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4020 const struct shader_info
*fs_info
=
4021 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
4023 unsigned urb_read_offset
, urb_read_length
;
4024 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
4025 ice
->shaders
.last_vue_map
,
4026 cso_rast
->light_twoside
,
4027 &urb_read_offset
, &urb_read_length
);
4029 unsigned sprite_coord_overrides
=
4030 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
4032 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
4033 sbe
.AttributeSwizzleEnable
= true;
4034 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
4035 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
4036 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
4037 sbe
.VertexURBEntryReadLength
= urb_read_length
;
4038 sbe
.ForceVertexURBEntryReadOffset
= true;
4039 sbe
.ForceVertexURBEntryReadLength
= true;
4040 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
4041 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
4043 for (int i
= 0; i
< 32; i
++) {
4044 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
4049 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
4052 /* ------------------------------------------------------------------- */
4055 * Populate VS program key fields based on the current state.
4058 iris_populate_vs_key(const struct iris_context
*ice
,
4059 const struct shader_info
*info
,
4060 gl_shader_stage last_stage
,
4061 struct iris_vs_prog_key
*key
)
4063 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4065 if (info
->clip_distance_array_size
== 0 &&
4066 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4067 last_stage
== MESA_SHADER_VERTEX
)
4068 key
->vue
.nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4072 * Populate TCS program key fields based on the current state.
4075 iris_populate_tcs_key(const struct iris_context
*ice
,
4076 struct iris_tcs_prog_key
*key
)
4081 * Populate TES program key fields based on the current state.
4084 iris_populate_tes_key(const struct iris_context
*ice
,
4085 const struct shader_info
*info
,
4086 gl_shader_stage last_stage
,
4087 struct iris_tes_prog_key
*key
)
4089 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4091 if (info
->clip_distance_array_size
== 0 &&
4092 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4093 last_stage
== MESA_SHADER_TESS_EVAL
)
4094 key
->vue
.nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4098 * Populate GS program key fields based on the current state.
4101 iris_populate_gs_key(const struct iris_context
*ice
,
4102 const struct shader_info
*info
,
4103 gl_shader_stage last_stage
,
4104 struct iris_gs_prog_key
*key
)
4106 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4108 if (info
->clip_distance_array_size
== 0 &&
4109 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
4110 last_stage
== MESA_SHADER_GEOMETRY
)
4111 key
->vue
.nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
4115 * Populate FS program key fields based on the current state.
4118 iris_populate_fs_key(const struct iris_context
*ice
,
4119 const struct shader_info
*info
,
4120 struct iris_fs_prog_key
*key
)
4122 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
4123 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
4124 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
4125 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
4126 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
4128 key
->nr_color_regions
= fb
->nr_cbufs
;
4130 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
4132 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
4134 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
4136 key
->flat_shade
= rast
->flatshade
&&
4137 (info
->inputs_read
& (VARYING_BIT_COL0
| VARYING_BIT_COL1
));
4139 key
->persample_interp
= rast
->force_persample_interp
;
4140 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
4142 key
->coherent_fb_fetch
= GEN_GEN
>= 9;
4144 key
->force_dual_color_blend
=
4145 screen
->driconf
.dual_color_blend_by_location
&&
4146 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
4148 /* TODO: Respect glHint for key->high_quality_derivatives */
4152 iris_populate_cs_key(const struct iris_context
*ice
,
4153 struct iris_cs_prog_key
*key
)
4158 KSP(const struct iris_compiled_shader
*shader
)
4160 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
4161 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
4164 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
4165 pkt.KernelStartPointer = KSP(shader); \
4166 pkt.BindingTableEntryCount = shader->bt.size_bytes / 4; \
4167 pkt.FloatingPointMode = prog_data->use_alt_mode; \
4169 pkt.DispatchGRFStartRegisterForURBData = \
4170 prog_data->dispatch_grf_start_reg; \
4171 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
4172 pkt.prefix##URBEntryReadOffset = 0; \
4174 pkt.StatisticsEnable = true; \
4175 pkt.Enable = true; \
4177 if (prog_data->total_scratch) { \
4178 struct iris_bo *bo = \
4179 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
4180 uint32_t scratch_addr = bo->gtt_offset; \
4181 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
4182 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr, \
4183 IRIS_DOMAIN_NONE); \
4187 * Encode most of 3DSTATE_VS based on the compiled shader.
4190 iris_store_vs_state(struct iris_context
*ice
,
4191 const struct gen_device_info
*devinfo
,
4192 struct iris_compiled_shader
*shader
)
4194 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4195 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4197 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
4198 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
4199 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
4200 vs
.SIMD8DispatchEnable
= true;
4201 vs
.UserClipDistanceCullTestEnableBitmask
=
4202 vue_prog_data
->cull_distance_mask
;
4207 * Encode most of 3DSTATE_HS based on the compiled shader.
4210 iris_store_tcs_state(struct iris_context
*ice
,
4211 const struct gen_device_info
*devinfo
,
4212 struct iris_compiled_shader
*shader
)
4214 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4215 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4216 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
4218 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
4219 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
4222 /* GEN:BUG:1604578095:
4224 * Hang occurs when the number of max threads is less than 2 times
4225 * the number of instance count. The number of max threads must be
4226 * more than 2 times the number of instance count.
4228 assert((devinfo
->max_tcs_threads
/ 2) > tcs_prog_data
->instances
);
4229 hs
.DispatchGRFStartRegisterForURBData
= prog_data
->dispatch_grf_start_reg
& 0x1f;
4230 hs
.DispatchGRFStartRegisterForURBData5
= prog_data
->dispatch_grf_start_reg
>> 5;
4233 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
4234 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
4235 hs
.IncludeVertexHandles
= true;
4238 /* Patch Count threshold specifies the maximum number of patches that
4239 * will be accumulated before a thread dispatch is forced.
4241 hs
.PatchCountThreshold
= tcs_prog_data
->patch_count_threshold
;
4245 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
4246 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
4252 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
4255 iris_store_tes_state(struct iris_context
*ice
,
4256 const struct gen_device_info
*devinfo
,
4257 struct iris_compiled_shader
*shader
)
4259 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4260 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4261 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
4263 uint32_t *te_state
= (void *) shader
->derived_data
;
4264 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
4266 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
4267 te
.Partitioning
= tes_prog_data
->partitioning
;
4268 te
.OutputTopology
= tes_prog_data
->output_topology
;
4269 te
.TEDomain
= tes_prog_data
->domain
;
4271 te
.MaximumTessellationFactorOdd
= 63.0;
4272 te
.MaximumTessellationFactorNotOdd
= 64.0;
4275 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
4276 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
4278 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
4279 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
4280 ds
.ComputeWCoordinateEnable
=
4281 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
4283 ds
.UserClipDistanceCullTestEnableBitmask
=
4284 vue_prog_data
->cull_distance_mask
;
4290 * Encode most of 3DSTATE_GS based on the compiled shader.
4293 iris_store_gs_state(struct iris_context
*ice
,
4294 const struct gen_device_info
*devinfo
,
4295 struct iris_compiled_shader
*shader
)
4297 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4298 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
4299 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
4301 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
4302 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
4304 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
4305 gs
.OutputTopology
= gs_prog_data
->output_topology
;
4306 gs
.ControlDataHeaderSize
=
4307 gs_prog_data
->control_data_header_size_hwords
;
4308 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
4309 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
4310 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
4311 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
4312 gs
.ReorderMode
= TRAILING
;
4313 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
4314 gs
.MaximumNumberofThreads
=
4315 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
4316 : (devinfo
->max_gs_threads
- 1);
4318 if (gs_prog_data
->static_vertex_count
!= -1) {
4319 gs
.StaticOutput
= true;
4320 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
4322 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
4324 gs
.UserClipDistanceCullTestEnableBitmask
=
4325 vue_prog_data
->cull_distance_mask
;
4327 const int urb_entry_write_offset
= 1;
4328 const uint32_t urb_entry_output_length
=
4329 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
4330 urb_entry_write_offset
;
4332 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
4333 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
4338 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
4341 iris_store_fs_state(struct iris_context
*ice
,
4342 const struct gen_device_info
*devinfo
,
4343 struct iris_compiled_shader
*shader
)
4345 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4346 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
4348 uint32_t *ps_state
= (void *) shader
->derived_data
;
4349 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
4351 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
4352 ps
.VectorMaskEnable
= true;
4353 ps
.BindingTableEntryCount
= shader
->bt
.size_bytes
/ 4;
4354 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
4355 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
4357 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
4359 /* From the documentation for this packet:
4360 * "If the PS kernel does not need the Position XY Offsets to
4361 * compute a Position Value, then this field should be programmed
4362 * to POSOFFSET_NONE."
4364 * "SW Recommendation: If the PS kernel needs the Position Offsets
4365 * to compute a Position XY value, this field should match Position
4366 * ZW Interpolation Mode to ensure a consistent position.xyzw
4369 * We only require XY sample offsets. So, this recommendation doesn't
4370 * look useful at the moment. We might need this in future.
4372 ps
.PositionXYOffsetSelect
=
4373 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
4375 if (prog_data
->total_scratch
) {
4376 struct iris_bo
*bo
=
4377 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4378 MESA_SHADER_FRAGMENT
);
4379 uint32_t scratch_addr
= bo
->gtt_offset
;
4380 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4381 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
,
4386 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
4387 psx
.PixelShaderValid
= true;
4388 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
4389 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
4390 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
4391 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
4392 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
4393 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
4394 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
4397 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
4398 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
4404 * Compute the size of the derived data (shader command packets).
4406 * This must match the data written by the iris_store_xs_state() functions.
4409 iris_store_cs_state(struct iris_context
*ice
,
4410 const struct gen_device_info
*devinfo
,
4411 struct iris_compiled_shader
*shader
)
4413 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4414 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
4415 void *map
= shader
->derived_data
;
4417 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
4418 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
4419 desc
.SharedLocalMemorySize
=
4420 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
4421 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
4422 desc
.CrossThreadConstantDataReadLength
=
4423 cs_prog_data
->push
.cross_thread
.regs
;
4425 /* TODO: Check if we are missing workarounds and enable mid-thread
4428 * We still have issues with mid-thread preemption (it was already
4429 * disabled by the kernel on gen11, due to missing workarounds). It's
4430 * possible that we are just missing some workarounds, and could enable
4431 * it later, but for now let's disable it to fix a GPU in compute in Car
4432 * Chase (and possibly more).
4434 desc
.ThreadPreemptionDisable
= true;
4440 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
4442 assert(cache_id
<= IRIS_CACHE_BLORP
);
4444 static const unsigned dwords
[] = {
4445 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
4446 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
4447 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
4448 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
4450 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
4451 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4452 [IRIS_CACHE_BLORP
] = 0,
4455 return sizeof(uint32_t) * dwords
[cache_id
];
4459 * Create any state packets corresponding to the given shader stage
4460 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
4461 * This means that we can look up a program in the in-memory cache and
4462 * get most of the state packet without having to reconstruct it.
4465 iris_store_derived_program_state(struct iris_context
*ice
,
4466 enum iris_program_cache_id cache_id
,
4467 struct iris_compiled_shader
*shader
)
4469 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
4470 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4474 iris_store_vs_state(ice
, devinfo
, shader
);
4476 case IRIS_CACHE_TCS
:
4477 iris_store_tcs_state(ice
, devinfo
, shader
);
4479 case IRIS_CACHE_TES
:
4480 iris_store_tes_state(ice
, devinfo
, shader
);
4483 iris_store_gs_state(ice
, devinfo
, shader
);
4486 iris_store_fs_state(ice
, devinfo
, shader
);
4489 iris_store_cs_state(ice
, devinfo
, shader
);
4490 case IRIS_CACHE_BLORP
:
4497 /* ------------------------------------------------------------------- */
4499 static const uint32_t push_constant_opcodes
[] = {
4500 [MESA_SHADER_VERTEX
] = 21,
4501 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
4502 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
4503 [MESA_SHADER_GEOMETRY
] = 22,
4504 [MESA_SHADER_FRAGMENT
] = 23,
4505 [MESA_SHADER_COMPUTE
] = 0,
4509 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4511 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
4513 iris_use_pinned_bo(batch
, state_bo
, false, IRIS_DOMAIN_NONE
);
4515 return ice
->state
.unbound_tex
.offset
;
4519 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4521 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
4522 if (!ice
->state
.null_fb
.res
)
4523 return use_null_surface(batch
, ice
);
4525 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
4527 iris_use_pinned_bo(batch
, state_bo
, false, IRIS_DOMAIN_NONE
);
4529 return ice
->state
.null_fb
.offset
;
4533 surf_state_offset_for_aux(struct iris_resource
*res
,
4535 enum isl_aux_usage aux_usage
)
4537 assert(aux_modes
& (1 << aux_usage
));
4538 return SURFACE_STATE_ALIGNMENT
*
4539 util_bitcount(aux_modes
& ((1 << aux_usage
) - 1));
4544 surf_state_update_clear_value(struct iris_batch
*batch
,
4545 struct iris_resource
*res
,
4546 struct iris_state_ref
*state
,
4548 enum isl_aux_usage aux_usage
)
4550 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4551 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
4552 uint64_t real_offset
= state
->offset
+ IRIS_MEMZONE_BINDER_START
;
4553 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
4554 uint32_t clear_offset
= offset_into_bo
+
4555 isl_dev
->ss
.clear_value_offset
+
4556 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
4557 uint32_t *color
= res
->aux
.clear_color
.u32
;
4559 assert(isl_dev
->ss
.clear_value_size
== 16);
4561 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
4562 iris_emit_pipe_control_write(batch
, "update fast clear value (Z)",
4563 PIPE_CONTROL_WRITE_IMMEDIATE
,
4564 state_bo
, clear_offset
, color
[0]);
4566 iris_emit_pipe_control_write(batch
, "update fast clear color (RG__)",
4567 PIPE_CONTROL_WRITE_IMMEDIATE
,
4568 state_bo
, clear_offset
,
4569 (uint64_t) color
[0] |
4570 (uint64_t) color
[1] << 32);
4571 iris_emit_pipe_control_write(batch
, "update fast clear color (__BA)",
4572 PIPE_CONTROL_WRITE_IMMEDIATE
,
4573 state_bo
, clear_offset
+ 8,
4574 (uint64_t) color
[2] |
4575 (uint64_t) color
[3] << 32);
4578 iris_emit_pipe_control_flush(batch
,
4579 "update fast clear: state cache invalidate",
4580 PIPE_CONTROL_FLUSH_ENABLE
|
4581 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
4586 update_clear_value(struct iris_context
*ice
,
4587 struct iris_batch
*batch
,
4588 struct iris_resource
*res
,
4589 struct iris_surface_state
*surf_state
,
4590 unsigned all_aux_modes
,
4591 struct isl_view
*view
)
4593 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4594 UNUSED
unsigned aux_modes
= all_aux_modes
;
4596 /* We only need to update the clear color in the surface state for gen8 and
4597 * gen9. Newer gens can read it directly from the clear color state buffer.
4600 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
4601 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
4604 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4606 surf_state_update_clear_value(batch
, res
, &surf_state
->ref
,
4607 all_aux_modes
, aux_usage
);
4610 /* TODO: Could update rather than re-filling */
4611 alloc_surface_states(surf_state
, all_aux_modes
);
4613 void *map
= surf_state
->cpu
;
4616 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4617 fill_surface_state(isl_dev
, map
, res
, &res
->surf
, view
, aux_usage
,
4619 map
+= SURFACE_STATE_ALIGNMENT
;
4622 upload_surface_states(ice
->state
.surface_uploader
, surf_state
);
4627 * Add a surface to the validation list, as well as the buffer containing
4628 * the corresponding SURFACE_STATE.
4630 * Returns the binding table entry (offset to SURFACE_STATE).
4633 use_surface(struct iris_context
*ice
,
4634 struct iris_batch
*batch
,
4635 struct pipe_surface
*p_surf
,
4637 enum isl_aux_usage aux_usage
,
4638 bool is_read_surface
,
4639 enum iris_domain access
)
4641 struct iris_surface
*surf
= (void *) p_surf
;
4642 struct iris_resource
*res
= (void *) p_surf
->texture
;
4643 uint32_t offset
= 0;
4645 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
),
4647 if (GEN_GEN
== 8 && is_read_surface
) {
4648 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state_read
.ref
.res
), false,
4651 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.ref
.res
), false,
4656 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
, access
);
4657 if (res
->aux
.clear_color_bo
)
4658 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false, access
);
4660 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
4661 sizeof(surf
->clear_color
)) != 0) {
4662 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
4663 res
->aux
.possible_usages
, &surf
->view
);
4665 update_clear_value(ice
, batch
, res
, &surf
->surface_state_read
,
4666 res
->aux
.possible_usages
, &surf
->read_view
);
4668 surf
->clear_color
= res
->aux
.clear_color
;
4672 offset
= (GEN_GEN
== 8 && is_read_surface
)
4673 ? surf
->surface_state_read
.ref
.offset
4674 : surf
->surface_state
.ref
.offset
;
4677 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4681 use_sampler_view(struct iris_context
*ice
,
4682 struct iris_batch
*batch
,
4683 struct iris_sampler_view
*isv
)
4685 enum isl_aux_usage aux_usage
=
4686 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
);
4688 iris_use_pinned_bo(batch
, isv
->res
->bo
, false, IRIS_DOMAIN_OTHER_READ
);
4689 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.ref
.res
), false,
4692 if (isv
->res
->aux
.bo
) {
4693 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
,
4694 false, IRIS_DOMAIN_OTHER_READ
);
4695 if (isv
->res
->aux
.clear_color_bo
)
4696 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
,
4697 false, IRIS_DOMAIN_OTHER_READ
);
4698 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
4699 sizeof(isv
->clear_color
)) != 0) {
4700 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
4701 isv
->res
->aux
.sampler_usages
, &isv
->view
);
4702 isv
->clear_color
= isv
->res
->aux
.clear_color
;
4706 return isv
->surface_state
.ref
.offset
+
4707 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
4712 use_ubo_ssbo(struct iris_batch
*batch
,
4713 struct iris_context
*ice
,
4714 struct pipe_shader_buffer
*buf
,
4715 struct iris_state_ref
*surf_state
,
4716 bool writable
, enum iris_domain access
)
4718 if (!buf
->buffer
|| !surf_state
->res
)
4719 return use_null_surface(batch
, ice
);
4721 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
, access
);
4722 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false,
4725 return surf_state
->offset
;
4729 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4730 struct iris_shader_state
*shs
, const struct shader_info
*info
,
4733 struct iris_image_view
*iv
= &shs
->image
[i
];
4734 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4737 return use_null_surface(batch
, ice
);
4739 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4741 iris_use_pinned_bo(batch
, res
->bo
, write
, IRIS_DOMAIN_NONE
);
4742 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.ref
.res
),
4743 false, IRIS_DOMAIN_NONE
);
4746 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
, IRIS_DOMAIN_NONE
);
4748 enum isl_aux_usage aux_usage
=
4749 iris_image_view_aux_usage(ice
, &iv
->base
, info
);
4751 return iv
->surface_state
.ref
.offset
+
4752 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4755 #define push_bt_entry(addr) \
4756 assert(addr >= binder_addr); \
4757 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4758 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4760 #define bt_assert(section) \
4761 if (!pin_only && shader->bt.used_mask[section] != 0) \
4762 assert(shader->bt.offsets[section] == s);
4765 * Populate the binding table for a given shader stage.
4767 * This fills out the table of pointers to surfaces required by the shader,
4768 * and also adds those buffers to the validation list so the kernel can make
4769 * resident before running our batch.
4772 iris_populate_binding_table(struct iris_context
*ice
,
4773 struct iris_batch
*batch
,
4774 gl_shader_stage stage
,
4777 const struct iris_binder
*binder
= &ice
->state
.binder
;
4778 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4779 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4783 struct iris_binding_table
*bt
= &shader
->bt
;
4784 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4785 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4786 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4788 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4791 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4793 /* TCS passthrough doesn't need a binding table. */
4794 assert(stage
== MESA_SHADER_TESS_CTRL
);
4798 if (stage
== MESA_SHADER_COMPUTE
&&
4799 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4800 /* surface for gl_NumWorkGroups */
4801 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4802 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4803 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false,
4804 IRIS_DOMAIN_OTHER_READ
);
4805 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false,
4807 push_bt_entry(grid_state
->offset
);
4810 if (stage
== MESA_SHADER_FRAGMENT
) {
4811 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4812 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4813 if (cso_fb
->nr_cbufs
) {
4814 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4816 if (cso_fb
->cbufs
[i
]) {
4817 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4818 ice
->state
.draw_aux_usage
[i
], false,
4819 IRIS_DOMAIN_RENDER_WRITE
);
4821 addr
= use_null_fb_surface(batch
, ice
);
4823 push_bt_entry(addr
);
4825 } else if (GEN_GEN
< 11) {
4826 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4827 push_bt_entry(addr
);
4831 #define foreach_surface_used(index, group) \
4833 for (int index = 0; index < bt->sizes[group]; index++) \
4834 if (iris_group_index_to_bti(bt, group, index) != \
4835 IRIS_SURFACE_NOT_USED)
4837 foreach_surface_used(i
, IRIS_SURFACE_GROUP_RENDER_TARGET_READ
) {
4838 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4840 if (cso_fb
->cbufs
[i
]) {
4841 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
],
4842 false, ice
->state
.draw_aux_usage
[i
], true,
4843 IRIS_DOMAIN_OTHER_READ
);
4844 push_bt_entry(addr
);
4848 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4849 struct iris_sampler_view
*view
= shs
->textures
[i
];
4850 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4851 : use_null_surface(batch
, ice
);
4852 push_bt_entry(addr
);
4855 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4856 uint32_t addr
= use_image(batch
, ice
, shs
, info
, i
);
4857 push_bt_entry(addr
);
4860 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4863 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4864 if (ish
->const_data
) {
4865 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false,
4866 IRIS_DOMAIN_OTHER_READ
);
4867 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4868 false, IRIS_DOMAIN_NONE
);
4869 addr
= ish
->const_data_state
.offset
;
4871 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4872 addr
= use_null_surface(batch
, ice
);
4875 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4876 &shs
->constbuf_surf_state
[i
], false,
4877 IRIS_DOMAIN_OTHER_READ
);
4880 push_bt_entry(addr
);
4883 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4885 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4886 shs
->writable_ssbos
& (1u << i
), IRIS_DOMAIN_NONE
);
4887 push_bt_entry(addr
);
4891 /* XXX: YUV surfaces not implemented yet */
4892 bt_assert(plane_start
[1], ...);
4893 bt_assert(plane_start
[2], ...);
4898 iris_use_optional_res(struct iris_batch
*batch
,
4899 struct pipe_resource
*res
,
4901 enum iris_domain access
)
4904 struct iris_bo
*bo
= iris_resource_bo(res
);
4905 iris_use_pinned_bo(batch
, bo
, writeable
, access
);
4910 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4911 struct pipe_surface
*zsbuf
,
4912 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4917 struct iris_resource
*zres
, *sres
;
4918 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4921 const enum iris_domain access
= cso_zsa
->depth_writes_enabled
?
4922 IRIS_DOMAIN_DEPTH_WRITE
: IRIS_DOMAIN_OTHER_READ
;
4923 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
,
4926 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4927 cso_zsa
->depth_writes_enabled
, access
);
4932 const enum iris_domain access
= cso_zsa
->stencil_writes_enabled
?
4933 IRIS_DOMAIN_DEPTH_WRITE
: IRIS_DOMAIN_OTHER_READ
;
4934 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
,
4939 /* ------------------------------------------------------------------- */
4942 * Pin any BOs which were installed by a previous batch, and restored
4943 * via the hardware logical context mechanism.
4945 * We don't need to re-emit all state every batch - the hardware context
4946 * mechanism will save and restore it for us. This includes pointers to
4947 * various BOs...which won't exist unless we ask the kernel to pin them
4948 * by adding them to the validation list.
4950 * We can skip buffers if we've re-emitted those packets, as we're
4951 * overwriting those stale pointers with new ones, and don't actually
4952 * refer to the old BOs.
4955 iris_restore_render_saved_bos(struct iris_context
*ice
,
4956 struct iris_batch
*batch
,
4957 const struct pipe_draw_info
*draw
)
4959 struct iris_genx_state
*genx
= ice
->state
.genx
;
4961 const uint64_t clean
= ~ice
->state
.dirty
;
4962 const uint64_t stage_clean
= ~ice
->state
.stage_dirty
;
4964 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4965 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false,
4969 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4970 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false,
4974 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4975 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false,
4979 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4980 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false,
4984 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4985 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false,
4989 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4990 for (int i
= 0; i
< 4; i
++) {
4991 struct iris_stream_output_target
*tgt
=
4992 (void *) ice
->state
.so_target
[i
];
4994 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4995 true, IRIS_DOMAIN_OTHER_WRITE
);
4996 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4997 true, IRIS_DOMAIN_OTHER_WRITE
);
5002 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5003 if (!(stage_clean
& (IRIS_STAGE_DIRTY_CONSTANTS_VS
<< stage
)))
5006 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5007 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5012 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
5014 for (int i
= 0; i
< 4; i
++) {
5015 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
5017 if (range
->length
== 0)
5020 /* Range block is a binding table index, map back to UBO index. */
5021 unsigned block_index
= iris_bti_to_group_index(
5022 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
5023 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
5025 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
5026 struct iris_resource
*res
= (void *) cbuf
->buffer
;
5029 iris_use_pinned_bo(batch
, res
->bo
, false, IRIS_DOMAIN_OTHER_READ
);
5031 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false,
5032 IRIS_DOMAIN_OTHER_READ
);
5036 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5037 if (stage_clean
& (IRIS_STAGE_DIRTY_BINDINGS_VS
<< stage
)) {
5038 /* Re-pin any buffers referred to by the binding table. */
5039 iris_populate_binding_table(ice
, batch
, stage
, true);
5043 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5044 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5045 struct pipe_resource
*res
= shs
->sampler_table
.res
;
5047 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false,
5051 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5052 if (stage_clean
& (IRIS_STAGE_DIRTY_VS
<< stage
)) {
5053 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5056 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
5057 iris_use_pinned_bo(batch
, bo
, false, IRIS_DOMAIN_NONE
);
5059 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5061 if (prog_data
->total_scratch
> 0) {
5062 struct iris_bo
*bo
=
5063 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
5064 iris_use_pinned_bo(batch
, bo
, true, IRIS_DOMAIN_NONE
);
5070 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
5071 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5072 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5073 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
5076 iris_use_optional_res(batch
, ice
->state
.last_res
.index_buffer
, false,
5077 IRIS_DOMAIN_OTHER_READ
);
5079 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5080 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
5082 const int i
= u_bit_scan64(&bound
);
5083 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
5084 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false,
5085 IRIS_DOMAIN_OTHER_READ
);
5091 iris_restore_compute_saved_bos(struct iris_context
*ice
,
5092 struct iris_batch
*batch
,
5093 const struct pipe_grid_info
*grid
)
5095 const uint64_t stage_clean
= ~ice
->state
.stage_dirty
;
5097 const int stage
= MESA_SHADER_COMPUTE
;
5098 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5100 if (stage_clean
& IRIS_STAGE_DIRTY_BINDINGS_CS
) {
5101 /* Re-pin any buffers referred to by the binding table. */
5102 iris_populate_binding_table(ice
, batch
, stage
, true);
5105 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
5107 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false,
5110 if ((stage_clean
& IRIS_STAGE_DIRTY_SAMPLER_STATES_CS
) &&
5111 (stage_clean
& IRIS_STAGE_DIRTY_BINDINGS_CS
) &&
5112 (stage_clean
& IRIS_STAGE_DIRTY_CONSTANTS_CS
) &&
5113 (stage_clean
& IRIS_STAGE_DIRTY_CS
)) {
5114 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false,
5118 if (stage_clean
& IRIS_STAGE_DIRTY_CS
) {
5119 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5122 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
5123 iris_use_pinned_bo(batch
, bo
, false, IRIS_DOMAIN_NONE
);
5125 struct iris_bo
*curbe_bo
=
5126 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
5127 iris_use_pinned_bo(batch
, curbe_bo
, false, IRIS_DOMAIN_NONE
);
5129 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5131 if (prog_data
->total_scratch
> 0) {
5132 struct iris_bo
*bo
=
5133 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
5134 iris_use_pinned_bo(batch
, bo
, true, IRIS_DOMAIN_NONE
);
5141 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
5144 iris_update_surface_base_address(struct iris_batch
*batch
,
5145 struct iris_binder
*binder
)
5147 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
5150 uint32_t mocs
= batch
->screen
->isl_dev
.mocs
.internal
;
5152 iris_batch_sync_region_start(batch
);
5154 flush_before_state_base_change(batch
);
5157 /* GEN:BUG:1607854226:
5159 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
5160 * mode by putting the pipeline temporarily in 3D mode..
5162 if (batch
->name
== IRIS_BATCH_COMPUTE
)
5163 emit_pipeline_select(batch
, _3D
);
5166 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
5167 sba
.SurfaceStateBaseAddressModifyEnable
= true;
5168 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
5170 /* The hardware appears to pay attention to the MOCS fields even
5171 * if you don't set the "Address Modify Enable" bit for the base.
5173 sba
.GeneralStateMOCS
= mocs
;
5174 sba
.StatelessDataPortAccessMOCS
= mocs
;
5175 sba
.DynamicStateMOCS
= mocs
;
5176 sba
.IndirectObjectMOCS
= mocs
;
5177 sba
.InstructionMOCS
= mocs
;
5178 sba
.SurfaceStateMOCS
= mocs
;
5180 sba
.BindlessSurfaceStateMOCS
= mocs
;
5185 /* GEN:BUG:1607854226:
5187 * Put the pipeline back into compute mode.
5189 if (batch
->name
== IRIS_BATCH_COMPUTE
)
5190 emit_pipeline_select(batch
, GPGPU
);
5193 flush_after_state_base_change(batch
);
5194 iris_batch_sync_region_end(batch
);
5196 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
5200 iris_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
5201 bool window_space_position
, float *zmin
, float *zmax
)
5203 if (window_space_position
) {
5208 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
5213 genX(invalidate_aux_map_state
)(struct iris_batch
*batch
)
5215 struct iris_screen
*screen
= batch
->screen
;
5216 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
5219 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
5220 if (batch
->last_aux_map_state
!= aux_map_state_num
) {
5221 /* HSD 1209978178: docs say that before programming the aux table:
5223 * "Driver must ensure that the engine is IDLE but ensure it doesn't
5224 * add extra flushes in the case it knows that the engine is already
5227 * An end of pipe sync is needed here, otherwise we see GPU hangs in
5228 * dEQP-GLES31.functional.copy_image.* tests.
5230 iris_emit_end_of_pipe_sync(batch
, "Invalidate aux map table",
5231 PIPE_CONTROL_CS_STALL
);
5233 /* If the aux-map state number increased, then we need to rewrite the
5234 * register. Rewriting the register is used to both set the aux-map
5235 * translation table address, and also to invalidate any previously
5236 * cached translations.
5238 iris_load_register_imm32(batch
, GENX(GFX_CCS_AUX_INV_num
), 1);
5239 batch
->last_aux_map_state
= aux_map_state_num
;
5244 init_aux_map_state(struct iris_batch
*batch
)
5246 struct iris_screen
*screen
= batch
->screen
;
5247 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
5251 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
5252 assert(base_addr
!= 0 && align64(base_addr
, 32 * 1024) == base_addr
);
5253 iris_load_register_imm64(batch
, GENX(GFX_AUX_TABLE_BASE_ADDR_num
),
5260 struct iris_address addr
;
5264 uint32_t max_length
;
5268 setup_constant_buffers(struct iris_context
*ice
,
5269 struct iris_batch
*batch
,
5271 struct push_bos
*push_bos
)
5273 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5274 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5275 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
5277 uint32_t push_range_sum
= 0;
5280 for (int i
= 0; i
< 4; i
++) {
5281 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
5283 if (range
->length
== 0)
5286 push_range_sum
+= range
->length
;
5288 if (range
->length
> push_bos
->max_length
)
5289 push_bos
->max_length
= range
->length
;
5291 /* Range block is a binding table index, map back to UBO index. */
5292 unsigned block_index
= iris_bti_to_group_index(
5293 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
5294 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
5296 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
5297 struct iris_resource
*res
= (void *) cbuf
->buffer
;
5299 assert(cbuf
->buffer_offset
% 32 == 0);
5301 push_bos
->buffers
[n
].length
= range
->length
;
5302 push_bos
->buffers
[n
].addr
=
5303 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
5304 : batch
->screen
->workaround_address
;
5308 /* From the 3DSTATE_CONSTANT_XS and 3DSTATE_CONSTANT_ALL programming notes:
5310 * "The sum of all four read length fields must be less than or
5311 * equal to the size of 64."
5313 assert(push_range_sum
<= 64);
5315 push_bos
->buffer_count
= n
;
5319 emit_push_constant_packets(struct iris_context
*ice
,
5320 struct iris_batch
*batch
,
5322 const struct push_bos
*push_bos
)
5324 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
5325 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5326 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
5328 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
5329 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
5331 pkt
.MOCS
= isl_dev
->mocs
.internal
;
5334 /* The Skylake PRM contains the following restriction:
5336 * "The driver must ensure The following case does not occur
5337 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
5338 * buffer 3 read length equal to zero committed followed by a
5339 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
5342 * To avoid this, we program the buffers in the highest slots.
5343 * This way, slot 0 is only used if slot 3 is also used.
5345 int n
= push_bos
->buffer_count
;
5347 const unsigned shift
= 4 - n
;
5348 for (int i
= 0; i
< n
; i
++) {
5349 pkt
.ConstantBody
.ReadLength
[i
+ shift
] =
5350 push_bos
->buffers
[i
].length
;
5351 pkt
.ConstantBody
.Buffer
[i
+ shift
] = push_bos
->buffers
[i
].addr
;
5359 emit_push_constant_packet_all(struct iris_context
*ice
,
5360 struct iris_batch
*batch
,
5361 uint32_t shader_mask
,
5362 const struct push_bos
*push_bos
)
5364 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
5367 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_ALL
), pc
) {
5368 pc
.ShaderUpdateEnable
= shader_mask
;
5373 const uint32_t n
= push_bos
->buffer_count
;
5374 const uint32_t max_pointers
= 4;
5375 const uint32_t num_dwords
= 2 + 2 * n
;
5376 uint32_t const_all
[2 + 2 * max_pointers
];
5377 uint32_t *dw
= &const_all
[0];
5379 assert(n
<= max_pointers
);
5380 iris_pack_command(GENX(3DSTATE_CONSTANT_ALL
), dw
, all
) {
5381 all
.DWordLength
= num_dwords
- 2;
5382 all
.MOCS
= isl_dev
->mocs
.internal
;
5383 all
.ShaderUpdateEnable
= shader_mask
;
5384 all
.PointerBufferMask
= (1 << n
) - 1;
5388 for (int i
= 0; i
< n
; i
++) {
5389 _iris_pack_state(batch
, GENX(3DSTATE_CONSTANT_ALL_DATA
),
5391 data
.PointerToConstantBuffer
= push_bos
->buffers
[i
].addr
;
5392 data
.ConstantBufferReadLength
= push_bos
->buffers
[i
].length
;
5395 iris_batch_emit(batch
, const_all
, sizeof(uint32_t) * num_dwords
);
5400 iris_upload_dirty_render_state(struct iris_context
*ice
,
5401 struct iris_batch
*batch
,
5402 const struct pipe_draw_info
*draw
)
5404 const uint64_t dirty
= ice
->state
.dirty
;
5405 const uint64_t stage_dirty
= ice
->state
.stage_dirty
;
5407 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
) &&
5408 !(stage_dirty
& IRIS_ALL_STAGE_DIRTY_FOR_RENDER
))
5411 struct iris_genx_state
*genx
= ice
->state
.genx
;
5412 struct iris_binder
*binder
= &ice
->state
.binder
;
5413 struct brw_wm_prog_data
*wm_prog_data
= (void *)
5414 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
5416 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
5417 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5418 uint32_t cc_vp_address
;
5420 /* XXX: could avoid streaming for depth_clip [0,1] case. */
5421 uint32_t *cc_vp_map
=
5422 stream_state(batch
, ice
->state
.dynamic_uploader
,
5423 &ice
->state
.last_res
.cc_vp
,
5424 4 * ice
->state
.num_viewports
*
5425 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
5426 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
5428 iris_viewport_zmin_zmax(&ice
->state
.viewports
[i
], cso_rast
->clip_halfz
,
5429 ice
->state
.window_space_position
,
5431 if (cso_rast
->depth_clip_near
)
5433 if (cso_rast
->depth_clip_far
)
5436 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
5437 ccv
.MinimumDepth
= zmin
;
5438 ccv
.MaximumDepth
= zmax
;
5441 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
5444 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
5445 ptr
.CCViewportPointer
= cc_vp_address
;
5449 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
5450 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5451 uint32_t sf_cl_vp_address
;
5453 stream_state(batch
, ice
->state
.dynamic_uploader
,
5454 &ice
->state
.last_res
.sf_cl_vp
,
5455 4 * ice
->state
.num_viewports
*
5456 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
5458 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
5459 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
5460 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
5462 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
5463 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
5464 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
5465 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
5467 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
5468 state
->scale
[0], state
->scale
[1],
5469 state
->translate
[0], state
->translate
[1],
5470 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
5472 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
5473 vp
.ViewportMatrixElementm00
= state
->scale
[0];
5474 vp
.ViewportMatrixElementm11
= state
->scale
[1];
5475 vp
.ViewportMatrixElementm22
= state
->scale
[2];
5476 vp
.ViewportMatrixElementm30
= state
->translate
[0];
5477 vp
.ViewportMatrixElementm31
= state
->translate
[1];
5478 vp
.ViewportMatrixElementm32
= state
->translate
[2];
5479 vp
.XMinClipGuardband
= gb_xmin
;
5480 vp
.XMaxClipGuardband
= gb_xmax
;
5481 vp
.YMinClipGuardband
= gb_ymin
;
5482 vp
.YMaxClipGuardband
= gb_ymax
;
5483 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
5484 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
5485 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
5486 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
5489 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
5492 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
5493 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
5497 if (dirty
& IRIS_DIRTY_URB
) {
5500 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
5501 if (!ice
->shaders
.prog
[i
]) {
5504 struct brw_vue_prog_data
*vue_prog_data
=
5505 (void *) ice
->shaders
.prog
[i
]->prog_data
;
5506 size
[i
] = vue_prog_data
->urb_entry_size
;
5508 assert(size
[i
] != 0);
5511 unsigned entries
[4], start
[4];
5512 gen_get_urb_config(&batch
->screen
->devinfo
,
5513 batch
->screen
->l3_config_3d
,
5514 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
5515 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
5516 size
, entries
, start
,
5517 &ice
->state
.urb_deref_block_size
);
5519 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
5520 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
5521 urb
._3DCommandSubOpcode
+= i
;
5522 urb
.VSURBStartingAddress
= start
[i
];
5523 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
5524 urb
.VSNumberofURBEntries
= entries
[i
];
5529 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
5530 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5531 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5532 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5533 const int header_dwords
= GENX(BLEND_STATE_length
);
5535 /* Always write at least one BLEND_STATE - the final RT message will
5536 * reference BLEND_STATE[0] even if there aren't color writes. There
5537 * may still be alpha testing, computed depth, and so on.
5539 const int rt_dwords
=
5540 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
5542 uint32_t blend_offset
;
5543 uint32_t *blend_map
=
5544 stream_state(batch
, ice
->state
.dynamic_uploader
,
5545 &ice
->state
.last_res
.blend
,
5546 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
5548 uint32_t blend_state_header
;
5549 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
5550 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5551 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
5554 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
5555 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
5557 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
5558 ptr
.BlendStatePointer
= blend_offset
;
5559 ptr
.BlendStatePointerValid
= true;
5563 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
5564 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5566 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5570 stream_state(batch
, ice
->state
.dynamic_uploader
,
5571 &ice
->state
.last_res
.color_calc
,
5572 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
5574 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
5575 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
5576 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
5577 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
5578 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
5579 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
5580 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
5582 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5583 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5586 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
5587 ptr
.ColorCalcStatePointer
= cc_offset
;
5588 ptr
.ColorCalcStatePointerValid
= true;
5592 /* GEN:BUG:1604061319
5594 * 3DSTATE_CONSTANT_* needs to be programmed before BTP_*
5596 * Testing shows that all the 3DSTATE_CONSTANT_XS need to be emitted if
5597 * any stage has a dirty binding table.
5599 const bool emit_const_wa
= GEN_GEN
>= 11 &&
5600 ((dirty
& IRIS_DIRTY_RENDER_BUFFER
) ||
5601 (stage_dirty
& IRIS_ALL_STAGE_DIRTY_BINDINGS
));
5604 uint32_t nobuffer_stages
= 0;
5607 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5608 if (!(stage_dirty
& (IRIS_STAGE_DIRTY_CONSTANTS_VS
<< stage
)) &&
5612 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5613 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5618 if (shs
->sysvals_need_upload
)
5619 upload_sysvals(ice
, stage
);
5621 struct push_bos push_bos
= {};
5622 setup_constant_buffers(ice
, batch
, stage
, &push_bos
);
5625 /* If this stage doesn't have any push constants, emit it later in a
5626 * single CONSTANT_ALL packet with all the other stages.
5628 if (push_bos
.buffer_count
== 0) {
5629 nobuffer_stages
|= 1 << stage
;
5633 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
5634 * contains only 5 bits, so we can only use it for buffers smaller than
5637 if (push_bos
.max_length
< 32) {
5638 emit_push_constant_packet_all(ice
, batch
, 1 << stage
, &push_bos
);
5642 emit_push_constant_packets(ice
, batch
, stage
, &push_bos
);
5646 if (nobuffer_stages
)
5647 emit_push_constant_packet_all(ice
, batch
, nobuffer_stages
, NULL
);
5650 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5651 /* Gen9 requires 3DSTATE_BINDING_TABLE_POINTERS_XS to be re-emitted
5652 * in order to commit constants. TODO: Investigate "Disable Gather
5653 * at Set Shader" to go back to legacy mode...
5655 if (stage_dirty
& ((IRIS_STAGE_DIRTY_BINDINGS_VS
|
5656 (GEN_GEN
== 9 ? IRIS_STAGE_DIRTY_CONSTANTS_VS
: 0))
5658 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
5659 ptr
._3DCommandSubOpcode
= 38 + stage
;
5660 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
5665 if (GEN_GEN
>= 11 && (dirty
& IRIS_DIRTY_RENDER_BUFFER
)) {
5666 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
5667 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
5669 /* The PIPE_CONTROL command description says:
5671 * "Whenever a Binding Table Index (BTI) used by a Render Target
5672 * Message points to a different RENDER_SURFACE_STATE, SW must issue a
5673 * Render Target Cache Flush by enabling this bit. When render target
5674 * flush is set due to new association of BTI, PS Scoreboard Stall bit
5675 * must be set in this packet."
5677 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
5678 iris_emit_pipe_control_flush(batch
, "workaround: RT BTI change [draw]",
5679 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5680 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
5683 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5684 if (stage_dirty
& (IRIS_STAGE_DIRTY_BINDINGS_VS
<< stage
)) {
5685 iris_populate_binding_table(ice
, batch
, stage
, false);
5689 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5690 if (!(stage_dirty
& (IRIS_STAGE_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
5691 !ice
->shaders
.prog
[stage
])
5694 iris_upload_sampler_states(ice
, stage
);
5696 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5697 struct pipe_resource
*res
= shs
->sampler_table
.res
;
5699 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false,
5702 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
5703 ptr
._3DCommandSubOpcode
= 43 + stage
;
5704 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
5708 if (ice
->state
.need_border_colors
)
5709 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false,
5712 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
5713 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
5715 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
5716 if (ice
->state
.framebuffer
.samples
> 0)
5717 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
5721 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
5722 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
5723 ms
.SampleMask
= ice
->state
.sample_mask
;
5727 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
5728 if (!(stage_dirty
& (IRIS_STAGE_DIRTY_VS
<< stage
)))
5731 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
5734 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5735 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
5736 iris_use_pinned_bo(batch
, cache
->bo
, false, IRIS_DOMAIN_NONE
);
5738 if (prog_data
->total_scratch
> 0) {
5739 struct iris_bo
*bo
=
5740 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
5741 iris_use_pinned_bo(batch
, bo
, true, IRIS_DOMAIN_NONE
);
5744 if (stage
== MESA_SHADER_FRAGMENT
) {
5745 UNUSED
struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5746 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5748 uint32_t ps_state
[GENX(3DSTATE_PS_length
)] = {0};
5749 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
5750 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
5751 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
5752 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
5754 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
5756 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
5757 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
5760 * 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
5762 if (GEN_GEN
>= 9 && cso_fb
->samples
== 16 &&
5763 !wm_prog_data
->persample_dispatch
) {
5764 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
5765 ps
._32PixelDispatchEnable
= false;
5768 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
5769 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
5770 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
5771 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
5772 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
5773 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
5775 ps
.KernelStartPointer0
= KSP(shader
) +
5776 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
5777 ps
.KernelStartPointer1
= KSP(shader
) +
5778 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
5779 ps
.KernelStartPointer2
= KSP(shader
) +
5780 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
5783 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
5784 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
5786 if (!wm_prog_data
->uses_sample_mask
)
5787 psx
.InputCoverageMaskState
= ICMS_NONE
;
5788 else if (wm_prog_data
->post_depth_coverage
)
5789 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
5790 else if (wm_prog_data
->inner_coverage
&&
5791 cso
->conservative_rasterization
)
5792 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
5794 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
5796 psx
.PixelShaderUsesInputCoverageMask
=
5797 wm_prog_data
->uses_sample_mask
;
5801 uint32_t *shader_ps
= (uint32_t *) shader
->derived_data
;
5802 uint32_t *shader_psx
= shader_ps
+ GENX(3DSTATE_PS_length
);
5803 iris_emit_merge(batch
, shader_ps
, ps_state
,
5804 GENX(3DSTATE_PS_length
));
5805 iris_emit_merge(batch
, shader_psx
, psx_state
,
5806 GENX(3DSTATE_PS_EXTRA_length
));
5808 iris_batch_emit(batch
, shader
->derived_data
,
5809 iris_derived_program_state_size(stage
));
5812 if (stage
== MESA_SHADER_TESS_EVAL
) {
5813 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
5814 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
5815 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
5816 } else if (stage
== MESA_SHADER_GEOMETRY
) {
5817 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
5822 if (ice
->state
.streamout_active
) {
5823 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
5824 iris_batch_emit(batch
, genx
->so_buffers
,
5825 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
5826 for (int i
= 0; i
< 4; i
++) {
5827 struct iris_stream_output_target
*tgt
=
5828 (void *) ice
->state
.so_target
[i
];
5831 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
5832 true, IRIS_DOMAIN_OTHER_WRITE
);
5833 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
5834 true, IRIS_DOMAIN_OTHER_WRITE
);
5839 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
5840 uint32_t *decl_list
=
5841 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
5842 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
5845 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5846 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5848 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
5849 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
5850 sol
.SOFunctionEnable
= true;
5851 sol
.SOStatisticsEnable
= true;
5853 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
5854 !ice
->state
.prims_generated_query_active
;
5855 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
5858 assert(ice
->state
.streamout
);
5860 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
5861 GENX(3DSTATE_STREAMOUT_length
));
5864 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5865 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
5869 if (dirty
& IRIS_DIRTY_CLIP
) {
5870 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5871 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5873 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
5874 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
5875 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
5876 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
5877 : ice
->state
.prim_is_points_or_lines
);
5879 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
5880 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
5881 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5882 if (cso_rast
->rasterizer_discard
)
5883 cl
.ClipMode
= CLIPMODE_REJECT_ALL
;
5884 else if (ice
->state
.window_space_position
)
5885 cl
.ClipMode
= CLIPMODE_ACCEPT_ALL
;
5887 cl
.ClipMode
= CLIPMODE_NORMAL
;
5889 cl
.PerspectiveDivideDisable
= ice
->state
.window_space_position
;
5890 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
5892 if (wm_prog_data
->barycentric_interp_modes
&
5893 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
5894 cl
.NonPerspectiveBarycentricEnable
= true;
5896 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
<= 1;
5897 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
5899 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
5900 ARRAY_SIZE(cso_rast
->clip
));
5903 if (dirty
& (IRIS_DIRTY_RASTER
| IRIS_DIRTY_URB
)) {
5904 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5905 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
5907 uint32_t dynamic_sf
[GENX(3DSTATE_SF_length
)];
5908 iris_pack_command(GENX(3DSTATE_SF
), &dynamic_sf
, sf
) {
5909 sf
.ViewportTransformEnable
= !ice
->state
.window_space_position
;
5912 sf
.DerefBlockSize
= ice
->state
.urb_deref_block_size
;
5915 iris_emit_merge(batch
, cso
->sf
, dynamic_sf
,
5916 ARRAY_SIZE(dynamic_sf
));
5919 if (dirty
& IRIS_DIRTY_WM
) {
5920 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5921 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
5923 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
5924 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5926 wm
.BarycentricInterpolationMode
=
5927 wm_prog_data
->barycentric_interp_modes
;
5929 if (wm_prog_data
->early_fragment_tests
)
5930 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
5931 else if (wm_prog_data
->has_side_effects
)
5932 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
5934 /* We could skip this bit if color writes are enabled. */
5935 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
5936 wm
.ForceThreadDispatchEnable
= ForceON
;
5938 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
5941 if (dirty
& IRIS_DIRTY_SBE
) {
5942 iris_emit_sbe(batch
, ice
);
5945 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
5946 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5947 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5948 const struct shader_info
*fs_info
=
5949 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
5951 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
5952 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
5953 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
5954 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5956 /* The dual source blending docs caution against using SRC1 factors
5957 * when the shader doesn't use a dual source render target write.
5958 * Empirically, this can lead to GPU hangs, and the results are
5959 * undefined anyway, so simply disable blending to avoid the hang.
5961 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
5962 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
5965 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
5966 ARRAY_SIZE(cso_blend
->ps_blend
));
5969 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
5970 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5971 #if GEN_GEN >= 9 && GEN_GEN < 12
5972 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5973 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5974 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5975 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5976 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5978 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
5980 /* Use modify disable fields which allow us to emit packets
5981 * directly instead of merging them later.
5983 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
5987 iris_batch_emit(batch
, cso
->depth_bounds
, sizeof(cso
->depth_bounds
));
5991 if (dirty
& IRIS_DIRTY_STENCIL_REF
) {
5993 /* Use modify disable fields which allow us to emit packets
5994 * directly instead of merging them later.
5996 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5997 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5998 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5999 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
6000 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
6001 wmds
.StencilTestMaskModifyDisable
= true;
6002 wmds
.StencilWriteMaskModifyDisable
= true;
6003 wmds
.StencilStateModifyDisable
= true;
6004 wmds
.DepthStateModifyDisable
= true;
6006 iris_batch_emit(batch
, stencil_refs
, sizeof(stencil_refs
));
6010 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
6011 uint32_t scissor_offset
=
6012 emit_state(batch
, ice
->state
.dynamic_uploader
,
6013 &ice
->state
.last_res
.scissor
,
6014 ice
->state
.scissors
,
6015 sizeof(struct pipe_scissor_state
) *
6016 ice
->state
.num_viewports
, 32);
6018 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
6019 ptr
.ScissorRectPointer
= scissor_offset
;
6023 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
6024 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
6026 /* Do not emit the clear params yets. We need to update the clear value
6029 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
6030 uint32_t cso_z_size
= batch
->screen
->isl_dev
.ds
.size
- clear_length
;;
6033 /* GEN:BUG:14010455700
6035 * ISL will change some CHICKEN registers depending on the depth surface
6036 * format, along with emitting the depth and stencil packets. In that
6037 * case, we want to do a depth flush and stall, so the pipeline is not
6038 * using these settings while we change the registers.
6040 iris_emit_end_of_pipe_sync(batch
,
6041 "Workaround: Stop pipeline for 14010455700",
6042 PIPE_CONTROL_DEPTH_STALL
|
6043 PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
6046 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
6047 if (GEN_GEN
>= 12) {
6048 /* GEN:BUG:1408224581
6050 * Workaround: Gen12LP Astep only An additional pipe control with
6051 * post-sync = store dword operation would be required.( w/a is to
6052 * have an additional pipe control after the stencil state whenever
6053 * the surface state bits of this state is changing).
6055 iris_emit_pipe_control_write(batch
, "WA for stencil state",
6056 PIPE_CONTROL_WRITE_IMMEDIATE
,
6057 batch
->screen
->workaround_address
.bo
,
6058 batch
->screen
->workaround_address
.offset
, 0);
6061 union isl_color_value clear_value
= { .f32
= { 0, } };
6063 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
6064 if (cso_fb
->zsbuf
) {
6065 struct iris_resource
*zres
, *sres
;
6066 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
6068 if (zres
&& zres
->aux
.bo
)
6069 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
6072 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
6073 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
6074 clear
.DepthClearValueValid
= true;
6075 clear
.DepthClearValue
= clear_value
.f32
[0];
6077 iris_batch_emit(batch
, clear_params
, clear_length
);
6080 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
6081 /* Listen for buffer changes, and also write enable changes. */
6082 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
6083 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
6086 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
6087 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
6088 for (int i
= 0; i
< 32; i
++) {
6089 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
6094 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
6095 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
6096 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
6099 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
6100 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
6101 topo
.PrimitiveTopologyType
=
6102 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
6106 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
6107 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
6108 uint64_t dynamic_bound
= ice
->state
.bound_vertex_buffers
;
6110 if (ice
->state
.vs_uses_draw_params
) {
6111 assert(ice
->draw
.draw_params
.res
);
6113 struct iris_vertex_buffer_state
*state
=
6114 &(ice
->state
.genx
->vertex_buffers
[count
]);
6115 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params
.res
);
6116 struct iris_resource
*res
= (void *) state
->resource
;
6118 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
6119 vb
.VertexBufferIndex
= count
;
6120 vb
.AddressModifyEnable
= true;
6122 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params
.offset
;
6123 vb
.BufferStartingAddress
=
6124 ro_bo(NULL
, res
->bo
->gtt_offset
+
6125 (int) ice
->draw
.draw_params
.offset
);
6126 vb
.MOCS
= iris_mocs(res
->bo
, &batch
->screen
->isl_dev
);
6128 dynamic_bound
|= 1ull << count
;
6132 if (ice
->state
.vs_uses_derived_draw_params
) {
6133 struct iris_vertex_buffer_state
*state
=
6134 &(ice
->state
.genx
->vertex_buffers
[count
]);
6135 pipe_resource_reference(&state
->resource
,
6136 ice
->draw
.derived_draw_params
.res
);
6137 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params
.res
;
6139 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
6140 vb
.VertexBufferIndex
= count
;
6141 vb
.AddressModifyEnable
= true;
6144 res
->bo
->size
- ice
->draw
.derived_draw_params
.offset
;
6145 vb
.BufferStartingAddress
=
6146 ro_bo(NULL
, res
->bo
->gtt_offset
+
6147 (int) ice
->draw
.derived_draw_params
.offset
);
6148 vb
.MOCS
= iris_mocs(res
->bo
, &batch
->screen
->isl_dev
);
6150 dynamic_bound
|= 1ull << count
;
6156 /* Gen11+ doesn't need the cache workaround below */
6157 uint64_t bound
= dynamic_bound
;
6159 const int i
= u_bit_scan64(&bound
);
6160 iris_use_optional_res(batch
, genx
->vertex_buffers
[i
].resource
,
6161 false, IRIS_DOMAIN_OTHER_READ
);
6164 /* The VF cache designers cut corners, and made the cache key's
6165 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
6166 * 32 bits of the address. If you have two vertex buffers which get
6167 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
6168 * you can get collisions (even within a single batch).
6170 * So, we need to do a VF cache invalidate if the buffer for a VB
6171 * slot slot changes [48:32] address bits from the previous time.
6173 unsigned flush_flags
= 0;
6175 uint64_t bound
= dynamic_bound
;
6177 const int i
= u_bit_scan64(&bound
);
6178 uint16_t high_bits
= 0;
6180 struct iris_resource
*res
=
6181 (void *) genx
->vertex_buffers
[i
].resource
;
6183 iris_use_pinned_bo(batch
, res
->bo
, false, IRIS_DOMAIN_OTHER_READ
);
6185 high_bits
= res
->bo
->gtt_offset
>> 32ull;
6186 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
6187 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
6188 PIPE_CONTROL_CS_STALL
;
6189 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
6195 iris_emit_pipe_control_flush(batch
,
6196 "workaround: VF cache 32-bit key [VB]",
6201 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
6204 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
6205 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
6206 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
6210 bound
= dynamic_bound
;
6212 const int i
= u_bit_scan64(&bound
);
6213 memcpy(map
, genx
->vertex_buffers
[i
].state
,
6214 sizeof(uint32_t) * vb_dwords
);
6220 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
6221 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
6222 const unsigned entries
= MAX2(cso
->count
, 1);
6223 if (!(ice
->state
.vs_needs_sgvs_element
||
6224 ice
->state
.vs_uses_derived_draw_params
||
6225 ice
->state
.vs_needs_edge_flag
)) {
6226 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
6227 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
6229 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
6230 const unsigned dyn_count
= cso
->count
+
6231 ice
->state
.vs_needs_sgvs_element
+
6232 ice
->state
.vs_uses_derived_draw_params
;
6234 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
6237 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
6239 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
6240 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
6241 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
6242 uint32_t *ve_pack_dest
=
6243 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
6244 GENX(VERTEX_ELEMENT_STATE_length
)];
6246 if (ice
->state
.vs_needs_sgvs_element
) {
6247 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
6248 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
6249 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
6251 ve
.VertexBufferIndex
=
6252 util_bitcount64(ice
->state
.bound_vertex_buffers
);
6253 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
6254 ve
.Component0Control
= base_ctrl
;
6255 ve
.Component1Control
= base_ctrl
;
6256 ve
.Component2Control
= VFCOMP_STORE_0
;
6257 ve
.Component3Control
= VFCOMP_STORE_0
;
6259 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
6261 if (ice
->state
.vs_uses_derived_draw_params
) {
6262 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
6264 ve
.VertexBufferIndex
=
6265 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
6266 ice
->state
.vs_uses_draw_params
;
6267 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
6268 ve
.Component0Control
= VFCOMP_STORE_SRC
;
6269 ve
.Component1Control
= VFCOMP_STORE_SRC
;
6270 ve
.Component2Control
= VFCOMP_STORE_0
;
6271 ve
.Component3Control
= VFCOMP_STORE_0
;
6273 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
6275 if (ice
->state
.vs_needs_edge_flag
) {
6276 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
6277 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
6280 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
6281 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
6284 if (!ice
->state
.vs_needs_edge_flag
) {
6285 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
6286 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
6288 assert(cso
->count
> 0);
6289 const unsigned edgeflag_index
= cso
->count
- 1;
6290 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
6291 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
6292 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
6294 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
6295 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
6296 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
6297 vi
.VertexElementIndex
= edgeflag_index
+
6298 ice
->state
.vs_needs_sgvs_element
+
6299 ice
->state
.vs_uses_derived_draw_params
;
6301 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
6302 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
6304 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
6305 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
6309 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
6310 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
6311 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
6312 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
6314 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
6315 if (vs_prog_data
->uses_vertexid
) {
6316 sgv
.VertexIDEnable
= true;
6317 sgv
.VertexIDComponentNumber
= 2;
6318 sgv
.VertexIDElementOffset
=
6319 cso
->count
- ice
->state
.vs_needs_edge_flag
;
6322 if (vs_prog_data
->uses_instanceid
) {
6323 sgv
.InstanceIDEnable
= true;
6324 sgv
.InstanceIDComponentNumber
= 3;
6325 sgv
.InstanceIDElementOffset
=
6326 cso
->count
- ice
->state
.vs_needs_edge_flag
;
6331 if (dirty
& IRIS_DIRTY_VF
) {
6332 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
6333 if (draw
->primitive_restart
) {
6334 vf
.IndexedDrawCutIndexEnable
= true;
6335 vf
.CutIndex
= draw
->restart_index
;
6340 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
6341 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
6342 vf
.StatisticsEnable
= true;
6347 if (dirty
& IRIS_DIRTY_PMA_FIX
) {
6348 bool enable
= want_pma_fix(ice
);
6349 genX(update_pma_fix
)(ice
, batch
, enable
);
6353 if (ice
->state
.current_hash_scale
!= 1)
6354 genX(emit_hashing_mode
)(ice
, batch
, UINT_MAX
, UINT_MAX
, 1);
6357 genX(invalidate_aux_map_state
)(batch
);
6362 iris_upload_render_state(struct iris_context
*ice
,
6363 struct iris_batch
*batch
,
6364 const struct pipe_draw_info
*draw
)
6366 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
6368 iris_batch_sync_region_start(batch
);
6370 /* Always pin the binder. If we're emitting new binding table pointers,
6371 * we need it. If not, we're probably inheriting old tables via the
6372 * context, and need it anyway. Since true zero-bindings cases are
6373 * practically non-existent, just pin it and avoid last_res tracking.
6375 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false,
6378 if (!batch
->contains_draw_with_next_seqno
) {
6379 iris_restore_render_saved_bos(ice
, batch
, draw
);
6380 batch
->contains_draw_with_next_seqno
= batch
->contains_draw
= true;
6383 iris_upload_dirty_render_state(ice
, batch
, draw
);
6385 if (draw
->index_size
> 0) {
6388 if (draw
->has_user_indices
) {
6389 u_upload_data(ice
->ctx
.stream_uploader
, 0,
6390 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
6391 &offset
, &ice
->state
.last_res
.index_buffer
);
6393 struct iris_resource
*res
= (void *) draw
->index
.resource
;
6394 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
6396 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
6397 draw
->index
.resource
);
6401 struct iris_genx_state
*genx
= ice
->state
.genx
;
6402 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
6404 uint32_t ib_packet
[GENX(3DSTATE_INDEX_BUFFER_length
)];
6405 iris_pack_command(GENX(3DSTATE_INDEX_BUFFER
), ib_packet
, ib
) {
6406 ib
.IndexFormat
= draw
->index_size
>> 1;
6407 ib
.MOCS
= iris_mocs(bo
, &batch
->screen
->isl_dev
);
6408 ib
.BufferSize
= bo
->size
- offset
;
6409 ib
.BufferStartingAddress
= ro_bo(NULL
, bo
->gtt_offset
+ offset
);
6412 if (memcmp(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
)) != 0) {
6413 memcpy(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
));
6414 iris_batch_emit(batch
, ib_packet
, sizeof(ib_packet
));
6415 iris_use_pinned_bo(batch
, bo
, false, IRIS_DOMAIN_OTHER_READ
);
6419 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
6420 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
6421 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
6422 iris_emit_pipe_control_flush(batch
,
6423 "workaround: VF cache 32-bit key [IB]",
6424 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
6425 PIPE_CONTROL_CS_STALL
);
6426 ice
->state
.last_index_bo_high_bits
= high_bits
;
6431 #define _3DPRIM_END_OFFSET 0x2420
6432 #define _3DPRIM_START_VERTEX 0x2430
6433 #define _3DPRIM_VERTEX_COUNT 0x2434
6434 #define _3DPRIM_INSTANCE_COUNT 0x2438
6435 #define _3DPRIM_START_INSTANCE 0x243C
6436 #define _3DPRIM_BASE_VERTEX 0x2440
6438 if (draw
->indirect
) {
6439 if (draw
->indirect
->indirect_draw_count
) {
6440 use_predicate
= true;
6442 struct iris_bo
*draw_count_bo
=
6443 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
6444 unsigned draw_count_offset
=
6445 draw
->indirect
->indirect_draw_count_offset
;
6447 iris_emit_pipe_control_flush(batch
,
6448 "ensure indirect draw buffer is flushed",
6449 PIPE_CONTROL_FLUSH_ENABLE
);
6451 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
6452 struct gen_mi_builder b
;
6453 gen_mi_builder_init(&b
, batch
);
6455 /* comparison = draw id < draw count */
6456 struct gen_mi_value comparison
=
6457 gen_mi_ult(&b
, gen_mi_imm(draw
->drawid
),
6458 gen_mi_mem32(ro_bo(draw_count_bo
,
6459 draw_count_offset
)));
6461 /* predicate = comparison & conditional rendering predicate */
6462 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_RESULT
),
6463 gen_mi_iand(&b
, comparison
,
6464 gen_mi_reg32(CS_GPR(15))));
6466 uint32_t mi_predicate
;
6468 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
6469 iris_load_register_imm64(batch
, MI_PREDICATE_SRC1
, draw
->drawid
);
6470 /* Upload the current draw count from the draw parameters buffer
6471 * to MI_PREDICATE_SRC0.
6473 iris_load_register_mem32(batch
, MI_PREDICATE_SRC0
,
6474 draw_count_bo
, draw_count_offset
);
6475 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
6476 iris_load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
6478 if (draw
->drawid
== 0) {
6479 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
6480 MI_PREDICATE_COMBINEOP_SET
|
6481 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
6483 /* While draw_index < draw_count the predicate's result will be
6484 * (draw_index == draw_count) ^ TRUE = TRUE
6485 * When draw_index == draw_count the result is
6486 * (TRUE) ^ TRUE = FALSE
6487 * After this all results will be:
6488 * (FALSE) ^ FALSE = FALSE
6490 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
6491 MI_PREDICATE_COMBINEOP_XOR
|
6492 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
6494 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
6497 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
6500 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6501 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
6502 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
6504 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6505 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
6506 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
6508 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6509 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
6510 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
6512 if (draw
->index_size
) {
6513 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6514 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
6515 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
6517 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6518 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
6519 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
6522 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6523 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
6524 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
6526 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
6527 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
6531 } else if (draw
->count_from_stream_output
) {
6532 struct iris_stream_output_target
*so
=
6533 (void *) draw
->count_from_stream_output
;
6535 /* XXX: Replace with actual cache tracking */
6536 iris_emit_pipe_control_flush(batch
,
6537 "draw count from stream output stall",
6538 PIPE_CONTROL_CS_STALL
);
6540 struct gen_mi_builder b
;
6541 gen_mi_builder_init(&b
, batch
);
6543 struct iris_address addr
=
6544 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
6545 struct gen_mi_value offset
=
6546 gen_mi_iadd_imm(&b
, gen_mi_mem32(addr
), -so
->base
.buffer_offset
);
6548 gen_mi_store(&b
, gen_mi_reg32(_3DPRIM_VERTEX_COUNT
),
6549 gen_mi_udiv32_imm(&b
, offset
, so
->stride
));
6551 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
6552 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
6553 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
6554 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
6557 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
6558 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
6559 prim
.PredicateEnable
= use_predicate
;
6561 if (draw
->indirect
|| draw
->count_from_stream_output
) {
6562 prim
.IndirectParameterEnable
= true;
6564 prim
.StartInstanceLocation
= draw
->start_instance
;
6565 prim
.InstanceCount
= draw
->instance_count
;
6566 prim
.VertexCountPerInstance
= draw
->count
;
6568 prim
.StartVertexLocation
= draw
->start
;
6570 if (draw
->index_size
) {
6571 prim
.BaseVertexLocation
+= draw
->index_bias
;
6573 prim
.StartVertexLocation
+= draw
->index_bias
;
6578 iris_batch_sync_region_end(batch
);
6582 iris_load_indirect_location(struct iris_context
*ice
,
6583 struct iris_batch
*batch
,
6584 const struct pipe_grid_info
*grid
)
6586 #define GPGPU_DISPATCHDIMX 0x2500
6587 #define GPGPU_DISPATCHDIMY 0x2504
6588 #define GPGPU_DISPATCHDIMZ 0x2508
6590 assert(grid
->indirect
);
6592 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
6593 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
6594 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6595 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
6596 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
6598 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6599 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
6600 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
6602 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6603 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
6604 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
6609 iris_upload_gpgpu_walker(struct iris_context
*ice
,
6610 struct iris_batch
*batch
,
6611 const struct pipe_grid_info
*grid
)
6613 const uint64_t stage_dirty
= ice
->state
.stage_dirty
;
6614 struct iris_screen
*screen
= batch
->screen
;
6615 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
6616 struct iris_binder
*binder
= &ice
->state
.binder
;
6617 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
6618 struct iris_compiled_shader
*shader
=
6619 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
6620 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
6621 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
6622 const uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
6623 const unsigned simd_size
=
6624 brw_cs_simd_size_for_group_size(devinfo
, cs_prog_data
, group_size
);
6625 const unsigned threads
= DIV_ROUND_UP(group_size
, simd_size
);
6628 if (stage_dirty
& IRIS_STAGE_DIRTY_CS
) {
6629 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
6631 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
6632 * the only bits that are changed are scoreboard related: Scoreboard
6633 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
6634 * these scoreboard related states, a MEDIA_STATE_FLUSH is
6637 iris_emit_pipe_control_flush(batch
,
6638 "workaround: stall before MEDIA_VFE_STATE",
6639 PIPE_CONTROL_CS_STALL
);
6641 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
6642 if (prog_data
->total_scratch
) {
6643 struct iris_bo
*bo
=
6644 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
6645 MESA_SHADER_COMPUTE
);
6646 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
6647 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0, IRIS_DOMAIN_NONE
);
6650 vfe
.MaximumNumberofThreads
=
6651 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
6653 vfe
.ResetGatewayTimer
=
6654 Resettingrelativetimerandlatchingtheglobaltimestamp
;
6657 vfe
.BypassGatewayControl
= true;
6659 vfe
.NumberofURBEntries
= 2;
6660 vfe
.URBEntryAllocationSize
= 2;
6662 vfe
.CURBEAllocationSize
=
6663 ALIGN(cs_prog_data
->push
.per_thread
.regs
* threads
+
6664 cs_prog_data
->push
.cross_thread
.regs
, 2);
6668 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
6669 if (stage_dirty
& IRIS_STAGE_DIRTY_CS
) {
6670 uint32_t curbe_data_offset
= 0;
6671 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
6672 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
6673 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
6674 const unsigned push_const_size
=
6675 brw_cs_push_const_total_size(cs_prog_data
, threads
);
6676 uint32_t *curbe_data_map
=
6677 stream_state(batch
, ice
->state
.dynamic_uploader
,
6678 &ice
->state
.last_res
.cs_thread_ids
,
6679 ALIGN(push_const_size
, 64), 64,
6680 &curbe_data_offset
);
6681 assert(curbe_data_map
);
6682 memset(curbe_data_map
, 0x5a, ALIGN(push_const_size
, 64));
6683 iris_fill_cs_push_const_buffer(cs_prog_data
, threads
, curbe_data_map
);
6685 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
6686 curbe
.CURBETotalDataLength
= ALIGN(push_const_size
, 64);
6687 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
6691 if (stage_dirty
& (IRIS_STAGE_DIRTY_SAMPLER_STATES_CS
|
6692 IRIS_STAGE_DIRTY_BINDINGS_CS
|
6693 IRIS_STAGE_DIRTY_CONSTANTS_CS
|
6694 IRIS_STAGE_DIRTY_CS
)) {
6695 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
6697 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
6698 idd
.KernelStartPointer
=
6699 KSP(shader
) + brw_cs_prog_data_prog_offset(cs_prog_data
, simd_size
);
6700 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
6701 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
6702 idd
.NumberofThreadsinGPGPUThreadGroup
= threads
;
6705 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
6706 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
6708 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
6709 load
.InterfaceDescriptorTotalLength
=
6710 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
6711 load
.InterfaceDescriptorDataStartAddress
=
6712 emit_state(batch
, ice
->state
.dynamic_uploader
,
6713 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
6718 iris_load_indirect_location(ice
, batch
, grid
);
6720 const uint32_t right_mask
= brw_cs_right_mask(group_size
, simd_size
);
6722 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
6723 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
6724 ggw
.SIMDSize
= simd_size
/ 16;
6725 ggw
.ThreadDepthCounterMaximum
= 0;
6726 ggw
.ThreadHeightCounterMaximum
= 0;
6727 ggw
.ThreadWidthCounterMaximum
= threads
- 1;
6728 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
6729 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
6730 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
6731 ggw
.RightExecutionMask
= right_mask
;
6732 ggw
.BottomExecutionMask
= 0xffffffff;
6735 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
6739 iris_upload_compute_state(struct iris_context
*ice
,
6740 struct iris_batch
*batch
,
6741 const struct pipe_grid_info
*grid
)
6743 const uint64_t stage_dirty
= ice
->state
.stage_dirty
;
6744 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
6745 struct iris_compiled_shader
*shader
=
6746 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
6748 iris_batch_sync_region_start(batch
);
6750 /* Always pin the binder. If we're emitting new binding table pointers,
6751 * we need it. If not, we're probably inheriting old tables via the
6752 * context, and need it anyway. Since true zero-bindings cases are
6753 * practically non-existent, just pin it and avoid last_res tracking.
6755 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false, IRIS_DOMAIN_NONE
);
6757 if ((stage_dirty
& IRIS_STAGE_DIRTY_CONSTANTS_CS
) &&
6758 shs
->sysvals_need_upload
)
6759 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
6761 if (stage_dirty
& IRIS_STAGE_DIRTY_BINDINGS_CS
)
6762 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
6764 if (stage_dirty
& IRIS_STAGE_DIRTY_SAMPLER_STATES_CS
)
6765 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
6767 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false,
6769 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false,
6772 if (ice
->state
.need_border_colors
)
6773 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false,
6777 genX(invalidate_aux_map_state
)(batch
);
6780 iris_upload_gpgpu_walker(ice
, batch
, grid
);
6782 if (!batch
->contains_draw_with_next_seqno
) {
6783 iris_restore_compute_saved_bos(ice
, batch
, grid
);
6784 batch
->contains_draw_with_next_seqno
= batch
->contains_draw
= true;
6787 iris_batch_sync_region_end(batch
);
6791 * State module teardown.
6794 iris_destroy_state(struct iris_context
*ice
)
6796 struct iris_genx_state
*genx
= ice
->state
.genx
;
6798 pipe_resource_reference(&ice
->draw
.draw_params
.res
, NULL
);
6799 pipe_resource_reference(&ice
->draw
.derived_draw_params
.res
, NULL
);
6801 /* Loop over all VBOs, including ones for draw parameters */
6802 for (unsigned i
= 0; i
< ARRAY_SIZE(genx
->vertex_buffers
); i
++) {
6803 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
6806 free(ice
->state
.genx
);
6808 for (int i
= 0; i
< 4; i
++) {
6809 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
6812 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
6813 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
6815 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
6817 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
6818 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
6819 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
6820 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
6821 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
6822 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
6824 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
6825 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
6826 pipe_resource_reference(&shs
->image
[i
].surface_state
.ref
.res
, NULL
);
6827 free(shs
->image
[i
].surface_state
.cpu
);
6829 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
6830 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
6831 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
6833 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
6834 pipe_sampler_view_reference((struct pipe_sampler_view
**)
6835 &shs
->textures
[i
], NULL
);
6839 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
6840 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
6842 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
6843 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
6845 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
6846 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
6847 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
6848 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
6849 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
6850 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
6851 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
6852 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
6855 /* ------------------------------------------------------------------- */
6858 iris_rebind_buffer(struct iris_context
*ice
,
6859 struct iris_resource
*res
)
6861 struct pipe_context
*ctx
= &ice
->ctx
;
6862 struct iris_genx_state
*genx
= ice
->state
.genx
;
6864 assert(res
->base
.target
== PIPE_BUFFER
);
6866 /* Buffers can't be framebuffer attachments, nor display related,
6867 * and we don't have upstream Clover support.
6869 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
6870 PIPE_BIND_RENDER_TARGET
|
6871 PIPE_BIND_BLENDABLE
|
6872 PIPE_BIND_DISPLAY_TARGET
|
6874 PIPE_BIND_COMPUTE_RESOURCE
|
6875 PIPE_BIND_GLOBAL
)));
6877 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
6878 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
6880 const int i
= u_bit_scan64(&bound_vbs
);
6881 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
6883 /* Update the CPU struct */
6884 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
6885 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
6886 uint64_t *addr
= (uint64_t *) &state
->state
[1];
6887 struct iris_bo
*bo
= iris_resource_bo(state
->resource
);
6889 if (*addr
!= bo
->gtt_offset
+ state
->offset
) {
6890 *addr
= bo
->gtt_offset
+ state
->offset
;
6891 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
6896 /* We don't need to handle PIPE_BIND_INDEX_BUFFER here: we re-emit
6897 * the 3DSTATE_INDEX_BUFFER packet whenever the address changes.
6899 * There is also no need to handle these:
6900 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
6901 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
6904 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
6905 /* XXX: be careful about resetting vs appending... */
6909 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
6910 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
6911 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
6913 if (!(res
->bind_stages
& (1 << s
)))
6916 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
6917 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
6918 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
6919 while (bound_cbufs
) {
6920 const int i
= u_bit_scan(&bound_cbufs
);
6921 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
6922 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
6924 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
6925 pipe_resource_reference(&surf_state
->res
, NULL
);
6926 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_CONSTANTS_VS
<< s
;
6931 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
6932 uint32_t bound_ssbos
= shs
->bound_ssbos
;
6933 while (bound_ssbos
) {
6934 const int i
= u_bit_scan(&bound_ssbos
);
6935 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
6937 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
6938 struct pipe_shader_buffer buf
= {
6939 .buffer
= &res
->base
,
6940 .buffer_offset
= ssbo
->buffer_offset
,
6941 .buffer_size
= ssbo
->buffer_size
,
6943 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
6944 (shs
->writable_ssbos
>> i
) & 1);
6949 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
6950 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
6951 while (bound_sampler_views
) {
6952 const int i
= u_bit_scan(&bound_sampler_views
);
6953 struct iris_sampler_view
*isv
= shs
->textures
[i
];
6954 struct iris_bo
*bo
= isv
->res
->bo
;
6956 if (update_surface_state_addrs(ice
->state
.surface_uploader
,
6957 &isv
->surface_state
, bo
)) {
6958 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_BINDINGS_VS
<< s
;
6963 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
6964 uint32_t bound_image_views
= shs
->bound_image_views
;
6965 while (bound_image_views
) {
6966 const int i
= u_bit_scan(&bound_image_views
);
6967 struct iris_image_view
*iv
= &shs
->image
[i
];
6968 struct iris_bo
*bo
= iris_resource_bo(iv
->base
.resource
);
6970 if (update_surface_state_addrs(ice
->state
.surface_uploader
,
6971 &iv
->surface_state
, bo
)) {
6972 ice
->state
.stage_dirty
|= IRIS_STAGE_DIRTY_BINDINGS_VS
<< s
;
6979 /* ------------------------------------------------------------------- */
6982 * Introduce a batch synchronization boundary, and update its cache coherency
6983 * status to reflect the execution of a PIPE_CONTROL command with the
6987 batch_mark_sync_for_pipe_control(struct iris_batch
*batch
, uint32_t flags
)
6989 iris_batch_sync_boundary(batch
);
6991 if ((flags
& PIPE_CONTROL_CS_STALL
)) {
6992 if ((flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
))
6993 iris_batch_mark_flush_sync(batch
, IRIS_DOMAIN_RENDER_WRITE
);
6995 if ((flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
))
6996 iris_batch_mark_flush_sync(batch
, IRIS_DOMAIN_DEPTH_WRITE
);
6998 if ((flags
& PIPE_CONTROL_FLUSH_ENABLE
))
6999 iris_batch_mark_flush_sync(batch
, IRIS_DOMAIN_OTHER_WRITE
);
7001 if ((flags
& (PIPE_CONTROL_CACHE_FLUSH_BITS
|
7002 PIPE_CONTROL_STALL_AT_SCOREBOARD
)))
7003 iris_batch_mark_flush_sync(batch
, IRIS_DOMAIN_OTHER_READ
);
7006 if ((flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
))
7007 iris_batch_mark_invalidate_sync(batch
, IRIS_DOMAIN_RENDER_WRITE
);
7009 if ((flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
))
7010 iris_batch_mark_invalidate_sync(batch
, IRIS_DOMAIN_DEPTH_WRITE
);
7012 if ((flags
& PIPE_CONTROL_FLUSH_ENABLE
))
7013 iris_batch_mark_invalidate_sync(batch
, IRIS_DOMAIN_OTHER_WRITE
);
7015 if ((flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) &&
7016 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
))
7017 iris_batch_mark_invalidate_sync(batch
, IRIS_DOMAIN_OTHER_READ
);
7021 flags_to_post_sync_op(uint32_t flags
)
7023 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
7024 return WriteImmediateData
;
7026 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
7027 return WritePSDepthCount
;
7029 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
7030 return WriteTimestamp
;
7036 * Do the given flags have a Post Sync or LRI Post Sync operation?
7038 static enum pipe_control_flags
7039 get_post_sync_flags(enum pipe_control_flags flags
)
7041 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
7042 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
7043 PIPE_CONTROL_WRITE_TIMESTAMP
|
7044 PIPE_CONTROL_LRI_POST_SYNC_OP
;
7046 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
7047 * "LRI Post Sync Operation". So more than one bit set would be illegal.
7049 assert(util_bitcount(flags
) <= 1);
7054 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
7057 * Emit a series of PIPE_CONTROL commands, taking into account any
7058 * workarounds necessary to actually accomplish the caller's request.
7060 * Unless otherwise noted, spec quotations in this function come from:
7062 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
7063 * Restrictions for PIPE_CONTROL.
7065 * You should not use this function directly. Use the helpers in
7066 * iris_pipe_control.c instead, which may split the pipe control further.
7069 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
7076 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
7077 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
7078 enum pipe_control_flags non_lri_post_sync_flags
=
7079 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
7081 /* Recursive PIPE_CONTROL workarounds --------------------------------
7082 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
7084 * We do these first because we want to look at the original operation,
7085 * rather than any workarounds we set.
7087 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
7088 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
7089 * lists several workarounds:
7091 * "Project: SKL, KBL, BXT
7093 * If the VF Cache Invalidation Enable is set to a 1 in a
7094 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
7095 * sets to 0, with the VF Cache Invalidation Enable set to 0
7096 * needs to be sent prior to the PIPE_CONTROL with VF Cache
7097 * Invalidation Enable set to a 1."
7099 iris_emit_raw_pipe_control(batch
,
7100 "workaround: recursive VF cache invalidate",
7104 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
7105 * invalidates the instruction cache
7107 if (GEN_GEN
== 12 && (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
)) {
7108 iris_emit_raw_pipe_control(batch
,
7109 "workaround: CS stall before instruction "
7111 PIPE_CONTROL_CS_STALL
|
7112 PIPE_CONTROL_STALL_AT_SCOREBOARD
, bo
, offset
,
7116 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0*/)) &&
7117 IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
7118 /* Project: SKL / Argument: LRI Post Sync Operation [23]
7120 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
7121 * programmed prior to programming a PIPECONTROL command with "LRI
7122 * Post Sync Operation" in GPGPU mode of operation (i.e when
7123 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
7125 * The same text exists a few rows below for Post Sync Op.
7127 * On Gen12 this is GEN:BUG:1607156449.
7129 iris_emit_raw_pipe_control(batch
,
7130 "workaround: CS stall before gpgpu post-sync",
7131 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
7134 /* "Flush Types" workarounds ---------------------------------------------
7135 * We do these now because they may add post-sync operations or CS stalls.
7138 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
7139 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
7141 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
7142 * 'Write PS Depth Count' or 'Write Timestamp'."
7145 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
7146 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
7147 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
7148 bo
= batch
->screen
->workaround_address
.bo
;
7149 offset
= batch
->screen
->workaround_address
.offset
;
7153 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
7154 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
7156 * "This bit must be DISABLED for operations other than writing
7159 * This seems like nonsense. An Ivybridge workaround requires us to
7160 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
7161 * operation. Gen8+ requires us to emit depth stalls and depth cache
7162 * flushes together. So, it's hard to imagine this means anything other
7163 * than "we originally intended this to be used for PS_DEPTH_COUNT".
7165 * We ignore the supposed restriction and do nothing.
7169 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
7170 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
7171 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
7173 * "This bit must be DISABLED for End-of-pipe (Read) fences,
7174 * PS_DEPTH_COUNT or TIMESTAMP queries."
7176 * TODO: Implement end-of-pipe checking.
7178 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
7179 PIPE_CONTROL_WRITE_TIMESTAMP
)));
7182 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
7183 /* From the PIPE_CONTROL instruction table, bit 1:
7185 * "This bit is ignored if Depth Stall Enable is set.
7186 * Further, the render cache is not flushed even if Write Cache
7187 * Flush Enable bit is set."
7189 * We assert that the caller doesn't do this combination, to try and
7190 * prevent mistakes. It shouldn't hurt the GPU, though.
7192 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
7193 * and "Render Target Flush" combo is explicitly required for BTI
7194 * update workarounds.
7196 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
7197 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
7200 /* PIPE_CONTROL page workarounds ------------------------------------- */
7202 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
7203 /* From the PIPE_CONTROL page itself:
7206 * Restriction: Pipe_control with CS-stall bit set must be issued
7207 * before a pipe-control command that has the State Cache
7208 * Invalidate bit set."
7210 flags
|= PIPE_CONTROL_CS_STALL
;
7213 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
7214 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
7217 * SW must always program Post-Sync Operation to "Write Immediate
7218 * Data" when Flush LLC is set."
7220 * For now, we just require the caller to do it.
7222 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
7225 /* "Post-Sync Operation" workarounds -------------------------------- */
7227 /* Project: All / Argument: Global Snapshot Count Reset [19]
7229 * "This bit must not be exercised on any product.
7230 * Requires stall bit ([20] of DW1) set."
7232 * We don't use this, so we just assert that it isn't used. The
7233 * PIPE_CONTROL instruction page indicates that they intended this
7234 * as a debug feature and don't think it is useful in production,
7235 * but it may actually be usable, should we ever want to.
7237 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
7239 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
7240 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
7241 /* Project: All / Arguments:
7243 * - Generic Media State Clear [16]
7244 * - Indirect State Pointers Disable [16]
7246 * "Requires stall bit ([20] of DW1) set."
7248 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
7249 * State Clear) says:
7251 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
7252 * programmed prior to programming a PIPECONTROL command with "Media
7253 * State Clear" set in GPGPU mode of operation"
7255 * This is a subset of the earlier rule, so there's nothing to do.
7257 flags
|= PIPE_CONTROL_CS_STALL
;
7260 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
7261 /* Project: All / Argument: Store Data Index
7263 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
7266 * For now, we just assert that the caller does this. We might want to
7267 * automatically add a write to the workaround BO...
7269 assert(non_lri_post_sync_flags
!= 0);
7272 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
7273 /* Project: All / Argument: Sync GFDT
7275 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
7276 * than '0' or 0x2520[13] must be set."
7278 * For now, we just assert that the caller does this.
7280 assert(non_lri_post_sync_flags
!= 0);
7283 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
7284 /* Project: IVB+ / Argument: TLB inv
7286 * "Requires stall bit ([20] of DW1) set."
7288 * Also, from the PIPE_CONTROL instruction table:
7291 * Post Sync Operation or CS stall must be set to ensure a TLB
7292 * invalidation occurs. Otherwise no cycle will occur to the TLB
7293 * cache to invalidate."
7295 * This is not a subset of the earlier rule, so there's nothing to do.
7297 flags
|= PIPE_CONTROL_CS_STALL
;
7300 if (GEN_GEN
>= 12 && ((flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ||
7301 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
))) {
7302 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
7305 * Unified Cache (Tile Cache Disabled):
7307 * When the Color and Depth (Z) streams are enabled to be cached in
7308 * the DC space of L2, Software must use "Render Target Cache Flush
7309 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
7310 * Flush" for getting the color and depth (Z) write data to be
7311 * globally observable. In this mode of operation it is not required
7312 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
7314 flags
|= PIPE_CONTROL_TILE_CACHE_FLUSH
;
7317 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
7318 /* TODO: The big Skylake GT4 post sync op workaround */
7321 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
7323 if (IS_COMPUTE_PIPELINE(batch
)) {
7324 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
7325 /* Project: SKL+ / Argument: Tex Invalidate
7326 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
7328 flags
|= PIPE_CONTROL_CS_STALL
;
7331 if (GEN_GEN
== 8 && (post_sync_flags
||
7332 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
7333 PIPE_CONTROL_DEPTH_STALL
|
7334 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
7335 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
7336 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
7337 /* Project: BDW / Arguments:
7339 * - LRI Post Sync Operation [23]
7340 * - Post Sync Op [15:14]
7342 * - Depth Stall [13]
7343 * - Render Target Cache Flush [12]
7344 * - Depth Cache Flush [0]
7345 * - DC Flush Enable [5]
7347 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
7350 flags
|= PIPE_CONTROL_CS_STALL
;
7352 /* Also, from the PIPE_CONTROL instruction table, bit 20:
7355 * This bit must be always set when PIPE_CONTROL command is
7356 * programmed by GPGPU and MEDIA workloads, except for the cases
7357 * when only Read Only Cache Invalidation bits are set (State
7358 * Cache Invalidation Enable, Instruction cache Invalidation
7359 * Enable, Texture Cache Invalidation Enable, Constant Cache
7360 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
7361 * need not implemented when FF_DOP_CG is disable via "Fixed
7362 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
7364 * It sounds like we could avoid CS stalls in some cases, but we
7365 * don't currently bother. This list isn't exactly the list above,
7371 /* "Stall" workarounds ----------------------------------------------
7372 * These have to come after the earlier ones because we may have added
7373 * some additional CS stalls above.
7376 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
7377 /* Project: PRE-SKL, VLV, CHV
7379 * "[All Stepping][All SKUs]:
7381 * One of the following must also be set:
7383 * - Render Target Cache Flush Enable ([12] of DW1)
7384 * - Depth Cache Flush Enable ([0] of DW1)
7385 * - Stall at Pixel Scoreboard ([1] of DW1)
7386 * - Depth Stall ([13] of DW1)
7387 * - Post-Sync Operation ([13] of DW1)
7388 * - DC Flush Enable ([5] of DW1)"
7390 * If we don't already have one of those bits set, we choose to add
7391 * "Stall at Pixel Scoreboard". Some of the other bits require a
7392 * CS stall as a workaround (see above), which would send us into
7393 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
7394 * appears to be safe, so we choose that.
7396 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
7397 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
7398 PIPE_CONTROL_WRITE_IMMEDIATE
|
7399 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
7400 PIPE_CONTROL_WRITE_TIMESTAMP
|
7401 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
7402 PIPE_CONTROL_DEPTH_STALL
|
7403 PIPE_CONTROL_DATA_CACHE_FLUSH
;
7404 if (!(flags
& wa_bits
))
7405 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
7408 if (GEN_GEN
>= 12 && (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
)) {
7409 /* GEN:BUG:1409600907:
7411 * "PIPE_CONTROL with Depth Stall Enable bit must be set
7412 * with any PIPE_CONTROL with Depth Flush Enable bit set.
7414 flags
|= PIPE_CONTROL_DEPTH_STALL
;
7417 /* Emit --------------------------------------------------------------- */
7419 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
7421 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
7422 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
7423 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
7424 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
7425 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
7426 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
7427 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
7428 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
7429 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
7430 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
7431 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
7432 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
7433 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
7434 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
7435 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
7436 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
7437 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
7439 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
7441 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
7442 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
7443 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
7444 (flags
& PIPE_CONTROL_FLUSH_HDC
) ? "HDC " : "",
7448 batch_mark_sync_for_pipe_control(batch
, flags
);
7449 iris_batch_sync_region_start(batch
);
7451 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
7453 pc
.TileCacheFlushEnable
= flags
& PIPE_CONTROL_TILE_CACHE_FLUSH
;
7456 pc
.HDCPipelineFlushEnable
= flags
& PIPE_CONTROL_FLUSH_HDC
;
7458 pc
.LRIPostSyncOperation
= NoLRIOperation
;
7459 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
7460 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
7461 pc
.StoreDataIndex
= 0;
7462 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
7463 pc
.GlobalSnapshotCountReset
=
7464 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
7465 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
7466 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
7467 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
7468 pc
.RenderTargetCacheFlushEnable
=
7469 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
7470 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
7471 pc
.StateCacheInvalidationEnable
=
7472 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
7473 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
7474 pc
.ConstantCacheInvalidationEnable
=
7475 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
7476 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
7477 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
7478 pc
.InstructionCacheInvalidateEnable
=
7479 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
7480 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
7481 pc
.IndirectStatePointersDisable
=
7482 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
7483 pc
.TextureCacheInvalidationEnable
=
7484 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
7485 pc
.Address
= rw_bo(bo
, offset
, IRIS_DOMAIN_OTHER_WRITE
);
7486 pc
.ImmediateData
= imm
;
7489 iris_batch_sync_region_end(batch
);
7494 * Preemption on Gen9 has to be enabled or disabled in various cases.
7496 * See these workarounds for preemption:
7497 * - WaDisableMidObjectPreemptionForGSLineStripAdj
7498 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
7499 * - WaDisableMidObjectPreemptionForLineLoop
7502 * We don't put this in the vtable because it's only used on Gen9.
7505 gen9_toggle_preemption(struct iris_context
*ice
,
7506 struct iris_batch
*batch
,
7507 const struct pipe_draw_info
*draw
)
7509 struct iris_genx_state
*genx
= ice
->state
.genx
;
7510 bool object_preemption
= true;
7512 /* WaDisableMidObjectPreemptionForGSLineStripAdj
7514 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
7515 * and GS is enabled."
7517 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
7518 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
7519 object_preemption
= false;
7521 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
7523 * "TriFan miscompare in Execlist Preemption test. Cut index that is
7524 * on a previous context. End the previous, the resume another context
7525 * with a tri-fan or polygon, and the vertex count is corrupted. If we
7526 * prempt again we will cause corruption.
7528 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
7530 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
7531 object_preemption
= false;
7533 /* WaDisableMidObjectPreemptionForLineLoop
7535 * "VF Stats Counters Missing a vertex when preemption enabled.
7537 * WA: Disable mid-draw preemption when the draw uses a lineloop
7540 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
7541 object_preemption
= false;
7545 * "VF is corrupting GAFS data when preempted on an instance boundary
7546 * and replayed with instancing enabled.
7548 * WA: Disable preemption when using instanceing."
7550 if (draw
->instance_count
> 1)
7551 object_preemption
= false;
7553 if (genx
->object_preemption
!= object_preemption
) {
7554 iris_enable_obj_preemption(batch
, object_preemption
);
7555 genx
->object_preemption
= object_preemption
;
7561 iris_lost_genx_state(struct iris_context
*ice
, struct iris_batch
*batch
)
7563 struct iris_genx_state
*genx
= ice
->state
.genx
;
7565 memset(genx
->last_index_buffer
, 0, sizeof(genx
->last_index_buffer
));
7569 iris_emit_mi_report_perf_count(struct iris_batch
*batch
,
7571 uint32_t offset_in_bytes
,
7574 iris_batch_sync_region_start(batch
);
7575 iris_emit_cmd(batch
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
7576 mi_rpc
.MemoryAddress
= rw_bo(bo
, offset_in_bytes
,
7577 IRIS_DOMAIN_OTHER_WRITE
);
7578 mi_rpc
.ReportID
= report_id
;
7580 iris_batch_sync_region_end(batch
);
7584 * Update the pixel hashing modes that determine the balancing of PS threads
7585 * across subslices and slices.
7587 * \param width Width bound of the rendering area (already scaled down if \p
7588 * scale is greater than 1).
7589 * \param height Height bound of the rendering area (already scaled down if \p
7590 * scale is greater than 1).
7591 * \param scale The number of framebuffer samples that could potentially be
7592 * affected by an individual channel of the PS thread. This is
7593 * typically one for single-sampled rendering, but for operations
7594 * like CCS resolves and fast clears a single PS invocation may
7595 * update a huge number of pixels, in which case a finer
7596 * balancing is desirable in order to maximally utilize the
7597 * bandwidth available. UINT_MAX can be used as shorthand for
7598 * "finest hashing mode available".
7601 genX(emit_hashing_mode
)(struct iris_context
*ice
, struct iris_batch
*batch
,
7602 unsigned width
, unsigned height
, unsigned scale
)
7605 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
7606 const unsigned slice_hashing
[] = {
7607 /* Because all Gen9 platforms with more than one slice require
7608 * three-way subslice hashing, a single "normal" 16x16 slice hashing
7609 * block is guaranteed to suffer from substantial imbalance, with one
7610 * subslice receiving twice as much work as the other two in the
7613 * The performance impact of that would be particularly severe when
7614 * three-way hashing is also in use for slice balancing (which is the
7615 * case for all Gen9 GT4 platforms), because one of the slices
7616 * receives one every three 16x16 blocks in either direction, which
7617 * is roughly the periodicity of the underlying subslice imbalance
7618 * pattern ("roughly" because in reality the hardware's
7619 * implementation of three-way hashing doesn't do exact modulo 3
7620 * arithmetic, which somewhat decreases the magnitude of this effect
7621 * in practice). This leads to a systematic subslice imbalance
7622 * within that slice regardless of the size of the primitive. The
7623 * 32x32 hashing mode guarantees that the subslice imbalance within a
7624 * single slice hashing block is minimal, largely eliminating this
7628 /* Finest slice hashing mode available. */
7631 const unsigned subslice_hashing
[] = {
7632 /* 16x16 would provide a slight cache locality benefit especially
7633 * visible in the sampler L1 cache efficiency of low-bandwidth
7634 * non-LLC platforms, but it comes at the cost of greater subslice
7635 * imbalance for primitives of dimensions approximately intermediate
7636 * between 16x4 and 16x16.
7639 /* Finest subslice hashing mode available. */
7642 /* Dimensions of the smallest hashing block of a given hashing mode. If
7643 * the rendering area is smaller than this there can't possibly be any
7644 * benefit from switching to this mode, so we optimize out the
7647 const unsigned min_size
[][2] = {
7651 const unsigned idx
= scale
> 1;
7653 if (width
> min_size
[idx
][0] || height
> min_size
[idx
][1]) {
7656 iris_pack_state(GENX(GT_MODE
), >_mode
, reg
) {
7657 reg
.SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0);
7658 reg
.SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0);
7659 reg
.SubsliceHashing
= subslice_hashing
[idx
];
7660 reg
.SubsliceHashingMask
= -1;
7663 iris_emit_raw_pipe_control(batch
,
7664 "workaround: CS stall before GT_MODE LRI",
7665 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
7666 PIPE_CONTROL_CS_STALL
,
7669 iris_emit_lri(batch
, GT_MODE
, gt_mode
);
7671 ice
->state
.current_hash_scale
= scale
;
7677 iris_set_frontend_noop(struct pipe_context
*ctx
, bool enable
)
7679 struct iris_context
*ice
= (struct iris_context
*) ctx
;
7681 if (iris_batch_prepare_noop(&ice
->batches
[IRIS_BATCH_RENDER
], enable
)) {
7682 ice
->state
.dirty
|= IRIS_ALL_DIRTY_FOR_RENDER
;
7683 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_FOR_RENDER
;
7686 if (iris_batch_prepare_noop(&ice
->batches
[IRIS_BATCH_COMPUTE
], enable
)) {
7687 ice
->state
.dirty
|= IRIS_ALL_DIRTY_FOR_COMPUTE
;
7688 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE
;
7693 genX(init_state
)(struct iris_context
*ice
)
7695 struct pipe_context
*ctx
= &ice
->ctx
;
7696 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
7698 ctx
->create_blend_state
= iris_create_blend_state
;
7699 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
7700 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
7701 ctx
->create_sampler_state
= iris_create_sampler_state
;
7702 ctx
->create_sampler_view
= iris_create_sampler_view
;
7703 ctx
->create_surface
= iris_create_surface
;
7704 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
7705 ctx
->bind_blend_state
= iris_bind_blend_state
;
7706 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
7707 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
7708 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
7709 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
7710 ctx
->delete_blend_state
= iris_delete_state
;
7711 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
7712 ctx
->delete_rasterizer_state
= iris_delete_state
;
7713 ctx
->delete_sampler_state
= iris_delete_state
;
7714 ctx
->delete_vertex_elements_state
= iris_delete_state
;
7715 ctx
->set_blend_color
= iris_set_blend_color
;
7716 ctx
->set_clip_state
= iris_set_clip_state
;
7717 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
7718 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
7719 ctx
->set_shader_images
= iris_set_shader_images
;
7720 ctx
->set_sampler_views
= iris_set_sampler_views
;
7721 ctx
->set_compute_resources
= iris_set_compute_resources
;
7722 ctx
->set_tess_state
= iris_set_tess_state
;
7723 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
7724 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
7725 ctx
->set_sample_mask
= iris_set_sample_mask
;
7726 ctx
->set_scissor_states
= iris_set_scissor_states
;
7727 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
7728 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
7729 ctx
->set_viewport_states
= iris_set_viewport_states
;
7730 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
7731 ctx
->surface_destroy
= iris_surface_destroy
;
7732 ctx
->draw_vbo
= iris_draw_vbo
;
7733 ctx
->launch_grid
= iris_launch_grid
;
7734 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
7735 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
7736 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
7737 ctx
->set_frontend_noop
= iris_set_frontend_noop
;
7739 screen
->vtbl
.destroy_state
= iris_destroy_state
;
7740 screen
->vtbl
.init_render_context
= iris_init_render_context
;
7741 screen
->vtbl
.init_compute_context
= iris_init_compute_context
;
7742 screen
->vtbl
.upload_render_state
= iris_upload_render_state
;
7743 screen
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
7744 screen
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
7745 screen
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
7746 screen
->vtbl
.emit_mi_report_perf_count
= iris_emit_mi_report_perf_count
;
7747 screen
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
7748 screen
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
7749 screen
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
7750 screen
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
7751 screen
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
7752 screen
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
7753 screen
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
7754 screen
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
7755 screen
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
7756 screen
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
7757 screen
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
7758 screen
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
7759 screen
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
7760 screen
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
7761 screen
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
7762 screen
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
7763 screen
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
7764 screen
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
7765 screen
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
7766 screen
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
7767 screen
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
7768 screen
->vtbl
.lost_genx_state
= iris_lost_genx_state
;
7770 ice
->state
.dirty
= ~0ull;
7771 ice
->state
.stage_dirty
= ~0ull;
7773 ice
->state
.statistics_counters_enabled
= true;
7775 ice
->state
.sample_mask
= 0xffff;
7776 ice
->state
.num_viewports
= 1;
7777 ice
->state
.prim_mode
= PIPE_PRIM_MAX
;
7778 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
7779 ice
->draw
.derived_params
.drawid
= -1;
7781 /* Make a 1x1x1 null surface for unbound textures */
7782 void *null_surf_map
=
7783 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
7784 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
7785 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
7786 ice
->state
.unbound_tex
.offset
+=
7787 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
7789 /* Default all scissor rectangles to be empty regions. */
7790 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
7791 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
7792 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,