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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_defines.h"
106 #include "iris_pipe.h"
107 #include "iris_resource.h"
109 #define __gen_address_type struct iris_address
110 #define __gen_user_data struct iris_batch
112 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
115 __gen_combine_address(struct iris_batch
*batch
, void *location
,
116 struct iris_address addr
, uint32_t delta
)
118 uint64_t result
= addr
.offset
+ delta
;
121 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
122 /* Assume this is a general address, not relative to a base. */
123 result
+= addr
.bo
->gtt_offset
;
129 #define __genxml_cmd_length(cmd) cmd ## _length
130 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
131 #define __genxml_cmd_header(cmd) cmd ## _header
132 #define __genxml_cmd_pack(cmd) cmd ## _pack
134 #define _iris_pack_command(batch, cmd, dst, name) \
135 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
136 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
137 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
141 #define iris_pack_command(cmd, dst, name) \
142 _iris_pack_command(NULL, cmd, dst, name)
144 #define iris_pack_state(cmd, dst, name) \
145 for (struct cmd name = {}, \
146 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
147 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
150 #define iris_emit_cmd(batch, cmd, name) \
151 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
153 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
155 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
156 for (uint32_t i = 0; i < num_dwords; i++) \
157 dw[i] = (dwords0)[i] | (dwords1)[i]; \
158 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
161 #include "genxml/genX_pack.h"
162 #include "genxml/gen_macros.h"
163 #include "genxml/genX_bits.h"
166 #define MOCS_PTE 0x18
169 #define MOCS_PTE (1 << 1)
170 #define MOCS_WB (2 << 1)
174 mocs(const struct iris_bo
*bo
)
176 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
180 * Statically assert that PIPE_* enums match the hardware packets.
181 * (As long as they match, we don't need to translate them.)
183 UNUSED
static void pipe_asserts()
185 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
187 /* pipe_logicop happens to match the hardware. */
188 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
189 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
190 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
191 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
192 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
193 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
194 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
195 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
196 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
197 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
198 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
199 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
200 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
201 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
202 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
203 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
205 /* pipe_blend_func happens to match the hardware. */
206 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
212 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
213 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
214 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
215 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
216 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
217 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
218 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
219 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
220 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
221 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
222 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
223 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
224 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
226 /* pipe_blend_func happens to match the hardware. */
227 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
228 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
229 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
230 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
231 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
233 /* pipe_stencil_op happens to match the hardware. */
234 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
235 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
236 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
237 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
238 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
239 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
240 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
241 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
243 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
244 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
245 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
250 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
252 static const unsigned map
[] = {
253 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
254 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
255 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
256 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
257 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
258 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
259 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
260 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
261 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
262 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
263 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
264 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
265 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
266 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
267 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
270 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
274 translate_compare_func(enum pipe_compare_func pipe_func
)
276 static const unsigned map
[] = {
277 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
278 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
279 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
280 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
281 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
282 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
283 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
284 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
286 return map
[pipe_func
];
290 translate_shadow_func(enum pipe_compare_func pipe_func
)
292 /* Gallium specifies the result of shadow comparisons as:
294 * 1 if ref <op> texel,
299 * 0 if texel <op> ref,
302 * So we need to flip the operator and also negate.
304 static const unsigned map
[] = {
305 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
306 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
307 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
308 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
309 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
310 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
311 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
312 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
314 return map
[pipe_func
];
318 translate_cull_mode(unsigned pipe_face
)
320 static const unsigned map
[4] = {
321 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
322 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
323 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
324 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
326 return map
[pipe_face
];
330 translate_fill_mode(unsigned pipe_polymode
)
332 static const unsigned map
[4] = {
333 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
334 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
335 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
336 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
338 return map
[pipe_polymode
];
342 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
344 static const unsigned map
[] = {
345 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
346 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
347 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
349 return map
[pipe_mip
];
353 translate_wrap(unsigned pipe_wrap
)
355 static const unsigned map
[] = {
356 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
357 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
358 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
359 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
360 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
361 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
363 /* These are unsupported. */
364 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
365 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
367 return map
[pipe_wrap
];
370 static struct iris_address
371 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
373 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
374 * validation list at CSO creation time, instead of draw time.
376 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
379 static struct iris_address
380 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
382 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
383 * validation list at CSO creation time, instead of draw time.
385 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
389 * Allocate space for some indirect state.
391 * Return a pointer to the map (to fill it out) and a state ref (for
392 * referring to the state in GPU commands).
395 upload_state(struct u_upload_mgr
*uploader
,
396 struct iris_state_ref
*ref
,
401 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
406 * Stream out temporary/short-lived state.
408 * This allocates space, pins the BO, and includes the BO address in the
409 * returned offset (which works because all state lives in 32-bit memory
413 stream_state(struct iris_batch
*batch
,
414 struct u_upload_mgr
*uploader
,
415 struct pipe_resource
**out_res
,
418 uint32_t *out_offset
)
422 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
424 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
425 iris_use_pinned_bo(batch
, bo
, false);
427 *out_offset
+= iris_bo_offset_from_base_address(bo
);
433 * stream_state() + memcpy.
436 emit_state(struct iris_batch
*batch
,
437 struct u_upload_mgr
*uploader
,
438 struct pipe_resource
**out_res
,
445 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
448 memcpy(map
, data
, size
);
454 * Did field 'x' change between 'old_cso' and 'new_cso'?
456 * (If so, we may want to set some dirty flags.)
458 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
459 #define cso_changed_memcmp(x) \
460 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
463 flush_for_state_base_change(struct iris_batch
*batch
)
465 /* Flush before emitting STATE_BASE_ADDRESS.
467 * This isn't documented anywhere in the PRM. However, it seems to be
468 * necessary prior to changing the surface state base adress. We've
469 * seen issues in Vulkan where we get GPU hangs when using multi-level
470 * command buffers which clear depth, reset state base address, and then
473 * Normally, in GL, we would trust the kernel to do sufficient stalls
474 * and flushes prior to executing our batch. However, it doesn't seem
475 * as if the kernel's flushing is always sufficient and we don't want to
478 * We make this an end-of-pipe sync instead of a normal flush because we
479 * do not know the current status of the GPU. On Haswell at least,
480 * having a fast-clear operation in flight at the same time as a normal
481 * rendering operation can cause hangs. Since the kernel's flushing is
482 * insufficient, we need to ensure that any rendering operations from
483 * other processes are definitely complete before we try to do our own
484 * rendering. It's a bit of a big hammer but it appears to work.
486 iris_emit_end_of_pipe_sync(batch
,
487 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
488 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
489 PIPE_CONTROL_DATA_CACHE_FLUSH
);
493 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
495 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
496 lri
.RegisterOffset
= reg
;
500 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
503 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
505 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
506 lrr
.SourceRegisterAddress
= src
;
507 lrr
.DestinationRegisterAddress
= dst
;
512 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
514 #if GEN_GEN >= 8 && GEN_GEN < 10
515 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
517 * Software must clear the COLOR_CALC_STATE Valid field in
518 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
519 * with Pipeline Select set to GPGPU.
521 * The internal hardware docs recommend the same workaround for Gen9
524 if (pipeline
== GPGPU
)
525 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
529 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
530 * PIPELINE_SELECT [DevBWR+]":
534 * Software must ensure all the write caches are flushed through a
535 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
536 * command to invalidate read only caches prior to programming
537 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
539 iris_emit_pipe_control_flush(batch
,
540 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
541 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
542 PIPE_CONTROL_DATA_CACHE_FLUSH
|
543 PIPE_CONTROL_CS_STALL
);
545 iris_emit_pipe_control_flush(batch
,
546 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
547 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
548 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
549 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
551 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
555 sel
.PipelineSelection
= pipeline
;
560 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
565 * "This chicken bit works around a hardware issue with barrier
566 * logic encountered when switching between GPGPU and 3D pipelines.
567 * To workaround the issue, this mode bit should be set after a
568 * pipeline is selected."
571 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
572 reg
.GLKBarrierMode
= value
;
573 reg
.GLKBarrierModeMask
= 1;
575 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
580 init_state_base_address(struct iris_batch
*batch
)
582 flush_for_state_base_change(batch
);
584 /* We program most base addresses once at context initialization time.
585 * Each base address points at a 4GB memory zone, and never needs to
586 * change. See iris_bufmgr.h for a description of the memory zones.
588 * The one exception is Surface State Base Address, which needs to be
589 * updated occasionally. See iris_binder.c for the details there.
591 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
592 sba
.GeneralStateMOCS
= MOCS_WB
;
593 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
594 sba
.DynamicStateMOCS
= MOCS_WB
;
595 sba
.IndirectObjectMOCS
= MOCS_WB
;
596 sba
.InstructionMOCS
= MOCS_WB
;
598 sba
.GeneralStateBaseAddressModifyEnable
= true;
599 sba
.DynamicStateBaseAddressModifyEnable
= true;
600 sba
.IndirectObjectBaseAddressModifyEnable
= true;
601 sba
.InstructionBaseAddressModifyEnable
= true;
602 sba
.GeneralStateBufferSizeModifyEnable
= true;
603 sba
.DynamicStateBufferSizeModifyEnable
= true;
605 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
606 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
608 sba
.IndirectObjectBufferSizeModifyEnable
= true;
609 sba
.InstructionBuffersizeModifyEnable
= true;
611 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
612 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
614 sba
.GeneralStateBufferSize
= 0xfffff;
615 sba
.IndirectObjectBufferSize
= 0xfffff;
616 sba
.InstructionBufferSize
= 0xfffff;
617 sba
.DynamicStateBufferSize
= 0xfffff;
622 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
623 bool has_slm
, bool wants_dc_cache
)
626 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
627 reg
.SLMEnable
= has_slm
;
629 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
630 * in L3CNTLREG register. The default setting of the bit is not the
631 * desirable behavior.
633 reg
.ErrorDetectionBehaviorControl
= true;
635 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
636 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
637 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
638 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
640 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
644 iris_emit_default_l3_config(struct iris_batch
*batch
,
645 const struct gen_device_info
*devinfo
,
648 bool wants_dc_cache
= true;
649 bool has_slm
= compute
;
650 const struct gen_l3_weights w
=
651 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
652 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
653 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
658 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
662 /* A fixed function pipe flush is required before modifying this field */
663 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
665 /* enable object level preemption */
666 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
667 reg
.ReplayMode
= enable
;
668 reg
.ReplayModeMask
= true;
670 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
675 * Upload the initial GPU state for a render context.
677 * This sets some invariant state that needs to be programmed a particular
678 * way, but we never actually change.
681 iris_init_render_context(struct iris_screen
*screen
,
682 struct iris_batch
*batch
,
683 struct iris_vtable
*vtbl
,
684 struct pipe_debug_callback
*dbg
)
686 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
689 emit_pipeline_select(batch
, _3D
);
691 iris_emit_default_l3_config(batch
, devinfo
, false);
693 init_state_base_address(batch
);
696 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
697 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
698 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
700 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
702 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
703 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
704 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
706 iris_emit_lri(batch
, INSTPM
, reg_val
);
710 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
711 reg
.FloatBlendOptimizationEnable
= true;
712 reg
.FloatBlendOptimizationEnableMask
= true;
713 reg
.PartialResolveDisableInVC
= true;
714 reg
.PartialResolveDisableInVCMask
= true;
716 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
718 if (devinfo
->is_geminilake
)
719 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
723 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
724 reg
.HeaderlessMessageforPreemptableContexts
= 1;
725 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
727 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
729 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
730 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
731 reg
.EnabledTexelOffsetPrecisionFix
= 1;
732 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
734 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
736 /* WA_2204188704: Pixel Shader Panic dispatch must be disabled. */
737 iris_pack_state(GENX(COMMON_SLICE_CHICKEN3
), ®_val
, reg
) {
738 reg
.PSThreadPanicDispatch
= 0x3;
739 reg
.PSThreadPanicDispatchMask
= 0x3;
741 iris_emit_lri(batch
, COMMON_SLICE_CHICKEN3
, reg_val
);
743 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
744 reg
.StateCacheRedirectToCSSectionEnable
= true;
745 reg
.StateCacheRedirectToCSSectionEnableMask
= true;
747 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
753 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
754 * changing it dynamically. We set it to the maximum size here, and
755 * instead include the render target dimensions in the viewport, so
756 * viewport extents clipping takes care of pruning stray geometry.
758 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
759 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
760 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
763 /* Set the initial MSAA sample positions. */
764 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
765 GEN_SAMPLE_POS_1X(pat
._1xSample
);
766 GEN_SAMPLE_POS_2X(pat
._2xSample
);
767 GEN_SAMPLE_POS_4X(pat
._4xSample
);
768 GEN_SAMPLE_POS_8X(pat
._8xSample
);
770 GEN_SAMPLE_POS_16X(pat
._16xSample
);
774 /* Use the legacy AA line coverage computation. */
775 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
777 /* Disable chromakeying (it's for media) */
778 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
780 /* We want regular rendering, not special HiZ operations. */
781 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
783 /* No polygon stippling offsets are necessary. */
784 /* TODO: may need to set an offset for origin-UL framebuffers */
785 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
787 /* Set a static partitioning of the push constant area. */
788 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
789 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
790 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
791 alloc
._3DCommandSubOpcode
= 18 + i
;
792 alloc
.ConstantBufferOffset
= 6 * i
;
793 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
798 /* Gen11+ is enabled for us by the kernel. */
799 iris_enable_obj_preemption(batch
, true);
804 iris_init_compute_context(struct iris_screen
*screen
,
805 struct iris_batch
*batch
,
806 struct iris_vtable
*vtbl
,
807 struct pipe_debug_callback
*dbg
)
809 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
811 emit_pipeline_select(batch
, GPGPU
);
813 iris_emit_default_l3_config(batch
, devinfo
, true);
815 init_state_base_address(batch
);
818 if (devinfo
->is_geminilake
)
819 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
823 struct iris_vertex_buffer_state
{
824 /** The VERTEX_BUFFER_STATE hardware structure. */
825 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
827 /** The resource to source vertex data from. */
828 struct pipe_resource
*resource
;
831 struct iris_depth_buffer_state
{
832 /* Depth/HiZ/Stencil related hardware packets. */
833 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
834 GENX(3DSTATE_STENCIL_BUFFER_length
) +
835 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
836 GENX(3DSTATE_CLEAR_PARAMS_length
)];
840 * Generation-specific context state (ice->state.genx->...).
842 * Most state can go in iris_context directly, but these encode hardware
843 * packets which vary by generation.
845 struct iris_genx_state
{
846 struct iris_vertex_buffer_state vertex_buffers
[33];
848 struct iris_depth_buffer_state depth_buffer
;
850 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
853 /* Is object level preemption enabled? */
854 bool object_preemption
;
859 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
861 } shaders
[MESA_SHADER_STAGES
];
865 * The pipe->set_blend_color() driver hook.
867 * This corresponds to our COLOR_CALC_STATE.
870 iris_set_blend_color(struct pipe_context
*ctx
,
871 const struct pipe_blend_color
*state
)
873 struct iris_context
*ice
= (struct iris_context
*) ctx
;
875 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
876 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
877 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
881 * Gallium CSO for blend state (see pipe_blend_state).
883 struct iris_blend_state
{
884 /** Partial 3DSTATE_PS_BLEND */
885 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
887 /** Partial BLEND_STATE */
888 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
889 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
891 bool alpha_to_coverage
; /* for shader key */
893 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
894 uint8_t blend_enables
;
896 /** Bitfield of whether color writes are enabled for RT[i] */
897 uint8_t color_write_enables
;
899 /** Does RT[0] use dual color blending? */
900 bool dual_color_blending
;
903 static enum pipe_blendfactor
904 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
907 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
908 return PIPE_BLENDFACTOR_ONE
;
910 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
911 return PIPE_BLENDFACTOR_ZERO
;
918 * The pipe->create_blend_state() driver hook.
920 * Translates a pipe_blend_state into iris_blend_state.
923 iris_create_blend_state(struct pipe_context
*ctx
,
924 const struct pipe_blend_state
*state
)
926 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
927 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
929 cso
->blend_enables
= 0;
930 cso
->color_write_enables
= 0;
931 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
933 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
935 bool indep_alpha_blend
= false;
937 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
938 const struct pipe_rt_blend_state
*rt
=
939 &state
->rt
[state
->independent_blend_enable
? i
: 0];
941 enum pipe_blendfactor src_rgb
=
942 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
943 enum pipe_blendfactor src_alpha
=
944 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
945 enum pipe_blendfactor dst_rgb
=
946 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
947 enum pipe_blendfactor dst_alpha
=
948 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
950 if (rt
->rgb_func
!= rt
->alpha_func
||
951 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
952 indep_alpha_blend
= true;
954 if (rt
->blend_enable
)
955 cso
->blend_enables
|= 1u << i
;
958 cso
->color_write_enables
|= 1u << i
;
960 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
961 be
.LogicOpEnable
= state
->logicop_enable
;
962 be
.LogicOpFunction
= state
->logicop_func
;
964 be
.PreBlendSourceOnlyClampEnable
= false;
965 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
966 be
.PreBlendColorClampEnable
= true;
967 be
.PostBlendColorClampEnable
= true;
969 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
971 be
.ColorBlendFunction
= rt
->rgb_func
;
972 be
.AlphaBlendFunction
= rt
->alpha_func
;
973 be
.SourceBlendFactor
= src_rgb
;
974 be
.SourceAlphaBlendFactor
= src_alpha
;
975 be
.DestinationBlendFactor
= dst_rgb
;
976 be
.DestinationAlphaBlendFactor
= dst_alpha
;
978 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
979 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
980 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
981 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
983 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
986 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
987 /* pb.HasWriteableRT is filled in at draw time. */
988 /* pb.AlphaTestEnable is filled in at draw time. */
989 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
990 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
992 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
994 pb
.SourceBlendFactor
=
995 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
996 pb
.SourceAlphaBlendFactor
=
997 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
998 pb
.DestinationBlendFactor
=
999 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1000 pb
.DestinationAlphaBlendFactor
=
1001 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1004 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1005 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1006 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1007 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1008 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1009 bs
.ColorDitherEnable
= state
->dither
;
1010 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1013 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1019 * The pipe->bind_blend_state() driver hook.
1021 * Bind a blending CSO and flag related dirty bits.
1024 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1026 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1027 struct iris_blend_state
*cso
= state
;
1029 ice
->state
.cso_blend
= cso
;
1030 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1032 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1033 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1034 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1035 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1039 * Return true if the FS writes to any color outputs which are not disabled
1040 * via color masking.
1043 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1044 const struct shader_info
*fs_info
)
1049 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1051 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1052 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1054 return cso_blend
->color_write_enables
& rt_outputs
;
1058 * Gallium CSO for depth, stencil, and alpha testing state.
1060 struct iris_depth_stencil_alpha_state
{
1061 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1062 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1064 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1065 struct pipe_alpha_state alpha
;
1067 /** Outbound to resolve and cache set tracking. */
1068 bool depth_writes_enabled
;
1069 bool stencil_writes_enabled
;
1073 * The pipe->create_depth_stencil_alpha_state() driver hook.
1075 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1076 * testing state since we need pieces of it in a variety of places.
1079 iris_create_zsa_state(struct pipe_context
*ctx
,
1080 const struct pipe_depth_stencil_alpha_state
*state
)
1082 struct iris_depth_stencil_alpha_state
*cso
=
1083 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1085 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1087 cso
->alpha
= state
->alpha
;
1088 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1089 cso
->stencil_writes_enabled
=
1090 state
->stencil
[0].writemask
!= 0 ||
1091 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1093 /* The state tracker needs to optimize away EQUAL writes for us. */
1094 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1096 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1097 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1098 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1099 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1100 wmds
.StencilTestFunction
=
1101 translate_compare_func(state
->stencil
[0].func
);
1102 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1103 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1104 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1105 wmds
.BackfaceStencilTestFunction
=
1106 translate_compare_func(state
->stencil
[1].func
);
1107 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1108 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1109 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1110 wmds
.StencilBufferWriteEnable
=
1111 state
->stencil
[0].writemask
!= 0 ||
1112 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1113 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1114 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1115 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1116 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1117 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1118 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1119 /* wmds.[Backface]StencilReferenceValue are merged later */
1126 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1128 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1131 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1133 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1134 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1135 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1138 if (cso_changed(alpha
.ref_value
))
1139 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1141 if (cso_changed(alpha
.enabled
))
1142 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1144 if (cso_changed(alpha
.func
))
1145 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1147 if (cso_changed(depth_writes_enabled
))
1148 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1150 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1151 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1154 ice
->state
.cso_zsa
= new_cso
;
1155 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1156 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1157 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1161 * Gallium CSO for rasterizer state.
1163 struct iris_rasterizer_state
{
1164 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1165 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1166 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1167 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1168 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1170 uint8_t num_clip_plane_consts
;
1171 bool clip_halfz
; /* for CC_VIEWPORT */
1172 bool depth_clip_near
; /* for CC_VIEWPORT */
1173 bool depth_clip_far
; /* for CC_VIEWPORT */
1174 bool flatshade
; /* for shader state */
1175 bool flatshade_first
; /* for stream output */
1176 bool clamp_fragment_color
; /* for shader state */
1177 bool light_twoside
; /* for shader state */
1178 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1179 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1180 bool line_stipple_enable
;
1181 bool poly_stipple_enable
;
1183 bool force_persample_interp
;
1184 bool conservative_rasterization
;
1185 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1186 uint16_t sprite_coord_enable
;
1190 get_line_width(const struct pipe_rasterizer_state
*state
)
1192 float line_width
= state
->line_width
;
1194 /* From the OpenGL 4.4 spec:
1196 * "The actual width of non-antialiased lines is determined by rounding
1197 * the supplied width to the nearest integer, then clamping it to the
1198 * implementation-dependent maximum non-antialiased line width."
1200 if (!state
->multisample
&& !state
->line_smooth
)
1201 line_width
= roundf(state
->line_width
);
1203 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1204 /* For 1 pixel line thickness or less, the general anti-aliasing
1205 * algorithm gives up, and a garbage line is generated. Setting a
1206 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1207 * (one-pixel-wide), non-antialiased lines.
1209 * Lines rendered with zero Line Width are rasterized using the
1210 * "Grid Intersection Quantization" rules as specified by the
1211 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1220 * The pipe->create_rasterizer_state() driver hook.
1223 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1224 const struct pipe_rasterizer_state
*state
)
1226 struct iris_rasterizer_state
*cso
=
1227 malloc(sizeof(struct iris_rasterizer_state
));
1229 cso
->multisample
= state
->multisample
;
1230 cso
->force_persample_interp
= state
->force_persample_interp
;
1231 cso
->clip_halfz
= state
->clip_halfz
;
1232 cso
->depth_clip_near
= state
->depth_clip_near
;
1233 cso
->depth_clip_far
= state
->depth_clip_far
;
1234 cso
->flatshade
= state
->flatshade
;
1235 cso
->flatshade_first
= state
->flatshade_first
;
1236 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1237 cso
->light_twoside
= state
->light_twoside
;
1238 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1239 cso
->half_pixel_center
= state
->half_pixel_center
;
1240 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1241 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1242 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1243 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1244 cso
->conservative_rasterization
=
1245 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1247 if (state
->clip_plane_enable
!= 0)
1248 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1250 cso
->num_clip_plane_consts
= 0;
1252 float line_width
= get_line_width(state
);
1254 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1255 sf
.StatisticsEnable
= true;
1256 sf
.ViewportTransformEnable
= true;
1257 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1258 sf
.LineEndCapAntialiasingRegionWidth
=
1259 state
->line_smooth
? _10pixels
: _05pixels
;
1260 sf
.LastPixelEnable
= state
->line_last_pixel
;
1261 sf
.LineWidth
= line_width
;
1262 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1263 !state
->point_quad_rasterization
;
1264 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1265 sf
.PointWidth
= state
->point_size
;
1267 if (state
->flatshade_first
) {
1268 sf
.TriangleFanProvokingVertexSelect
= 1;
1270 sf
.TriangleStripListProvokingVertexSelect
= 2;
1271 sf
.TriangleFanProvokingVertexSelect
= 2;
1272 sf
.LineStripListProvokingVertexSelect
= 1;
1276 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1277 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1278 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1279 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1280 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1281 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1282 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1283 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1284 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1285 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1286 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1287 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1288 rr
.SmoothPointEnable
= state
->point_smooth
;
1289 rr
.AntialiasingEnable
= state
->line_smooth
;
1290 rr
.ScissorRectangleEnable
= state
->scissor
;
1292 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1293 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1294 rr
.ConservativeRasterizationEnable
=
1295 cso
->conservative_rasterization
;
1297 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1301 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1302 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1303 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1305 cl
.EarlyCullEnable
= true;
1306 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1307 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1308 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1309 cl
.GuardbandClipTestEnable
= true;
1310 cl
.ClipEnable
= true;
1311 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1312 cl
.MinimumPointWidth
= 0.125;
1313 cl
.MaximumPointWidth
= 255.875;
1315 if (state
->flatshade_first
) {
1316 cl
.TriangleFanProvokingVertexSelect
= 1;
1318 cl
.TriangleStripListProvokingVertexSelect
= 2;
1319 cl
.TriangleFanProvokingVertexSelect
= 2;
1320 cl
.LineStripListProvokingVertexSelect
= 1;
1324 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1325 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1326 * filled in at draw time from the FS program.
1328 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1329 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1330 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1331 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1332 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1335 /* Remap from 0..255 back to 1..256 */
1336 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1338 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1339 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1340 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1341 line
.LineStippleRepeatCount
= line_stipple_factor
;
1348 * The pipe->bind_rasterizer_state() driver hook.
1350 * Bind a rasterizer CSO and flag related dirty bits.
1353 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1355 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1356 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1357 struct iris_rasterizer_state
*new_cso
= state
;
1360 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1361 if (cso_changed_memcmp(line_stipple
))
1362 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1364 if (cso_changed(half_pixel_center
))
1365 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1367 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1368 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1370 if (cso_changed(rasterizer_discard
))
1371 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1373 if (cso_changed(flatshade_first
))
1374 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1376 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1377 cso_changed(clip_halfz
))
1378 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1380 if (cso_changed(sprite_coord_enable
) ||
1381 cso_changed(sprite_coord_mode
) ||
1382 cso_changed(light_twoside
))
1383 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1385 if (cso_changed(conservative_rasterization
))
1386 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1389 ice
->state
.cso_rast
= new_cso
;
1390 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1391 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1392 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1396 * Return true if the given wrap mode requires the border color to exist.
1398 * (We can skip uploading it if the sampler isn't going to use it.)
1401 wrap_mode_needs_border_color(unsigned wrap_mode
)
1403 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1407 * Gallium CSO for sampler state.
1409 struct iris_sampler_state
{
1410 union pipe_color_union border_color
;
1411 bool needs_border_color
;
1413 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1417 * The pipe->create_sampler_state() driver hook.
1419 * We fill out SAMPLER_STATE (except for the border color pointer), and
1420 * store that on the CPU. It doesn't make sense to upload it to a GPU
1421 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1422 * all bound sampler states to be in contiguous memor.
1425 iris_create_sampler_state(struct pipe_context
*ctx
,
1426 const struct pipe_sampler_state
*state
)
1428 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1433 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1434 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1436 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1437 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1438 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1440 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1442 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1443 wrap_mode_needs_border_color(wrap_t
) ||
1444 wrap_mode_needs_border_color(wrap_r
);
1446 float min_lod
= state
->min_lod
;
1447 unsigned mag_img_filter
= state
->mag_img_filter
;
1449 // XXX: explain this code ported from ilo...I don't get it at all...
1450 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1451 state
->min_lod
> 0.0f
) {
1453 mag_img_filter
= state
->min_img_filter
;
1456 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1457 samp
.TCXAddressControlMode
= wrap_s
;
1458 samp
.TCYAddressControlMode
= wrap_t
;
1459 samp
.TCZAddressControlMode
= wrap_r
;
1460 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1461 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1462 samp
.MinModeFilter
= state
->min_img_filter
;
1463 samp
.MagModeFilter
= mag_img_filter
;
1464 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1465 samp
.MaximumAnisotropy
= RATIO21
;
1467 if (state
->max_anisotropy
>= 2) {
1468 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1469 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1470 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1473 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1474 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1476 samp
.MaximumAnisotropy
=
1477 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1480 /* Set address rounding bits if not using nearest filtering. */
1481 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1482 samp
.UAddressMinFilterRoundingEnable
= true;
1483 samp
.VAddressMinFilterRoundingEnable
= true;
1484 samp
.RAddressMinFilterRoundingEnable
= true;
1487 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1488 samp
.UAddressMagFilterRoundingEnable
= true;
1489 samp
.VAddressMagFilterRoundingEnable
= true;
1490 samp
.RAddressMagFilterRoundingEnable
= true;
1493 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1494 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1496 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1498 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1499 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1500 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1501 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1503 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1510 * The pipe->bind_sampler_states() driver hook.
1513 iris_bind_sampler_states(struct pipe_context
*ctx
,
1514 enum pipe_shader_type p_stage
,
1515 unsigned start
, unsigned count
,
1518 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1519 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1520 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1522 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1524 for (int i
= 0; i
< count
; i
++) {
1525 shs
->samplers
[start
+ i
] = states
[i
];
1528 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1532 * Upload the sampler states into a contiguous area of GPU memory, for
1533 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1535 * Also fill out the border color state pointers.
1538 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1540 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1541 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1543 /* We assume the state tracker will call pipe->bind_sampler_states()
1544 * if the program's number of textures changes.
1546 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1551 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1552 * in the dynamic state memory zone, so we can point to it via the
1553 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1556 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1557 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1561 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1562 shs
->sampler_table
.offset
+=
1563 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1565 /* Make sure all land in the same BO */
1566 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1568 ice
->state
.need_border_colors
&= ~(1 << stage
);
1570 for (int i
= 0; i
< count
; i
++) {
1571 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1572 struct iris_sampler_view
*tex
= shs
->textures
[i
];
1575 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1576 } else if (!state
->needs_border_color
) {
1577 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1579 ice
->state
.need_border_colors
|= 1 << stage
;
1581 /* We may need to swizzle the border color for format faking.
1582 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
1583 * This means we need to move the border color's A channel into
1584 * the R or G channels so that those read swizzles will move it
1587 union pipe_color_union
*color
= &state
->border_color
;
1588 union pipe_color_union tmp
;
1590 enum pipe_format internal_format
= tex
->res
->internal_format
;
1592 if (util_format_is_alpha(internal_format
)) {
1593 unsigned char swz
[4] = {
1594 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
1595 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1597 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1599 } else if (util_format_is_luminance_alpha(internal_format
) &&
1600 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
1601 unsigned char swz
[4] = {
1602 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
1603 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1605 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1610 /* Stream out the border color and merge the pointer. */
1611 uint32_t offset
= iris_upload_border_color(ice
, color
);
1613 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1614 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1615 dyns
.BorderColorPointer
= offset
;
1618 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1619 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1622 map
+= GENX(SAMPLER_STATE_length
);
1626 static enum isl_channel_select
1627 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1630 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1631 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1632 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1633 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1634 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1635 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1636 default: unreachable("invalid swizzle");
1641 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1644 enum isl_format format
,
1645 struct isl_swizzle swizzle
,
1649 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1650 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1652 /* The ARB_texture_buffer_specification says:
1654 * "The number of texels in the buffer texture's texel array is given by
1656 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1658 * where <buffer_size> is the size of the buffer object, in basic
1659 * machine units and <components> and <base_type> are the element count
1660 * and base data type for elements, as specified in Table X.1. The
1661 * number of texels in the texel array is then clamped to the
1662 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1664 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1665 * so that when ISL divides by stride to obtain the number of texels, that
1666 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1668 unsigned final_size
=
1669 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1671 isl_buffer_fill_state(isl_dev
, map
,
1672 .address
= bo
->gtt_offset
+ offset
,
1673 .size_B
= final_size
,
1680 #define SURFACE_STATE_ALIGNMENT 64
1683 * Allocate several contiguous SURFACE_STATE structures, one for each
1684 * supported auxiliary surface mode.
1687 alloc_surface_states(struct u_upload_mgr
*mgr
,
1688 struct iris_state_ref
*ref
,
1689 unsigned aux_usages
)
1691 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1693 /* If this changes, update this to explicitly align pointers */
1694 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1696 assert(aux_usages
!= 0);
1699 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1700 SURFACE_STATE_ALIGNMENT
);
1702 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1708 fill_surface_state(struct isl_device
*isl_dev
,
1710 struct iris_resource
*res
,
1711 struct isl_view
*view
,
1714 struct isl_surf_fill_state_info f
= {
1717 .mocs
= mocs(res
->bo
),
1718 .address
= res
->bo
->gtt_offset
,
1721 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1722 f
.aux_surf
= &res
->aux
.surf
;
1723 f
.aux_usage
= aux_usage
;
1724 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1725 f
.clear_color
= res
->aux
.clear_color
;
1728 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1732 * The pipe->create_sampler_view() driver hook.
1734 static struct pipe_sampler_view
*
1735 iris_create_sampler_view(struct pipe_context
*ctx
,
1736 struct pipe_resource
*tex
,
1737 const struct pipe_sampler_view
*tmpl
)
1739 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1740 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1741 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1742 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1747 /* initialize base object */
1749 isv
->base
.context
= ctx
;
1750 isv
->base
.texture
= NULL
;
1751 pipe_reference_init(&isv
->base
.reference
, 1);
1752 pipe_resource_reference(&isv
->base
.texture
, tex
);
1754 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1755 struct iris_resource
*zres
, *sres
;
1756 const struct util_format_description
*desc
=
1757 util_format_description(tmpl
->format
);
1759 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1761 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1764 isv
->res
= (struct iris_resource
*) tex
;
1766 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1767 &isv
->surface_state
,
1768 isv
->res
->aux
.sampler_usages
);
1772 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1774 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1775 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1776 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1778 const struct iris_format_info fmt
=
1779 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1781 isv
->clear_color
= isv
->res
->aux
.clear_color
;
1783 isv
->view
= (struct isl_view
) {
1785 .swizzle
= (struct isl_swizzle
) {
1786 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1787 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1788 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1789 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1794 /* Fill out SURFACE_STATE for this view. */
1795 if (tmpl
->target
!= PIPE_BUFFER
) {
1796 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1797 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1798 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1799 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1800 isv
->view
.array_len
=
1801 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1803 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
1805 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1807 /* If we have a multisampled depth buffer, do not create a sampler
1808 * surface state with HiZ.
1810 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
,
1813 map
+= SURFACE_STATE_ALIGNMENT
;
1816 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1817 isv
->view
.format
, isv
->view
.swizzle
,
1818 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
1825 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1826 struct pipe_sampler_view
*state
)
1828 struct iris_sampler_view
*isv
= (void *) state
;
1829 pipe_resource_reference(&state
->texture
, NULL
);
1830 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1835 * The pipe->create_surface() driver hook.
1837 * In Gallium nomenclature, "surfaces" are a view of a resource that
1838 * can be bound as a render target or depth/stencil buffer.
1840 static struct pipe_surface
*
1841 iris_create_surface(struct pipe_context
*ctx
,
1842 struct pipe_resource
*tex
,
1843 const struct pipe_surface
*tmpl
)
1845 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1846 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1847 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1848 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1849 struct pipe_surface
*psurf
= &surf
->base
;
1850 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1855 pipe_reference_init(&psurf
->reference
, 1);
1856 pipe_resource_reference(&psurf
->texture
, tex
);
1857 psurf
->context
= ctx
;
1858 psurf
->format
= tmpl
->format
;
1859 psurf
->width
= tex
->width0
;
1860 psurf
->height
= tex
->height0
;
1861 psurf
->texture
= tex
;
1862 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1863 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1864 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1866 isl_surf_usage_flags_t usage
= 0;
1868 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1869 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1870 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1872 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1874 const struct iris_format_info fmt
=
1875 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1877 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1878 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1879 /* Framebuffer validation will reject this invalid case, but it
1880 * hasn't had the opportunity yet. In the meantime, we need to
1881 * avoid hitting ISL asserts about unsupported formats below.
1887 surf
->view
= (struct isl_view
) {
1889 .base_level
= tmpl
->u
.tex
.level
,
1891 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1892 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1893 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1897 surf
->clear_color
= res
->aux
.clear_color
;
1899 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1900 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1901 ISL_SURF_USAGE_STENCIL_BIT
))
1905 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1906 &surf
->surface_state
,
1907 res
->aux
.possible_usages
);
1911 unsigned aux_modes
= res
->aux
.possible_usages
;
1913 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1915 fill_surface_state(&screen
->isl_dev
, map
, res
, &surf
->view
, aux_usage
);
1917 map
+= SURFACE_STATE_ALIGNMENT
;
1925 fill_default_image_param(struct brw_image_param
*param
)
1927 memset(param
, 0, sizeof(*param
));
1928 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1929 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1930 * detailed explanation of these parameters.
1932 param
->swizzling
[0] = 0xff;
1933 param
->swizzling
[1] = 0xff;
1937 fill_buffer_image_param(struct brw_image_param
*param
,
1938 enum pipe_format pfmt
,
1941 const unsigned cpp
= util_format_get_blocksize(pfmt
);
1943 fill_default_image_param(param
);
1944 param
->size
[0] = size
/ cpp
;
1945 param
->stride
[0] = cpp
;
1948 #define isl_surf_fill_image_param(x, ...)
1949 #define fill_default_image_param(x, ...)
1950 #define fill_buffer_image_param(x, ...)
1954 * The pipe->set_shader_images() driver hook.
1957 iris_set_shader_images(struct pipe_context
*ctx
,
1958 enum pipe_shader_type p_stage
,
1959 unsigned start_slot
, unsigned count
,
1960 const struct pipe_image_view
*p_images
)
1962 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1963 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1964 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1965 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1966 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1968 struct iris_genx_state
*genx
= ice
->state
.genx
;
1969 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
1972 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
1974 for (unsigned i
= 0; i
< count
; i
++) {
1975 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
1977 if (p_images
&& p_images
[i
].resource
) {
1978 const struct pipe_image_view
*img
= &p_images
[i
];
1979 struct iris_resource
*res
= (void *) img
->resource
;
1981 // XXX: these are not retained forever, use a separate uploader?
1983 alloc_surface_states(ice
->state
.surface_uploader
,
1984 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
1989 iv
->base
.resource
= NULL
;
1990 pipe_resource_reference(&iv
->base
.resource
, &res
->base
);
1992 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
1994 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1996 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1997 enum isl_format isl_fmt
=
1998 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2000 bool untyped_fallback
= false;
2002 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2003 /* On Gen8, try to use typed surfaces reads (which support a
2004 * limited number of formats), and if not possible, fall back
2007 untyped_fallback
= GEN_GEN
== 8 &&
2008 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2010 if (untyped_fallback
)
2011 isl_fmt
= ISL_FORMAT_RAW
;
2013 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2016 if (res
->base
.target
!= PIPE_BUFFER
) {
2017 struct isl_view view
= {
2019 .base_level
= img
->u
.tex
.level
,
2021 .base_array_layer
= img
->u
.tex
.first_layer
,
2022 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2023 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2027 if (untyped_fallback
) {
2028 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
2029 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2032 /* Images don't support compression */
2033 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2035 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2037 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
, usage
);
2039 map
+= SURFACE_STATE_ALIGNMENT
;
2043 isl_surf_fill_image_param(&screen
->isl_dev
,
2044 &image_params
[start_slot
+ i
],
2047 util_range_add(&res
->valid_buffer_range
, img
->u
.buf
.offset
,
2048 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2050 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
2051 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2052 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2053 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2054 img
->format
, img
->u
.buf
.size
);
2057 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2058 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2059 fill_default_image_param(&image_params
[start_slot
+ i
]);
2063 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2065 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2066 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2068 /* Broadwell also needs brw_image_params re-uploaded */
2070 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2071 shs
->cbuf0_needs_upload
= true;
2077 * The pipe->set_sampler_views() driver hook.
2080 iris_set_sampler_views(struct pipe_context
*ctx
,
2081 enum pipe_shader_type p_stage
,
2082 unsigned start
, unsigned count
,
2083 struct pipe_sampler_view
**views
)
2085 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2086 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2087 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2089 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2091 for (unsigned i
= 0; i
< count
; i
++) {
2092 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2093 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2094 &shs
->textures
[start
+ i
], pview
);
2095 struct iris_sampler_view
*view
= (void *) pview
;
2097 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2098 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2102 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2104 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2105 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2109 * The pipe->set_tess_state() driver hook.
2112 iris_set_tess_state(struct pipe_context
*ctx
,
2113 const float default_outer_level
[4],
2114 const float default_inner_level
[2])
2116 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2117 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2119 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2120 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2122 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2123 shs
->cbuf0_needs_upload
= true;
2127 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2129 struct iris_surface
*surf
= (void *) p_surf
;
2130 pipe_resource_reference(&p_surf
->texture
, NULL
);
2131 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2136 iris_set_clip_state(struct pipe_context
*ctx
,
2137 const struct pipe_clip_state
*state
)
2139 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2140 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2142 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2144 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
2145 shs
->cbuf0_needs_upload
= true;
2149 * The pipe->set_polygon_stipple() driver hook.
2152 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2153 const struct pipe_poly_stipple
*state
)
2155 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2156 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2157 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2161 * The pipe->set_sample_mask() driver hook.
2164 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2166 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2168 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2169 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2171 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2172 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2176 * The pipe->set_scissor_states() driver hook.
2178 * This corresponds to our SCISSOR_RECT state structures. It's an
2179 * exact match, so we just store them, and memcpy them out later.
2182 iris_set_scissor_states(struct pipe_context
*ctx
,
2183 unsigned start_slot
,
2184 unsigned num_scissors
,
2185 const struct pipe_scissor_state
*rects
)
2187 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2189 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2190 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2191 /* If the scissor was out of bounds and got clamped to 0 width/height
2192 * at the bounds, the subtraction of 1 from maximums could produce a
2193 * negative number and thus not clip anything. Instead, just provide
2194 * a min > max scissor inside the bounds, which produces the expected
2197 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2198 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2201 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2202 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2203 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2208 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2212 * The pipe->set_stencil_ref() driver hook.
2214 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2217 iris_set_stencil_ref(struct pipe_context
*ctx
,
2218 const struct pipe_stencil_ref
*state
)
2220 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2221 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2223 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2225 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2229 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2231 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2235 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2236 float m00
, float m11
, float m30
, float m31
,
2237 float *xmin
, float *xmax
,
2238 float *ymin
, float *ymax
)
2240 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2241 * Strips and Fans documentation:
2243 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2244 * fixed-point "guardband" range supported by the rasterization hardware"
2248 * "In almost all circumstances, if an object’s vertices are actually
2249 * modified by this clamping (i.e., had X or Y coordinates outside of
2250 * the guardband extent the rendered object will not match the intended
2251 * result. Therefore software should take steps to ensure that this does
2252 * not happen - e.g., by clipping objects such that they do not exceed
2253 * these limits after the Drawing Rectangle is applied."
2255 * I believe the fundamental restriction is that the rasterizer (in
2256 * the SF/WM stages) have a limit on the number of pixels that can be
2257 * rasterized. We need to ensure any coordinates beyond the rasterizer
2258 * limit are handled by the clipper. So effectively that limit becomes
2259 * the clipper's guardband size.
2261 * It goes on to say:
2263 * "In addition, in order to be correctly rendered, objects must have a
2264 * screenspace bounding box not exceeding 8K in the X or Y direction.
2265 * This additional restriction must also be comprehended by software,
2266 * i.e., enforced by use of clipping."
2268 * This makes no sense. Gen7+ hardware supports 16K render targets,
2269 * and you definitely need to be able to draw polygons that fill the
2270 * surface. Our assumption is that the rasterizer was limited to 8K
2271 * on Sandybridge, which only supports 8K surfaces, and it was actually
2272 * increased to 16K on Ivybridge and later.
2274 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2276 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2278 if (m00
!= 0 && m11
!= 0) {
2279 /* First, we compute the screen-space render area */
2280 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2281 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2282 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2283 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2285 /* We want the guardband to be centered on that */
2286 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2287 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2288 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2289 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2291 /* Now we need it in native device coordinates */
2292 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2293 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2294 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2295 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2297 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2298 * flipped upside-down. X should be fine though.
2300 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2301 *xmin
= ndc_gb_xmin
;
2302 *xmax
= ndc_gb_xmax
;
2303 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2304 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2306 /* The viewport scales to 0, so nothing will be rendered. */
2315 * The pipe->set_viewport_states() driver hook.
2317 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2318 * the guardband yet, as we need the framebuffer dimensions, but we can
2319 * at least fill out the rest.
2322 iris_set_viewport_states(struct pipe_context
*ctx
,
2323 unsigned start_slot
,
2325 const struct pipe_viewport_state
*states
)
2327 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2329 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2331 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2333 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2334 !ice
->state
.cso_rast
->depth_clip_far
))
2335 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2339 * The pipe->set_framebuffer_state() driver hook.
2341 * Sets the current draw FBO, including color render targets, depth,
2342 * and stencil buffers.
2345 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2346 const struct pipe_framebuffer_state
*state
)
2348 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2349 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2350 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2351 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2352 struct iris_resource
*zres
;
2353 struct iris_resource
*stencil_res
;
2355 unsigned samples
= util_framebuffer_get_num_samples(state
);
2356 unsigned layers
= util_framebuffer_get_num_layers(state
);
2358 if (cso
->samples
!= samples
) {
2359 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2362 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2363 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2366 if ((cso
->layers
== 0) != (layers
== 0)) {
2367 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2370 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2371 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2374 util_copy_framebuffer_state(cso
, state
);
2375 cso
->samples
= samples
;
2376 cso
->layers
= layers
;
2378 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2380 struct isl_view view
= {
2383 .base_array_layer
= 0,
2385 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2388 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2391 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2394 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2395 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2397 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2400 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2402 info
.depth_surf
= &zres
->surf
;
2403 info
.depth_address
= zres
->bo
->gtt_offset
;
2404 info
.mocs
= mocs(zres
->bo
);
2406 view
.format
= zres
->surf
.format
;
2408 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2409 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2410 info
.hiz_surf
= &zres
->aux
.surf
;
2411 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
;
2416 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2417 info
.stencil_surf
= &stencil_res
->surf
;
2418 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2420 view
.format
= stencil_res
->surf
.format
;
2421 info
.mocs
= mocs(stencil_res
->bo
);
2426 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2428 /* Make a null surface for unbound buffers */
2429 void *null_surf_map
=
2430 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2431 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2432 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2433 isl_extent3d(MAX2(cso
->width
, 1),
2434 MAX2(cso
->height
, 1),
2435 cso
->layers
? cso
->layers
: 1));
2436 ice
->state
.null_fb
.offset
+=
2437 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2439 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2441 /* Render target change */
2442 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2444 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2446 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2449 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2450 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2452 /* The PIPE_CONTROL command description says:
2454 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2455 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2456 * Target Cache Flush by enabling this bit. When render target flush
2457 * is set due to new association of BTI, PS Scoreboard Stall bit must
2458 * be set in this packet."
2460 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2461 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2462 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2463 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2468 upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
2469 struct pipe_shader_buffer
*buf
,
2470 struct iris_state_ref
*surf_state
,
2473 struct pipe_context
*ctx
= &ice
->ctx
;
2474 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2476 // XXX: these are not retained forever, use a separate uploader?
2478 upload_state(ice
->state
.surface_uploader
, surf_state
,
2479 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2480 if (!unlikely(map
)) {
2481 surf_state
->res
= NULL
;
2485 struct iris_resource
*res
= (void *) buf
->buffer
;
2486 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
2487 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
2489 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2490 .address
= res
->bo
->gtt_offset
+ buf
->buffer_offset
,
2491 .size_B
= buf
->buffer_size
,
2492 .format
= ssbo
? ISL_FORMAT_RAW
2493 : ISL_FORMAT_R32G32B32A32_FLOAT
,
2494 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2496 .mocs
= mocs(res
->bo
))
2501 * The pipe->set_constant_buffer() driver hook.
2503 * This uploads any constant data in user buffers, and references
2504 * any UBO resources containing constant data.
2507 iris_set_constant_buffer(struct pipe_context
*ctx
,
2508 enum pipe_shader_type p_stage
, unsigned index
,
2509 const struct pipe_constant_buffer
*input
)
2511 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2512 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2513 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2514 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
2516 if (input
&& input
->buffer
) {
2517 shs
->bound_cbufs
|= 1u << index
;
2521 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
2522 cbuf
->buffer_offset
= input
->buffer_offset
;
2524 MIN2(input
->buffer_size
,
2525 iris_resource_bo(input
->buffer
)->size
- cbuf
->buffer_offset
);
2527 struct iris_resource
*res
= (void *) cbuf
->buffer
;
2528 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2530 upload_ubo_ssbo_surf_state(ice
, cbuf
, &shs
->constbuf_surf_state
[index
],
2533 shs
->bound_cbufs
&= ~(1u << index
);
2534 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2535 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
2540 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2542 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2544 shs
->cbuf0_needs_upload
= true;
2547 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2548 // XXX: maybe not necessary all the time...?
2549 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2550 // XXX: pull model we may need actual new bindings...
2551 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2555 upload_uniforms(struct iris_context
*ice
,
2556 gl_shader_stage stage
)
2558 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
2559 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2560 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[0];
2561 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2563 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2564 shs
->cbuf0
.buffer_size
;
2566 if (upload_size
== 0)
2569 uint32_t *map
= NULL
;
2570 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
2571 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2573 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2574 uint32_t sysval
= shader
->system_values
[i
];
2577 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2579 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2580 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2581 struct brw_image_param
*param
=
2582 &genx
->shaders
[stage
].image_param
[img
];
2584 assert(offset
< sizeof(struct brw_image_param
));
2585 value
= ((uint32_t *) param
)[offset
];
2587 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2589 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2590 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2591 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2592 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2593 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2594 if (stage
== MESA_SHADER_TESS_CTRL
) {
2595 value
= ice
->state
.vertices_per_patch
;
2597 assert(stage
== MESA_SHADER_TESS_EVAL
);
2598 const struct shader_info
*tcs_info
=
2599 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2601 value
= tcs_info
->tess
.tcs_vertices_out
;
2603 value
= ice
->state
.vertices_per_patch
;
2605 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
2606 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
2607 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
2608 value
= fui(ice
->state
.default_outer_level
[i
]);
2609 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
2610 value
= fui(ice
->state
.default_inner_level
[0]);
2611 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
2612 value
= fui(ice
->state
.default_inner_level
[1]);
2614 assert(!"unhandled system value");
2620 if (shs
->cbuf0
.user_buffer
) {
2621 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2624 cbuf
->buffer_size
= upload_size
;
2625 upload_ubo_ssbo_surf_state(ice
, cbuf
, &shs
->constbuf_surf_state
[0], false);
2629 * The pipe->set_shader_buffers() driver hook.
2631 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2632 * SURFACE_STATE here, as the buffer offset may change each time.
2635 iris_set_shader_buffers(struct pipe_context
*ctx
,
2636 enum pipe_shader_type p_stage
,
2637 unsigned start_slot
, unsigned count
,
2638 const struct pipe_shader_buffer
*buffers
,
2639 unsigned writable_bitmask
)
2641 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2642 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2643 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2645 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
2647 shs
->bound_ssbos
&= ~modified_bits
;
2648 shs
->writable_ssbos
&= ~modified_bits
;
2649 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
2651 for (unsigned i
= 0; i
< count
; i
++) {
2652 if (buffers
&& buffers
[i
].buffer
) {
2653 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
2654 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
2655 struct iris_state_ref
*surf_state
=
2656 &shs
->ssbo_surf_state
[start_slot
+ i
];
2657 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
2658 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
2660 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
2662 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
2664 upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
2666 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2668 util_range_add(&res
->valid_buffer_range
, ssbo
->buffer_offset
,
2669 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
2671 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
2672 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
2677 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2681 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2687 * The pipe->set_vertex_buffers() driver hook.
2689 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2692 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2693 unsigned start_slot
, unsigned count
,
2694 const struct pipe_vertex_buffer
*buffers
)
2696 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2697 struct iris_genx_state
*genx
= ice
->state
.genx
;
2699 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2701 for (unsigned i
= 0; i
< count
; i
++) {
2702 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2703 struct iris_vertex_buffer_state
*state
=
2704 &genx
->vertex_buffers
[start_slot
+ i
];
2707 pipe_resource_reference(&state
->resource
, NULL
);
2711 /* We may see user buffers that are NULL bindings. */
2712 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
2714 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2715 struct iris_resource
*res
= (void *) state
->resource
;
2718 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2719 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2722 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2723 vb
.VertexBufferIndex
= start_slot
+ i
;
2724 vb
.AddressModifyEnable
= true;
2725 vb
.BufferPitch
= buffer
->stride
;
2727 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
2728 vb
.BufferStartingAddress
=
2729 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2730 vb
.MOCS
= mocs(res
->bo
);
2732 vb
.NullVertexBuffer
= true;
2737 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2741 * Gallium CSO for vertex elements.
2743 struct iris_vertex_element_state
{
2744 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2745 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2746 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2747 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2752 * The pipe->create_vertex_elements() driver hook.
2754 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2755 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2756 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2757 * needed. In these cases we will need information available at draw time.
2758 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2759 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2760 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2763 iris_create_vertex_elements(struct pipe_context
*ctx
,
2765 const struct pipe_vertex_element
*state
)
2767 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2768 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2769 struct iris_vertex_element_state
*cso
=
2770 malloc(sizeof(struct iris_vertex_element_state
));
2774 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2776 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2779 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2780 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2783 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2785 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2786 ve
.Component0Control
= VFCOMP_STORE_0
;
2787 ve
.Component1Control
= VFCOMP_STORE_0
;
2788 ve
.Component2Control
= VFCOMP_STORE_0
;
2789 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2792 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2796 for (int i
= 0; i
< count
; i
++) {
2797 const struct iris_format_info fmt
=
2798 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2799 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2800 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2802 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2803 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
2804 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
2805 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
2807 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2808 : VFCOMP_STORE_1_FP
;
2811 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2812 ve
.EdgeFlagEnable
= false;
2813 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2815 ve
.SourceElementOffset
= state
[i
].src_offset
;
2816 ve
.SourceElementFormat
= fmt
.fmt
;
2817 ve
.Component0Control
= comp
[0];
2818 ve
.Component1Control
= comp
[1];
2819 ve
.Component2Control
= comp
[2];
2820 ve
.Component3Control
= comp
[3];
2823 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2824 vi
.VertexElementIndex
= i
;
2825 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2826 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2829 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2830 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2833 /* An alternative version of the last VE and VFI is stored so it
2834 * can be used at draw time in case Vertex Shader uses EdgeFlag
2837 const unsigned edgeflag_index
= count
- 1;
2838 const struct iris_format_info fmt
=
2839 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
2840 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
2841 ve
.EdgeFlagEnable
= true ;
2842 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
2844 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
2845 ve
.SourceElementFormat
= fmt
.fmt
;
2846 ve
.Component0Control
= VFCOMP_STORE_SRC
;
2847 ve
.Component1Control
= VFCOMP_STORE_0
;
2848 ve
.Component2Control
= VFCOMP_STORE_0
;
2849 ve
.Component3Control
= VFCOMP_STORE_0
;
2851 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
2852 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
2853 * at draw time, as it should change if SGVs are emitted.
2855 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
2856 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
2864 * The pipe->bind_vertex_elements_state() driver hook.
2867 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2869 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2870 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2871 struct iris_vertex_element_state
*new_cso
= state
;
2873 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2874 * we need to re-emit it to ensure we're overriding the right one.
2876 if (new_cso
&& cso_changed(count
))
2877 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2879 ice
->state
.cso_vertex_elements
= state
;
2880 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2884 * The pipe->create_stream_output_target() driver hook.
2886 * "Target" here refers to a destination buffer. We translate this into
2887 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2888 * know which buffer this represents, or whether we ought to zero the
2889 * write-offsets, or append. Those are handled in the set() hook.
2891 static struct pipe_stream_output_target
*
2892 iris_create_stream_output_target(struct pipe_context
*ctx
,
2893 struct pipe_resource
*p_res
,
2894 unsigned buffer_offset
,
2895 unsigned buffer_size
)
2897 struct iris_resource
*res
= (void *) p_res
;
2898 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2902 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2904 pipe_reference_init(&cso
->base
.reference
, 1);
2905 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2906 cso
->base
.buffer_offset
= buffer_offset
;
2907 cso
->base
.buffer_size
= buffer_size
;
2908 cso
->base
.context
= ctx
;
2910 util_range_add(&res
->valid_buffer_range
, buffer_offset
,
2911 buffer_offset
+ buffer_size
);
2913 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2919 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2920 struct pipe_stream_output_target
*state
)
2922 struct iris_stream_output_target
*cso
= (void *) state
;
2924 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2925 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2931 * The pipe->set_stream_output_targets() driver hook.
2933 * At this point, we know which targets are bound to a particular index,
2934 * and also whether we want to append or start over. We can finish the
2935 * 3DSTATE_SO_BUFFER packets we started earlier.
2938 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2939 unsigned num_targets
,
2940 struct pipe_stream_output_target
**targets
,
2941 const unsigned *offsets
)
2943 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2944 struct iris_genx_state
*genx
= ice
->state
.genx
;
2945 uint32_t *so_buffers
= genx
->so_buffers
;
2947 const bool active
= num_targets
> 0;
2948 if (ice
->state
.streamout_active
!= active
) {
2949 ice
->state
.streamout_active
= active
;
2950 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2952 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2953 * it's a non-pipelined command. If we're switching streamout on, we
2954 * may have missed emitting it earlier, so do so now. (We're already
2955 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2958 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2961 for (int i
= 0; i
< 4; i
++) {
2962 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2963 i
< num_targets
? targets
[i
] : NULL
);
2966 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2970 for (unsigned i
= 0; i
< 4; i
++,
2971 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2973 if (i
>= num_targets
|| !targets
[i
]) {
2974 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2975 sob
.SOBufferIndex
= i
;
2979 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2980 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2982 /* Note that offsets[i] will either be 0, causing us to zero
2983 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2984 * "continue appending at the existing offset."
2986 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2988 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
2989 sob
.SurfaceBaseAddress
=
2990 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
2991 sob
.SOBufferEnable
= true;
2992 sob
.StreamOffsetWriteEnable
= true;
2993 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2994 sob
.MOCS
= mocs(res
->bo
);
2996 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
2998 sob
.SOBufferIndex
= i
;
2999 sob
.StreamOffset
= offsets
[i
];
3000 sob
.StreamOutputBufferOffsetAddress
=
3001 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3002 tgt
->offset
.offset
);
3006 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3010 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3011 * 3DSTATE_STREAMOUT packets.
3013 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3014 * hardware to record. We can create it entirely based on the shader, with
3015 * no dynamic state dependencies.
3017 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3018 * state-based settings. We capture the shader-related ones here, and merge
3019 * the rest in at draw time.
3022 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3023 const struct brw_vue_map
*vue_map
)
3025 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3026 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3027 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3028 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3030 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3032 memset(so_decl
, 0, sizeof(so_decl
));
3034 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3035 * command feels strange -- each dword pair contains a SO_DECL per stream.
3037 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3038 const struct pipe_stream_output
*output
= &info
->output
[i
];
3039 const int buffer
= output
->output_buffer
;
3040 const int varying
= output
->register_index
;
3041 const unsigned stream_id
= output
->stream
;
3042 assert(stream_id
< MAX_VERTEX_STREAMS
);
3044 buffer_mask
[stream_id
] |= 1 << buffer
;
3046 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3048 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3049 * array. Instead, it simply increments DstOffset for the following
3050 * input by the number of components that should be skipped.
3052 * Our hardware is unusual in that it requires us to program SO_DECLs
3053 * for fake "hole" components, rather than simply taking the offset
3054 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3055 * program as many size = 4 holes as we can, then a final hole to
3056 * accommodate the final 1, 2, or 3 remaining.
3058 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3060 while (skip_components
> 0) {
3061 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3063 .OutputBufferSlot
= output
->output_buffer
,
3064 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3066 skip_components
-= 4;
3069 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3071 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3072 .OutputBufferSlot
= output
->output_buffer
,
3073 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3075 ((1 << output
->num_components
) - 1) << output
->start_component
,
3078 if (decls
[stream_id
] > max_decls
)
3079 max_decls
= decls
[stream_id
];
3082 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3083 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3084 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3086 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3087 int urb_entry_read_offset
= 0;
3088 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3089 urb_entry_read_offset
;
3091 /* We always read the whole vertex. This could be reduced at some
3092 * point by reading less and offsetting the register index in the
3095 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3096 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3097 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3098 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3099 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3100 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3101 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3102 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3104 /* Set buffer pitches; 0 means unbound. */
3105 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3106 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3107 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3108 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3111 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3112 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3113 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3114 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3115 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3116 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3117 list
.NumEntries0
= decls
[0];
3118 list
.NumEntries1
= decls
[1];
3119 list
.NumEntries2
= decls
[2];
3120 list
.NumEntries3
= decls
[3];
3123 for (int i
= 0; i
< max_decls
; i
++) {
3124 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3125 entry
.Stream0Decl
= so_decl
[0][i
];
3126 entry
.Stream1Decl
= so_decl
[1][i
];
3127 entry
.Stream2Decl
= so_decl
[2][i
];
3128 entry
.Stream3Decl
= so_decl
[3][i
];
3136 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3137 const struct brw_vue_map
*last_vue_map
,
3138 bool two_sided_color
,
3139 unsigned *out_offset
,
3140 unsigned *out_length
)
3142 /* The compiler computes the first URB slot without considering COL/BFC
3143 * swizzling (because it doesn't know whether it's enabled), so we need
3144 * to do that here too. This may result in a smaller offset, which
3147 const unsigned first_slot
=
3148 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3150 /* This becomes the URB read offset (counted in pairs of slots). */
3151 assert(first_slot
% 2 == 0);
3152 *out_offset
= first_slot
/ 2;
3154 /* We need to adjust the inputs read to account for front/back color
3155 * swizzling, as it can make the URB length longer.
3157 for (int c
= 0; c
<= 1; c
++) {
3158 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3159 /* If two sided color is enabled, the fragment shader's gl_Color
3160 * (COL0) input comes from either the gl_FrontColor (COL0) or
3161 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3163 if (two_sided_color
)
3164 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3166 /* If front color isn't written, we opt to give them back color
3167 * instead of an undefined value. Switch from COL to BFC.
3169 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3170 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3171 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3176 /* Compute the minimum URB Read Length necessary for the FS inputs.
3178 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3179 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3181 * "This field should be set to the minimum length required to read the
3182 * maximum source attribute. The maximum source attribute is indicated
3183 * by the maximum value of the enabled Attribute # Source Attribute if
3184 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3185 * enable is not set.
3186 * read_length = ceiling((max_source_attr + 1) / 2)
3188 * [errata] Corruption/Hang possible if length programmed larger than
3191 * Similar text exists for Ivy Bridge.
3193 * We find the last URB slot that's actually read by the FS.
3195 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3196 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3197 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3200 /* The URB read length is the difference of the two, counted in pairs. */
3201 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3205 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3206 const struct iris_context
*ice
,
3207 unsigned urb_read_offset
,
3208 unsigned sprite_coord_enables
)
3210 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3211 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3212 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3213 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3214 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3216 /* XXX: this should be generated when putting programs in place */
3218 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3219 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3220 if (input_index
< 0 || input_index
>= 16)
3223 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3224 &attr_overrides
[input_index
];
3225 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3227 /* Viewport and Layer are stored in the VUE header. We need to override
3228 * them to zero if earlier stages didn't write them, as GL requires that
3229 * they read back as zero when not explicitly set.
3232 case VARYING_SLOT_VIEWPORT
:
3233 case VARYING_SLOT_LAYER
:
3234 attr
->ComponentOverrideX
= true;
3235 attr
->ComponentOverrideW
= true;
3236 attr
->ConstantSource
= CONST_0000
;
3238 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3239 attr
->ComponentOverrideY
= true;
3240 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3241 attr
->ComponentOverrideZ
= true;
3244 case VARYING_SLOT_PRIMITIVE_ID
:
3245 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3247 attr
->ComponentOverrideX
= true;
3248 attr
->ComponentOverrideY
= true;
3249 attr
->ComponentOverrideZ
= true;
3250 attr
->ComponentOverrideW
= true;
3251 attr
->ConstantSource
= PRIM_ID
;
3259 if (sprite_coord_enables
& (1 << input_index
))
3262 /* If there was only a back color written but not front, use back
3263 * as the color instead of undefined.
3265 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3266 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3267 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3268 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3270 /* Not written by the previous stage - undefined. */
3272 attr
->ComponentOverrideX
= true;
3273 attr
->ComponentOverrideY
= true;
3274 attr
->ComponentOverrideZ
= true;
3275 attr
->ComponentOverrideW
= true;
3276 attr
->ConstantSource
= CONST_0001_FLOAT
;
3280 /* Compute the location of the attribute relative to the read offset,
3281 * which is counted in 256-bit increments (two 128-bit VUE slots).
3283 const int source_attr
= slot
- 2 * urb_read_offset
;
3284 assert(source_attr
>= 0 && source_attr
<= 32);
3285 attr
->SourceAttribute
= source_attr
;
3287 /* If we are doing two-sided color, and the VUE slot following this one
3288 * represents a back-facing color, then we need to instruct the SF unit
3289 * to do back-facing swizzling.
3291 if (cso_rast
->light_twoside
&&
3292 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3293 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3294 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3295 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3296 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3299 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3300 for (int i
= 0; i
< 16; i
++)
3301 sbes
.Attribute
[i
] = attr_overrides
[i
];
3306 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3307 const struct iris_rasterizer_state
*cso
)
3309 unsigned overrides
= 0;
3311 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3312 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3314 for (int i
= 0; i
< 8; i
++) {
3315 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3316 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3317 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3324 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3326 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3327 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3328 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3329 const struct shader_info
*fs_info
=
3330 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3332 unsigned urb_read_offset
, urb_read_length
;
3333 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3334 ice
->shaders
.last_vue_map
,
3335 cso_rast
->light_twoside
,
3336 &urb_read_offset
, &urb_read_length
);
3338 unsigned sprite_coord_overrides
=
3339 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3341 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3342 sbe
.AttributeSwizzleEnable
= true;
3343 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3344 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3345 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3346 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3347 sbe
.ForceVertexURBEntryReadOffset
= true;
3348 sbe
.ForceVertexURBEntryReadLength
= true;
3349 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3350 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3352 for (int i
= 0; i
< 32; i
++) {
3353 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3358 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3361 /* ------------------------------------------------------------------- */
3364 * Populate VS program key fields based on the current state.
3367 iris_populate_vs_key(const struct iris_context
*ice
,
3368 const struct shader_info
*info
,
3369 struct brw_vs_prog_key
*key
)
3371 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3373 if (info
->clip_distance_array_size
== 0 &&
3374 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3375 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3379 * Populate TCS program key fields based on the current state.
3382 iris_populate_tcs_key(const struct iris_context
*ice
,
3383 struct brw_tcs_prog_key
*key
)
3388 * Populate TES program key fields based on the current state.
3391 iris_populate_tes_key(const struct iris_context
*ice
,
3392 struct brw_tes_prog_key
*key
)
3397 * Populate GS program key fields based on the current state.
3400 iris_populate_gs_key(const struct iris_context
*ice
,
3401 struct brw_gs_prog_key
*key
)
3406 * Populate FS program key fields based on the current state.
3409 iris_populate_fs_key(const struct iris_context
*ice
,
3410 struct brw_wm_prog_key
*key
)
3412 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3413 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3414 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3415 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3416 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3418 key
->nr_color_regions
= fb
->nr_cbufs
;
3420 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3422 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
3424 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
3426 /* XXX: only bother if COL0/1 are read */
3427 key
->flat_shade
= rast
->flatshade
;
3429 key
->persample_interp
= rast
->force_persample_interp
;
3430 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3432 key
->coherent_fb_fetch
= true;
3434 key
->force_dual_color_blend
=
3435 screen
->driconf
.dual_color_blend_by_location
&&
3436 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
3438 /* TODO: support key->force_dual_color_blend for Unigine */
3439 /* TODO: Respect glHint for key->high_quality_derivatives */
3443 iris_populate_cs_key(const struct iris_context
*ice
,
3444 struct brw_cs_prog_key
*key
)
3449 KSP(const struct iris_compiled_shader
*shader
)
3451 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3452 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3455 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3456 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3457 * this WA on C0 stepping.
3459 * TODO: Fill out SamplerCount for prefetching?
3462 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3463 pkt.KernelStartPointer = KSP(shader); \
3464 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3465 prog_data->binding_table.size_bytes / 4; \
3466 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3468 pkt.DispatchGRFStartRegisterForURBData = \
3469 prog_data->dispatch_grf_start_reg; \
3470 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3471 pkt.prefix##URBEntryReadOffset = 0; \
3473 pkt.StatisticsEnable = true; \
3474 pkt.Enable = true; \
3476 if (prog_data->total_scratch) { \
3477 struct iris_bo *bo = \
3478 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3479 uint32_t scratch_addr = bo->gtt_offset; \
3480 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3481 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3485 * Encode most of 3DSTATE_VS based on the compiled shader.
3488 iris_store_vs_state(struct iris_context
*ice
,
3489 const struct gen_device_info
*devinfo
,
3490 struct iris_compiled_shader
*shader
)
3492 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3493 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3495 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3496 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3497 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3498 vs
.SIMD8DispatchEnable
= true;
3499 vs
.UserClipDistanceCullTestEnableBitmask
=
3500 vue_prog_data
->cull_distance_mask
;
3505 * Encode most of 3DSTATE_HS based on the compiled shader.
3508 iris_store_tcs_state(struct iris_context
*ice
,
3509 const struct gen_device_info
*devinfo
,
3510 struct iris_compiled_shader
*shader
)
3512 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3513 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3514 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3516 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3517 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3519 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3520 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3521 hs
.IncludeVertexHandles
= true;
3526 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3529 iris_store_tes_state(struct iris_context
*ice
,
3530 const struct gen_device_info
*devinfo
,
3531 struct iris_compiled_shader
*shader
)
3533 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3534 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3535 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3537 uint32_t *te_state
= (void *) shader
->derived_data
;
3538 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3540 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3541 te
.Partitioning
= tes_prog_data
->partitioning
;
3542 te
.OutputTopology
= tes_prog_data
->output_topology
;
3543 te
.TEDomain
= tes_prog_data
->domain
;
3545 te
.MaximumTessellationFactorOdd
= 63.0;
3546 te
.MaximumTessellationFactorNotOdd
= 64.0;
3549 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3550 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3552 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3553 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3554 ds
.ComputeWCoordinateEnable
=
3555 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3557 ds
.UserClipDistanceCullTestEnableBitmask
=
3558 vue_prog_data
->cull_distance_mask
;
3564 * Encode most of 3DSTATE_GS based on the compiled shader.
3567 iris_store_gs_state(struct iris_context
*ice
,
3568 const struct gen_device_info
*devinfo
,
3569 struct iris_compiled_shader
*shader
)
3571 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3572 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3573 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3575 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3576 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3578 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3579 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3580 gs
.ControlDataHeaderSize
=
3581 gs_prog_data
->control_data_header_size_hwords
;
3582 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3583 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3584 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3585 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3586 gs
.ReorderMode
= TRAILING
;
3587 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3588 gs
.MaximumNumberofThreads
=
3589 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3590 : (devinfo
->max_gs_threads
- 1);
3592 if (gs_prog_data
->static_vertex_count
!= -1) {
3593 gs
.StaticOutput
= true;
3594 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3596 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3598 gs
.UserClipDistanceCullTestEnableBitmask
=
3599 vue_prog_data
->cull_distance_mask
;
3601 const int urb_entry_write_offset
= 1;
3602 const uint32_t urb_entry_output_length
=
3603 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3604 urb_entry_write_offset
;
3606 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3607 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3612 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3615 iris_store_fs_state(struct iris_context
*ice
,
3616 const struct gen_device_info
*devinfo
,
3617 struct iris_compiled_shader
*shader
)
3619 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3620 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3622 uint32_t *ps_state
= (void *) shader
->derived_data
;
3623 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3625 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3626 ps
.VectorMaskEnable
= true;
3627 // XXX: WABTPPrefetchDisable, see above, drop at C0
3628 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3629 prog_data
->binding_table
.size_bytes
/ 4;
3630 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3631 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3633 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3635 /* From the documentation for this packet:
3636 * "If the PS kernel does not need the Position XY Offsets to
3637 * compute a Position Value, then this field should be programmed
3638 * to POSOFFSET_NONE."
3640 * "SW Recommendation: If the PS kernel needs the Position Offsets
3641 * to compute a Position XY value, this field should match Position
3642 * ZW Interpolation Mode to ensure a consistent position.xyzw
3645 * We only require XY sample offsets. So, this recommendation doesn't
3646 * look useful at the moment. We might need this in future.
3648 ps
.PositionXYOffsetSelect
=
3649 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3650 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3651 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3652 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3654 // XXX: Disable SIMD32 with 16x MSAA
3656 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3657 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3658 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3659 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3660 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3661 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3663 ps
.KernelStartPointer0
=
3664 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3665 ps
.KernelStartPointer1
=
3666 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3667 ps
.KernelStartPointer2
=
3668 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3670 if (prog_data
->total_scratch
) {
3671 struct iris_bo
*bo
=
3672 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3673 MESA_SHADER_FRAGMENT
);
3674 uint32_t scratch_addr
= bo
->gtt_offset
;
3675 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3676 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3680 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3681 psx
.PixelShaderValid
= true;
3682 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3683 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3684 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3685 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3686 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3687 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3688 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3691 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3692 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3694 psx
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
3701 * Compute the size of the derived data (shader command packets).
3703 * This must match the data written by the iris_store_xs_state() functions.
3706 iris_store_cs_state(struct iris_context
*ice
,
3707 const struct gen_device_info
*devinfo
,
3708 struct iris_compiled_shader
*shader
)
3710 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3711 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3712 void *map
= shader
->derived_data
;
3714 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3715 desc
.KernelStartPointer
= KSP(shader
);
3716 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3717 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3718 desc
.SharedLocalMemorySize
=
3719 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3720 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3721 desc
.CrossThreadConstantDataReadLength
=
3722 cs_prog_data
->push
.cross_thread
.regs
;
3727 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3729 assert(cache_id
<= IRIS_CACHE_BLORP
);
3731 static const unsigned dwords
[] = {
3732 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3733 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3734 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3735 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3737 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3738 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3739 [IRIS_CACHE_BLORP
] = 0,
3742 return sizeof(uint32_t) * dwords
[cache_id
];
3746 * Create any state packets corresponding to the given shader stage
3747 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3748 * This means that we can look up a program in the in-memory cache and
3749 * get most of the state packet without having to reconstruct it.
3752 iris_store_derived_program_state(struct iris_context
*ice
,
3753 enum iris_program_cache_id cache_id
,
3754 struct iris_compiled_shader
*shader
)
3756 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3757 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3761 iris_store_vs_state(ice
, devinfo
, shader
);
3763 case IRIS_CACHE_TCS
:
3764 iris_store_tcs_state(ice
, devinfo
, shader
);
3766 case IRIS_CACHE_TES
:
3767 iris_store_tes_state(ice
, devinfo
, shader
);
3770 iris_store_gs_state(ice
, devinfo
, shader
);
3773 iris_store_fs_state(ice
, devinfo
, shader
);
3776 iris_store_cs_state(ice
, devinfo
, shader
);
3777 case IRIS_CACHE_BLORP
:
3784 /* ------------------------------------------------------------------- */
3786 static const uint32_t push_constant_opcodes
[] = {
3787 [MESA_SHADER_VERTEX
] = 21,
3788 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3789 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3790 [MESA_SHADER_GEOMETRY
] = 22,
3791 [MESA_SHADER_FRAGMENT
] = 23,
3792 [MESA_SHADER_COMPUTE
] = 0,
3796 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3798 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3800 iris_use_pinned_bo(batch
, state_bo
, false);
3802 return ice
->state
.unbound_tex
.offset
;
3806 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3808 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3809 if (!ice
->state
.null_fb
.res
)
3810 return use_null_surface(batch
, ice
);
3812 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3814 iris_use_pinned_bo(batch
, state_bo
, false);
3816 return ice
->state
.null_fb
.offset
;
3820 surf_state_offset_for_aux(struct iris_resource
*res
,
3822 enum isl_aux_usage aux_usage
)
3824 return SURFACE_STATE_ALIGNMENT
*
3825 util_bitcount(res
->aux
.possible_usages
& ((1 << aux_usage
) - 1));
3829 surf_state_update_clear_value(struct iris_batch
*batch
,
3830 struct iris_resource
*res
,
3831 struct iris_state_ref
*state
,
3833 enum isl_aux_usage aux_usage
)
3835 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
3836 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
3837 uint64_t real_offset
= state
->offset
+
3838 IRIS_MEMZONE_BINDER_START
;
3839 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
3840 uint32_t clear_offset
= offset_into_bo
+
3841 isl_dev
->ss
.clear_value_offset
+
3842 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
3844 batch
->vtbl
->copy_mem_mem(batch
, state_bo
, clear_offset
,
3845 res
->aux
.clear_color_bo
,
3846 res
->aux
.clear_color_offset
,
3847 isl_dev
->ss
.clear_value_size
);
3851 update_clear_value(struct iris_context
*ice
,
3852 struct iris_batch
*batch
,
3853 struct iris_resource
*res
,
3854 struct iris_state_ref
*state
,
3856 struct isl_view
*view
)
3858 struct iris_screen
*screen
= batch
->screen
;
3859 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3861 /* We only need to update the clear color in the surface state for gen8 and
3862 * gen9. Newer gens can read it directly from the clear color state buffer.
3864 if (devinfo
->gen
> 9)
3867 if (devinfo
->gen
== 9) {
3868 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
3869 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
3872 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3874 surf_state_update_clear_value(batch
, res
, state
, aux_modes
,
3877 } else if (devinfo
->gen
== 8) {
3878 pipe_resource_reference(&state
->res
, NULL
);
3879 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
3880 state
, res
->aux
.possible_usages
);
3882 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3883 fill_surface_state(&screen
->isl_dev
, map
, res
, view
, aux_usage
);
3884 map
+= SURFACE_STATE_ALIGNMENT
;
3890 * Add a surface to the validation list, as well as the buffer containing
3891 * the corresponding SURFACE_STATE.
3893 * Returns the binding table entry (offset to SURFACE_STATE).
3896 use_surface(struct iris_context
*ice
,
3897 struct iris_batch
*batch
,
3898 struct pipe_surface
*p_surf
,
3900 enum isl_aux_usage aux_usage
)
3902 struct iris_surface
*surf
= (void *) p_surf
;
3903 struct iris_resource
*res
= (void *) p_surf
->texture
;
3905 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3906 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3909 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
3910 if (res
->aux
.clear_color_bo
)
3911 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
3913 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
3914 sizeof(surf
->clear_color
)) != 0) {
3915 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
3916 res
->aux
.possible_usages
, &surf
->view
);
3917 surf
->clear_color
= res
->aux
.clear_color
;
3921 return surf
->surface_state
.offset
+
3922 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
3926 use_sampler_view(struct iris_context
*ice
,
3927 struct iris_batch
*batch
,
3928 struct iris_sampler_view
*isv
)
3931 enum isl_aux_usage aux_usage
=
3932 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
3934 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3935 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3937 if (isv
->res
->aux
.bo
) {
3938 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
3939 if (isv
->res
->aux
.clear_color_bo
)
3940 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
3941 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
3942 sizeof(isv
->clear_color
)) != 0) {
3943 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
3944 isv
->res
->aux
.sampler_usages
, &isv
->view
);
3945 isv
->clear_color
= isv
->res
->aux
.clear_color
;
3949 return isv
->surface_state
.offset
+
3950 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
3955 use_ubo_ssbo(struct iris_batch
*batch
,
3956 struct iris_context
*ice
,
3957 struct pipe_shader_buffer
*buf
,
3958 struct iris_state_ref
*surf_state
,
3962 return use_null_surface(batch
, ice
);
3964 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
3965 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3967 return surf_state
->offset
;
3971 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3972 struct iris_shader_state
*shs
, int i
)
3974 struct iris_image_view
*iv
= &shs
->image
[i
];
3975 struct iris_resource
*res
= (void *) iv
->base
.resource
;
3978 return use_null_surface(batch
, ice
);
3980 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
3982 iris_use_pinned_bo(batch
, res
->bo
, write
);
3983 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
3986 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
3988 return iv
->surface_state
.offset
;
3991 #define push_bt_entry(addr) \
3992 assert(addr >= binder_addr); \
3993 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
3994 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3996 #define bt_assert(section, exists) \
3997 if (!pin_only) assert(prog_data->binding_table.section == \
3998 (exists) ? s : 0xd0d0d0d0)
4001 * Populate the binding table for a given shader stage.
4003 * This fills out the table of pointers to surfaces required by the shader,
4004 * and also adds those buffers to the validation list so the kernel can make
4005 * resident before running our batch.
4008 iris_populate_binding_table(struct iris_context
*ice
,
4009 struct iris_batch
*batch
,
4010 gl_shader_stage stage
,
4013 const struct iris_binder
*binder
= &ice
->state
.binder
;
4014 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4018 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4019 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4020 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4022 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
4023 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4026 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4028 /* TCS passthrough doesn't need a binding table. */
4029 assert(stage
== MESA_SHADER_TESS_CTRL
);
4033 if (stage
== MESA_SHADER_COMPUTE
) {
4034 /* surface for gl_NumWorkGroups */
4035 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4036 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4037 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4038 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4039 push_bt_entry(grid_state
->offset
);
4042 if (stage
== MESA_SHADER_FRAGMENT
) {
4043 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4044 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4045 if (cso_fb
->nr_cbufs
) {
4046 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4048 if (cso_fb
->cbufs
[i
]) {
4049 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4050 ice
->state
.draw_aux_usage
[i
]);
4052 addr
= use_null_fb_surface(batch
, ice
);
4054 push_bt_entry(addr
);
4057 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4058 push_bt_entry(addr
);
4062 unsigned num_textures
= util_last_bit(info
->textures_used
);
4064 bt_assert(texture_start
, num_textures
> 0);
4066 for (int i
= 0; i
< num_textures
; i
++) {
4067 struct iris_sampler_view
*view
= shs
->textures
[i
];
4068 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4069 : use_null_surface(batch
, ice
);
4070 push_bt_entry(addr
);
4073 bt_assert(image_start
, info
->num_images
> 0);
4075 for (int i
= 0; i
< info
->num_images
; i
++) {
4076 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4077 push_bt_entry(addr
);
4080 bt_assert(ubo_start
, shader
->num_cbufs
> 0);
4082 for (int i
= 0; i
< shader
->num_cbufs
; i
++) {
4083 uint32_t addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4084 &shs
->constbuf_surf_state
[i
], false);
4085 push_bt_entry(addr
);
4088 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
4090 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
4091 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
4092 * in st_atom_storagebuf.c so it'll compact them into one range, with
4093 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
4095 if (info
->num_abos
+ info
->num_ssbos
> 0) {
4096 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
4098 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4099 shs
->writable_ssbos
& (1u << i
));
4100 push_bt_entry(addr
);
4105 /* XXX: YUV surfaces not implemented yet */
4106 bt_assert(plane_start
[1], ...);
4107 bt_assert(plane_start
[2], ...);
4112 iris_use_optional_res(struct iris_batch
*batch
,
4113 struct pipe_resource
*res
,
4117 struct iris_bo
*bo
= iris_resource_bo(res
);
4118 iris_use_pinned_bo(batch
, bo
, writeable
);
4123 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4124 struct pipe_surface
*zsbuf
,
4125 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4130 struct iris_resource
*zres
, *sres
;
4131 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4134 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4136 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4137 cso_zsa
->depth_writes_enabled
);
4142 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4146 /* ------------------------------------------------------------------- */
4149 * Pin any BOs which were installed by a previous batch, and restored
4150 * via the hardware logical context mechanism.
4152 * We don't need to re-emit all state every batch - the hardware context
4153 * mechanism will save and restore it for us. This includes pointers to
4154 * various BOs...which won't exist unless we ask the kernel to pin them
4155 * by adding them to the validation list.
4157 * We can skip buffers if we've re-emitted those packets, as we're
4158 * overwriting those stale pointers with new ones, and don't actually
4159 * refer to the old BOs.
4162 iris_restore_render_saved_bos(struct iris_context
*ice
,
4163 struct iris_batch
*batch
,
4164 const struct pipe_draw_info
*draw
)
4166 struct iris_genx_state
*genx
= ice
->state
.genx
;
4168 const uint64_t clean
= ~ice
->state
.dirty
;
4170 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4171 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4174 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4175 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4178 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4179 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4182 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4183 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4186 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4187 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4190 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4191 for (int i
= 0; i
< 4; i
++) {
4192 struct iris_stream_output_target
*tgt
=
4193 (void *) ice
->state
.so_target
[i
];
4195 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4197 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4203 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4204 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4207 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4208 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4213 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4215 for (int i
= 0; i
< 4; i
++) {
4216 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4218 if (range
->length
== 0)
4221 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4222 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4225 iris_use_pinned_bo(batch
, res
->bo
, false);
4227 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4231 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4232 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4233 /* Re-pin any buffers referred to by the binding table. */
4234 iris_populate_binding_table(ice
, batch
, stage
, true);
4238 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4239 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4240 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4242 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4245 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4246 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4247 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4250 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4251 iris_use_pinned_bo(batch
, bo
, false);
4253 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4255 if (prog_data
->total_scratch
> 0) {
4256 struct iris_bo
*bo
=
4257 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4258 iris_use_pinned_bo(batch
, bo
, true);
4264 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4265 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4266 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4267 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4270 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
4271 /* This draw didn't emit a new index buffer, so we are inheriting the
4272 * older index buffer. This draw didn't need it, but future ones may.
4274 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4275 iris_use_pinned_bo(batch
, bo
, false);
4278 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4279 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4281 const int i
= u_bit_scan64(&bound
);
4282 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4283 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4289 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4290 struct iris_batch
*batch
,
4291 const struct pipe_grid_info
*grid
)
4293 const uint64_t clean
= ~ice
->state
.dirty
;
4295 const int stage
= MESA_SHADER_COMPUTE
;
4296 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4298 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
4299 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4302 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4303 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
4305 if (range
->length
> 0) {
4306 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4307 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4310 iris_use_pinned_bo(batch
, res
->bo
, false);
4312 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4317 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4318 /* Re-pin any buffers referred to by the binding table. */
4319 iris_populate_binding_table(ice
, batch
, stage
, true);
4322 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4324 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4326 if (clean
& IRIS_DIRTY_CS
) {
4327 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4330 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4331 iris_use_pinned_bo(batch
, bo
, false);
4333 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4335 if (prog_data
->total_scratch
> 0) {
4336 struct iris_bo
*bo
=
4337 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4338 iris_use_pinned_bo(batch
, bo
, true);
4345 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4348 iris_update_surface_base_address(struct iris_batch
*batch
,
4349 struct iris_binder
*binder
)
4351 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4354 flush_for_state_base_change(batch
);
4356 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4357 sba
.SurfaceStateMOCS
= MOCS_WB
;
4358 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4359 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4362 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4366 iris_upload_dirty_render_state(struct iris_context
*ice
,
4367 struct iris_batch
*batch
,
4368 const struct pipe_draw_info
*draw
)
4370 const uint64_t dirty
= ice
->state
.dirty
;
4372 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4375 struct iris_genx_state
*genx
= ice
->state
.genx
;
4376 struct iris_binder
*binder
= &ice
->state
.binder
;
4377 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4378 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4380 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4381 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4382 uint32_t cc_vp_address
;
4384 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4385 uint32_t *cc_vp_map
=
4386 stream_state(batch
, ice
->state
.dynamic_uploader
,
4387 &ice
->state
.last_res
.cc_vp
,
4388 4 * ice
->state
.num_viewports
*
4389 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4390 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4392 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
4393 cso_rast
->clip_halfz
, &zmin
, &zmax
);
4394 if (cso_rast
->depth_clip_near
)
4396 if (cso_rast
->depth_clip_far
)
4399 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4400 ccv
.MinimumDepth
= zmin
;
4401 ccv
.MaximumDepth
= zmax
;
4404 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4407 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4408 ptr
.CCViewportPointer
= cc_vp_address
;
4412 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4413 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4414 uint32_t sf_cl_vp_address
;
4416 stream_state(batch
, ice
->state
.dynamic_uploader
,
4417 &ice
->state
.last_res
.sf_cl_vp
,
4418 4 * ice
->state
.num_viewports
*
4419 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4421 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4422 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4423 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4425 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4426 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4427 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4428 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4430 calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4431 state
->scale
[0], state
->scale
[1],
4432 state
->translate
[0], state
->translate
[1],
4433 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4435 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4436 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4437 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4438 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4439 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4440 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4441 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4442 vp
.XMinClipGuardband
= gb_xmin
;
4443 vp
.XMaxClipGuardband
= gb_xmax
;
4444 vp
.YMinClipGuardband
= gb_ymin
;
4445 vp
.YMaxClipGuardband
= gb_ymax
;
4446 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4447 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4448 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4449 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4452 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4455 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4456 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4460 if (dirty
& IRIS_DIRTY_URB
) {
4463 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
4464 if (!ice
->shaders
.prog
[i
]) {
4467 struct brw_vue_prog_data
*vue_prog_data
=
4468 (void *) ice
->shaders
.prog
[i
]->prog_data
;
4469 size
[i
] = vue_prog_data
->urb_entry_size
;
4471 assert(size
[i
] != 0);
4474 genX(emit_urb_setup
)(ice
, batch
, size
,
4475 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
4476 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
4479 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4480 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4481 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4482 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4483 const int header_dwords
= GENX(BLEND_STATE_length
);
4485 /* Always write at least one BLEND_STATE - the final RT message will
4486 * reference BLEND_STATE[0] even if there aren't color writes. There
4487 * may still be alpha testing, computed depth, and so on.
4489 const int rt_dwords
=
4490 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4492 uint32_t blend_offset
;
4493 uint32_t *blend_map
=
4494 stream_state(batch
, ice
->state
.dynamic_uploader
,
4495 &ice
->state
.last_res
.blend
,
4496 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4498 uint32_t blend_state_header
;
4499 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4500 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4501 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4504 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4505 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4507 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4508 ptr
.BlendStatePointer
= blend_offset
;
4509 ptr
.BlendStatePointerValid
= true;
4513 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4514 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4516 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4520 stream_state(batch
, ice
->state
.dynamic_uploader
,
4521 &ice
->state
.last_res
.color_calc
,
4522 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4524 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4525 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4526 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4527 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4528 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4529 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4530 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4532 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4533 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4536 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4537 ptr
.ColorCalcStatePointer
= cc_offset
;
4538 ptr
.ColorCalcStatePointerValid
= true;
4542 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4543 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4546 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4547 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4552 if (shs
->cbuf0_needs_upload
)
4553 upload_uniforms(ice
, stage
);
4555 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4557 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4558 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4560 /* The Skylake PRM contains the following restriction:
4562 * "The driver must ensure The following case does not occur
4563 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4564 * buffer 3 read length equal to zero committed followed by a
4565 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4568 * To avoid this, we program the buffers in the highest slots.
4569 * This way, slot 0 is only used if slot 3 is also used.
4573 for (int i
= 3; i
>= 0; i
--) {
4574 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4576 if (range
->length
== 0)
4579 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4580 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4582 assert(cbuf
->buffer_offset
% 32 == 0);
4584 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4585 pkt
.ConstantBody
.Buffer
[n
] =
4586 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
4587 : ro_bo(batch
->screen
->workaround_bo
, 0);
4594 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4595 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4596 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4597 ptr
._3DCommandSubOpcode
= 38 + stage
;
4598 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4603 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4604 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4605 iris_populate_binding_table(ice
, batch
, stage
, false);
4609 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4610 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4611 !ice
->shaders
.prog
[stage
])
4614 iris_upload_sampler_states(ice
, stage
);
4616 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4617 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4619 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4621 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4622 ptr
._3DCommandSubOpcode
= 43 + stage
;
4623 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4627 if (ice
->state
.need_border_colors
)
4628 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4630 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4631 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4633 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4634 if (ice
->state
.framebuffer
.samples
> 0)
4635 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4639 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4640 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4641 ms
.SampleMask
= ice
->state
.sample_mask
;
4645 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4646 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4649 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4652 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4653 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4654 iris_use_pinned_bo(batch
, cache
->bo
, false);
4656 if (prog_data
->total_scratch
> 0) {
4657 struct iris_bo
*bo
=
4658 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4659 iris_use_pinned_bo(batch
, bo
, true);
4662 if (stage
== MESA_SHADER_FRAGMENT
&& wm_prog_data
->uses_sample_mask
) {
4663 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
4664 uint32_t *shader_psx
= ((uint32_t*)shader
->derived_data
) +
4665 GENX(3DSTATE_PS_length
);
4666 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4668 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), &psx_state
, psx
) {
4669 if (wm_prog_data
->post_depth_coverage
)
4670 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4671 else if (wm_prog_data
->inner_coverage
&& cso
->conservative_rasterization
)
4672 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4674 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4677 iris_batch_emit(batch
, shader
->derived_data
,
4678 sizeof(uint32_t) * GENX(3DSTATE_PS_length
));
4679 iris_emit_merge(batch
,
4682 GENX(3DSTATE_PS_EXTRA_length
));
4685 iris_batch_emit(batch
, shader
->derived_data
,
4686 iris_derived_program_state_size(stage
));
4688 if (stage
== MESA_SHADER_TESS_EVAL
) {
4689 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4690 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4691 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4692 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4693 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4698 if (ice
->state
.streamout_active
) {
4699 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4700 iris_batch_emit(batch
, genx
->so_buffers
,
4701 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4702 for (int i
= 0; i
< 4; i
++) {
4703 struct iris_stream_output_target
*tgt
=
4704 (void *) ice
->state
.so_target
[i
];
4706 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4708 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4714 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4715 uint32_t *decl_list
=
4716 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4717 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4720 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4721 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4723 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4724 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4725 sol
.SOFunctionEnable
= true;
4726 sol
.SOStatisticsEnable
= true;
4728 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4729 !ice
->state
.prims_generated_query_active
;
4730 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4733 assert(ice
->state
.streamout
);
4735 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4736 GENX(3DSTATE_STREAMOUT_length
));
4739 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4740 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4744 if (dirty
& IRIS_DIRTY_CLIP
) {
4745 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4746 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4748 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4749 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4750 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4751 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4753 if (wm_prog_data
->barycentric_interp_modes
&
4754 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4755 cl
.NonPerspectiveBarycentricEnable
= true;
4757 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4758 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4760 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4761 ARRAY_SIZE(cso_rast
->clip
));
4764 if (dirty
& IRIS_DIRTY_RASTER
) {
4765 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4766 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4767 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4771 if (dirty
& IRIS_DIRTY_WM
) {
4772 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4773 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4775 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4776 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4778 wm
.BarycentricInterpolationMode
=
4779 wm_prog_data
->barycentric_interp_modes
;
4781 if (wm_prog_data
->early_fragment_tests
)
4782 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4783 else if (wm_prog_data
->has_side_effects
)
4784 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4786 /* We could skip this bit if color writes are enabled. */
4787 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
4788 wm
.ForceThreadDispatchEnable
= ForceON
;
4790 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4793 if (dirty
& IRIS_DIRTY_SBE
) {
4794 iris_emit_sbe(batch
, ice
);
4797 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4798 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4799 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4800 const struct shader_info
*fs_info
=
4801 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
4803 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4804 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4805 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
4806 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4809 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4810 ARRAY_SIZE(cso_blend
->ps_blend
));
4813 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4814 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4816 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4817 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4818 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4819 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4820 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4822 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4824 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
4828 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4829 uint32_t scissor_offset
=
4830 emit_state(batch
, ice
->state
.dynamic_uploader
,
4831 &ice
->state
.last_res
.scissor
,
4832 ice
->state
.scissors
,
4833 sizeof(struct pipe_scissor_state
) *
4834 ice
->state
.num_viewports
, 32);
4836 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4837 ptr
.ScissorRectPointer
= scissor_offset
;
4841 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4842 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4844 /* Do not emit the clear params yets. We need to update the clear value
4847 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
4848 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
4849 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
4851 union isl_color_value clear_value
= { .f32
= { 0, } };
4853 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4854 if (cso_fb
->zsbuf
) {
4855 struct iris_resource
*zres
, *sres
;
4856 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4858 if (zres
&& zres
->aux
.bo
)
4859 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
4862 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
4863 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
4864 clear
.DepthClearValueValid
= true;
4865 clear
.DepthClearValue
= clear_value
.f32
[0];
4867 iris_batch_emit(batch
, clear_params
, clear_length
);
4870 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4871 /* Listen for buffer changes, and also write enable changes. */
4872 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4873 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4876 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4877 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4878 for (int i
= 0; i
< 32; i
++) {
4879 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4884 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4885 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4886 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4889 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4890 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4891 topo
.PrimitiveTopologyType
=
4892 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4896 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4897 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4898 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
4900 if (ice
->state
.vs_uses_draw_params
) {
4901 if (ice
->draw
.draw_params_offset
== 0) {
4902 u_upload_data(ice
->state
.dynamic_uploader
, 0, sizeof(ice
->draw
.params
),
4903 4, &ice
->draw
.params
, &ice
->draw
.draw_params_offset
,
4904 &ice
->draw
.draw_params_res
);
4906 assert(ice
->draw
.draw_params_res
);
4908 struct iris_vertex_buffer_state
*state
=
4909 &(ice
->state
.genx
->vertex_buffers
[count
]);
4910 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params_res
);
4911 struct iris_resource
*res
= (void *) state
->resource
;
4913 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
4914 vb
.VertexBufferIndex
= count
;
4915 vb
.AddressModifyEnable
= true;
4917 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params_offset
;
4918 vb
.BufferStartingAddress
=
4919 ro_bo(NULL
, res
->bo
->gtt_offset
+
4920 (int) ice
->draw
.draw_params_offset
);
4921 vb
.MOCS
= mocs(res
->bo
);
4923 dynamic_bound
|= 1ull << count
;
4927 if (ice
->state
.vs_uses_derived_draw_params
) {
4928 u_upload_data(ice
->state
.dynamic_uploader
, 0,
4929 sizeof(ice
->draw
.derived_params
), 4,
4930 &ice
->draw
.derived_params
,
4931 &ice
->draw
.derived_draw_params_offset
,
4932 &ice
->draw
.derived_draw_params_res
);
4934 struct iris_vertex_buffer_state
*state
=
4935 &(ice
->state
.genx
->vertex_buffers
[count
]);
4936 pipe_resource_reference(&state
->resource
,
4937 ice
->draw
.derived_draw_params_res
);
4938 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params_res
;
4940 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
4941 vb
.VertexBufferIndex
= count
;
4942 vb
.AddressModifyEnable
= true;
4945 res
->bo
->size
- ice
->draw
.derived_draw_params_offset
;
4946 vb
.BufferStartingAddress
=
4947 ro_bo(NULL
, res
->bo
->gtt_offset
+
4948 (int) ice
->draw
.derived_draw_params_offset
);
4949 vb
.MOCS
= mocs(res
->bo
);
4951 dynamic_bound
|= 1ull << count
;
4956 /* The VF cache designers cut corners, and made the cache key's
4957 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4958 * 32 bits of the address. If you have two vertex buffers which get
4959 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4960 * you can get collisions (even within a single batch).
4962 * So, we need to do a VF cache invalidate if the buffer for a VB
4963 * slot slot changes [48:32] address bits from the previous time.
4965 unsigned flush_flags
= 0;
4967 uint64_t bound
= dynamic_bound
;
4969 const int i
= u_bit_scan64(&bound
);
4970 uint16_t high_bits
= 0;
4972 struct iris_resource
*res
=
4973 (void *) genx
->vertex_buffers
[i
].resource
;
4975 iris_use_pinned_bo(batch
, res
->bo
, false);
4977 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4978 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4979 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
4980 PIPE_CONTROL_CS_STALL
;
4981 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4984 /* If the buffer was written to by streamout, we may need
4985 * to stall so those writes land and become visible to the
4988 * TODO: This may stall more than necessary.
4990 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
4991 flush_flags
|= PIPE_CONTROL_CS_STALL
;
4996 iris_emit_pipe_control_flush(batch
, flush_flags
);
4998 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5001 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5002 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5003 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5007 bound
= dynamic_bound
;
5009 const int i
= u_bit_scan64(&bound
);
5010 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5011 sizeof(uint32_t) * vb_dwords
);
5017 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5018 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5019 const unsigned entries
= MAX2(cso
->count
, 1);
5020 if (!(ice
->state
.vs_needs_sgvs_element
||
5021 ice
->state
.vs_uses_derived_draw_params
||
5022 ice
->state
.vs_needs_edge_flag
)) {
5023 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5024 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5026 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5027 const unsigned dyn_count
= cso
->count
+
5028 ice
->state
.vs_needs_sgvs_element
+
5029 ice
->state
.vs_uses_derived_draw_params
;
5031 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5034 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5036 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5037 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5038 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5039 uint32_t *ve_pack_dest
=
5040 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5041 GENX(VERTEX_ELEMENT_STATE_length
)];
5043 if (ice
->state
.vs_needs_sgvs_element
) {
5044 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5045 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5046 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5048 ve
.VertexBufferIndex
=
5049 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5050 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5051 ve
.Component0Control
= base_ctrl
;
5052 ve
.Component1Control
= base_ctrl
;
5053 ve
.Component2Control
= VFCOMP_STORE_0
;
5054 ve
.Component3Control
= VFCOMP_STORE_0
;
5056 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5058 if (ice
->state
.vs_uses_derived_draw_params
) {
5059 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5061 ve
.VertexBufferIndex
=
5062 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5063 ice
->state
.vs_uses_draw_params
;
5064 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5065 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5066 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5067 ve
.Component2Control
= VFCOMP_STORE_0
;
5068 ve
.Component3Control
= VFCOMP_STORE_0
;
5070 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5072 if (ice
->state
.vs_needs_edge_flag
) {
5073 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5074 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5077 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5078 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5081 if (!ice
->state
.vs_needs_edge_flag
) {
5082 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5083 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5085 assert(cso
->count
> 0);
5086 const unsigned edgeflag_index
= cso
->count
- 1;
5087 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5088 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5089 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5091 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5092 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5093 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5094 vi
.VertexElementIndex
= edgeflag_index
+
5095 ice
->state
.vs_needs_sgvs_element
+
5096 ice
->state
.vs_uses_derived_draw_params
;
5098 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5099 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5101 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5102 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5106 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5107 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5108 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5109 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5111 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5112 if (vs_prog_data
->uses_vertexid
) {
5113 sgv
.VertexIDEnable
= true;
5114 sgv
.VertexIDComponentNumber
= 2;
5115 sgv
.VertexIDElementOffset
=
5116 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5119 if (vs_prog_data
->uses_instanceid
) {
5120 sgv
.InstanceIDEnable
= true;
5121 sgv
.InstanceIDComponentNumber
= 3;
5122 sgv
.InstanceIDElementOffset
=
5123 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5128 if (dirty
& IRIS_DIRTY_VF
) {
5129 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5130 if (draw
->primitive_restart
) {
5131 vf
.IndexedDrawCutIndexEnable
= true;
5132 vf
.CutIndex
= draw
->restart_index
;
5137 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5138 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5139 vf
.StatisticsEnable
= true;
5143 /* TODO: Gen8 PMA fix */
5147 iris_upload_render_state(struct iris_context
*ice
,
5148 struct iris_batch
*batch
,
5149 const struct pipe_draw_info
*draw
)
5151 /* Always pin the binder. If we're emitting new binding table pointers,
5152 * we need it. If not, we're probably inheriting old tables via the
5153 * context, and need it anyway. Since true zero-bindings cases are
5154 * practically non-existent, just pin it and avoid last_res tracking.
5156 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5158 if (!batch
->contains_draw
) {
5159 iris_restore_render_saved_bos(ice
, batch
, draw
);
5160 batch
->contains_draw
= true;
5163 iris_upload_dirty_render_state(ice
, batch
, draw
);
5165 if (draw
->index_size
> 0) {
5168 if (draw
->has_user_indices
) {
5169 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5170 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5171 &offset
, &ice
->state
.last_res
.index_buffer
);
5173 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5174 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5176 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5177 draw
->index
.resource
);
5181 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5183 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
5184 ib
.IndexFormat
= draw
->index_size
>> 1;
5186 ib
.BufferSize
= bo
->size
- offset
;
5187 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
5190 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5191 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5192 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5193 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5194 PIPE_CONTROL_CS_STALL
);
5195 ice
->state
.last_index_bo_high_bits
= high_bits
;
5199 #define _3DPRIM_END_OFFSET 0x2420
5200 #define _3DPRIM_START_VERTEX 0x2430
5201 #define _3DPRIM_VERTEX_COUNT 0x2434
5202 #define _3DPRIM_INSTANCE_COUNT 0x2438
5203 #define _3DPRIM_START_INSTANCE 0x243C
5204 #define _3DPRIM_BASE_VERTEX 0x2440
5206 if (draw
->indirect
) {
5207 /* We don't support this MultidrawIndirect. */
5208 assert(!draw
->indirect
->indirect_draw_count
);
5210 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
5213 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5214 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
5215 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5217 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5218 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5219 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5221 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5222 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5223 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5225 if (draw
->index_size
) {
5226 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5227 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5228 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5230 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5231 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5232 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5235 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5236 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5237 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5239 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5240 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5244 } else if (draw
->count_from_stream_output
) {
5245 struct iris_stream_output_target
*so
=
5246 (void *) draw
->count_from_stream_output
;
5248 /* XXX: Replace with actual cache tracking */
5249 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
5251 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5252 lrm
.RegisterAddress
= CS_GPR(0);
5254 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5256 if (so
->base
.buffer_offset
)
5257 iris_math_add32_gpr0(ice
, batch
, -so
->base
.buffer_offset
);
5258 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
5259 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
5261 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5262 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5263 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5264 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5267 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5268 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5269 prim
.PredicateEnable
=
5270 ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5272 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5273 prim
.IndirectParameterEnable
= true;
5275 prim
.StartInstanceLocation
= draw
->start_instance
;
5276 prim
.InstanceCount
= draw
->instance_count
;
5277 prim
.VertexCountPerInstance
= draw
->count
;
5279 // XXX: this is probably bonkers.
5280 prim
.StartVertexLocation
= draw
->start
;
5282 if (draw
->index_size
) {
5283 prim
.BaseVertexLocation
+= draw
->index_bias
;
5285 prim
.StartVertexLocation
+= draw
->index_bias
;
5288 //prim.BaseVertexLocation = ...;
5294 iris_upload_compute_state(struct iris_context
*ice
,
5295 struct iris_batch
*batch
,
5296 const struct pipe_grid_info
*grid
)
5298 const uint64_t dirty
= ice
->state
.dirty
;
5299 struct iris_screen
*screen
= batch
->screen
;
5300 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5301 struct iris_binder
*binder
= &ice
->state
.binder
;
5302 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5303 struct iris_compiled_shader
*shader
=
5304 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5305 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5306 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5308 /* Always pin the binder. If we're emitting new binding table pointers,
5309 * we need it. If not, we're probably inheriting old tables via the
5310 * context, and need it anyway. Since true zero-bindings cases are
5311 * practically non-existent, just pin it and avoid last_res tracking.
5313 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5315 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
5316 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
5318 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5319 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5321 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
5322 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
5324 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5325 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5327 if (ice
->state
.need_border_colors
)
5328 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5330 if (dirty
& IRIS_DIRTY_CS
) {
5331 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5333 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5334 * the only bits that are changed are scoreboard related: Scoreboard
5335 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5336 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5339 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
5341 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5342 if (prog_data
->total_scratch
) {
5343 struct iris_bo
*bo
=
5344 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5345 MESA_SHADER_COMPUTE
);
5346 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5347 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5350 vfe
.MaximumNumberofThreads
=
5351 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5353 vfe
.ResetGatewayTimer
=
5354 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5357 vfe
.BypassGatewayControl
= true;
5359 vfe
.NumberofURBEntries
= 2;
5360 vfe
.URBEntryAllocationSize
= 2;
5362 vfe
.CURBEAllocationSize
=
5363 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5364 cs_prog_data
->push
.cross_thread
.regs
, 2);
5368 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5369 uint32_t curbe_data_offset
= 0;
5370 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5371 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5372 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5373 struct pipe_resource
*curbe_data_res
= NULL
;
5374 uint32_t *curbe_data_map
=
5375 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
5376 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5377 &curbe_data_offset
);
5378 assert(curbe_data_map
);
5379 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5380 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5382 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
5383 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5384 curbe
.CURBETotalDataLength
=
5385 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5386 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5390 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5391 IRIS_DIRTY_BINDINGS_CS
|
5392 IRIS_DIRTY_CONSTANTS_CS
|
5394 struct pipe_resource
*desc_res
= NULL
;
5395 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5397 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5398 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5399 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5402 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5403 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5405 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5406 load
.InterfaceDescriptorTotalLength
=
5407 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5408 load
.InterfaceDescriptorDataStartAddress
=
5409 emit_state(batch
, ice
->state
.dynamic_uploader
,
5410 &desc_res
, desc
, sizeof(desc
), 32);
5413 pipe_resource_reference(&desc_res
, NULL
);
5416 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5417 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5418 uint32_t right_mask
;
5421 right_mask
= ~0u >> (32 - remainder
);
5423 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5425 #define GPGPU_DISPATCHDIMX 0x2500
5426 #define GPGPU_DISPATCHDIMY 0x2504
5427 #define GPGPU_DISPATCHDIMZ 0x2508
5429 if (grid
->indirect
) {
5430 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5431 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5432 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5433 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5434 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5436 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5437 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5438 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5440 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5441 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5442 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5446 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5447 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5448 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5449 ggw
.ThreadDepthCounterMaximum
= 0;
5450 ggw
.ThreadHeightCounterMaximum
= 0;
5451 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5452 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5453 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5454 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5455 ggw
.RightExecutionMask
= right_mask
;
5456 ggw
.BottomExecutionMask
= 0xffffffff;
5459 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5461 if (!batch
->contains_draw
) {
5462 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5463 batch
->contains_draw
= true;
5468 * State module teardown.
5471 iris_destroy_state(struct iris_context
*ice
)
5473 struct iris_genx_state
*genx
= ice
->state
.genx
;
5475 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5477 const int i
= u_bit_scan64(&bound_vbs
);
5478 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5480 free(ice
->state
.genx
);
5482 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5483 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5485 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5487 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5488 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5489 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5490 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5491 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
5492 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
5494 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5495 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
5496 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5498 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5499 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
5500 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
5502 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5503 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5504 &shs
->textures
[i
], NULL
);
5508 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5509 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5511 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5512 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5514 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5515 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5516 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5517 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5518 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5519 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5522 /* ------------------------------------------------------------------- */
5525 iris_rebind_buffer(struct iris_context
*ice
,
5526 struct iris_resource
*res
,
5527 uint64_t old_address
)
5529 struct pipe_context
*ctx
= &ice
->ctx
;
5530 struct iris_screen
*screen
= (void *) ctx
->screen
;
5531 struct iris_genx_state
*genx
= ice
->state
.genx
;
5533 assert(res
->base
.target
== PIPE_BUFFER
);
5535 /* Buffers can't be framebuffer attachments, nor display related,
5536 * and we don't have upstream Clover support.
5538 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
5539 PIPE_BIND_RENDER_TARGET
|
5540 PIPE_BIND_BLENDABLE
|
5541 PIPE_BIND_DISPLAY_TARGET
|
5543 PIPE_BIND_COMPUTE_RESOURCE
|
5544 PIPE_BIND_GLOBAL
)));
5546 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
5547 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5549 const int i
= u_bit_scan64(&bound_vbs
);
5550 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
5552 /* Update the CPU struct */
5553 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
5554 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
5555 uint64_t *addr
= (uint64_t *) &state
->state
[1];
5557 if (*addr
== old_address
) {
5558 *addr
= res
->bo
->gtt_offset
;
5559 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
5564 /* No need to handle these:
5565 * - PIPE_BIND_INDEX_BUFFER (emitted for every indexed draw)
5566 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
5567 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
5570 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
5571 /* XXX: be careful about resetting vs appending... */
5575 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
5576 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
5577 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
5579 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
5580 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
5581 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
5582 while (bound_cbufs
) {
5583 const int i
= u_bit_scan(&bound_cbufs
);
5584 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
5585 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
5587 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
5588 upload_ubo_ssbo_surf_state(ice
, cbuf
, surf_state
, false);
5589 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
5594 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
5595 uint32_t bound_ssbos
= shs
->bound_ssbos
;
5596 while (bound_ssbos
) {
5597 const int i
= u_bit_scan(&bound_ssbos
);
5598 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
5600 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
5601 struct pipe_shader_buffer buf
= {
5602 .buffer
= &res
->base
,
5603 .buffer_offset
= ssbo
->buffer_offset
,
5604 .buffer_size
= ssbo
->buffer_size
,
5606 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
5607 (shs
->writable_ssbos
>> i
) & 1);
5612 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
5613 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
5614 while (bound_sampler_views
) {
5615 const int i
= u_bit_scan(&bound_sampler_views
);
5616 struct iris_sampler_view
*isv
= shs
->textures
[i
];
5618 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
5619 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
5620 &isv
->surface_state
,
5621 isv
->res
->aux
.sampler_usages
);
5623 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
5624 isv
->view
.format
, isv
->view
.swizzle
,
5625 isv
->base
.u
.buf
.offset
,
5626 isv
->base
.u
.buf
.size
);
5627 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
5632 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
5633 uint32_t bound_image_views
= shs
->bound_image_views
;
5634 while (bound_image_views
) {
5635 const int i
= u_bit_scan(&bound_image_views
);
5636 struct iris_image_view
*iv
= &shs
->image
[i
];
5638 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
5639 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
5646 /* ------------------------------------------------------------------- */
5649 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
5652 _iris_emit_lrr(batch
, dst
, src
);
5656 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
5659 _iris_emit_lrr(batch
, dst
, src
);
5660 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
5664 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
5667 _iris_emit_lri(batch
, reg
, val
);
5671 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
5674 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
5675 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
5679 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
5682 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5683 struct iris_bo
*bo
, uint32_t offset
)
5685 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5686 lrm
.RegisterAddress
= reg
;
5687 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
5692 * Load a 64-bit value from a buffer into a MMIO register via
5693 * two MI_LOAD_REGISTER_MEM commands.
5696 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5697 struct iris_bo
*bo
, uint32_t offset
)
5699 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
5700 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
5704 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5705 struct iris_bo
*bo
, uint32_t offset
,
5708 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
5709 srm
.RegisterAddress
= reg
;
5710 srm
.MemoryAddress
= rw_bo(bo
, offset
);
5711 srm
.PredicateEnable
= predicated
;
5716 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5717 struct iris_bo
*bo
, uint32_t offset
,
5720 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
5721 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
5725 iris_store_data_imm32(struct iris_batch
*batch
,
5726 struct iris_bo
*bo
, uint32_t offset
,
5729 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
5730 sdi
.Address
= rw_bo(bo
, offset
);
5731 sdi
.ImmediateData
= imm
;
5736 iris_store_data_imm64(struct iris_batch
*batch
,
5737 struct iris_bo
*bo
, uint32_t offset
,
5740 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
5741 * 2 in genxml but it's actually variable length and we need 5 DWords.
5743 void *map
= iris_get_command_space(batch
, 4 * 5);
5744 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
5745 sdi
.DWordLength
= 5 - 2;
5746 sdi
.Address
= rw_bo(bo
, offset
);
5747 sdi
.ImmediateData
= imm
;
5752 iris_copy_mem_mem(struct iris_batch
*batch
,
5753 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
5754 struct iris_bo
*src_bo
, uint32_t src_offset
,
5757 /* MI_COPY_MEM_MEM operates on DWords. */
5758 assert(bytes
% 4 == 0);
5759 assert(dst_offset
% 4 == 0);
5760 assert(src_offset
% 4 == 0);
5762 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
5763 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
5764 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
5765 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
5770 /* ------------------------------------------------------------------- */
5773 flags_to_post_sync_op(uint32_t flags
)
5775 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
5776 return WriteImmediateData
;
5778 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
5779 return WritePSDepthCount
;
5781 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
5782 return WriteTimestamp
;
5788 * Do the given flags have a Post Sync or LRI Post Sync operation?
5790 static enum pipe_control_flags
5791 get_post_sync_flags(enum pipe_control_flags flags
)
5793 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
5794 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5795 PIPE_CONTROL_WRITE_TIMESTAMP
|
5796 PIPE_CONTROL_LRI_POST_SYNC_OP
;
5798 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
5799 * "LRI Post Sync Operation". So more than one bit set would be illegal.
5801 assert(util_bitcount(flags
) <= 1);
5806 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
5809 * Emit a series of PIPE_CONTROL commands, taking into account any
5810 * workarounds necessary to actually accomplish the caller's request.
5812 * Unless otherwise noted, spec quotations in this function come from:
5814 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5815 * Restrictions for PIPE_CONTROL.
5817 * You should not use this function directly. Use the helpers in
5818 * iris_pipe_control.c instead, which may split the pipe control further.
5821 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
5822 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
5824 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5825 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5826 enum pipe_control_flags non_lri_post_sync_flags
=
5827 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5829 /* Recursive PIPE_CONTROL workarounds --------------------------------
5830 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5832 * We do these first because we want to look at the original operation,
5833 * rather than any workarounds we set.
5835 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5836 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5837 * lists several workarounds:
5839 * "Project: SKL, KBL, BXT
5841 * If the VF Cache Invalidation Enable is set to a 1 in a
5842 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5843 * sets to 0, with the VF Cache Invalidation Enable set to 0
5844 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5845 * Invalidation Enable set to a 1."
5847 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
5850 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
5851 /* Project: SKL / Argument: LRI Post Sync Operation [23]
5853 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5854 * programmed prior to programming a PIPECONTROL command with "LRI
5855 * Post Sync Operation" in GPGPU mode of operation (i.e when
5856 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
5858 * The same text exists a few rows below for Post Sync Op.
5860 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5863 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5865 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5866 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5867 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5869 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
5873 /* "Flush Types" workarounds ---------------------------------------------
5874 * We do these now because they may add post-sync operations or CS stalls.
5877 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5878 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5880 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5881 * 'Write PS Depth Count' or 'Write Timestamp'."
5884 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5885 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5886 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5887 bo
= batch
->screen
->workaround_bo
;
5891 /* #1130 from Gen10 workarounds page:
5893 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5894 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5895 * board stall if Render target cache flush is enabled."
5897 * Applicable to CNL B0 and C0 steppings only.
5899 * The wording here is unclear, and this workaround doesn't look anything
5900 * like the internal bug report recommendations, but leave it be for now...
5902 if (GEN_GEN
== 10) {
5903 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5904 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5905 } else if (flags
& non_lri_post_sync_flags
) {
5906 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5910 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5911 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5913 * "This bit must be DISABLED for operations other than writing
5916 * This seems like nonsense. An Ivybridge workaround requires us to
5917 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5918 * operation. Gen8+ requires us to emit depth stalls and depth cache
5919 * flushes together. So, it's hard to imagine this means anything other
5920 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5922 * We ignore the supposed restriction and do nothing.
5926 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5927 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5928 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5930 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5931 * PS_DEPTH_COUNT or TIMESTAMP queries."
5933 * TODO: Implement end-of-pipe checking.
5935 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5936 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5939 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5940 /* From the PIPE_CONTROL instruction table, bit 1:
5942 * "This bit is ignored if Depth Stall Enable is set.
5943 * Further, the render cache is not flushed even if Write Cache
5944 * Flush Enable bit is set."
5946 * We assert that the caller doesn't do this combination, to try and
5947 * prevent mistakes. It shouldn't hurt the GPU, though.
5949 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5950 * and "Render Target Flush" combo is explicitly required for BTI
5951 * update workarounds.
5953 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5954 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5957 /* PIPE_CONTROL page workarounds ------------------------------------- */
5959 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5960 /* From the PIPE_CONTROL page itself:
5963 * Restriction: Pipe_control with CS-stall bit set must be issued
5964 * before a pipe-control command that has the State Cache
5965 * Invalidate bit set."
5967 flags
|= PIPE_CONTROL_CS_STALL
;
5970 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5971 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5974 * SW must always program Post-Sync Operation to "Write Immediate
5975 * Data" when Flush LLC is set."
5977 * For now, we just require the caller to do it.
5979 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5982 /* "Post-Sync Operation" workarounds -------------------------------- */
5984 /* Project: All / Argument: Global Snapshot Count Reset [19]
5986 * "This bit must not be exercised on any product.
5987 * Requires stall bit ([20] of DW1) set."
5989 * We don't use this, so we just assert that it isn't used. The
5990 * PIPE_CONTROL instruction page indicates that they intended this
5991 * as a debug feature and don't think it is useful in production,
5992 * but it may actually be usable, should we ever want to.
5994 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
5996 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
5997 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
5998 /* Project: All / Arguments:
6000 * - Generic Media State Clear [16]
6001 * - Indirect State Pointers Disable [16]
6003 * "Requires stall bit ([20] of DW1) set."
6005 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6006 * State Clear) says:
6008 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6009 * programmed prior to programming a PIPECONTROL command with "Media
6010 * State Clear" set in GPGPU mode of operation"
6012 * This is a subset of the earlier rule, so there's nothing to do.
6014 flags
|= PIPE_CONTROL_CS_STALL
;
6017 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6018 /* Project: All / Argument: Store Data Index
6020 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6023 * For now, we just assert that the caller does this. We might want to
6024 * automatically add a write to the workaround BO...
6026 assert(non_lri_post_sync_flags
!= 0);
6029 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6030 /* Project: All / Argument: Sync GFDT
6032 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6033 * than '0' or 0x2520[13] must be set."
6035 * For now, we just assert that the caller does this.
6037 assert(non_lri_post_sync_flags
!= 0);
6040 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6041 /* Project: IVB+ / Argument: TLB inv
6043 * "Requires stall bit ([20] of DW1) set."
6045 * Also, from the PIPE_CONTROL instruction table:
6048 * Post Sync Operation or CS stall must be set to ensure a TLB
6049 * invalidation occurs. Otherwise no cycle will occur to the TLB
6050 * cache to invalidate."
6052 * This is not a subset of the earlier rule, so there's nothing to do.
6054 flags
|= PIPE_CONTROL_CS_STALL
;
6057 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6058 /* TODO: The big Skylake GT4 post sync op workaround */
6061 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6063 if (IS_COMPUTE_PIPELINE(batch
)) {
6064 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6065 /* Project: SKL+ / Argument: Tex Invalidate
6066 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6068 flags
|= PIPE_CONTROL_CS_STALL
;
6071 if (GEN_GEN
== 8 && (post_sync_flags
||
6072 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6073 PIPE_CONTROL_DEPTH_STALL
|
6074 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6075 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6076 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6077 /* Project: BDW / Arguments:
6079 * - LRI Post Sync Operation [23]
6080 * - Post Sync Op [15:14]
6082 * - Depth Stall [13]
6083 * - Render Target Cache Flush [12]
6084 * - Depth Cache Flush [0]
6085 * - DC Flush Enable [5]
6087 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6090 flags
|= PIPE_CONTROL_CS_STALL
;
6092 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6095 * This bit must be always set when PIPE_CONTROL command is
6096 * programmed by GPGPU and MEDIA workloads, except for the cases
6097 * when only Read Only Cache Invalidation bits are set (State
6098 * Cache Invalidation Enable, Instruction cache Invalidation
6099 * Enable, Texture Cache Invalidation Enable, Constant Cache
6100 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6101 * need not implemented when FF_DOP_CG is disable via "Fixed
6102 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6104 * It sounds like we could avoid CS stalls in some cases, but we
6105 * don't currently bother. This list isn't exactly the list above,
6111 /* "Stall" workarounds ----------------------------------------------
6112 * These have to come after the earlier ones because we may have added
6113 * some additional CS stalls above.
6116 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6117 /* Project: PRE-SKL, VLV, CHV
6119 * "[All Stepping][All SKUs]:
6121 * One of the following must also be set:
6123 * - Render Target Cache Flush Enable ([12] of DW1)
6124 * - Depth Cache Flush Enable ([0] of DW1)
6125 * - Stall at Pixel Scoreboard ([1] of DW1)
6126 * - Depth Stall ([13] of DW1)
6127 * - Post-Sync Operation ([13] of DW1)
6128 * - DC Flush Enable ([5] of DW1)"
6130 * If we don't already have one of those bits set, we choose to add
6131 * "Stall at Pixel Scoreboard". Some of the other bits require a
6132 * CS stall as a workaround (see above), which would send us into
6133 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6134 * appears to be safe, so we choose that.
6136 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6137 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6138 PIPE_CONTROL_WRITE_IMMEDIATE
|
6139 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6140 PIPE_CONTROL_WRITE_TIMESTAMP
|
6141 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6142 PIPE_CONTROL_DEPTH_STALL
|
6143 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6144 if (!(flags
& wa_bits
))
6145 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6148 /* Emit --------------------------------------------------------------- */
6150 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6151 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6152 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6153 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6154 pc
.StoreDataIndex
= 0;
6155 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6156 pc
.GlobalSnapshotCountReset
=
6157 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6158 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6159 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6160 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6161 pc
.RenderTargetCacheFlushEnable
=
6162 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6163 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6164 pc
.StateCacheInvalidationEnable
=
6165 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6166 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6167 pc
.ConstantCacheInvalidationEnable
=
6168 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6169 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6170 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6171 pc
.InstructionCacheInvalidateEnable
=
6172 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6173 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6174 pc
.IndirectStatePointersDisable
=
6175 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6176 pc
.TextureCacheInvalidationEnable
=
6177 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6178 pc
.Address
= rw_bo(bo
, offset
);
6179 pc
.ImmediateData
= imm
;
6184 genX(emit_urb_setup
)(struct iris_context
*ice
,
6185 struct iris_batch
*batch
,
6186 const unsigned size
[4],
6187 bool tess_present
, bool gs_present
)
6189 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6190 const unsigned push_size_kB
= 32;
6191 unsigned entries
[4];
6194 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6196 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6197 1024 * ice
->shaders
.urb_size
,
6198 tess_present
, gs_present
,
6199 size
, entries
, start
);
6201 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6202 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6203 urb
._3DCommandSubOpcode
+= i
;
6204 urb
.VSURBStartingAddress
= start
[i
];
6205 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6206 urb
.VSNumberofURBEntries
= entries
[i
];
6213 * Preemption on Gen9 has to be enabled or disabled in various cases.
6215 * See these workarounds for preemption:
6216 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6217 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6218 * - WaDisableMidObjectPreemptionForLineLoop
6221 * We don't put this in the vtable because it's only used on Gen9.
6224 gen9_toggle_preemption(struct iris_context
*ice
,
6225 struct iris_batch
*batch
,
6226 const struct pipe_draw_info
*draw
)
6228 struct iris_genx_state
*genx
= ice
->state
.genx
;
6229 bool object_preemption
= true;
6231 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6233 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6234 * and GS is enabled."
6236 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6237 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6238 object_preemption
= false;
6240 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6242 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6243 * on a previous context. End the previous, the resume another context
6244 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6245 * prempt again we will cause corruption.
6247 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6249 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6250 object_preemption
= false;
6252 /* WaDisableMidObjectPreemptionForLineLoop
6254 * "VF Stats Counters Missing a vertex when preemption enabled.
6256 * WA: Disable mid-draw preemption when the draw uses a lineloop
6259 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
6260 object_preemption
= false;
6264 * "VF is corrupting GAFS data when preempted on an instance boundary
6265 * and replayed with instancing enabled.
6267 * WA: Disable preemption when using instanceing."
6269 if (draw
->instance_count
> 1)
6270 object_preemption
= false;
6272 if (genx
->object_preemption
!= object_preemption
) {
6273 iris_enable_obj_preemption(batch
, object_preemption
);
6274 genx
->object_preemption
= object_preemption
;
6280 genX(init_state
)(struct iris_context
*ice
)
6282 struct pipe_context
*ctx
= &ice
->ctx
;
6283 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
6285 ctx
->create_blend_state
= iris_create_blend_state
;
6286 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
6287 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
6288 ctx
->create_sampler_state
= iris_create_sampler_state
;
6289 ctx
->create_sampler_view
= iris_create_sampler_view
;
6290 ctx
->create_surface
= iris_create_surface
;
6291 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
6292 ctx
->bind_blend_state
= iris_bind_blend_state
;
6293 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
6294 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
6295 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
6296 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
6297 ctx
->delete_blend_state
= iris_delete_state
;
6298 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
6299 ctx
->delete_rasterizer_state
= iris_delete_state
;
6300 ctx
->delete_sampler_state
= iris_delete_state
;
6301 ctx
->delete_vertex_elements_state
= iris_delete_state
;
6302 ctx
->set_blend_color
= iris_set_blend_color
;
6303 ctx
->set_clip_state
= iris_set_clip_state
;
6304 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
6305 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
6306 ctx
->set_shader_images
= iris_set_shader_images
;
6307 ctx
->set_sampler_views
= iris_set_sampler_views
;
6308 ctx
->set_tess_state
= iris_set_tess_state
;
6309 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
6310 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
6311 ctx
->set_sample_mask
= iris_set_sample_mask
;
6312 ctx
->set_scissor_states
= iris_set_scissor_states
;
6313 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
6314 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
6315 ctx
->set_viewport_states
= iris_set_viewport_states
;
6316 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
6317 ctx
->surface_destroy
= iris_surface_destroy
;
6318 ctx
->draw_vbo
= iris_draw_vbo
;
6319 ctx
->launch_grid
= iris_launch_grid
;
6320 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
6321 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
6322 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
6324 ice
->vtbl
.destroy_state
= iris_destroy_state
;
6325 ice
->vtbl
.init_render_context
= iris_init_render_context
;
6326 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
6327 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
6328 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
6329 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
6330 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
6331 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
6332 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
6333 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
6334 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
6335 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
6336 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
6337 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
6338 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
6339 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
6340 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
6341 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
6342 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
6343 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
6344 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
6345 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
6346 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
6347 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
6348 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
6349 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
6350 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
6351 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
6352 ice
->vtbl
.mocs
= mocs
;
6354 ice
->state
.dirty
= ~0ull;
6356 ice
->state
.statistics_counters_enabled
= true;
6358 ice
->state
.sample_mask
= 0xffff;
6359 ice
->state
.num_viewports
= 1;
6360 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
6362 /* Make a 1x1x1 null surface for unbound textures */
6363 void *null_surf_map
=
6364 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
6365 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
6366 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
6367 ice
->state
.unbound_tex
.offset
+=
6368 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
6370 /* Default all scissor rectangles to be empty regions. */
6371 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
6372 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
6373 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,