2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/u_transfer.h"
31 #include "intel/compiler/brw_compiler.h"
32 #include "iris_context.h"
33 #include "iris_resource.h"
35 #define __gen_address_type unsigned
36 #define __gen_user_data void
39 __gen_combine_address(void *user_data
, void *location
,
40 unsigned address
, uint32_t delta
)
45 #define __genxml_cmd_length(cmd) cmd ## _length
46 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
47 #define __genxml_cmd_header(cmd) cmd ## _header
48 #define __genxml_cmd_pack(cmd) cmd ## _pack
50 #define iris_pack_command(cmd, dst, name) \
51 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
52 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
53 __genxml_cmd_pack(cmd)(NULL, (void *)dst, &name), \
56 #define iris_pack_state(cmd, dst, name) \
57 for (struct cmd name = {}, \
58 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
59 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
62 #include "genxml/genX_pack.h"
63 #include "genxml/gen_macros.h"
65 #define MOCS_WB (2 << 1)
67 UNUSED
static void pipe_asserts()
69 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
71 /* pipe_logicop happens to match the hardware. */
72 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
73 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
74 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
75 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
76 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
77 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
78 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
79 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
80 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
81 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
82 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
83 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
84 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
85 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
86 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
87 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
89 /* pipe_blend_func happens to match the hardware. */
90 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
91 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
92 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
93 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
94 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
95 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
96 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
97 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
98 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
99 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
100 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
101 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
102 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
103 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
104 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
105 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
106 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
107 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
108 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
110 /* pipe_blend_func happens to match the hardware. */
111 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
112 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
113 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
114 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
115 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
117 /* pipe_stencil_op happens to match the hardware. */
118 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
119 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
120 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
121 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
122 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
123 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
124 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
125 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
130 translate_compare_func(enum pipe_compare_func pipe_func
)
132 static const unsigned map
[] = {
133 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
134 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
135 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
136 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
137 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
138 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
139 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
140 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
142 return map
[pipe_func
];
146 translate_shadow_func(enum pipe_compare_func pipe_func
)
148 /* Gallium specifies the result of shadow comparisons as:
150 * 1 if ref <op> texel,
155 * 0 if texel <op> ref,
158 * So we need to flip the operator and also negate.
160 static const unsigned map
[] = {
161 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
162 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
163 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
164 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
165 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
166 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
167 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
168 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
170 return map
[pipe_func
];
174 translate_cull_mode(unsigned pipe_face
)
176 static const unsigned map
[4] = {
177 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
178 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
179 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
180 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
182 return map
[pipe_face
];
186 translate_fill_mode(unsigned pipe_polymode
)
188 static const unsigned map
[4] = {
189 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
190 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
191 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
192 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
194 return map
[pipe_polymode
];
198 iris_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
203 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
208 iris_set_blend_color(struct pipe_context
*ctx
,
209 const struct pipe_blend_color
*state
)
211 struct iris_context
*ice
= (struct iris_context
*) ctx
;
213 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
214 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
217 struct iris_blend_state
{
218 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
219 uint32_t blend_state
[GENX(BLEND_STATE_length
)];
220 uint32_t blend_entries
[BRW_MAX_DRAW_BUFFERS
*
221 GENX(BLEND_STATE_ENTRY_length
)];
225 iris_create_blend_state(struct pipe_context
*ctx
,
226 const struct pipe_blend_state
*state
)
228 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
230 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
231 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
232 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
233 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
234 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
235 bs
.ColorDitherEnable
= state
->dither
;
236 //bs.AlphaTestEnable = <comes from alpha state> :(
237 //bs.AlphaTestFunction = <comes from alpha state> :(
240 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
241 //pb.HasWriteableRT = <comes from somewhere> :(
242 //pb.AlphaTestEnable = <comes from alpha state> :(
243 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
244 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
246 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
248 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
249 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
250 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
251 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
254 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
255 iris_pack_state(GENX(BLEND_STATE_ENTRY
), &cso
->blend_entries
[i
], be
) {
256 be
.LogicOpEnable
= state
->logicop_enable
;
257 be
.LogicOpFunction
= state
->logicop_func
;
259 be
.PreBlendSourceOnlyClampEnable
= false;
260 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
261 be
.PreBlendColorClampEnable
= true;
262 be
.PostBlendColorClampEnable
= true;
264 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
266 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
267 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
268 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
269 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
270 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
271 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
273 be
.WriteDisableRed
= state
->rt
[i
].colormask
& PIPE_MASK_R
;
274 be
.WriteDisableGreen
= state
->rt
[i
].colormask
& PIPE_MASK_G
;
275 be
.WriteDisableBlue
= state
->rt
[i
].colormask
& PIPE_MASK_B
;
276 be
.WriteDisableAlpha
= state
->rt
[i
].colormask
& PIPE_MASK_A
;
283 struct iris_depth_stencil_alpha_state
{
284 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
285 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
287 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
291 iris_create_dsa_state(struct pipe_context
*ctx
,
292 const struct pipe_depth_stencil_alpha_state
*state
)
294 struct iris_depth_stencil_alpha_state
*cso
=
295 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
297 cso
->alpha
= state
->alpha
;
299 bool two_sided_stencil
= state
->stencil
[1].enabled
;
301 /* The state tracker needs to optimize away EQUAL writes for us. */
302 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
304 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
305 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
306 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
307 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
308 wmds
.StencilTestFunction
=
309 translate_compare_func(state
->stencil
[0].func
);
310 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
311 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
312 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
313 wmds
.BackfaceStencilTestFunction
=
314 translate_compare_func(state
->stencil
[1].func
);
315 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
316 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
317 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
318 wmds
.StencilBufferWriteEnable
=
319 state
->stencil
[0].writemask
!= 0 ||
320 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
321 wmds
.DepthTestEnable
= state
->depth
.enabled
;
322 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
323 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
324 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
325 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
326 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
327 //wmds.StencilReferenceValue = <comes from elsewhere>
328 //wmds.BackfaceStencilReferenceValue = <comes from elsewhere>
331 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
332 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
333 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
339 struct iris_rasterizer_state
{
340 uint32_t sf
[GENX(3DSTATE_SF_length
)];
341 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
342 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
343 uint32_t wm
[GENX(3DSTATE_WM_length
)];
345 bool flatshade
; /* for shader state */
346 bool light_twoside
; /* for shader state */
347 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
348 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
350 uint8_t line_stipple_factor
;
351 uint16_t line_stipple_pattern
;
355 iris_create_rasterizer_state(struct pipe_context
*ctx
,
356 const struct pipe_rasterizer_state
*state
)
358 struct iris_rasterizer_state
*cso
=
359 malloc(sizeof(struct iris_rasterizer_state
));
362 sprite_coord_mode
-> SBE PointSpriteTextureCoordinateOrigin
363 sprite_coord_enable
-> SBE PointSpriteTextureCoordinateEnable
364 point_quad_rasterization
-> SBE
?
369 force_persample_interp
- ?
372 offset_units_unscaled
- cap
not exposed
375 unsigned line_stipple_factor
:8; /**< [1..256] actually */
376 unsigned line_stipple_pattern
:16;
379 cso
->flatshade
= state
->flatshade
;
380 cso
->light_twoside
= state
->light_twoside
;
381 cso
->rasterizer_discard
= state
->rasterizer_discard
;
382 cso
->line_stipple_factor
= state
->line_stipple_factor
;
383 cso
->line_stipple_pattern
= state
->line_stipple_pattern
;
384 // for 3DSTATE_MULTISAMPLE, if we want it.
385 //cso->half_pixel_center = state->half_pixel_center;
387 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
388 sf
.StatisticsEnable
= true;
389 sf
.ViewportTransformEnable
= true;
390 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
391 sf
.LineEndCapAntialiasingRegionWidth
=
392 state
->line_smooth
? _10pixels
: _05pixels
;
393 sf
.LastPixelEnable
= state
->line_last_pixel
;
394 sf
.LineWidth
= state
->line_width
;
395 sf
.SmoothPointEnable
= state
->point_smooth
;
396 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
397 sf
.PointWidth
= state
->point_size
;
399 if (state
->flatshade_first
) {
400 sf
.TriangleStripListProvokingVertexSelect
= 2;
401 sf
.TriangleFanProvokingVertexSelect
= 2;
402 sf
.LineStripListProvokingVertexSelect
= 1;
404 sf
.TriangleFanProvokingVertexSelect
= 1;
409 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
410 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
411 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
412 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
413 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
414 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
415 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
416 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
417 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
418 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
419 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
420 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
421 rr
.SmoothPointEnable
= state
->point_smooth
;
422 rr
.AntialiasingEnable
= state
->line_smooth
;
423 rr
.ScissorRectangleEnable
= state
->scissor
;
424 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
425 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
426 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
429 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
430 cl
.StatisticsEnable
= true;
431 cl
.EarlyCullEnable
= true;
432 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
433 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
434 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
435 cl
.GuardbandClipTestEnable
= true;
436 cl
.ClipMode
= CLIPMODE_NORMAL
;
437 cl
.ClipEnable
= true;
438 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
439 cl
.MinimumPointWidth
= 0.125;
440 cl
.MaximumPointWidth
= 255.875;
441 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
442 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
444 if (state
->flatshade_first
) {
445 cl
.TriangleStripListProvokingVertexSelect
= 2;
446 cl
.TriangleFanProvokingVertexSelect
= 2;
447 cl
.LineStripListProvokingVertexSelect
= 1;
449 cl
.TriangleFanProvokingVertexSelect
= 1;
453 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
454 wm
.LineAntialiasingRegionWidth
= _10pixels
;
455 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
456 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
457 wm
.StatisticsEnable
= true;
458 wm
.LineStippleEnable
= state
->line_stipple_enable
;
459 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
460 // wm.BarycentricInterpolationMode = <comes from FS program> :(
461 // wm.EarlyDepthStencilControl = <comes from FS program> :(
468 translate_wrap(unsigned pipe_wrap
)
470 static const unsigned map
[] = {
471 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
472 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
473 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
474 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
475 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
476 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
477 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
478 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
480 return map
[pipe_wrap
];
484 * Return true if the given wrap mode requires the border color to exist.
487 wrap_mode_needs_border_color(unsigned wrap_mode
)
489 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
493 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
495 static const unsigned map
[] = {
496 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
497 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
498 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
500 return map
[pipe_mip
];
503 struct iris_sampler_state
{
504 struct pipe_sampler_state base
;
506 bool needs_border_color
;
508 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
512 iris_create_sampler_state(struct pipe_context
*pctx
,
513 const struct pipe_sampler_state
*state
)
515 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
520 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
521 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
523 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
524 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
525 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
527 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
528 wrap_mode_needs_border_color(wrap_t
) ||
529 wrap_mode_needs_border_color(wrap_r
);
531 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
532 samp
.TCXAddressControlMode
= wrap_s
;
533 samp
.TCYAddressControlMode
= wrap_t
;
534 samp
.TCZAddressControlMode
= wrap_r
;
535 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
536 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
537 samp
.MinModeFilter
= state
->min_img_filter
;
538 samp
.MagModeFilter
= state
->mag_img_filter
;
539 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
540 samp
.MaximumAnisotropy
= RATIO21
;
542 if (state
->max_anisotropy
>= 2) {
543 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
544 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
545 samp
.AnisotropicAlgorithm
= EWAApproximation
;
548 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
549 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
551 samp
.MaximumAnisotropy
=
552 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
555 /* Set address rounding bits if not using nearest filtering. */
556 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
557 samp
.UAddressMinFilterRoundingEnable
= true;
558 samp
.VAddressMinFilterRoundingEnable
= true;
559 samp
.RAddressMinFilterRoundingEnable
= true;
562 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
563 samp
.UAddressMagFilterRoundingEnable
= true;
564 samp
.VAddressMagFilterRoundingEnable
= true;
565 samp
.RAddressMagFilterRoundingEnable
= true;
568 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
569 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
571 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
573 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
574 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
575 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
576 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
578 //samp.BorderColorPointer = <<comes from elsewhere>>
584 static struct pipe_sampler_view
*
585 iris_create_sampler_view(struct pipe_context
*ctx
,
586 struct pipe_resource
*texture
,
587 const struct pipe_sampler_view
*state
)
589 struct pipe_sampler_view
*sampler_view
= CALLOC_STRUCT(pipe_sampler_view
);
594 /* initialize base object */
595 *sampler_view
= *state
;
596 sampler_view
->texture
= NULL
;
597 pipe_resource_reference(&sampler_view
->texture
, texture
);
598 pipe_reference_init(&sampler_view
->reference
, 1);
599 sampler_view
->context
= ctx
;
603 static struct pipe_surface
*
604 iris_create_surface(struct pipe_context
*ctx
,
605 struct pipe_resource
*tex
,
606 const struct pipe_surface
*surf_tmpl
)
608 struct pipe_surface
*surface
= CALLOC_STRUCT(pipe_surface
);
613 pipe_reference_init(&surface
->reference
, 1);
614 pipe_resource_reference(&surface
->texture
, tex
);
615 surface
->context
= ctx
;
616 surface
->format
= surf_tmpl
->format
;
617 surface
->width
= tex
->width0
;
618 surface
->height
= tex
->height0
;
619 surface
->texture
= tex
;
620 surface
->u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
621 surface
->u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
622 surface
->u
.tex
.level
= surf_tmpl
->u
.tex
.level
;
628 iris_set_sampler_views(struct pipe_context
*ctx
,
629 enum pipe_shader_type shader
,
630 unsigned start
, unsigned count
,
631 struct pipe_sampler_view
**views
)
636 iris_bind_sampler_states(struct pipe_context
*ctx
,
637 enum pipe_shader_type shader
,
638 unsigned start
, unsigned count
,
644 iris_set_clip_state(struct pipe_context
*ctx
,
645 const struct pipe_clip_state
*state
)
650 iris_set_polygon_stipple(struct pipe_context
*ctx
,
651 const struct pipe_poly_stipple
*state
)
653 struct iris_context
*ice
= (struct iris_context
*) ctx
;
654 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
655 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
659 iris_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
664 iris_set_scissor_states(struct pipe_context
*ctx
,
666 unsigned num_scissors
,
667 const struct pipe_scissor_state
*state
)
669 struct iris_context
*ice
= (struct iris_context
*) ctx
;
671 for (unsigned i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
672 ice
->state
.scissors
[i
] = *state
;
675 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
679 iris_set_stencil_ref(struct pipe_context
*ctx
,
680 const struct pipe_stencil_ref
*state
)
682 struct iris_context
*ice
= (struct iris_context
*) ctx
;
683 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
684 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
688 iris_set_viewport_states(struct pipe_context
*ctx
,
690 unsigned num_viewports
,
691 const struct pipe_viewport_state
*state
)
696 iris_set_framebuffer_state(struct pipe_context
*ctx
,
697 const struct pipe_framebuffer_state
*state
)
702 iris_set_constant_buffer(struct pipe_context
*ctx
,
703 enum pipe_shader_type shader
, uint index
,
704 const struct pipe_constant_buffer
*cb
)
710 iris_sampler_view_destroy(struct pipe_context
*ctx
,
711 struct pipe_sampler_view
*state
)
713 pipe_resource_reference(&state
->texture
, NULL
);
719 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*surface
)
721 pipe_resource_reference(&surface
->texture
, NULL
);
726 iris_bind_state(struct pipe_context
*ctx
, void *state
)
731 iris_delete_state(struct pipe_context
*ctx
, void *state
)
736 struct iris_vertex_buffer_state
{
737 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
738 unsigned length
; /* length of 3DSTATE_VERTEX_BUFFERS in DWords */
742 iris_set_vertex_buffers(struct pipe_context
*ctx
,
743 unsigned start_slot
, unsigned count
,
744 const struct pipe_vertex_buffer
*buffers
)
746 struct iris_vertex_buffer_state
*cso
=
747 malloc(sizeof(struct iris_vertex_buffer_state
));
749 cso
->length
= 4 * count
- 1;
751 iris_pack_state(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
752 vb
.DWordLength
= cso
->length
;
755 /* If there are no buffers, do nothing. We can leave the stale
756 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
757 * elements that point to them, it should be fine.
762 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
764 for (unsigned i
= 0; i
< count
; i
++) {
765 assert(!buffers
[i
].is_user_buffer
);
767 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
768 vb
.VertexBufferIndex
= start_slot
+ i
;
770 vb
.AddressModifyEnable
= true;
771 vb
.BufferPitch
= buffers
[i
].stride
;
772 //vb.BufferStartingAddress = ro_bo(bo, buffers[i].buffer_offset);
773 //vb.BufferSize = bo->size;
776 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
779 /* XXX: actually do something with this! */
782 struct iris_vertex_element_state
{
783 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
784 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)];
789 iris_create_vertex_elements(struct pipe_context
*ctx
,
791 const struct pipe_vertex_element
*state
)
793 struct iris_vertex_element_state
*cso
=
794 malloc(sizeof(struct iris_vertex_element_state
));
799 * - create edge flag one
801 * - if those are necessary, use count + 1/2/3... OR in the length
803 iris_pack_state(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
805 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
807 for (int i
= 0; i
< count
; i
++) {
808 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
809 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
811 ve
.SourceElementOffset
= state
[i
].src_offset
;
812 ve
.SourceElementFormat
=
813 iris_isl_format_for_pipe_format(state
[i
].src_format
);
816 iris_pack_state(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
, vi
) {
817 vi
.VertexElementIndex
= i
;
818 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
819 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
822 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
829 iris_create_compute_state(struct pipe_context
*ctx
,
830 const struct pipe_compute_state
*state
)
835 static struct pipe_stream_output_target
*
836 iris_create_stream_output_target(struct pipe_context
*ctx
,
837 struct pipe_resource
*res
,
838 unsigned buffer_offset
,
839 unsigned buffer_size
)
841 struct pipe_stream_output_target
*t
=
842 CALLOC_STRUCT(pipe_stream_output_target
);
846 pipe_reference_init(&t
->reference
, 1);
847 pipe_resource_reference(&t
->buffer
, res
);
848 t
->buffer_offset
= buffer_offset
;
849 t
->buffer_size
= buffer_size
;
854 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
855 struct pipe_stream_output_target
*t
)
857 pipe_resource_reference(&t
->buffer
, NULL
);
862 iris_set_stream_output_targets(struct pipe_context
*ctx
,
863 unsigned num_targets
,
864 struct pipe_stream_output_target
**targets
,
865 const unsigned *offsets
)
870 iris_init_state_functions(struct pipe_context
*ctx
)
872 ctx
->create_blend_state
= iris_create_blend_state
;
873 ctx
->create_depth_stencil_alpha_state
= iris_create_dsa_state
;
874 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
875 ctx
->create_sampler_state
= iris_create_sampler_state
;
876 ctx
->create_sampler_view
= iris_create_sampler_view
;
877 ctx
->create_surface
= iris_create_surface
;
878 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
879 ctx
->create_compute_state
= iris_create_compute_state
;
880 ctx
->bind_blend_state
= iris_bind_state
;
881 ctx
->bind_depth_stencil_alpha_state
= iris_bind_state
;
882 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
883 ctx
->bind_fs_state
= iris_bind_state
;
884 ctx
->bind_rasterizer_state
= iris_bind_state
;
885 ctx
->bind_vertex_elements_state
= iris_bind_state
;
886 ctx
->bind_compute_state
= iris_bind_state
;
887 ctx
->bind_tcs_state
= iris_bind_state
;
888 ctx
->bind_tes_state
= iris_bind_state
;
889 ctx
->bind_gs_state
= iris_bind_state
;
890 ctx
->bind_vs_state
= iris_bind_state
;
891 ctx
->delete_blend_state
= iris_delete_state
;
892 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
893 ctx
->delete_fs_state
= iris_delete_state
;
894 ctx
->delete_rasterizer_state
= iris_delete_state
;
895 ctx
->delete_sampler_state
= iris_delete_state
;
896 ctx
->delete_vertex_elements_state
= iris_delete_state
;
897 ctx
->delete_compute_state
= iris_delete_state
;
898 ctx
->delete_tcs_state
= iris_delete_state
;
899 ctx
->delete_tes_state
= iris_delete_state
;
900 ctx
->delete_gs_state
= iris_delete_state
;
901 ctx
->delete_vs_state
= iris_delete_state
;
902 ctx
->set_blend_color
= iris_set_blend_color
;
903 ctx
->set_clip_state
= iris_set_clip_state
;
904 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
905 ctx
->set_sampler_views
= iris_set_sampler_views
;
906 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
907 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
908 ctx
->set_sample_mask
= iris_set_sample_mask
;
909 ctx
->set_scissor_states
= iris_set_scissor_states
;
910 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
911 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
912 ctx
->set_viewport_states
= iris_set_viewport_states
;
913 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
914 ctx
->surface_destroy
= iris_surface_destroy
;
915 ctx
->draw_vbo
= iris_draw_vbo
;
916 ctx
->launch_grid
= iris_launch_grid
;
917 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
918 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
919 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;