src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __NV50_IR_DRIVER_H__
  24 #define __NV50_IR_DRIVER_H__
  25
  26 #include "pipe/p_shader_tokens.h"
  27
  28 #include "tgsi/tgsi_util.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_scan.h"
  31
  32 struct nir_shader_compiler_options;
  33
  34 /*
  35  * This struct constitutes linkage information in TGSI terminology.
  36  *
  37  * It is created by the code generator and handed to the pipe driver
  38  * for input/output slot assignment.
  39  */
  40 struct nv50_ir_varying
  41 {
  42    uint8_t slot[4]; /* native slots for xyzw (addresses in 32-bit words) */
  43
  44    unsigned mask     : 4; /* vec4 mask */
  45    unsigned linear   : 1; /* linearly interpolated if true (and not flat) */
  46    unsigned flat     : 1;
  47    unsigned sc       : 1; /* special colour interpolation mode (SHADE_MODEL) */
  48    unsigned centroid : 1;
  49    unsigned patch    : 1; /* patch constant value */
  50    unsigned regular  : 1; /* driver-specific meaning (e.g. input in sreg) */
  51    unsigned input    : 1; /* indicates direction of system values */
  52    unsigned oread    : 1; /* true if output is read from parallel TCP */
  53
  54    ubyte id; /* TGSI register index */
  55    ubyte sn; /* TGSI semantic name */
  56    ubyte si; /* TGSI semantic index */
  57 };
  58
  59 #ifndef NDEBUG
  60 # define NV50_IR_DEBUG_BASIC     (1 << 0)
  61 # define NV50_IR_DEBUG_VERBOSE   (2 << 0)
  62 # define NV50_IR_DEBUG_REG_ALLOC (1 << 2)
  63 #else
  64 # define NV50_IR_DEBUG_BASIC     0
  65 # define NV50_IR_DEBUG_VERBOSE   0
  66 # define NV50_IR_DEBUG_REG_ALLOC 0
  67 #endif
  68
  69 struct nv50_ir_prog_symbol
  70 {
  71    uint32_t label;
  72    uint32_t offset;
  73 };
  74
  75 #define NVISA_GF100_CHIPSET    0xc0
  76 #define NVISA_GK104_CHIPSET    0xe0
  77 #define NVISA_GK20A_CHIPSET    0xea
  78 #define NVISA_GM107_CHIPSET    0x110
  79 #define NVISA_GM200_CHIPSET    0x120
  80 #define NVISA_GV100_CHIPSET    0x140
  81
  82 struct nv50_ir_prog_info_out;
  83
  84 /* used for the input data and assignSlot interface */
  85 struct nv50_ir_prog_info
  86 {
  87    uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
  88
  89    uint8_t type; /* PIPE_SHADER */
  90
  91    uint8_t optLevel; /* optimization level (0 to 3) */
  92    uint8_t dbgFlags;
  93    bool omitLineNum; /* only used for printing the prog when dbgFlags is set */
  94
  95    struct {
  96       uint32_t smemSize;  /* required shared memory per block */
  97       uint8_t sourceRep;  /* PIPE_SHADER_IR_* */
  98       const void *source;
  99    } bin;
 100
 101    union {
 102       struct {
 103          uint32_t inputOffset; /* base address for user args */
 104          uint32_t gridInfoBase;  /* base address for NTID,NCTAID */
 105          uint16_t numThreads[3]; /* max number of threads */
 106       } cp;
 107    } prop;
 108
 109    struct {
 110       int8_t genUserClip;        /* request user clip planes for ClipVertex */
 111       uint8_t auxCBSlot;         /* driver constant buffer slot */
 112       uint16_t ucpBase;          /* base address for UCPs */
 113       uint16_t drawInfoBase;     /* base address for draw parameters */
 114       uint16_t alphaRefBase;     /* base address for alpha test values */
 115       int8_t viewportId;         /* output index of ViewportIndex */
 116       bool mul_zero_wins;        /* program wants for x*0 = 0 */
 117       bool nv50styleSurfaces;    /* generate gX[] access for raw buffers */
 118       uint16_t texBindBase;      /* base address for tex handles (nve4) */
 119       uint16_t fbtexBindBase;    /* base address for fbtex handle (nve4) */
 120       uint16_t suInfoBase;       /* base address for surface info (nve4) */
 121       uint16_t bindlessBase;     /* base address for bindless image info (nve4) */
 122       uint16_t bufInfoBase;      /* base address for buffer info */
 123       uint16_t sampleInfoBase;   /* base address for sample positions */
 124       uint8_t msInfoCBSlot;      /* cX[] used for multisample info */
 125       uint16_t msInfoBase;       /* base address for multisample info */
 126       uint16_t uboInfoBase;      /* base address for compute UBOs (gk104+) */
 127    } io;
 128
 129    /* driver callback to assign input/output locations */
 130    int (*assignSlots)(struct nv50_ir_prog_info_out *);
 131 };
 132
 133 /* the produced binary with metadata */
 134 struct nv50_ir_prog_info_out
 135 {
 136    uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
 137
 138    uint8_t type; /* PIPE_SHADER */
 139
 140    struct {
 141       int16_t maxGPR;     /* may be -1 if none used */
 142       uint32_t tlsSpace;  /* required local memory per thread */
 143       uint32_t smemSize;  /* required shared memory per block */
 144       uint32_t *code;
 145       uint32_t codeSize;
 146       uint32_t instructions;
 147       void *relocData;
 148       void *fixupData;
 149    } bin;
 150
 151    struct nv50_ir_varying sv[PIPE_MAX_SHADER_INPUTS];
 152    struct nv50_ir_varying in[PIPE_MAX_SHADER_INPUTS];
 153    struct nv50_ir_varying out[PIPE_MAX_SHADER_OUTPUTS];
 154    uint8_t numInputs;
 155    uint8_t numOutputs;
 156    uint8_t numPatchConstants; /* also included in numInputs/numOutputs */
 157    uint8_t numSysVals;
 158
 159    union {
 160       struct {
 161          bool usesDrawParameters;
 162       } vp;
 163       struct {
 164          uint8_t outputPatchSize;
 165          uint8_t partitioning;    /* PIPE_TESS_PART */
 166          int8_t winding;          /* +1 (clockwise) / -1 (counter-clockwise) */
 167          uint8_t domain;          /* PIPE_PRIM_{QUADS,TRIANGLES,LINES} */
 168          uint8_t outputPrim;      /* PIPE_PRIM_{TRIANGLES,LINES,POINTS} */
 169       } tp;
 170       struct {
 171          uint8_t outputPrim;
 172          unsigned instanceCount;
 173          unsigned maxVertices;
 174       } gp;
 175       struct {
 176          unsigned numColourResults;
 177          bool writesDepth;
 178          bool earlyFragTests;
 179          bool postDepthCoverage;
 180          bool usesDiscard;
 181          bool usesSampleMaskIn;
 182          bool readsFramebuffer;
 183          bool readsSampleLocations;
 184          bool separateFragData;
 185       } fp;
 186    } prop;
 187
 188    struct {
 189       uint8_t clipDistances;     /* number of clip distance outputs */
 190       uint8_t cullDistances;     /* number of cull distance outputs */
 191       int8_t genUserClip;        /* request user clip planes for ClipVertex */
 192       uint8_t instanceId;        /* system value index of InstanceID */
 193       uint8_t vertexId;          /* system value index of VertexID */
 194       uint8_t edgeFlagIn;
 195       uint8_t edgeFlagOut;
 196       uint8_t fragDepth;         /* output index of FragDepth */
 197       uint8_t sampleMask;        /* output index of SampleMask */
 198       uint8_t globalAccess;      /* 1 for read, 2 for wr, 3 for rw */
 199       bool fp64;                 /* program uses fp64 math */
 200       bool layer_viewport_relative;
 201    } io;
 202
 203    uint8_t numBarriers;
 204
 205    void *driverPriv;
 206 };
 207
 208 #ifdef __cplusplus
 209 extern "C" {
 210 #endif
 211
 212 const struct nir_shader_compiler_options *
 213 nv50_ir_nir_shader_compiler_options(int chipset);
 214
 215 extern int nv50_ir_generate_code(struct nv50_ir_prog_info *,
 216                                  struct nv50_ir_prog_info_out *);
 217
 218 extern void nv50_ir_relocate_code(void *relocData, uint32_t *code,
 219                                   uint32_t codePos,
 220                                   uint32_t libPos,
 221                                   uint32_t dataPos);
 222
 223 extern void
 224 nv50_ir_apply_fixups(void *fixupData, uint32_t *code,
 225                      bool force_per_sample, bool flatshade,
 226                      uint8_t alphatest);
 227
 228 /* obtain code that will be shared among programs */
 229 extern void nv50_ir_get_target_library(uint32_t chipset,
 230                                        const uint32_t **code, uint32_t *size);
 231
 232 #ifdef __cplusplus
 233 }
 234 #endif
 235
 236 #endif // __NV50_IR_DRIVER_H__