src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

   1 /*
   2  * Copyright 2017 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Karol Herbst <kherbst@redhat.com>
  23  */
  24
  25 #include "compiler/nir/nir.h"
  26
  27 #include "util/u_debug.h"
  28
  29 #include "codegen/nv50_ir.h"
  30 #include "codegen/nv50_ir_from_common.h"
  31 #include "codegen/nv50_ir_lowering_helper.h"
  32 #include "codegen/nv50_ir_util.h"
  33
  34 #if __cplusplus >= 201103L
  35 #include <unordered_map>
  36 #else
  37 #include <tr1/unordered_map>
  38 #endif
  39 #include <cstring>
  40 #include <list>
  41 #include <vector>
  42
  43 namespace {
  44
  45 #if __cplusplus >= 201103L
  46 using std::hash;
  47 using std::unordered_map;
  48 #else
  49 using std::tr1::hash;
  50 using std::tr1::unordered_map;
  51 #endif
  52
  53 using namespace nv50_ir;
  54
  55 int
  56 type_size(const struct glsl_type *type, bool bindless)
  57 {
  58    return glsl_count_attribute_slots(type, false);
  59 }
  60
  61 class Converter : public ConverterCommon
  62 {
  63 public:
  64    Converter(Program *, nir_shader *, nv50_ir_prog_info *);
  65
  66    bool run();
  67 private:
  68    typedef std::vector<LValue*> LValues;
  69    typedef unordered_map<unsigned, LValues> NirDefMap;
  70    typedef unordered_map<unsigned, nir_load_const_instr*> ImmediateMap;
  71    typedef unordered_map<unsigned, uint32_t> NirArrayLMemOffsets;
  72    typedef unordered_map<unsigned, BasicBlock*> NirBlockMap;
  73
  74    CacheMode convert(enum gl_access_qualifier);
  75    TexTarget convert(glsl_sampler_dim, bool isArray, bool isShadow);
  76    LValues& convert(nir_alu_dest *);
  77    BasicBlock* convert(nir_block *);
  78    LValues& convert(nir_dest *);
  79    SVSemantic convert(nir_intrinsic_op);
  80    Value* convert(nir_load_const_instr*, uint8_t);
  81    LValues& convert(nir_register *);
  82    LValues& convert(nir_ssa_def *);
  83
  84    ImgFormat convertGLImgFormat(GLuint);
  85
  86    Value* getSrc(nir_alu_src *, uint8_t component = 0);
  87    Value* getSrc(nir_register *, uint8_t);
  88    Value* getSrc(nir_src *, uint8_t, bool indirect = false);
  89    Value* getSrc(nir_ssa_def *, uint8_t);
  90
  91    // returned value is the constant part of the given source (either the
  92    // nir_src or the selected source component of an intrinsic). Even though
  93    // this is mostly an optimization to be able to skip indirects in a few
  94    // cases, sometimes we require immediate values or set some fileds on
  95    // instructions (e.g. tex) in order for codegen to consume those.
  96    // If the found value has not a constant part, the Value gets returned
  97    // through the Value parameter.
  98    uint32_t getIndirect(nir_src *, uint8_t, Value *&);
  99    uint32_t getIndirect(nir_intrinsic_instr *, uint8_t s, uint8_t c, Value *&);
 100
 101    uint32_t getSlotAddress(nir_intrinsic_instr *, uint8_t idx, uint8_t slot);
 102
 103    void setInterpolate(nv50_ir_varying *,
 104                        uint8_t,
 105                        bool centroid,
 106                        unsigned semantics);
 107
 108    Instruction *loadFrom(DataFile, uint8_t, DataType, Value *def, uint32_t base,
 109                          uint8_t c, Value *indirect0 = NULL,
 110                          Value *indirect1 = NULL, bool patch = false);
 111    void storeTo(nir_intrinsic_instr *, DataFile, operation, DataType,
 112                 Value *src, uint8_t idx, uint8_t c, Value *indirect0 = NULL,
 113                 Value *indirect1 = NULL);
 114
 115    bool isFloatType(nir_alu_type);
 116    bool isSignedType(nir_alu_type);
 117    bool isResultFloat(nir_op);
 118    bool isResultSigned(nir_op);
 119
 120    DataType getDType(nir_alu_instr *);
 121    DataType getDType(nir_intrinsic_instr *);
 122    DataType getDType(nir_intrinsic_instr *, bool isSigned);
 123    DataType getDType(nir_op, uint8_t);
 124
 125    std::vector<DataType> getSTypes(nir_alu_instr *);
 126    DataType getSType(nir_src &, bool isFloat, bool isSigned);
 127
 128    operation getOperation(nir_intrinsic_op);
 129    operation getOperation(nir_op);
 130    operation getOperation(nir_texop);
 131    operation preOperationNeeded(nir_op);
 132
 133    int getSubOp(nir_intrinsic_op);
 134    int getSubOp(nir_op);
 135
 136    CondCode getCondCode(nir_op);
 137
 138    bool assignSlots();
 139    bool parseNIR();
 140
 141    bool visit(nir_alu_instr *);
 142    bool visit(nir_block *);
 143    bool visit(nir_cf_node *);
 144    bool visit(nir_deref_instr *);
 145    bool visit(nir_function *);
 146    bool visit(nir_if *);
 147    bool visit(nir_instr *);
 148    bool visit(nir_intrinsic_instr *);
 149    bool visit(nir_jump_instr *);
 150    bool visit(nir_load_const_instr*);
 151    bool visit(nir_loop *);
 152    bool visit(nir_ssa_undef_instr *);
 153    bool visit(nir_tex_instr *);
 154
 155    // tex stuff
 156    Value* applyProjection(Value *src, Value *proj);
 157    unsigned int getNIRArgCount(TexInstruction::Target&);
 158
 159    // image stuff
 160    uint16_t handleDeref(nir_deref_instr *, Value * & indirect, const nir_variable * &);
 161    CacheMode getCacheModeFromVar(const nir_variable *);
 162
 163    nir_shader *nir;
 164
 165    NirDefMap ssaDefs;
 166    NirDefMap regDefs;
 167    ImmediateMap immediates;
 168    NirArrayLMemOffsets regToLmemOffset;
 169    NirBlockMap blocks;
 170    unsigned int curLoopDepth;
 171
 172    BasicBlock *exit;
 173    Value *zero;
 174    Instruction *immInsertPos;
 175
 176    int clipVertexOutput;
 177
 178    union {
 179       struct {
 180          Value *position;
 181       } fp;
 182    };
 183 };
 184
 185 Converter::Converter(Program *prog, nir_shader *nir, nv50_ir_prog_info *info)
 186    : ConverterCommon(prog, info),
 187      nir(nir),
 188      curLoopDepth(0),
 189      clipVertexOutput(-1)
 190 {
 191    zero = mkImm((uint32_t)0);
 192 }
 193
 194 BasicBlock *
 195 Converter::convert(nir_block *block)
 196 {
 197    NirBlockMap::iterator it = blocks.find(block->index);
 198    if (it != blocks.end())
 199       return it->second;
 200
 201    BasicBlock *bb = new BasicBlock(func);
 202    blocks[block->index] = bb;
 203    return bb;
 204 }
 205
 206 bool
 207 Converter::isFloatType(nir_alu_type type)
 208 {
 209    return nir_alu_type_get_base_type(type) == nir_type_float;
 210 }
 211
 212 bool
 213 Converter::isSignedType(nir_alu_type type)
 214 {
 215    return nir_alu_type_get_base_type(type) == nir_type_int;
 216 }
 217
 218 bool
 219 Converter::isResultFloat(nir_op op)
 220 {
 221    const nir_op_info &info = nir_op_infos[op];
 222    if (info.output_type != nir_type_invalid)
 223       return isFloatType(info.output_type);
 224
 225    ERROR("isResultFloat not implemented for %s\n", nir_op_infos[op].name);
 226    assert(false);
 227    return true;
 228 }
 229
 230 bool
 231 Converter::isResultSigned(nir_op op)
 232 {
 233    switch (op) {
 234    // there is no umul and we get wrong results if we treat all muls as signed
 235    case nir_op_imul:
 236    case nir_op_inot:
 237       return false;
 238    default:
 239       const nir_op_info &info = nir_op_infos[op];
 240       if (info.output_type != nir_type_invalid)
 241          return isSignedType(info.output_type);
 242       ERROR("isResultSigned not implemented for %s\n", nir_op_infos[op].name);
 243       assert(false);
 244       return true;
 245    }
 246 }
 247
 248 DataType
 249 Converter::getDType(nir_alu_instr *insn)
 250 {
 251    if (insn->dest.dest.is_ssa)
 252       return getDType(insn->op, insn->dest.dest.ssa.bit_size);
 253    else
 254       return getDType(insn->op, insn->dest.dest.reg.reg->bit_size);
 255 }
 256
 257 DataType
 258 Converter::getDType(nir_intrinsic_instr *insn)
 259 {
 260    bool isSigned;
 261    switch (insn->intrinsic) {
 262    case nir_intrinsic_shared_atomic_imax:
 263    case nir_intrinsic_shared_atomic_imin:
 264    case nir_intrinsic_ssbo_atomic_imax:
 265    case nir_intrinsic_ssbo_atomic_imin:
 266       isSigned = true;
 267       break;
 268    default:
 269       isSigned = false;
 270       break;
 271    }
 272
 273    return getDType(insn, isSigned);
 274 }
 275
 276 DataType
 277 Converter::getDType(nir_intrinsic_instr *insn, bool isSigned)
 278 {
 279    if (insn->dest.is_ssa)
 280       return typeOfSize(insn->dest.ssa.bit_size / 8, false, isSigned);
 281    else
 282       return typeOfSize(insn->dest.reg.reg->bit_size / 8, false, isSigned);
 283 }
 284
 285 DataType
 286 Converter::getDType(nir_op op, uint8_t bitSize)
 287 {
 288    DataType ty = typeOfSize(bitSize / 8, isResultFloat(op), isResultSigned(op));
 289    if (ty == TYPE_NONE) {
 290       ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos[op].name, bitSize);
 291       assert(false);
 292    }
 293    return ty;
 294 }
 295
 296 std::vector<DataType>
 297 Converter::getSTypes(nir_alu_instr *insn)
 298 {
 299    const nir_op_info &info = nir_op_infos[insn->op];
 300    std::vector<DataType> res(info.num_inputs);
 301
 302    for (uint8_t i = 0; i < info.num_inputs; ++i) {
 303       if (info.input_types[i] != nir_type_invalid) {
 304          res[i] = getSType(insn->src[i].src, isFloatType(info.input_types[i]), isSignedType(info.input_types[i]));
 305       } else {
 306          ERROR("getSType not implemented for %s idx %u\n", info.name, i);
 307          assert(false);
 308          res[i] = TYPE_NONE;
 309          break;
 310       }
 311    }
 312
 313    return res;
 314 }
 315
 316 DataType
 317 Converter::getSType(nir_src &src, bool isFloat, bool isSigned)
 318 {
 319    uint8_t bitSize;
 320    if (src.is_ssa)
 321       bitSize = src.ssa->bit_size;
 322    else
 323       bitSize = src.reg.reg->bit_size;
 324
 325    DataType ty = typeOfSize(bitSize / 8, isFloat, isSigned);
 326    if (ty == TYPE_NONE) {
 327       const char *str;
 328       if (isFloat)
 329          str = "float";
 330       else if (isSigned)
 331          str = "int";
 332       else
 333          str = "uint";
 334       ERROR("couldn't get Type for %s with bitSize %u\n", str, bitSize);
 335       assert(false);
 336    }
 337    return ty;
 338 }
 339
 340 operation
 341 Converter::getOperation(nir_op op)
 342 {
 343    switch (op) {
 344    // basic ops with float and int variants
 345    case nir_op_fabs:
 346    case nir_op_iabs:
 347       return OP_ABS;
 348    case nir_op_fadd:
 349    case nir_op_iadd:
 350       return OP_ADD;
 351    case nir_op_fand:
 352    case nir_op_iand:
 353       return OP_AND;
 354    case nir_op_ifind_msb:
 355    case nir_op_ufind_msb:
 356       return OP_BFIND;
 357    case nir_op_fceil:
 358       return OP_CEIL;
 359    case nir_op_fcos:
 360       return OP_COS;
 361    case nir_op_f2f32:
 362    case nir_op_f2f64:
 363    case nir_op_f2i32:
 364    case nir_op_f2i64:
 365    case nir_op_f2u32:
 366    case nir_op_f2u64:
 367    case nir_op_i2f32:
 368    case nir_op_i2f64:
 369    case nir_op_i2i32:
 370    case nir_op_i2i64:
 371    case nir_op_u2f32:
 372    case nir_op_u2f64:
 373    case nir_op_u2u32:
 374    case nir_op_u2u64:
 375       return OP_CVT;
 376    case nir_op_fddx:
 377    case nir_op_fddx_coarse:
 378    case nir_op_fddx_fine:
 379       return OP_DFDX;
 380    case nir_op_fddy:
 381    case nir_op_fddy_coarse:
 382    case nir_op_fddy_fine:
 383       return OP_DFDY;
 384    case nir_op_fdiv:
 385    case nir_op_idiv:
 386    case nir_op_udiv:
 387       return OP_DIV;
 388    case nir_op_fexp2:
 389       return OP_EX2;
 390    case nir_op_ffloor:
 391       return OP_FLOOR;
 392    case nir_op_ffma:
 393       return OP_FMA;
 394    case nir_op_flog2:
 395       return OP_LG2;
 396    case nir_op_fmax:
 397    case nir_op_imax:
 398    case nir_op_umax:
 399       return OP_MAX;
 400    case nir_op_pack_64_2x32_split:
 401       return OP_MERGE;
 402    case nir_op_fmin:
 403    case nir_op_imin:
 404    case nir_op_umin:
 405       return OP_MIN;
 406    case nir_op_fmod:
 407    case nir_op_imod:
 408    case nir_op_umod:
 409    case nir_op_frem:
 410    case nir_op_irem:
 411       return OP_MOD;
 412    case nir_op_fmul:
 413    case nir_op_imul:
 414    case nir_op_imul_high:
 415    case nir_op_umul_high:
 416       return OP_MUL;
 417    case nir_op_fneg:
 418    case nir_op_ineg:
 419       return OP_NEG;
 420    case nir_op_fnot:
 421    case nir_op_inot:
 422       return OP_NOT;
 423    case nir_op_for:
 424    case nir_op_ior:
 425       return OP_OR;
 426    case nir_op_fpow:
 427       return OP_POW;
 428    case nir_op_frcp:
 429       return OP_RCP;
 430    case nir_op_frsq:
 431       return OP_RSQ;
 432    case nir_op_fsat:
 433       return OP_SAT;
 434    case nir_op_feq32:
 435    case nir_op_ieq32:
 436    case nir_op_fge32:
 437    case nir_op_ige32:
 438    case nir_op_uge32:
 439    case nir_op_flt32:
 440    case nir_op_ilt32:
 441    case nir_op_ult32:
 442    case nir_op_fne32:
 443    case nir_op_ine32:
 444       return OP_SET;
 445    case nir_op_ishl:
 446       return OP_SHL;
 447    case nir_op_ishr:
 448    case nir_op_ushr:
 449       return OP_SHR;
 450    case nir_op_fsin:
 451       return OP_SIN;
 452    case nir_op_fsqrt:
 453       return OP_SQRT;
 454    case nir_op_fsub:
 455    case nir_op_isub:
 456       return OP_SUB;
 457    case nir_op_ftrunc:
 458       return OP_TRUNC;
 459    case nir_op_fxor:
 460    case nir_op_ixor:
 461       return OP_XOR;
 462    default:
 463       ERROR("couldn't get operation for op %s\n", nir_op_infos[op].name);
 464       assert(false);
 465       return OP_NOP;
 466    }
 467 }
 468
 469 operation
 470 Converter::getOperation(nir_texop op)
 471 {
 472    switch (op) {
 473    case nir_texop_tex:
 474       return OP_TEX;
 475    case nir_texop_lod:
 476       return OP_TXLQ;
 477    case nir_texop_txb:
 478       return OP_TXB;
 479    case nir_texop_txd:
 480       return OP_TXD;
 481    case nir_texop_txf:
 482    case nir_texop_txf_ms:
 483       return OP_TXF;
 484    case nir_texop_tg4:
 485       return OP_TXG;
 486    case nir_texop_txl:
 487       return OP_TXL;
 488    case nir_texop_query_levels:
 489    case nir_texop_texture_samples:
 490    case nir_texop_txs:
 491       return OP_TXQ;
 492    default:
 493       ERROR("couldn't get operation for nir_texop %u\n", op);
 494       assert(false);
 495       return OP_NOP;
 496    }
 497 }
 498
 499 operation
 500 Converter::getOperation(nir_intrinsic_op op)
 501 {
 502    switch (op) {
 503    case nir_intrinsic_emit_vertex:
 504       return OP_EMIT;
 505    case nir_intrinsic_end_primitive:
 506       return OP_RESTART;
 507    case nir_intrinsic_bindless_image_atomic_add:
 508    case nir_intrinsic_image_atomic_add:
 509    case nir_intrinsic_image_deref_atomic_add:
 510    case nir_intrinsic_bindless_image_atomic_and:
 511    case nir_intrinsic_image_atomic_and:
 512    case nir_intrinsic_image_deref_atomic_and:
 513    case nir_intrinsic_bindless_image_atomic_comp_swap:
 514    case nir_intrinsic_image_atomic_comp_swap:
 515    case nir_intrinsic_image_deref_atomic_comp_swap:
 516    case nir_intrinsic_bindless_image_atomic_exchange:
 517    case nir_intrinsic_image_atomic_exchange:
 518    case nir_intrinsic_image_deref_atomic_exchange:
 519    case nir_intrinsic_bindless_image_atomic_max:
 520    case nir_intrinsic_image_atomic_max:
 521    case nir_intrinsic_image_deref_atomic_max:
 522    case nir_intrinsic_bindless_image_atomic_min:
 523    case nir_intrinsic_image_atomic_min:
 524    case nir_intrinsic_image_deref_atomic_min:
 525    case nir_intrinsic_bindless_image_atomic_or:
 526    case nir_intrinsic_image_atomic_or:
 527    case nir_intrinsic_image_deref_atomic_or:
 528    case nir_intrinsic_bindless_image_atomic_xor:
 529    case nir_intrinsic_image_atomic_xor:
 530    case nir_intrinsic_image_deref_atomic_xor:
 531       return OP_SUREDP;
 532    case nir_intrinsic_bindless_image_load:
 533    case nir_intrinsic_image_load:
 534    case nir_intrinsic_image_deref_load:
 535       return OP_SULDP;
 536    case nir_intrinsic_bindless_image_samples:
 537    case nir_intrinsic_image_samples:
 538    case nir_intrinsic_image_deref_samples:
 539    case nir_intrinsic_bindless_image_size:
 540    case nir_intrinsic_image_size:
 541    case nir_intrinsic_image_deref_size:
 542       return OP_SUQ;
 543    case nir_intrinsic_bindless_image_store:
 544    case nir_intrinsic_image_store:
 545    case nir_intrinsic_image_deref_store:
 546       return OP_SUSTP;
 547    default:
 548       ERROR("couldn't get operation for nir_intrinsic_op %u\n", op);
 549       assert(false);
 550       return OP_NOP;
 551    }
 552 }
 553
 554 operation
 555 Converter::preOperationNeeded(nir_op op)
 556 {
 557    switch (op) {
 558    case nir_op_fcos:
 559    case nir_op_fsin:
 560       return OP_PRESIN;
 561    default:
 562       return OP_NOP;
 563    }
 564 }
 565
 566 int
 567 Converter::getSubOp(nir_op op)
 568 {
 569    switch (op) {
 570    case nir_op_imul_high:
 571    case nir_op_umul_high:
 572       return NV50_IR_SUBOP_MUL_HIGH;
 573    default:
 574       return 0;
 575    }
 576 }
 577
 578 int
 579 Converter::getSubOp(nir_intrinsic_op op)
 580 {
 581    switch (op) {
 582    case nir_intrinsic_bindless_image_atomic_add:
 583    case nir_intrinsic_image_atomic_add:
 584    case nir_intrinsic_image_deref_atomic_add:
 585    case nir_intrinsic_shared_atomic_add:
 586    case nir_intrinsic_ssbo_atomic_add:
 587       return  NV50_IR_SUBOP_ATOM_ADD;
 588    case nir_intrinsic_bindless_image_atomic_and:
 589    case nir_intrinsic_image_atomic_and:
 590    case nir_intrinsic_image_deref_atomic_and:
 591    case nir_intrinsic_shared_atomic_and:
 592    case nir_intrinsic_ssbo_atomic_and:
 593       return  NV50_IR_SUBOP_ATOM_AND;
 594    case nir_intrinsic_bindless_image_atomic_comp_swap:
 595    case nir_intrinsic_image_atomic_comp_swap:
 596    case nir_intrinsic_image_deref_atomic_comp_swap:
 597    case nir_intrinsic_shared_atomic_comp_swap:
 598    case nir_intrinsic_ssbo_atomic_comp_swap:
 599       return  NV50_IR_SUBOP_ATOM_CAS;
 600    case nir_intrinsic_bindless_image_atomic_exchange:
 601    case nir_intrinsic_image_atomic_exchange:
 602    case nir_intrinsic_image_deref_atomic_exchange:
 603    case nir_intrinsic_shared_atomic_exchange:
 604    case nir_intrinsic_ssbo_atomic_exchange:
 605       return  NV50_IR_SUBOP_ATOM_EXCH;
 606    case nir_intrinsic_bindless_image_atomic_or:
 607    case nir_intrinsic_image_atomic_or:
 608    case nir_intrinsic_image_deref_atomic_or:
 609    case nir_intrinsic_shared_atomic_or:
 610    case nir_intrinsic_ssbo_atomic_or:
 611       return  NV50_IR_SUBOP_ATOM_OR;
 612    case nir_intrinsic_bindless_image_atomic_max:
 613    case nir_intrinsic_image_atomic_max:
 614    case nir_intrinsic_image_deref_atomic_max:
 615    case nir_intrinsic_shared_atomic_imax:
 616    case nir_intrinsic_shared_atomic_umax:
 617    case nir_intrinsic_ssbo_atomic_imax:
 618    case nir_intrinsic_ssbo_atomic_umax:
 619       return  NV50_IR_SUBOP_ATOM_MAX;
 620    case nir_intrinsic_bindless_image_atomic_min:
 621    case nir_intrinsic_image_atomic_min:
 622    case nir_intrinsic_image_deref_atomic_min:
 623    case nir_intrinsic_shared_atomic_imin:
 624    case nir_intrinsic_shared_atomic_umin:
 625    case nir_intrinsic_ssbo_atomic_imin:
 626    case nir_intrinsic_ssbo_atomic_umin:
 627       return  NV50_IR_SUBOP_ATOM_MIN;
 628    case nir_intrinsic_bindless_image_atomic_xor:
 629    case nir_intrinsic_image_atomic_xor:
 630    case nir_intrinsic_image_deref_atomic_xor:
 631    case nir_intrinsic_shared_atomic_xor:
 632    case nir_intrinsic_ssbo_atomic_xor:
 633       return  NV50_IR_SUBOP_ATOM_XOR;
 634
 635    case nir_intrinsic_group_memory_barrier:
 636    case nir_intrinsic_memory_barrier:
 637    case nir_intrinsic_memory_barrier_atomic_counter:
 638    case nir_intrinsic_memory_barrier_buffer:
 639    case nir_intrinsic_memory_barrier_image:
 640       return NV50_IR_SUBOP_MEMBAR(M, GL);
 641    case nir_intrinsic_memory_barrier_shared:
 642       return NV50_IR_SUBOP_MEMBAR(M, CTA);
 643
 644    case nir_intrinsic_vote_all:
 645       return NV50_IR_SUBOP_VOTE_ALL;
 646    case nir_intrinsic_vote_any:
 647       return NV50_IR_SUBOP_VOTE_ANY;
 648    case nir_intrinsic_vote_ieq:
 649       return NV50_IR_SUBOP_VOTE_UNI;
 650    default:
 651       return 0;
 652    }
 653 }
 654
 655 CondCode
 656 Converter::getCondCode(nir_op op)
 657 {
 658    switch (op) {
 659    case nir_op_feq32:
 660    case nir_op_ieq32:
 661       return CC_EQ;
 662    case nir_op_fge32:
 663    case nir_op_ige32:
 664    case nir_op_uge32:
 665       return CC_GE;
 666    case nir_op_flt32:
 667    case nir_op_ilt32:
 668    case nir_op_ult32:
 669       return CC_LT;
 670    case nir_op_fne32:
 671       return CC_NEU;
 672    case nir_op_ine32:
 673       return CC_NE;
 674    default:
 675       ERROR("couldn't get CondCode for op %s\n", nir_op_infos[op].name);
 676       assert(false);
 677       return CC_FL;
 678    }
 679 }
 680
 681 Converter::LValues&
 682 Converter::convert(nir_alu_dest *dest)
 683 {
 684    return convert(&dest->dest);
 685 }
 686
 687 Converter::LValues&
 688 Converter::convert(nir_dest *dest)
 689 {
 690    if (dest->is_ssa)
 691       return convert(&dest->ssa);
 692    if (dest->reg.indirect) {
 693       ERROR("no support for indirects.");
 694       assert(false);
 695    }
 696    return convert(dest->reg.reg);
 697 }
 698
 699 Converter::LValues&
 700 Converter::convert(nir_register *reg)
 701 {
 702    NirDefMap::iterator it = regDefs.find(reg->index);
 703    if (it != regDefs.end())
 704       return it->second;
 705
 706    LValues newDef(reg->num_components);
 707    for (uint8_t i = 0; i < reg->num_components; i++)
 708       newDef[i] = getScratch(std::max(4, reg->bit_size / 8));
 709    return regDefs[reg->index] = newDef;
 710 }
 711
 712 Converter::LValues&
 713 Converter::convert(nir_ssa_def *def)
 714 {
 715    NirDefMap::iterator it = ssaDefs.find(def->index);
 716    if (it != ssaDefs.end())
 717       return it->second;
 718
 719    LValues newDef(def->num_components);
 720    for (uint8_t i = 0; i < def->num_components; i++)
 721       newDef[i] = getSSA(std::max(4, def->bit_size / 8));
 722    return ssaDefs[def->index] = newDef;
 723 }
 724
 725 Value*
 726 Converter::getSrc(nir_alu_src *src, uint8_t component)
 727 {
 728    if (src->abs || src->negate) {
 729       ERROR("modifiers currently not supported on nir_alu_src\n");
 730       assert(false);
 731    }
 732    return getSrc(&src->src, src->swizzle[component]);
 733 }
 734
 735 Value*
 736 Converter::getSrc(nir_register *reg, uint8_t idx)
 737 {
 738    NirDefMap::iterator it = regDefs.find(reg->index);
 739    if (it == regDefs.end())
 740       return convert(reg)[idx];
 741    return it->second[idx];
 742 }
 743
 744 Value*
 745 Converter::getSrc(nir_src *src, uint8_t idx, bool indirect)
 746 {
 747    if (src->is_ssa)
 748       return getSrc(src->ssa, idx);
 749
 750    if (src->reg.indirect) {
 751       if (indirect)
 752          return getSrc(src->reg.indirect, idx);
 753       ERROR("no support for indirects.");
 754       assert(false);
 755       return NULL;
 756    }
 757
 758    return getSrc(src->reg.reg, idx);
 759 }
 760
 761 Value*
 762 Converter::getSrc(nir_ssa_def *src, uint8_t idx)
 763 {
 764    ImmediateMap::iterator iit = immediates.find(src->index);
 765    if (iit != immediates.end())
 766       return convert((*iit).second, idx);
 767
 768    NirDefMap::iterator it = ssaDefs.find(src->index);
 769    if (it == ssaDefs.end()) {
 770       ERROR("SSA value %u not found\n", src->index);
 771       assert(false);
 772       return NULL;
 773    }
 774    return it->second[idx];
 775 }
 776
 777 uint32_t
 778 Converter::getIndirect(nir_src *src, uint8_t idx, Value *&indirect)
 779 {
 780    nir_const_value *offset = nir_src_as_const_value(*src);
 781
 782    if (offset) {
 783       indirect = NULL;
 784       return offset[0].u32;
 785    }
 786
 787    indirect = getSrc(src, idx, true);
 788    return 0;
 789 }
 790
 791 uint32_t
 792 Converter::getIndirect(nir_intrinsic_instr *insn, uint8_t s, uint8_t c, Value *&indirect)
 793 {
 794    int32_t idx = nir_intrinsic_base(insn) + getIndirect(&insn->src[s], c, indirect);
 795    if (indirect)
 796       indirect = mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), indirect, loadImm(NULL, 4));
 797    return idx;
 798 }
 799
 800 static void
 801 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot, unsigned *name, unsigned *index)
 802 {
 803    assert(name && index);
 804
 805    if (slot >= VERT_ATTRIB_MAX) {
 806       ERROR("invalid varying slot %u\n", slot);
 807       assert(false);
 808       return;
 809    }
 810
 811    if (slot >= VERT_ATTRIB_GENERIC0 &&
 812        slot < VERT_ATTRIB_GENERIC0 + VERT_ATTRIB_GENERIC_MAX) {
 813       *name = TGSI_SEMANTIC_GENERIC;
 814       *index = slot - VERT_ATTRIB_GENERIC0;
 815       return;
 816    }
 817
 818    if (slot >= VERT_ATTRIB_TEX0 &&
 819        slot < VERT_ATTRIB_TEX0 + VERT_ATTRIB_TEX_MAX) {
 820       *name = TGSI_SEMANTIC_TEXCOORD;
 821       *index = slot - VERT_ATTRIB_TEX0;
 822       return;
 823    }
 824
 825    switch (slot) {
 826    case VERT_ATTRIB_COLOR0:
 827       *name = TGSI_SEMANTIC_COLOR;
 828       *index = 0;
 829       break;
 830    case VERT_ATTRIB_COLOR1:
 831       *name = TGSI_SEMANTIC_COLOR;
 832       *index = 1;
 833       break;
 834    case VERT_ATTRIB_EDGEFLAG:
 835       *name = TGSI_SEMANTIC_EDGEFLAG;
 836       *index = 0;
 837       break;
 838    case VERT_ATTRIB_FOG:
 839       *name = TGSI_SEMANTIC_FOG;
 840       *index = 0;
 841       break;
 842    case VERT_ATTRIB_NORMAL:
 843       *name = TGSI_SEMANTIC_NORMAL;
 844       *index = 0;
 845       break;
 846    case VERT_ATTRIB_POS:
 847       *name = TGSI_SEMANTIC_POSITION;
 848       *index = 0;
 849       break;
 850    case VERT_ATTRIB_POINT_SIZE:
 851       *name = TGSI_SEMANTIC_PSIZE;
 852       *index = 0;
 853       break;
 854    default:
 855       ERROR("unknown vert attrib slot %u\n", slot);
 856       assert(false);
 857       break;
 858    }
 859 }
 860
 861 static void
 862 varying_slot_to_tgsi_semantic(gl_varying_slot slot, unsigned *name, unsigned *index)
 863 {
 864    assert(name && index);
 865
 866    if (slot >= VARYING_SLOT_TESS_MAX) {
 867       ERROR("invalid varying slot %u\n", slot);
 868       assert(false);
 869       return;
 870    }
 871
 872    if (slot >= VARYING_SLOT_PATCH0) {
 873       *name = TGSI_SEMANTIC_PATCH;
 874       *index = slot - VARYING_SLOT_PATCH0;
 875       return;
 876    }
 877
 878    if (slot >= VARYING_SLOT_VAR0) {
 879       *name = TGSI_SEMANTIC_GENERIC;
 880       *index = slot - VARYING_SLOT_VAR0;
 881       return;
 882    }
 883
 884    if (slot >= VARYING_SLOT_TEX0 && slot <= VARYING_SLOT_TEX7) {
 885       *name = TGSI_SEMANTIC_TEXCOORD;
 886       *index = slot - VARYING_SLOT_TEX0;
 887       return;
 888    }
 889
 890    switch (slot) {
 891    case VARYING_SLOT_BFC0:
 892       *name = TGSI_SEMANTIC_BCOLOR;
 893       *index = 0;
 894       break;
 895    case VARYING_SLOT_BFC1:
 896       *name = TGSI_SEMANTIC_BCOLOR;
 897       *index = 1;
 898       break;
 899    case VARYING_SLOT_CLIP_DIST0:
 900       *name = TGSI_SEMANTIC_CLIPDIST;
 901       *index = 0;
 902       break;
 903    case VARYING_SLOT_CLIP_DIST1:
 904       *name = TGSI_SEMANTIC_CLIPDIST;
 905       *index = 1;
 906       break;
 907    case VARYING_SLOT_CLIP_VERTEX:
 908       *name = TGSI_SEMANTIC_CLIPVERTEX;
 909       *index = 0;
 910       break;
 911    case VARYING_SLOT_COL0:
 912       *name = TGSI_SEMANTIC_COLOR;
 913       *index = 0;
 914       break;
 915    case VARYING_SLOT_COL1:
 916       *name = TGSI_SEMANTIC_COLOR;
 917       *index = 1;
 918       break;
 919    case VARYING_SLOT_EDGE:
 920       *name = TGSI_SEMANTIC_EDGEFLAG;
 921       *index = 0;
 922       break;
 923    case VARYING_SLOT_FACE:
 924       *name = TGSI_SEMANTIC_FACE;
 925       *index = 0;
 926       break;
 927    case VARYING_SLOT_FOGC:
 928       *name = TGSI_SEMANTIC_FOG;
 929       *index = 0;
 930       break;
 931    case VARYING_SLOT_LAYER:
 932       *name = TGSI_SEMANTIC_LAYER;
 933       *index = 0;
 934       break;
 935    case VARYING_SLOT_PNTC:
 936       *name = TGSI_SEMANTIC_PCOORD;
 937       *index = 0;
 938       break;
 939    case VARYING_SLOT_POS:
 940       *name = TGSI_SEMANTIC_POSITION;
 941       *index = 0;
 942       break;
 943    case VARYING_SLOT_PRIMITIVE_ID:
 944       *name = TGSI_SEMANTIC_PRIMID;
 945       *index = 0;
 946       break;
 947    case VARYING_SLOT_PSIZ:
 948       *name = TGSI_SEMANTIC_PSIZE;
 949       *index = 0;
 950       break;
 951    case VARYING_SLOT_TESS_LEVEL_INNER:
 952       *name = TGSI_SEMANTIC_TESSINNER;
 953       *index = 0;
 954       break;
 955    case VARYING_SLOT_TESS_LEVEL_OUTER:
 956       *name = TGSI_SEMANTIC_TESSOUTER;
 957       *index = 0;
 958       break;
 959    case VARYING_SLOT_VIEWPORT:
 960       *name = TGSI_SEMANTIC_VIEWPORT_INDEX;
 961       *index = 0;
 962       break;
 963    default:
 964       ERROR("unknown varying slot %u\n", slot);
 965       assert(false);
 966       break;
 967    }
 968 }
 969
 970 static void
 971 frag_result_to_tgsi_semantic(unsigned slot, unsigned *name, unsigned *index)
 972 {
 973    if (slot >= FRAG_RESULT_DATA0) {
 974       *name = TGSI_SEMANTIC_COLOR;
 975       *index = slot - FRAG_RESULT_COLOR - 2; // intentional
 976       return;
 977    }
 978
 979    switch (slot) {
 980    case FRAG_RESULT_COLOR:
 981       *name = TGSI_SEMANTIC_COLOR;
 982       *index = 0;
 983       break;
 984    case FRAG_RESULT_DEPTH:
 985       *name = TGSI_SEMANTIC_POSITION;
 986       *index = 0;
 987       break;
 988    case FRAG_RESULT_SAMPLE_MASK:
 989       *name = TGSI_SEMANTIC_SAMPLEMASK;
 990       *index = 0;
 991       break;
 992    default:
 993       ERROR("unknown frag result slot %u\n", slot);
 994       assert(false);
 995       break;
 996    }
 997 }
 998
 999 // copy of _mesa_sysval_to_semantic
1000 static void
1001 system_val_to_tgsi_semantic(unsigned val, unsigned *name, unsigned *index)
1002 {
1003    *index = 0;
1004    switch (val) {
1005    // Vertex shader
1006    case SYSTEM_VALUE_VERTEX_ID:
1007       *name = TGSI_SEMANTIC_VERTEXID;
1008       break;
1009    case SYSTEM_VALUE_INSTANCE_ID:
1010       *name = TGSI_SEMANTIC_INSTANCEID;
1011       break;
1012    case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
1013       *name = TGSI_SEMANTIC_VERTEXID_NOBASE;
1014       break;
1015    case SYSTEM_VALUE_BASE_VERTEX:
1016       *name = TGSI_SEMANTIC_BASEVERTEX;
1017       break;
1018    case SYSTEM_VALUE_BASE_INSTANCE:
1019       *name = TGSI_SEMANTIC_BASEINSTANCE;
1020       break;
1021    case SYSTEM_VALUE_DRAW_ID:
1022       *name = TGSI_SEMANTIC_DRAWID;
1023       break;
1024
1025    // Geometry shader
1026    case SYSTEM_VALUE_INVOCATION_ID:
1027       *name = TGSI_SEMANTIC_INVOCATIONID;
1028       break;
1029
1030    // Fragment shader
1031    case SYSTEM_VALUE_FRAG_COORD:
1032       *name = TGSI_SEMANTIC_POSITION;
1033       break;
1034    case SYSTEM_VALUE_FRONT_FACE:
1035       *name = TGSI_SEMANTIC_FACE;
1036       break;
1037    case SYSTEM_VALUE_SAMPLE_ID:
1038       *name = TGSI_SEMANTIC_SAMPLEID;
1039       break;
1040    case SYSTEM_VALUE_SAMPLE_POS:
1041       *name = TGSI_SEMANTIC_SAMPLEPOS;
1042       break;
1043    case SYSTEM_VALUE_SAMPLE_MASK_IN:
1044       *name = TGSI_SEMANTIC_SAMPLEMASK;
1045       break;
1046    case SYSTEM_VALUE_HELPER_INVOCATION:
1047       *name = TGSI_SEMANTIC_HELPER_INVOCATION;
1048       break;
1049
1050    // Tessellation shader
1051    case SYSTEM_VALUE_TESS_COORD:
1052       *name = TGSI_SEMANTIC_TESSCOORD;
1053       break;
1054    case SYSTEM_VALUE_VERTICES_IN:
1055       *name = TGSI_SEMANTIC_VERTICESIN;
1056       break;
1057    case SYSTEM_VALUE_PRIMITIVE_ID:
1058       *name = TGSI_SEMANTIC_PRIMID;
1059       break;
1060    case SYSTEM_VALUE_TESS_LEVEL_OUTER:
1061       *name = TGSI_SEMANTIC_TESSOUTER;
1062       break;
1063    case SYSTEM_VALUE_TESS_LEVEL_INNER:
1064       *name = TGSI_SEMANTIC_TESSINNER;
1065       break;
1066
1067    // Compute shader
1068    case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
1069       *name = TGSI_SEMANTIC_THREAD_ID;
1070       break;
1071    case SYSTEM_VALUE_WORK_GROUP_ID:
1072       *name = TGSI_SEMANTIC_BLOCK_ID;
1073       break;
1074    case SYSTEM_VALUE_NUM_WORK_GROUPS:
1075       *name = TGSI_SEMANTIC_GRID_SIZE;
1076       break;
1077    case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
1078       *name = TGSI_SEMANTIC_BLOCK_SIZE;
1079       break;
1080
1081    // ARB_shader_ballot
1082    case SYSTEM_VALUE_SUBGROUP_SIZE:
1083       *name = TGSI_SEMANTIC_SUBGROUP_SIZE;
1084       break;
1085    case SYSTEM_VALUE_SUBGROUP_INVOCATION:
1086       *name = TGSI_SEMANTIC_SUBGROUP_INVOCATION;
1087       break;
1088    case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
1089       *name = TGSI_SEMANTIC_SUBGROUP_EQ_MASK;
1090       break;
1091    case SYSTEM_VALUE_SUBGROUP_GE_MASK:
1092       *name = TGSI_SEMANTIC_SUBGROUP_GE_MASK;
1093       break;
1094    case SYSTEM_VALUE_SUBGROUP_GT_MASK:
1095       *name = TGSI_SEMANTIC_SUBGROUP_GT_MASK;
1096       break;
1097    case SYSTEM_VALUE_SUBGROUP_LE_MASK:
1098       *name = TGSI_SEMANTIC_SUBGROUP_LE_MASK;
1099       break;
1100    case SYSTEM_VALUE_SUBGROUP_LT_MASK:
1101       *name = TGSI_SEMANTIC_SUBGROUP_LT_MASK;
1102       break;
1103
1104    default:
1105       ERROR("unknown system value %u\n", val);
1106       assert(false);
1107       break;
1108    }
1109 }
1110
1111 void
1112 Converter::setInterpolate(nv50_ir_varying *var,
1113                           uint8_t mode,
1114                           bool centroid,
1115                           unsigned semantic)
1116 {
1117    switch (mode) {
1118    case INTERP_MODE_FLAT:
1119       var->flat = 1;
1120       break;
1121    case INTERP_MODE_NONE:
1122       if (semantic == TGSI_SEMANTIC_COLOR)
1123          var->sc = 1;
1124       else if (semantic == TGSI_SEMANTIC_POSITION)
1125          var->linear = 1;
1126       break;
1127    case INTERP_MODE_NOPERSPECTIVE:
1128       var->linear = 1;
1129       break;
1130    case INTERP_MODE_SMOOTH:
1131       break;
1132    }
1133    var->centroid = centroid;
1134 }
1135
1136 static uint16_t
1137 calcSlots(const glsl_type *type, Program::Type stage, const shader_info &info,
1138           bool input, const nir_variable *var)
1139 {
1140    if (!type->is_array())
1141       return type->count_attribute_slots(false);
1142
1143    uint16_t slots;
1144    switch (stage) {
1145    case Program::TYPE_GEOMETRY:
1146       slots = type->uniform_locations();
1147       if (input)
1148          slots /= info.gs.vertices_in;
1149       break;
1150    case Program::TYPE_TESSELLATION_CONTROL:
1151    case Program::TYPE_TESSELLATION_EVAL:
1152       // remove first dimension
1153       if (var->data.patch || (!input && stage == Program::TYPE_TESSELLATION_EVAL))
1154          slots = type->uniform_locations();
1155       else
1156          slots = type->fields.array->uniform_locations();
1157       break;
1158    default:
1159       slots = type->count_attribute_slots(false);
1160       break;
1161    }
1162
1163    return slots;
1164 }
1165
1166 bool Converter::assignSlots() {
1167    unsigned name;
1168    unsigned index;
1169
1170    info->io.viewportId = -1;
1171    info->numInputs = 0;
1172
1173    // we have to fixup the uniform locations for arrays
1174    unsigned numImages = 0;
1175    nir_foreach_variable(var, &nir->uniforms) {
1176       const glsl_type *type = var->type;
1177       if (!type->without_array()->is_image())
1178          continue;
1179       var->data.driver_location = numImages;
1180       numImages += type->is_array() ? type->arrays_of_arrays_size() : 1;
1181    }
1182
1183    nir_foreach_variable(var, &nir->inputs) {
1184       const glsl_type *type = var->type;
1185       int slot = var->data.location;
1186       uint16_t slots = calcSlots(type, prog->getType(), nir->info, true, var);
1187       uint32_t comp = type->is_array() ? type->without_array()->component_slots()
1188                                        : type->component_slots();
1189       uint32_t frac = var->data.location_frac;
1190       uint32_t vary = var->data.driver_location;
1191
1192       if (glsl_base_type_is_64bit(type->without_array()->base_type)) {
1193          if (comp > 2)
1194             slots *= 2;
1195       }
1196
1197       assert(vary + slots <= PIPE_MAX_SHADER_INPUTS);
1198
1199       switch(prog->getType()) {
1200       case Program::TYPE_FRAGMENT:
1201          varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
1202          for (uint16_t i = 0; i < slots; ++i) {
1203             setInterpolate(&info->in[vary + i], var->data.interpolation,
1204                            var->data.centroid | var->data.sample, name);
1205          }
1206          break;
1207       case Program::TYPE_GEOMETRY:
1208          varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
1209          break;
1210       case Program::TYPE_TESSELLATION_CONTROL:
1211       case Program::TYPE_TESSELLATION_EVAL:
1212          varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
1213          if (var->data.patch && name == TGSI_SEMANTIC_PATCH)
1214             info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
1215          break;
1216       case Program::TYPE_VERTEX:
1217          vert_attrib_to_tgsi_semantic((gl_vert_attrib)slot, &name, &index);
1218          switch (name) {
1219          case TGSI_SEMANTIC_EDGEFLAG:
1220             info->io.edgeFlagIn = vary;
1221             break;
1222          default:
1223             break;
1224          }
1225          break;
1226       default:
1227          ERROR("unknown shader type %u in assignSlots\n", prog->getType());
1228          return false;
1229       }
1230
1231       for (uint16_t i = 0u; i < slots; ++i, ++vary) {
1232          info->in[vary].id = vary;
1233          info->in[vary].patch = var->data.patch;
1234          info->in[vary].sn = name;
1235          info->in[vary].si = index + i;
1236          if (glsl_base_type_is_64bit(type->without_array()->base_type))
1237             if (i & 0x1)
1238                info->in[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) >> 0x4);
1239             else
1240                info->in[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) & 0xf);
1241          else
1242             info->in[vary].mask |= ((1 << comp) - 1) << frac;
1243       }
1244       info->numInputs = std::max<uint8_t>(info->numInputs, vary);
1245    }
1246
1247    info->numOutputs = 0;
1248    nir_foreach_variable(var, &nir->outputs) {
1249       const glsl_type *type = var->type;
1250       int slot = var->data.location;
1251       uint16_t slots = calcSlots(type, prog->getType(), nir->info, false, var);
1252       uint32_t comp = type->is_array() ? type->without_array()->component_slots()
1253                                        : type->component_slots();
1254       uint32_t frac = var->data.location_frac;
1255       uint32_t vary = var->data.driver_location;
1256
1257       if (glsl_base_type_is_64bit(type->without_array()->base_type)) {
1258          if (comp > 2)
1259             slots *= 2;
1260       }
1261
1262       assert(vary < PIPE_MAX_SHADER_OUTPUTS);
1263
1264       switch(prog->getType()) {
1265       case Program::TYPE_FRAGMENT:
1266          frag_result_to_tgsi_semantic((gl_frag_result)slot, &name, &index);
1267          switch (name) {
1268          case TGSI_SEMANTIC_COLOR:
1269             if (!var->data.fb_fetch_output)
1270                info->prop.fp.numColourResults++;
1271             info->prop.fp.separateFragData = true;
1272             // sometimes we get FRAG_RESULT_DATAX with data.index 0
1273             // sometimes we get FRAG_RESULT_DATA0 with data.index X
1274             index = index == 0 ? var->data.index : index;
1275             break;
1276          case TGSI_SEMANTIC_POSITION:
1277             info->io.fragDepth = vary;
1278             info->prop.fp.writesDepth = true;
1279             break;
1280          case TGSI_SEMANTIC_SAMPLEMASK:
1281             info->io.sampleMask = vary;
1282             break;
1283          default:
1284             break;
1285          }
1286          break;
1287       case Program::TYPE_GEOMETRY:
1288       case Program::TYPE_TESSELLATION_CONTROL:
1289       case Program::TYPE_TESSELLATION_EVAL:
1290       case Program::TYPE_VERTEX:
1291          varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
1292
1293          if (var->data.patch && name != TGSI_SEMANTIC_TESSINNER &&
1294              name != TGSI_SEMANTIC_TESSOUTER)
1295             info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
1296
1297          switch (name) {
1298          case TGSI_SEMANTIC_CLIPDIST:
1299             info->io.genUserClip = -1;
1300             break;
1301          case TGSI_SEMANTIC_CLIPVERTEX:
1302             clipVertexOutput = vary;
1303             break;
1304          case TGSI_SEMANTIC_EDGEFLAG:
1305             info->io.edgeFlagOut = vary;
1306             break;
1307          case TGSI_SEMANTIC_POSITION:
1308             if (clipVertexOutput < 0)
1309                clipVertexOutput = vary;
1310             break;
1311          default:
1312             break;
1313          }
1314          break;
1315       default:
1316          ERROR("unknown shader type %u in assignSlots\n", prog->getType());
1317          return false;
1318       }
1319
1320       for (uint16_t i = 0u; i < slots; ++i, ++vary) {
1321          info->out[vary].id = vary;
1322          info->out[vary].patch = var->data.patch;
1323          info->out[vary].sn = name;
1324          info->out[vary].si = index + i;
1325          if (glsl_base_type_is_64bit(type->without_array()->base_type))
1326             if (i & 0x1)
1327                info->out[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) >> 0x4);
1328             else
1329                info->out[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) & 0xf);
1330          else
1331             info->out[vary].mask |= ((1 << comp) - 1) << frac;
1332
1333          if (nir->info.outputs_read & 1ll << slot)
1334             info->out[vary].oread = 1;
1335       }
1336       info->numOutputs = std::max<uint8_t>(info->numOutputs, vary);
1337    }
1338
1339    info->numSysVals = 0;
1340    for (uint8_t i = 0; i < 64; ++i) {
1341       if (!(nir->info.system_values_read & 1ll << i))
1342          continue;
1343
1344       system_val_to_tgsi_semantic(i, &name, &index);
1345       info->sv[info->numSysVals].sn = name;
1346       info->sv[info->numSysVals].si = index;
1347       info->sv[info->numSysVals].input = 0; // TODO inferSysValDirection(sn);
1348
1349       switch (i) {
1350       case SYSTEM_VALUE_INSTANCE_ID:
1351          info->io.instanceId = info->numSysVals;
1352          break;
1353       case SYSTEM_VALUE_TESS_LEVEL_INNER:
1354       case SYSTEM_VALUE_TESS_LEVEL_OUTER:
1355          info->sv[info->numSysVals].patch = 1;
1356          break;
1357       case SYSTEM_VALUE_VERTEX_ID:
1358          info->io.vertexId = info->numSysVals;
1359          break;
1360       default:
1361          break;
1362       }
1363
1364       info->numSysVals += 1;
1365    }
1366
1367    if (info->io.genUserClip > 0) {
1368       info->io.clipDistances = info->io.genUserClip;
1369
1370       const unsigned int nOut = (info->io.genUserClip + 3) / 4;
1371
1372       for (unsigned int n = 0; n < nOut; ++n) {
1373          unsigned int i = info->numOutputs++;
1374          info->out[i].id = i;
1375          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
1376          info->out[i].si = n;
1377          info->out[i].mask = ((1 << info->io.clipDistances) - 1) >> (n * 4);
1378       }
1379    }
1380
1381    return info->assignSlots(info) == 0;
1382 }
1383
1384 uint32_t
1385 Converter::getSlotAddress(nir_intrinsic_instr *insn, uint8_t idx, uint8_t slot)
1386 {
1387    DataType ty;
1388    int offset = nir_intrinsic_component(insn);
1389    bool input;
1390
1391    if (nir_intrinsic_infos[insn->intrinsic].has_dest)
1392       ty = getDType(insn);
1393    else
1394       ty = getSType(insn->src[0], false, false);
1395
1396    switch (insn->intrinsic) {
1397    case nir_intrinsic_load_input:
1398    case nir_intrinsic_load_interpolated_input:
1399    case nir_intrinsic_load_per_vertex_input:
1400       input = true;
1401       break;
1402    case nir_intrinsic_load_output:
1403    case nir_intrinsic_load_per_vertex_output:
1404    case nir_intrinsic_store_output:
1405    case nir_intrinsic_store_per_vertex_output:
1406       input = false;
1407       break;
1408    default:
1409       ERROR("unknown intrinsic in getSlotAddress %s",
1410             nir_intrinsic_infos[insn->intrinsic].name);
1411       input = false;
1412       assert(false);
1413       break;
1414    }
1415
1416    if (typeSizeof(ty) == 8) {
1417       slot *= 2;
1418       slot += offset;
1419       if (slot >= 4) {
1420          idx += 1;
1421          slot -= 4;
1422       }
1423    } else {
1424       slot += offset;
1425    }
1426
1427    assert(slot < 4);
1428    assert(!input || idx < PIPE_MAX_SHADER_INPUTS);
1429    assert(input || idx < PIPE_MAX_SHADER_OUTPUTS);
1430
1431    const nv50_ir_varying *vary = input ? info->in : info->out;
1432    return vary[idx].slot[slot] * 4;
1433 }
1434
1435 Instruction *
1436 Converter::loadFrom(DataFile file, uint8_t i, DataType ty, Value *def,
1437                     uint32_t base, uint8_t c, Value *indirect0,
1438                     Value *indirect1, bool patch)
1439 {
1440    unsigned int tySize = typeSizeof(ty);
1441
1442    if (tySize == 8 &&
1443        (file == FILE_MEMORY_CONST || file == FILE_MEMORY_BUFFER || indirect0)) {
1444       Value *lo = getSSA();
1445       Value *hi = getSSA();
1446
1447       Instruction *loi =
1448          mkLoad(TYPE_U32, lo,
1449                 mkSymbol(file, i, TYPE_U32, base + c * tySize),
1450                 indirect0);
1451       loi->setIndirect(0, 1, indirect1);
1452       loi->perPatch = patch;
1453
1454       Instruction *hii =
1455          mkLoad(TYPE_U32, hi,
1456                 mkSymbol(file, i, TYPE_U32, base + c * tySize + 4),
1457                 indirect0);
1458       hii->setIndirect(0, 1, indirect1);
1459       hii->perPatch = patch;
1460
1461       return mkOp2(OP_MERGE, ty, def, lo, hi);
1462    } else {
1463       Instruction *ld =
1464          mkLoad(ty, def, mkSymbol(file, i, ty, base + c * tySize), indirect0);
1465       ld->setIndirect(0, 1, indirect1);
1466       ld->perPatch = patch;
1467       return ld;
1468    }
1469 }
1470
1471 void
1472 Converter::storeTo(nir_intrinsic_instr *insn, DataFile file, operation op,
1473                    DataType ty, Value *src, uint8_t idx, uint8_t c,
1474                    Value *indirect0, Value *indirect1)
1475 {
1476    uint8_t size = typeSizeof(ty);
1477    uint32_t address = getSlotAddress(insn, idx, c);
1478
1479    if (size == 8 && indirect0) {
1480       Value *split[2];
1481       mkSplit(split, 4, src);
1482
1483       if (op == OP_EXPORT) {
1484          split[0] = mkMov(getSSA(), split[0], ty)->getDef(0);
1485          split[1] = mkMov(getSSA(), split[1], ty)->getDef(0);
1486       }
1487
1488       mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address), indirect0,
1489               split[0])->perPatch = info->out[idx].patch;
1490       mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address + 4), indirect0,
1491               split[1])->perPatch = info->out[idx].patch;
1492    } else {
1493       if (op == OP_EXPORT)
1494          src = mkMov(getSSA(size), src, ty)->getDef(0);
1495       mkStore(op, ty, mkSymbol(file, 0, ty, address), indirect0,
1496               src)->perPatch = info->out[idx].patch;
1497    }
1498 }
1499
1500 bool
1501 Converter::parseNIR()
1502 {
1503    info->bin.tlsSpace = 0;
1504    info->io.clipDistances = nir->info.clip_distance_array_size;
1505    info->io.cullDistances = nir->info.cull_distance_array_size;
1506
1507    switch(prog->getType()) {
1508    case Program::TYPE_COMPUTE:
1509       info->prop.cp.numThreads[0] = nir->info.cs.local_size[0];
1510       info->prop.cp.numThreads[1] = nir->info.cs.local_size[1];
1511       info->prop.cp.numThreads[2] = nir->info.cs.local_size[2];
1512       info->bin.smemSize = nir->info.cs.shared_size;
1513       break;
1514    case Program::TYPE_FRAGMENT:
1515       info->prop.fp.earlyFragTests = nir->info.fs.early_fragment_tests;
1516       info->prop.fp.persampleInvocation =
1517          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_ID) ||
1518          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1519       info->prop.fp.postDepthCoverage = nir->info.fs.post_depth_coverage;
1520       info->prop.fp.readsSampleLocations =
1521          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1522       info->prop.fp.usesDiscard = nir->info.fs.uses_discard;
1523       info->prop.fp.usesSampleMaskIn =
1524          !!(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN);
1525       break;
1526    case Program::TYPE_GEOMETRY:
1527       info->prop.gp.inputPrim = nir->info.gs.input_primitive;
1528       info->prop.gp.instanceCount = nir->info.gs.invocations;
1529       info->prop.gp.maxVertices = nir->info.gs.vertices_out;
1530       info->prop.gp.outputPrim = nir->info.gs.output_primitive;
1531       break;
1532    case Program::TYPE_TESSELLATION_CONTROL:
1533    case Program::TYPE_TESSELLATION_EVAL:
1534       if (nir->info.tess.primitive_mode == GL_ISOLINES)
1535          info->prop.tp.domain = GL_LINES;
1536       else
1537          info->prop.tp.domain = nir->info.tess.primitive_mode;
1538       info->prop.tp.outputPatchSize = nir->info.tess.tcs_vertices_out;
1539       info->prop.tp.outputPrim =
1540          nir->info.tess.point_mode ? PIPE_PRIM_POINTS : PIPE_PRIM_TRIANGLES;
1541       info->prop.tp.partitioning = (nir->info.tess.spacing + 1) % 3;
1542       info->prop.tp.winding = !nir->info.tess.ccw;
1543       break;
1544    case Program::TYPE_VERTEX:
1545       info->prop.vp.usesDrawParameters =
1546          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) ||
1547          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE)) ||
1548          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID));
1549       break;
1550    default:
1551       break;
1552    }
1553
1554    return true;
1555 }
1556
1557 bool
1558 Converter::visit(nir_function *function)
1559 {
1560    // we only support emiting the main function for now
1561    assert(!strcmp(function->name, "main"));
1562    assert(function->impl);
1563
1564    // usually the blocks will set everything up, but main is special
1565    BasicBlock *entry = new BasicBlock(prog->main);
1566    exit = new BasicBlock(prog->main);
1567    blocks[nir_start_block(function->impl)->index] = entry;
1568    prog->main->setEntry(entry);
1569    prog->main->setExit(exit);
1570
1571    setPosition(entry, true);
1572
1573    if (info->io.genUserClip > 0) {
1574       for (int c = 0; c < 4; ++c)
1575          clipVtx[c] = getScratch();
1576    }
1577
1578    switch (prog->getType()) {
1579    case Program::TYPE_TESSELLATION_CONTROL:
1580       outBase = mkOp2v(
1581          OP_SUB, TYPE_U32, getSSA(),
1582          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
1583          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
1584       break;
1585    case Program::TYPE_FRAGMENT: {
1586       Symbol *sv = mkSysVal(SV_POSITION, 3);
1587       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
1588       fp.position = mkOp1v(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
1589       break;
1590    }
1591    default:
1592       break;
1593    }
1594
1595    nir_foreach_register(reg, &function->impl->registers) {
1596       if (reg->num_array_elems) {
1597          // TODO: packed variables would be nice, but MemoryOpt fails
1598          // replace 4 with reg->num_components
1599          uint32_t size = 4 * reg->num_array_elems * (reg->bit_size / 8);
1600          regToLmemOffset[reg->index] = info->bin.tlsSpace;
1601          info->bin.tlsSpace += size;
1602       }
1603    }
1604
1605    nir_index_ssa_defs(function->impl);
1606    foreach_list_typed(nir_cf_node, node, node, &function->impl->body) {
1607       if (!visit(node))
1608          return false;
1609    }
1610
1611    bb->cfg.attach(&exit->cfg, Graph::Edge::TREE);
1612    setPosition(exit, true);
1613
1614    if ((prog->getType() == Program::TYPE_VERTEX ||
1615         prog->getType() == Program::TYPE_TESSELLATION_EVAL)
1616        && info->io.genUserClip > 0)
1617       handleUserClipPlanes();
1618
1619    // TODO: for non main function this needs to be a OP_RETURN
1620    mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
1621    return true;
1622 }
1623
1624 bool
1625 Converter::visit(nir_cf_node *node)
1626 {
1627    switch (node->type) {
1628    case nir_cf_node_block:
1629       return visit(nir_cf_node_as_block(node));
1630    case nir_cf_node_if:
1631       return visit(nir_cf_node_as_if(node));
1632    case nir_cf_node_loop:
1633       return visit(nir_cf_node_as_loop(node));
1634    default:
1635       ERROR("unknown nir_cf_node type %u\n", node->type);
1636       return false;
1637    }
1638 }
1639
1640 bool
1641 Converter::visit(nir_block *block)
1642 {
1643    if (!block->predecessors->entries && block->instr_list.is_empty())
1644       return true;
1645
1646    BasicBlock *bb = convert(block);
1647
1648    setPosition(bb, true);
1649    nir_foreach_instr(insn, block) {
1650       if (!visit(insn))
1651          return false;
1652    }
1653    return true;
1654 }
1655
1656 bool
1657 Converter::visit(nir_if *nif)
1658 {
1659    DataType sType = getSType(nif->condition, false, false);
1660    Value *src = getSrc(&nif->condition, 0);
1661
1662    nir_block *lastThen = nir_if_last_then_block(nif);
1663    nir_block *lastElse = nir_if_last_else_block(nif);
1664
1665    assert(!lastThen->successors[1]);
1666    assert(!lastElse->successors[1]);
1667
1668    BasicBlock *ifBB = convert(nir_if_first_then_block(nif));
1669    BasicBlock *elseBB = convert(nir_if_first_else_block(nif));
1670
1671    bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
1672    bb->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
1673
1674    // we only insert joinats, if both nodes end up at the end of the if again.
1675    // the reason for this to not happens are breaks/continues/ret/... which
1676    // have their own handling
1677    if (lastThen->successors[0] == lastElse->successors[0])
1678       bb->joinAt = mkFlow(OP_JOINAT, convert(lastThen->successors[0]),
1679                           CC_ALWAYS, NULL);
1680
1681    mkFlow(OP_BRA, elseBB, CC_EQ, src)->setType(sType);
1682
1683    foreach_list_typed(nir_cf_node, node, node, &nif->then_list) {
1684       if (!visit(node))
1685          return false;
1686    }
1687    setPosition(convert(lastThen), true);
1688    if (!bb->getExit() ||
1689        !bb->getExit()->asFlow() ||
1690         bb->getExit()->asFlow()->op == OP_JOIN) {
1691       BasicBlock *tailBB = convert(lastThen->successors[0]);
1692       mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1693       bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1694    }
1695
1696    foreach_list_typed(nir_cf_node, node, node, &nif->else_list) {
1697       if (!visit(node))
1698          return false;
1699    }
1700    setPosition(convert(lastElse), true);
1701    if (!bb->getExit() ||
1702        !bb->getExit()->asFlow() ||
1703         bb->getExit()->asFlow()->op == OP_JOIN) {
1704       BasicBlock *tailBB = convert(lastElse->successors[0]);
1705       mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1706       bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1707    }
1708
1709    if (lastThen->successors[0] == lastElse->successors[0]) {
1710       setPosition(convert(lastThen->successors[0]), true);
1711       mkFlow(OP_JOIN, NULL, CC_ALWAYS, NULL)->fixed = 1;
1712    }
1713
1714    return true;
1715 }
1716
1717 bool
1718 Converter::visit(nir_loop *loop)
1719 {
1720    curLoopDepth += 1;
1721    func->loopNestingBound = std::max(func->loopNestingBound, curLoopDepth);
1722
1723    BasicBlock *loopBB = convert(nir_loop_first_block(loop));
1724    BasicBlock *tailBB =
1725       convert(nir_cf_node_as_block(nir_cf_node_next(&loop->cf_node)));
1726    bb->cfg.attach(&loopBB->cfg, Graph::Edge::TREE);
1727
1728    mkFlow(OP_PREBREAK, tailBB, CC_ALWAYS, NULL);
1729    setPosition(loopBB, false);
1730    mkFlow(OP_PRECONT, loopBB, CC_ALWAYS, NULL);
1731
1732    foreach_list_typed(nir_cf_node, node, node, &loop->body) {
1733       if (!visit(node))
1734          return false;
1735    }
1736    Instruction *insn = bb->getExit();
1737    if (bb->cfg.incidentCount() != 0) {
1738       if (!insn || !insn->asFlow()) {
1739          mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
1740          bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
1741       } else if (insn && insn->op == OP_BRA && !insn->getPredicate() &&
1742                  tailBB->cfg.incidentCount() == 0) {
1743          // RA doesn't like having blocks around with no incident edge,
1744          // so we create a fake one to make it happy
1745          bb->cfg.attach(&tailBB->cfg, Graph::Edge::TREE);
1746       }
1747    }
1748
1749    curLoopDepth -= 1;
1750
1751    return true;
1752 }
1753
1754 bool
1755 Converter::visit(nir_instr *insn)
1756 {
1757    // we need an insertion point for on the fly generated immediate loads
1758    immInsertPos = bb->getExit();
1759    switch (insn->type) {
1760    case nir_instr_type_alu:
1761       return visit(nir_instr_as_alu(insn));
1762    case nir_instr_type_deref:
1763       return visit(nir_instr_as_deref(insn));
1764    case nir_instr_type_intrinsic:
1765       return visit(nir_instr_as_intrinsic(insn));
1766    case nir_instr_type_jump:
1767       return visit(nir_instr_as_jump(insn));
1768    case nir_instr_type_load_const:
1769       return visit(nir_instr_as_load_const(insn));
1770    case nir_instr_type_ssa_undef:
1771       return visit(nir_instr_as_ssa_undef(insn));
1772    case nir_instr_type_tex:
1773       return visit(nir_instr_as_tex(insn));
1774    default:
1775       ERROR("unknown nir_instr type %u\n", insn->type);
1776       return false;
1777    }
1778    return true;
1779 }
1780
1781 SVSemantic
1782 Converter::convert(nir_intrinsic_op intr)
1783 {
1784    switch (intr) {
1785    case nir_intrinsic_load_base_vertex:
1786       return SV_BASEVERTEX;
1787    case nir_intrinsic_load_base_instance:
1788       return SV_BASEINSTANCE;
1789    case nir_intrinsic_load_draw_id:
1790       return SV_DRAWID;
1791    case nir_intrinsic_load_front_face:
1792       return SV_FACE;
1793    case nir_intrinsic_load_helper_invocation:
1794       return SV_THREAD_KILL;
1795    case nir_intrinsic_load_instance_id:
1796       return SV_INSTANCE_ID;
1797    case nir_intrinsic_load_invocation_id:
1798       return SV_INVOCATION_ID;
1799    case nir_intrinsic_load_local_group_size:
1800       return SV_NTID;
1801    case nir_intrinsic_load_local_invocation_id:
1802       return SV_TID;
1803    case nir_intrinsic_load_num_work_groups:
1804       return SV_NCTAID;
1805    case nir_intrinsic_load_patch_vertices_in:
1806       return SV_VERTEX_COUNT;
1807    case nir_intrinsic_load_primitive_id:
1808       return SV_PRIMITIVE_ID;
1809    case nir_intrinsic_load_sample_id:
1810       return SV_SAMPLE_INDEX;
1811    case nir_intrinsic_load_sample_mask_in:
1812       return SV_SAMPLE_MASK;
1813    case nir_intrinsic_load_sample_pos:
1814       return SV_SAMPLE_POS;
1815    case nir_intrinsic_load_subgroup_eq_mask:
1816       return SV_LANEMASK_EQ;
1817    case nir_intrinsic_load_subgroup_ge_mask:
1818       return SV_LANEMASK_GE;
1819    case nir_intrinsic_load_subgroup_gt_mask:
1820       return SV_LANEMASK_GT;
1821    case nir_intrinsic_load_subgroup_le_mask:
1822       return SV_LANEMASK_LE;
1823    case nir_intrinsic_load_subgroup_lt_mask:
1824       return SV_LANEMASK_LT;
1825    case nir_intrinsic_load_subgroup_invocation:
1826       return SV_LANEID;
1827    case nir_intrinsic_load_tess_coord:
1828       return SV_TESS_COORD;
1829    case nir_intrinsic_load_tess_level_inner:
1830       return SV_TESS_INNER;
1831    case nir_intrinsic_load_tess_level_outer:
1832       return SV_TESS_OUTER;
1833    case nir_intrinsic_load_vertex_id:
1834       return SV_VERTEX_ID;
1835    case nir_intrinsic_load_work_group_id:
1836       return SV_CTAID;
1837    default:
1838       ERROR("unknown SVSemantic for nir_intrinsic_op %s\n",
1839             nir_intrinsic_infos[intr].name);
1840       assert(false);
1841       return SV_LAST;
1842    }
1843 }
1844
1845 ImgFormat
1846 Converter::convertGLImgFormat(GLuint format)
1847 {
1848 #define FMT_CASE(a, b) \
1849   case GL_ ## a: return nv50_ir::FMT_ ## b
1850
1851    switch (format) {
1852    FMT_CASE(NONE, NONE);
1853
1854    FMT_CASE(RGBA32F, RGBA32F);
1855    FMT_CASE(RGBA16F, RGBA16F);
1856    FMT_CASE(RG32F, RG32F);
1857    FMT_CASE(RG16F, RG16F);
1858    FMT_CASE(R11F_G11F_B10F, R11G11B10F);
1859    FMT_CASE(R32F, R32F);
1860    FMT_CASE(R16F, R16F);
1861
1862    FMT_CASE(RGBA32UI, RGBA32UI);
1863    FMT_CASE(RGBA16UI, RGBA16UI);
1864    FMT_CASE(RGB10_A2UI, RGB10A2UI);
1865    FMT_CASE(RGBA8UI, RGBA8UI);
1866    FMT_CASE(RG32UI, RG32UI);
1867    FMT_CASE(RG16UI, RG16UI);
1868    FMT_CASE(RG8UI, RG8UI);
1869    FMT_CASE(R32UI, R32UI);
1870    FMT_CASE(R16UI, R16UI);
1871    FMT_CASE(R8UI, R8UI);
1872
1873    FMT_CASE(RGBA32I, RGBA32I);
1874    FMT_CASE(RGBA16I, RGBA16I);
1875    FMT_CASE(RGBA8I, RGBA8I);
1876    FMT_CASE(RG32I, RG32I);
1877    FMT_CASE(RG16I, RG16I);
1878    FMT_CASE(RG8I, RG8I);
1879    FMT_CASE(R32I, R32I);
1880    FMT_CASE(R16I, R16I);
1881    FMT_CASE(R8I, R8I);
1882
1883    FMT_CASE(RGBA16, RGBA16);
1884    FMT_CASE(RGB10_A2, RGB10A2);
1885    FMT_CASE(RGBA8, RGBA8);
1886    FMT_CASE(RG16, RG16);
1887    FMT_CASE(RG8, RG8);
1888    FMT_CASE(R16, R16);
1889    FMT_CASE(R8, R8);
1890
1891    FMT_CASE(RGBA16_SNORM, RGBA16_SNORM);
1892    FMT_CASE(RGBA8_SNORM, RGBA8_SNORM);
1893    FMT_CASE(RG16_SNORM, RG16_SNORM);
1894    FMT_CASE(RG8_SNORM, RG8_SNORM);
1895    FMT_CASE(R16_SNORM, R16_SNORM);
1896    FMT_CASE(R8_SNORM, R8_SNORM);
1897
1898    FMT_CASE(BGRA_INTEGER, BGRA8);
1899    default:
1900       ERROR("unknown format %x\n", format);
1901       assert(false);
1902       return nv50_ir::FMT_NONE;
1903    }
1904 #undef FMT_CASE
1905 }
1906
1907 bool
1908 Converter::visit(nir_intrinsic_instr *insn)
1909 {
1910    nir_intrinsic_op op = insn->intrinsic;
1911    const nir_intrinsic_info &opInfo = nir_intrinsic_infos[op];
1912
1913    switch (op) {
1914    case nir_intrinsic_load_uniform: {
1915       LValues &newDefs = convert(&insn->dest);
1916       const DataType dType = getDType(insn);
1917       Value *indirect;
1918       uint32_t coffset = getIndirect(insn, 0, 0, indirect);
1919       for (uint8_t i = 0; i < insn->num_components; ++i) {
1920          loadFrom(FILE_MEMORY_CONST, 0, dType, newDefs[i], 16 * coffset, i, indirect);
1921       }
1922       break;
1923    }
1924    case nir_intrinsic_store_output:
1925    case nir_intrinsic_store_per_vertex_output: {
1926       Value *indirect;
1927       DataType dType = getSType(insn->src[0], false, false);
1928       uint32_t idx = getIndirect(insn, op == nir_intrinsic_store_output ? 1 : 2, 0, indirect);
1929
1930       for (uint8_t i = 0u; i < insn->num_components; ++i) {
1931          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
1932             continue;
1933
1934          uint8_t offset = 0;
1935          Value *src = getSrc(&insn->src[0], i);
1936          switch (prog->getType()) {
1937          case Program::TYPE_FRAGMENT: {
1938             if (info->out[idx].sn == TGSI_SEMANTIC_POSITION) {
1939                // TGSI uses a different interface than NIR, TGSI stores that
1940                // value in the z component, NIR in X
1941                offset += 2;
1942                src = mkOp1v(OP_SAT, TYPE_F32, getScratch(), src);
1943             }
1944             break;
1945          }
1946          case Program::TYPE_GEOMETRY:
1947          case Program::TYPE_VERTEX: {
1948             if (info->io.genUserClip > 0 && idx == clipVertexOutput) {
1949                mkMov(clipVtx[i], src);
1950                src = clipVtx[i];
1951             }
1952             break;
1953          }
1954          default:
1955             break;
1956          }
1957
1958          storeTo(insn, FILE_SHADER_OUTPUT, OP_EXPORT, dType, src, idx, i + offset, indirect);
1959       }
1960       break;
1961    }
1962    case nir_intrinsic_load_input:
1963    case nir_intrinsic_load_interpolated_input:
1964    case nir_intrinsic_load_output: {
1965       LValues &newDefs = convert(&insn->dest);
1966
1967       // FBFetch
1968       if (prog->getType() == Program::TYPE_FRAGMENT &&
1969           op == nir_intrinsic_load_output) {
1970          std::vector<Value*> defs, srcs;
1971          uint8_t mask = 0;
1972
1973          srcs.push_back(getSSA());
1974          srcs.push_back(getSSA());
1975          Value *x = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 0));
1976          Value *y = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 1));
1977          mkCvt(OP_CVT, TYPE_U32, srcs[0], TYPE_F32, x)->rnd = ROUND_Z;
1978          mkCvt(OP_CVT, TYPE_U32, srcs[1], TYPE_F32, y)->rnd = ROUND_Z;
1979
1980          srcs.push_back(mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LAYER, 0)));
1981          srcs.push_back(mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_SAMPLE_INDEX, 0)));
1982
1983          for (uint8_t i = 0u; i < insn->num_components; ++i) {
1984             defs.push_back(newDefs[i]);
1985             mask |= 1 << i;
1986          }
1987
1988          TexInstruction *texi = mkTex(OP_TXF, TEX_TARGET_2D_MS_ARRAY, 0, 0, defs, srcs);
1989          texi->tex.levelZero = 1;
1990          texi->tex.mask = mask;
1991          texi->tex.useOffsets = 0;
1992          texi->tex.r = 0xffff;
1993          texi->tex.s = 0xffff;
1994
1995          info->prop.fp.readsFramebuffer = true;
1996          break;
1997       }
1998
1999       const DataType dType = getDType(insn);
2000       Value *indirect;
2001       bool input = op != nir_intrinsic_load_output;
2002       operation nvirOp;
2003       uint32_t mode = 0;
2004
2005       uint32_t idx = getIndirect(insn, op == nir_intrinsic_load_interpolated_input ? 1 : 0, 0, indirect);
2006       nv50_ir_varying& vary = input ? info->in[idx] : info->out[idx];
2007
2008       // see load_barycentric_* handling
2009       if (prog->getType() == Program::TYPE_FRAGMENT) {
2010          mode = translateInterpMode(&vary, nvirOp);
2011          if (op == nir_intrinsic_load_interpolated_input) {
2012             ImmediateValue immMode;
2013             if (getSrc(&insn->src[0], 1)->getUniqueInsn()->src(0).getImmediate(immMode))
2014                mode |= immMode.reg.data.u32;
2015          }
2016       }
2017
2018       for (uint8_t i = 0u; i < insn->num_components; ++i) {
2019          uint32_t address = getSlotAddress(insn, idx, i);
2020          Symbol *sym = mkSymbol(input ? FILE_SHADER_INPUT : FILE_SHADER_OUTPUT, 0, dType, address);
2021          if (prog->getType() == Program::TYPE_FRAGMENT) {
2022             int s = 1;
2023             if (typeSizeof(dType) == 8) {
2024                Value *lo = getSSA();
2025                Value *hi = getSSA();
2026                Instruction *interp;
2027
2028                interp = mkOp1(nvirOp, TYPE_U32, lo, sym);
2029                if (nvirOp == OP_PINTERP)
2030                   interp->setSrc(s++, fp.position);
2031                if (mode & NV50_IR_INTERP_OFFSET)
2032                   interp->setSrc(s++, getSrc(&insn->src[0], 0));
2033                interp->setInterpolate(mode);
2034                interp->setIndirect(0, 0, indirect);
2035
2036                Symbol *sym1 = mkSymbol(input ? FILE_SHADER_INPUT : FILE_SHADER_OUTPUT, 0, dType, address + 4);
2037                interp = mkOp1(nvirOp, TYPE_U32, hi, sym1);
2038                if (nvirOp == OP_PINTERP)
2039                   interp->setSrc(s++, fp.position);
2040                if (mode & NV50_IR_INTERP_OFFSET)
2041                   interp->setSrc(s++, getSrc(&insn->src[0], 0));
2042                interp->setInterpolate(mode);
2043                interp->setIndirect(0, 0, indirect);
2044
2045                mkOp2(OP_MERGE, dType, newDefs[i], lo, hi);
2046             } else {
2047                Instruction *interp = mkOp1(nvirOp, dType, newDefs[i], sym);
2048                if (nvirOp == OP_PINTERP)
2049                   interp->setSrc(s++, fp.position);
2050                if (mode & NV50_IR_INTERP_OFFSET)
2051                   interp->setSrc(s++, getSrc(&insn->src[0], 0));
2052                interp->setInterpolate(mode);
2053                interp->setIndirect(0, 0, indirect);
2054             }
2055          } else {
2056             mkLoad(dType, newDefs[i], sym, indirect)->perPatch = vary.patch;
2057          }
2058       }
2059       break;
2060    }
2061    case nir_intrinsic_load_barycentric_at_offset:
2062    case nir_intrinsic_load_barycentric_at_sample:
2063    case nir_intrinsic_load_barycentric_centroid:
2064    case nir_intrinsic_load_barycentric_pixel:
2065    case nir_intrinsic_load_barycentric_sample: {
2066       LValues &newDefs = convert(&insn->dest);
2067       uint32_t mode;
2068
2069       if (op == nir_intrinsic_load_barycentric_centroid ||
2070           op == nir_intrinsic_load_barycentric_sample) {
2071          mode = NV50_IR_INTERP_CENTROID;
2072       } else if (op == nir_intrinsic_load_barycentric_at_offset) {
2073          Value *offs[2];
2074          for (uint8_t c = 0; c < 2; c++) {
2075             offs[c] = getScratch();
2076             mkOp2(OP_MIN, TYPE_F32, offs[c], getSrc(&insn->src[0], c), loadImm(NULL, 0.4375f));
2077             mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
2078             mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
2079             mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
2080          }
2081          mkOp3v(OP_INSBF, TYPE_U32, newDefs[0], offs[1], mkImm(0x1010), offs[0]);
2082
2083          mode = NV50_IR_INTERP_OFFSET;
2084       } else if (op == nir_intrinsic_load_barycentric_pixel) {
2085          mode = NV50_IR_INTERP_DEFAULT;
2086       } else if (op == nir_intrinsic_load_barycentric_at_sample) {
2087          info->prop.fp.readsSampleLocations = true;
2088          mkOp1(OP_PIXLD, TYPE_U32, newDefs[0], getSrc(&insn->src[0], 0))->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
2089          mode = NV50_IR_INTERP_OFFSET;
2090       } else {
2091          unreachable("all intrinsics already handled above");
2092       }
2093
2094       loadImm(newDefs[1], mode);
2095       break;
2096    }
2097    case nir_intrinsic_discard:
2098       mkOp(OP_DISCARD, TYPE_NONE, NULL);
2099       break;
2100    case nir_intrinsic_discard_if: {
2101       Value *pred = getSSA(1, FILE_PREDICATE);
2102       if (insn->num_components > 1) {
2103          ERROR("nir_intrinsic_discard_if only with 1 component supported!\n");
2104          assert(false);
2105          return false;
2106       }
2107       mkCmp(OP_SET, CC_NE, TYPE_U8, pred, TYPE_U32, getSrc(&insn->src[0], 0), zero);
2108       mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, pred);
2109       break;
2110    }
2111    case nir_intrinsic_load_base_vertex:
2112    case nir_intrinsic_load_base_instance:
2113    case nir_intrinsic_load_draw_id:
2114    case nir_intrinsic_load_front_face:
2115    case nir_intrinsic_load_helper_invocation:
2116    case nir_intrinsic_load_instance_id:
2117    case nir_intrinsic_load_invocation_id:
2118    case nir_intrinsic_load_local_group_size:
2119    case nir_intrinsic_load_local_invocation_id:
2120    case nir_intrinsic_load_num_work_groups:
2121    case nir_intrinsic_load_patch_vertices_in:
2122    case nir_intrinsic_load_primitive_id:
2123    case nir_intrinsic_load_sample_id:
2124    case nir_intrinsic_load_sample_mask_in:
2125    case nir_intrinsic_load_sample_pos:
2126    case nir_intrinsic_load_subgroup_eq_mask:
2127    case nir_intrinsic_load_subgroup_ge_mask:
2128    case nir_intrinsic_load_subgroup_gt_mask:
2129    case nir_intrinsic_load_subgroup_le_mask:
2130    case nir_intrinsic_load_subgroup_lt_mask:
2131    case nir_intrinsic_load_subgroup_invocation:
2132    case nir_intrinsic_load_tess_coord:
2133    case nir_intrinsic_load_tess_level_inner:
2134    case nir_intrinsic_load_tess_level_outer:
2135    case nir_intrinsic_load_vertex_id:
2136    case nir_intrinsic_load_work_group_id: {
2137       const DataType dType = getDType(insn);
2138       SVSemantic sv = convert(op);
2139       LValues &newDefs = convert(&insn->dest);
2140
2141       for (uint8_t i = 0u; i < insn->num_components; ++i) {
2142          Value *def;
2143          if (typeSizeof(dType) == 8)
2144             def = getSSA();
2145          else
2146             def = newDefs[i];
2147
2148          if (sv == SV_TID && info->prop.cp.numThreads[i] == 1) {
2149             loadImm(def, 0u);
2150          } else {
2151             Symbol *sym = mkSysVal(sv, i);
2152             Instruction *rdsv = mkOp1(OP_RDSV, TYPE_U32, def, sym);
2153             if (sv == SV_TESS_OUTER || sv == SV_TESS_INNER)
2154                rdsv->perPatch = 1;
2155          }
2156
2157          if (typeSizeof(dType) == 8)
2158             mkOp2(OP_MERGE, dType, newDefs[i], def, loadImm(getSSA(), 0u));
2159       }
2160       break;
2161    }
2162    // constants
2163    case nir_intrinsic_load_subgroup_size: {
2164       LValues &newDefs = convert(&insn->dest);
2165       loadImm(newDefs[0], 32u);
2166       break;
2167    }
2168    case nir_intrinsic_vote_all:
2169    case nir_intrinsic_vote_any:
2170    case nir_intrinsic_vote_ieq: {
2171       LValues &newDefs = convert(&insn->dest);
2172       Value *pred = getScratch(1, FILE_PREDICATE);
2173       mkCmp(OP_SET, CC_NE, TYPE_U32, pred, TYPE_U32, getSrc(&insn->src[0], 0), zero);
2174       mkOp1(OP_VOTE, TYPE_U32, pred, pred)->subOp = getSubOp(op);
2175       mkCvt(OP_CVT, TYPE_U32, newDefs[0], TYPE_U8, pred);
2176       break;
2177    }
2178    case nir_intrinsic_ballot: {
2179       LValues &newDefs = convert(&insn->dest);
2180       Value *pred = getSSA(1, FILE_PREDICATE);
2181       mkCmp(OP_SET, CC_NE, TYPE_U32, pred, TYPE_U32, getSrc(&insn->src[0], 0), zero);
2182       mkOp1(OP_VOTE, TYPE_U32, newDefs[0], pred)->subOp = NV50_IR_SUBOP_VOTE_ANY;
2183       break;
2184    }
2185    case nir_intrinsic_read_first_invocation:
2186    case nir_intrinsic_read_invocation: {
2187       LValues &newDefs = convert(&insn->dest);
2188       const DataType dType = getDType(insn);
2189       Value *tmp = getScratch();
2190
2191       if (op == nir_intrinsic_read_first_invocation) {
2192          mkOp1(OP_VOTE, TYPE_U32, tmp, mkImm(1))->subOp = NV50_IR_SUBOP_VOTE_ANY;
2193          mkOp2(OP_EXTBF, TYPE_U32, tmp, tmp, mkImm(0x2000))->subOp = NV50_IR_SUBOP_EXTBF_REV;
2194          mkOp1(OP_BFIND, TYPE_U32, tmp, tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT;
2195       } else
2196          tmp = getSrc(&insn->src[1], 0);
2197
2198       for (uint8_t i = 0; i < insn->num_components; ++i) {
2199          mkOp3(OP_SHFL, dType, newDefs[i], getSrc(&insn->src[0], i), tmp, mkImm(0x1f))
2200             ->subOp = NV50_IR_SUBOP_SHFL_IDX;
2201       }
2202       break;
2203    }
2204    case nir_intrinsic_load_per_vertex_input: {
2205       const DataType dType = getDType(insn);
2206       LValues &newDefs = convert(&insn->dest);
2207       Value *indirectVertex;
2208       Value *indirectOffset;
2209       uint32_t baseVertex = getIndirect(&insn->src[0], 0, indirectVertex);
2210       uint32_t idx = getIndirect(insn, 1, 0, indirectOffset);
2211
2212       Value *vtxBase = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
2213                               mkImm(baseVertex), indirectVertex);
2214       for (uint8_t i = 0u; i < insn->num_components; ++i) {
2215          uint32_t address = getSlotAddress(insn, idx, i);
2216          loadFrom(FILE_SHADER_INPUT, 0, dType, newDefs[i], address, 0,
2217                   indirectOffset, vtxBase, info->in[idx].patch);
2218       }
2219       break;
2220    }
2221    case nir_intrinsic_load_per_vertex_output: {
2222       const DataType dType = getDType(insn);
2223       LValues &newDefs = convert(&insn->dest);
2224       Value *indirectVertex;
2225       Value *indirectOffset;
2226       uint32_t baseVertex = getIndirect(&insn->src[0], 0, indirectVertex);
2227       uint32_t idx = getIndirect(insn, 1, 0, indirectOffset);
2228       Value *vtxBase = NULL;
2229
2230       if (indirectVertex)
2231          vtxBase = indirectVertex;
2232       else
2233          vtxBase = loadImm(NULL, baseVertex);
2234
2235       vtxBase = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, FILE_ADDRESS), outBase, vtxBase);
2236
2237       for (uint8_t i = 0u; i < insn->num_components; ++i) {
2238          uint32_t address = getSlotAddress(insn, idx, i);
2239          loadFrom(FILE_SHADER_OUTPUT, 0, dType, newDefs[i], address, 0,
2240                   indirectOffset, vtxBase, info->in[idx].patch);
2241       }
2242       break;
2243    }
2244    case nir_intrinsic_emit_vertex:
2245       if (info->io.genUserClip > 0)
2246          handleUserClipPlanes();
2247       // fallthrough
2248    case nir_intrinsic_end_primitive: {
2249       uint32_t idx = nir_intrinsic_stream_id(insn);
2250       mkOp1(getOperation(op), TYPE_U32, NULL, mkImm(idx))->fixed = 1;
2251       break;
2252    }
2253    case nir_intrinsic_load_ubo: {
2254       const DataType dType = getDType(insn);
2255       LValues &newDefs = convert(&insn->dest);
2256       Value *indirectIndex;
2257       Value *indirectOffset;
2258       uint32_t index = getIndirect(&insn->src[0], 0, indirectIndex) + 1;
2259       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2260
2261       for (uint8_t i = 0u; i < insn->num_components; ++i) {
2262          loadFrom(FILE_MEMORY_CONST, index, dType, newDefs[i], offset, i,
2263                   indirectOffset, indirectIndex);
2264       }
2265       break;
2266    }
2267    case nir_intrinsic_get_buffer_size: {
2268       LValues &newDefs = convert(&insn->dest);
2269       const DataType dType = getDType(insn);
2270       Value *indirectBuffer;
2271       uint32_t buffer = getIndirect(&insn->src[0], 0, indirectBuffer);
2272
2273       Symbol *sym = mkSymbol(FILE_MEMORY_BUFFER, buffer, dType, 0);
2274       mkOp1(OP_BUFQ, dType, newDefs[0], sym)->setIndirect(0, 0, indirectBuffer);
2275       break;
2276    }
2277    case nir_intrinsic_store_ssbo: {
2278       DataType sType = getSType(insn->src[0], false, false);
2279       Value *indirectBuffer;
2280       Value *indirectOffset;
2281       uint32_t buffer = getIndirect(&insn->src[1], 0, indirectBuffer);
2282       uint32_t offset = getIndirect(&insn->src[2], 0, indirectOffset);
2283
2284       for (uint8_t i = 0u; i < insn->num_components; ++i) {
2285          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
2286             continue;
2287          Symbol *sym = mkSymbol(FILE_MEMORY_BUFFER, buffer, sType,
2288                                 offset + i * typeSizeof(sType));
2289          mkStore(OP_STORE, sType, sym, indirectOffset, getSrc(&insn->src[0], i))
2290             ->setIndirect(0, 1, indirectBuffer);
2291       }
2292       info->io.globalAccess |= 0x2;
2293       break;
2294    }
2295    case nir_intrinsic_load_ssbo: {
2296       const DataType dType = getDType(insn);
2297       LValues &newDefs = convert(&insn->dest);
2298       Value *indirectBuffer;
2299       Value *indirectOffset;
2300       uint32_t buffer = getIndirect(&insn->src[0], 0, indirectBuffer);
2301       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2302
2303       for (uint8_t i = 0u; i < insn->num_components; ++i)
2304          loadFrom(FILE_MEMORY_BUFFER, buffer, dType, newDefs[i], offset, i,
2305                   indirectOffset, indirectBuffer);
2306
2307       info->io.globalAccess |= 0x1;
2308       break;
2309    }
2310    case nir_intrinsic_shared_atomic_add:
2311    case nir_intrinsic_shared_atomic_and:
2312    case nir_intrinsic_shared_atomic_comp_swap:
2313    case nir_intrinsic_shared_atomic_exchange:
2314    case nir_intrinsic_shared_atomic_or:
2315    case nir_intrinsic_shared_atomic_imax:
2316    case nir_intrinsic_shared_atomic_imin:
2317    case nir_intrinsic_shared_atomic_umax:
2318    case nir_intrinsic_shared_atomic_umin:
2319    case nir_intrinsic_shared_atomic_xor: {
2320       const DataType dType = getDType(insn);
2321       LValues &newDefs = convert(&insn->dest);
2322       Value *indirectOffset;
2323       uint32_t offset = getIndirect(&insn->src[0], 0, indirectOffset);
2324       Symbol *sym = mkSymbol(FILE_MEMORY_SHARED, 0, dType, offset);
2325       Instruction *atom = mkOp2(OP_ATOM, dType, newDefs[0], sym, getSrc(&insn->src[1], 0));
2326       if (op == nir_intrinsic_shared_atomic_comp_swap)
2327          atom->setSrc(2, getSrc(&insn->src[2], 0));
2328       atom->setIndirect(0, 0, indirectOffset);
2329       atom->subOp = getSubOp(op);
2330       break;
2331    }
2332    case nir_intrinsic_ssbo_atomic_add:
2333    case nir_intrinsic_ssbo_atomic_and:
2334    case nir_intrinsic_ssbo_atomic_comp_swap:
2335    case nir_intrinsic_ssbo_atomic_exchange:
2336    case nir_intrinsic_ssbo_atomic_or:
2337    case nir_intrinsic_ssbo_atomic_imax:
2338    case nir_intrinsic_ssbo_atomic_imin:
2339    case nir_intrinsic_ssbo_atomic_umax:
2340    case nir_intrinsic_ssbo_atomic_umin:
2341    case nir_intrinsic_ssbo_atomic_xor: {
2342       const DataType dType = getDType(insn);
2343       LValues &newDefs = convert(&insn->dest);
2344       Value *indirectBuffer;
2345       Value *indirectOffset;
2346       uint32_t buffer = getIndirect(&insn->src[0], 0, indirectBuffer);
2347       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2348
2349       Symbol *sym = mkSymbol(FILE_MEMORY_BUFFER, buffer, dType, offset);
2350       Instruction *atom = mkOp2(OP_ATOM, dType, newDefs[0], sym,
2351                                 getSrc(&insn->src[2], 0));
2352       if (op == nir_intrinsic_ssbo_atomic_comp_swap)
2353          atom->setSrc(2, getSrc(&insn->src[3], 0));
2354       atom->setIndirect(0, 0, indirectOffset);
2355       atom->setIndirect(0, 1, indirectBuffer);
2356       atom->subOp = getSubOp(op);
2357
2358       info->io.globalAccess |= 0x2;
2359       break;
2360    }
2361    case nir_intrinsic_bindless_image_atomic_add:
2362    case nir_intrinsic_bindless_image_atomic_and:
2363    case nir_intrinsic_bindless_image_atomic_comp_swap:
2364    case nir_intrinsic_bindless_image_atomic_exchange:
2365    case nir_intrinsic_bindless_image_atomic_max:
2366    case nir_intrinsic_bindless_image_atomic_min:
2367    case nir_intrinsic_bindless_image_atomic_or:
2368    case nir_intrinsic_bindless_image_atomic_xor:
2369    case nir_intrinsic_bindless_image_load:
2370    case nir_intrinsic_bindless_image_samples:
2371    case nir_intrinsic_bindless_image_size:
2372    case nir_intrinsic_bindless_image_store: {
2373       std::vector<Value*> srcs, defs;
2374       Value *indirect = getSrc(&insn->src[0], 0);
2375       DataType ty;
2376
2377       uint32_t mask = 0;
2378       TexInstruction::Target target =
2379          convert(nir_intrinsic_image_dim(insn), !!nir_intrinsic_image_array(insn), false);
2380       unsigned int argCount = getNIRArgCount(target);
2381       uint16_t location = 0;
2382
2383       if (opInfo.has_dest) {
2384          LValues &newDefs = convert(&insn->dest);
2385          for (uint8_t i = 0u; i < newDefs.size(); ++i) {
2386             defs.push_back(newDefs[i]);
2387             mask |= 1 << i;
2388          }
2389       }
2390
2391       switch (op) {
2392       case nir_intrinsic_bindless_image_atomic_add:
2393       case nir_intrinsic_bindless_image_atomic_and:
2394       case nir_intrinsic_bindless_image_atomic_comp_swap:
2395       case nir_intrinsic_bindless_image_atomic_exchange:
2396       case nir_intrinsic_bindless_image_atomic_max:
2397       case nir_intrinsic_bindless_image_atomic_min:
2398       case nir_intrinsic_bindless_image_atomic_or:
2399       case nir_intrinsic_bindless_image_atomic_xor:
2400          ty = getDType(insn);
2401          mask = 0x1;
2402          info->io.globalAccess |= 0x2;
2403          break;
2404       case nir_intrinsic_bindless_image_load:
2405          ty = TYPE_U32;
2406          info->io.globalAccess |= 0x1;
2407          break;
2408       case nir_intrinsic_bindless_image_store:
2409          ty = TYPE_U32;
2410          mask = 0xf;
2411          info->io.globalAccess |= 0x2;
2412          break;
2413       case nir_intrinsic_bindless_image_samples:
2414          mask = 0x8;
2415          ty = TYPE_U32;
2416          break;
2417       case nir_intrinsic_bindless_image_size:
2418          ty = TYPE_U32;
2419          break;
2420       default:
2421          unreachable("unhandled image opcode");
2422          break;
2423       }
2424
2425       // coords
2426       if (opInfo.num_srcs >= 2)
2427          for (unsigned int i = 0u; i < argCount; ++i)
2428             srcs.push_back(getSrc(&insn->src[1], i));
2429
2430       // the sampler is just another src added after coords
2431       if (opInfo.num_srcs >= 3 && target.isMS())
2432          srcs.push_back(getSrc(&insn->src[2], 0));
2433
2434       if (opInfo.num_srcs >= 4) {
2435          unsigned components = opInfo.src_components[3] ? opInfo.src_components[3] : insn->num_components;
2436          for (uint8_t i = 0u; i < components; ++i)
2437             srcs.push_back(getSrc(&insn->src[3], i));
2438       }
2439
2440       if (opInfo.num_srcs >= 5)
2441          // 1 for aotmic swap
2442          for (uint8_t i = 0u; i < opInfo.src_components[4]; ++i)
2443             srcs.push_back(getSrc(&insn->src[4], i));
2444
2445       TexInstruction *texi = mkTex(getOperation(op), target.getEnum(), location, 0, defs, srcs);
2446       texi->tex.bindless = false;
2447       texi->tex.format = &nv50_ir::TexInstruction::formatTable[convertGLImgFormat(nir_intrinsic_format(insn))];
2448       texi->tex.mask = mask;
2449       texi->tex.bindless = true;
2450       texi->cache = convert(nir_intrinsic_access(insn));
2451       texi->setType(ty);
2452       texi->subOp = getSubOp(op);
2453
2454       if (indirect)
2455          texi->setIndirectR(indirect);
2456
2457       break;
2458    }
2459    case nir_intrinsic_image_deref_atomic_add:
2460    case nir_intrinsic_image_deref_atomic_and:
2461    case nir_intrinsic_image_deref_atomic_comp_swap:
2462    case nir_intrinsic_image_deref_atomic_exchange:
2463    case nir_intrinsic_image_deref_atomic_max:
2464    case nir_intrinsic_image_deref_atomic_min:
2465    case nir_intrinsic_image_deref_atomic_or:
2466    case nir_intrinsic_image_deref_atomic_xor:
2467    case nir_intrinsic_image_deref_load:
2468    case nir_intrinsic_image_deref_samples:
2469    case nir_intrinsic_image_deref_size:
2470    case nir_intrinsic_image_deref_store: {
2471       const nir_variable *tex;
2472       std::vector<Value*> srcs, defs;
2473       Value *indirect;
2474       DataType ty;
2475
2476       uint32_t mask = 0;
2477       nir_deref_instr *deref = nir_src_as_deref(insn->src[0]);
2478       const glsl_type *type = deref->type;
2479       TexInstruction::Target target =
2480          convert((glsl_sampler_dim)type->sampler_dimensionality,
2481                  type->sampler_array, type->sampler_shadow);
2482       unsigned int argCount = getNIRArgCount(target);
2483       uint16_t location = handleDeref(deref, indirect, tex);
2484
2485       if (opInfo.has_dest) {
2486          LValues &newDefs = convert(&insn->dest);
2487          for (uint8_t i = 0u; i < newDefs.size(); ++i) {
2488             defs.push_back(newDefs[i]);
2489             mask |= 1 << i;
2490          }
2491       }
2492
2493       switch (op) {
2494       case nir_intrinsic_image_deref_atomic_add:
2495       case nir_intrinsic_image_deref_atomic_and:
2496       case nir_intrinsic_image_deref_atomic_comp_swap:
2497       case nir_intrinsic_image_deref_atomic_exchange:
2498       case nir_intrinsic_image_deref_atomic_max:
2499       case nir_intrinsic_image_deref_atomic_min:
2500       case nir_intrinsic_image_deref_atomic_or:
2501       case nir_intrinsic_image_deref_atomic_xor:
2502          ty = getDType(insn);
2503          mask = 0x1;
2504          info->io.globalAccess |= 0x2;
2505          break;
2506       case nir_intrinsic_image_deref_load:
2507          ty = TYPE_U32;
2508          info->io.globalAccess |= 0x1;
2509          break;
2510       case nir_intrinsic_image_deref_store:
2511          ty = TYPE_U32;
2512          mask = 0xf;
2513          info->io.globalAccess |= 0x2;
2514          break;
2515       case nir_intrinsic_image_deref_samples:
2516          mask = 0x8;
2517          ty = TYPE_U32;
2518          break;
2519       case nir_intrinsic_image_deref_size:
2520          ty = TYPE_U32;
2521          break;
2522       default:
2523          unreachable("unhandled image opcode");
2524          break;
2525       }
2526
2527       // coords
2528       if (opInfo.num_srcs >= 2)
2529          for (unsigned int i = 0u; i < argCount; ++i)
2530             srcs.push_back(getSrc(&insn->src[1], i));
2531
2532       // the sampler is just another src added after coords
2533       if (opInfo.num_srcs >= 3 && target.isMS())
2534          srcs.push_back(getSrc(&insn->src[2], 0));
2535
2536       if (opInfo.num_srcs >= 4) {
2537          unsigned components = opInfo.src_components[3] ? opInfo.src_components[3] : insn->num_components;
2538          for (uint8_t i = 0u; i < components; ++i)
2539             srcs.push_back(getSrc(&insn->src[3], i));
2540       }
2541
2542       if (opInfo.num_srcs >= 5)
2543          // 1 for aotmic swap
2544          for (uint8_t i = 0u; i < opInfo.src_components[4]; ++i)
2545             srcs.push_back(getSrc(&insn->src[4], i));
2546
2547       TexInstruction *texi = mkTex(getOperation(op), target.getEnum(), location, 0, defs, srcs);
2548       texi->tex.bindless = false;
2549       texi->tex.format = &nv50_ir::TexInstruction::formatTable[convertGLImgFormat(tex->data.image.format)];
2550       texi->tex.mask = mask;
2551       texi->cache = getCacheModeFromVar(tex);
2552       texi->setType(ty);
2553       texi->subOp = getSubOp(op);
2554
2555       if (indirect)
2556          texi->setIndirectR(indirect);
2557
2558       break;
2559    }
2560    case nir_intrinsic_store_shared: {
2561       DataType sType = getSType(insn->src[0], false, false);
2562       Value *indirectOffset;
2563       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2564
2565       for (uint8_t i = 0u; i < insn->num_components; ++i) {
2566          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
2567             continue;
2568          Symbol *sym = mkSymbol(FILE_MEMORY_SHARED, 0, sType, offset + i * typeSizeof(sType));
2569          mkStore(OP_STORE, sType, sym, indirectOffset, getSrc(&insn->src[0], i));
2570       }
2571       break;
2572    }
2573    case nir_intrinsic_load_shared: {
2574       const DataType dType = getDType(insn);
2575       LValues &newDefs = convert(&insn->dest);
2576       Value *indirectOffset;
2577       uint32_t offset = getIndirect(&insn->src[0], 0, indirectOffset);
2578
2579       for (uint8_t i = 0u; i < insn->num_components; ++i)
2580          loadFrom(FILE_MEMORY_SHARED, 0, dType, newDefs[i], offset, i, indirectOffset);
2581
2582       break;
2583    }
2584    case nir_intrinsic_barrier: {
2585       // TODO: add flag to shader_info
2586       info->numBarriers = 1;
2587       Instruction *bar = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2588       bar->fixed = 1;
2589       bar->subOp = NV50_IR_SUBOP_BAR_SYNC;
2590       break;
2591    }
2592    case nir_intrinsic_group_memory_barrier:
2593    case nir_intrinsic_memory_barrier:
2594    case nir_intrinsic_memory_barrier_atomic_counter:
2595    case nir_intrinsic_memory_barrier_buffer:
2596    case nir_intrinsic_memory_barrier_image:
2597    case nir_intrinsic_memory_barrier_shared: {
2598       Instruction *bar = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2599       bar->fixed = 1;
2600       bar->subOp = getSubOp(op);
2601       break;
2602    }
2603    case nir_intrinsic_shader_clock: {
2604       const DataType dType = getDType(insn);
2605       LValues &newDefs = convert(&insn->dest);
2606
2607       loadImm(newDefs[0], 0u);
2608       mkOp1(OP_RDSV, dType, newDefs[1], mkSysVal(SV_CLOCK, 0))->fixed = 1;
2609       break;
2610    }
2611    default:
2612       ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos[op].name);
2613       return false;
2614    }
2615
2616    return true;
2617 }
2618
2619 bool
2620 Converter::visit(nir_jump_instr *insn)
2621 {
2622    switch (insn->type) {
2623    case nir_jump_return:
2624       // TODO: this only works in the main function
2625       mkFlow(OP_BRA, exit, CC_ALWAYS, NULL);
2626       bb->cfg.attach(&exit->cfg, Graph::Edge::CROSS);
2627       break;
2628    case nir_jump_break:
2629    case nir_jump_continue: {
2630       bool isBreak = insn->type == nir_jump_break;
2631       nir_block *block = insn->instr.block;
2632       assert(!block->successors[1]);
2633       BasicBlock *target = convert(block->successors[0]);
2634       mkFlow(isBreak ? OP_BREAK : OP_CONT, target, CC_ALWAYS, NULL);
2635       bb->cfg.attach(&target->cfg, isBreak ? Graph::Edge::CROSS : Graph::Edge::BACK);
2636       break;
2637    }
2638    default:
2639       ERROR("unknown nir_jump_type %u\n", insn->type);
2640       return false;
2641    }
2642
2643    return true;
2644 }
2645
2646 Value*
2647 Converter::convert(nir_load_const_instr *insn, uint8_t idx)
2648 {
2649    Value *val;
2650
2651    if (immInsertPos)
2652       setPosition(immInsertPos, true);
2653    else
2654       setPosition(bb, false);
2655
2656    switch (insn->def.bit_size) {
2657    case 64:
2658       val = loadImm(getSSA(8), insn->value[idx].u64);
2659       break;
2660    case 32:
2661       val = loadImm(getSSA(4), insn->value[idx].u32);
2662       break;
2663    case 16:
2664       val = loadImm(getSSA(2), insn->value[idx].u16);
2665       break;
2666    case 8:
2667       val = loadImm(getSSA(1), insn->value[idx].u8);
2668       break;
2669    default:
2670       unreachable("unhandled bit size!\n");
2671    }
2672    setPosition(bb, true);
2673    return val;
2674 }
2675
2676 bool
2677 Converter::visit(nir_load_const_instr *insn)
2678 {
2679    assert(insn->def.bit_size <= 64);
2680    immediates[insn->def.index] = insn;
2681    return true;
2682 }
2683
2684 #define DEFAULT_CHECKS \
2685       if (insn->dest.dest.ssa.num_components > 1) { \
2686          ERROR("nir_alu_instr only supported with 1 component!\n"); \
2687          return false; \
2688       } \
2689       if (insn->dest.write_mask != 1) { \
2690          ERROR("nir_alu_instr only with write_mask of 1 supported!\n"); \
2691          return false; \
2692       }
2693 bool
2694 Converter::visit(nir_alu_instr *insn)
2695 {
2696    const nir_op op = insn->op;
2697    const nir_op_info &info = nir_op_infos[op];
2698    DataType dType = getDType(insn);
2699    const std::vector<DataType> sTypes = getSTypes(insn);
2700
2701    Instruction *oldPos = this->bb->getExit();
2702
2703    switch (op) {
2704    case nir_op_fabs:
2705    case nir_op_iabs:
2706    case nir_op_fadd:
2707    case nir_op_iadd:
2708    case nir_op_fand:
2709    case nir_op_iand:
2710    case nir_op_fceil:
2711    case nir_op_fcos:
2712    case nir_op_fddx:
2713    case nir_op_fddx_coarse:
2714    case nir_op_fddx_fine:
2715    case nir_op_fddy:
2716    case nir_op_fddy_coarse:
2717    case nir_op_fddy_fine:
2718    case nir_op_fdiv:
2719    case nir_op_idiv:
2720    case nir_op_udiv:
2721    case nir_op_fexp2:
2722    case nir_op_ffloor:
2723    case nir_op_ffma:
2724    case nir_op_flog2:
2725    case nir_op_fmax:
2726    case nir_op_imax:
2727    case nir_op_umax:
2728    case nir_op_fmin:
2729    case nir_op_imin:
2730    case nir_op_umin:
2731    case nir_op_fmod:
2732    case nir_op_imod:
2733    case nir_op_umod:
2734    case nir_op_fmul:
2735    case nir_op_imul:
2736    case nir_op_imul_high:
2737    case nir_op_umul_high:
2738    case nir_op_fneg:
2739    case nir_op_ineg:
2740    case nir_op_fnot:
2741    case nir_op_inot:
2742    case nir_op_for:
2743    case nir_op_ior:
2744    case nir_op_pack_64_2x32_split:
2745    case nir_op_fpow:
2746    case nir_op_frcp:
2747    case nir_op_frem:
2748    case nir_op_irem:
2749    case nir_op_frsq:
2750    case nir_op_fsat:
2751    case nir_op_ishr:
2752    case nir_op_ushr:
2753    case nir_op_fsin:
2754    case nir_op_fsqrt:
2755    case nir_op_fsub:
2756    case nir_op_isub:
2757    case nir_op_ftrunc:
2758    case nir_op_ishl:
2759    case nir_op_fxor:
2760    case nir_op_ixor: {
2761       DEFAULT_CHECKS;
2762       LValues &newDefs = convert(&insn->dest);
2763       operation preOp = preOperationNeeded(op);
2764       if (preOp != OP_NOP) {
2765          assert(info.num_inputs < 2);
2766          Value *tmp = getSSA(typeSizeof(dType));
2767          Instruction *i0 = mkOp(preOp, dType, tmp);
2768          Instruction *i1 = mkOp(getOperation(op), dType, newDefs[0]);
2769          if (info.num_inputs) {
2770             i0->setSrc(0, getSrc(&insn->src[0]));
2771             i1->setSrc(0, tmp);
2772          }
2773          i1->subOp = getSubOp(op);
2774       } else {
2775          Instruction *i = mkOp(getOperation(op), dType, newDefs[0]);
2776          for (unsigned s = 0u; s < info.num_inputs; ++s) {
2777             i->setSrc(s, getSrc(&insn->src[s]));
2778          }
2779          i->subOp = getSubOp(op);
2780       }
2781       break;
2782    }
2783    case nir_op_ifind_msb:
2784    case nir_op_ufind_msb: {
2785       DEFAULT_CHECKS;
2786       LValues &newDefs = convert(&insn->dest);
2787       dType = sTypes[0];
2788       mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0]));
2789       break;
2790    }
2791    case nir_op_fround_even: {
2792       DEFAULT_CHECKS;
2793       LValues &newDefs = convert(&insn->dest);
2794       mkCvt(OP_CVT, dType, newDefs[0], dType, getSrc(&insn->src[0]))->rnd = ROUND_NI;
2795       break;
2796    }
2797    // convert instructions
2798    case nir_op_f2f32:
2799    case nir_op_f2i32:
2800    case nir_op_f2u32:
2801    case nir_op_i2f32:
2802    case nir_op_i2i32:
2803    case nir_op_u2f32:
2804    case nir_op_u2u32:
2805    case nir_op_f2f64:
2806    case nir_op_f2i64:
2807    case nir_op_f2u64:
2808    case nir_op_i2f64:
2809    case nir_op_i2i64:
2810    case nir_op_u2f64:
2811    case nir_op_u2u64: {
2812       DEFAULT_CHECKS;
2813       LValues &newDefs = convert(&insn->dest);
2814       Instruction *i = mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0]));
2815       if (op == nir_op_f2i32 || op == nir_op_f2i64 || op == nir_op_f2u32 || op == nir_op_f2u64)
2816          i->rnd = ROUND_Z;
2817       i->sType = sTypes[0];
2818       break;
2819    }
2820    // compare instructions
2821    case nir_op_feq32:
2822    case nir_op_ieq32:
2823    case nir_op_fge32:
2824    case nir_op_ige32:
2825    case nir_op_uge32:
2826    case nir_op_flt32:
2827    case nir_op_ilt32:
2828    case nir_op_ult32:
2829    case nir_op_fne32:
2830    case nir_op_ine32: {
2831       DEFAULT_CHECKS;
2832       LValues &newDefs = convert(&insn->dest);
2833       Instruction *i = mkCmp(getOperation(op),
2834                              getCondCode(op),
2835                              dType,
2836                              newDefs[0],
2837                              dType,
2838                              getSrc(&insn->src[0]),
2839                              getSrc(&insn->src[1]));
2840       if (info.num_inputs == 3)
2841          i->setSrc(2, getSrc(&insn->src[2]));
2842       i->sType = sTypes[0];
2843       break;
2844    }
2845    // those are weird ALU ops and need special handling, because
2846    //   1. they are always componend based
2847    //   2. they basically just merge multiple values into one data type
2848    case nir_op_imov:
2849    case nir_op_fmov:
2850       if (!insn->dest.dest.is_ssa && insn->dest.dest.reg.reg->num_array_elems) {
2851          nir_reg_dest& reg = insn->dest.dest.reg;
2852          uint32_t goffset = regToLmemOffset[reg.reg->index];
2853          uint8_t comps = reg.reg->num_components;
2854          uint8_t size = reg.reg->bit_size / 8;
2855          uint8_t csize = 4 * size; // TODO after fixing MemoryOpts: comps * size;
2856          uint32_t aoffset = csize * reg.base_offset;
2857          Value *indirect = NULL;
2858
2859          if (reg.indirect)
2860             indirect = mkOp2v(OP_MUL, TYPE_U32, getSSA(4, FILE_ADDRESS),
2861                               getSrc(reg.indirect, 0), mkImm(csize));
2862
2863          for (uint8_t i = 0u; i < comps; ++i) {
2864             if (!((1u << i) & insn->dest.write_mask))
2865                continue;
2866
2867             Symbol *sym = mkSymbol(FILE_MEMORY_LOCAL, 0, dType, goffset + aoffset + i * size);
2868             mkStore(OP_STORE, dType, sym, indirect, getSrc(&insn->src[0], i));
2869          }
2870          break;
2871       } else if (!insn->src[0].src.is_ssa && insn->src[0].src.reg.reg->num_array_elems) {
2872          LValues &newDefs = convert(&insn->dest);
2873          nir_reg_src& reg = insn->src[0].src.reg;
2874          uint32_t goffset = regToLmemOffset[reg.reg->index];
2875          // uint8_t comps = reg.reg->num_components;
2876          uint8_t size = reg.reg->bit_size / 8;
2877          uint8_t csize = 4 * size; // TODO after fixing MemoryOpts: comps * size;
2878          uint32_t aoffset = csize * reg.base_offset;
2879          Value *indirect = NULL;
2880
2881          if (reg.indirect)
2882             indirect = mkOp2v(OP_MUL, TYPE_U32, getSSA(4, FILE_ADDRESS), getSrc(reg.indirect, 0), mkImm(csize));
2883
2884          for (uint8_t i = 0u; i < newDefs.size(); ++i)
2885             loadFrom(FILE_MEMORY_LOCAL, 0, dType, newDefs[i], goffset + aoffset, i, indirect);
2886
2887          break;
2888       } else {
2889          LValues &newDefs = convert(&insn->dest);
2890          for (LValues::size_type c = 0u; c < newDefs.size(); ++c) {
2891             mkMov(newDefs[c], getSrc(&insn->src[0], c), dType);
2892          }
2893       }
2894       break;
2895    case nir_op_vec2:
2896    case nir_op_vec3:
2897    case nir_op_vec4: {
2898       LValues &newDefs = convert(&insn->dest);
2899       for (LValues::size_type c = 0u; c < newDefs.size(); ++c) {
2900          mkMov(newDefs[c], getSrc(&insn->src[c]), dType);
2901       }
2902       break;
2903    }
2904    // (un)pack
2905    case nir_op_pack_64_2x32: {
2906       LValues &newDefs = convert(&insn->dest);
2907       Instruction *merge = mkOp(OP_MERGE, dType, newDefs[0]);
2908       merge->setSrc(0, getSrc(&insn->src[0], 0));
2909       merge->setSrc(1, getSrc(&insn->src[0], 1));
2910       break;
2911    }
2912    case nir_op_pack_half_2x16_split: {
2913       LValues &newDefs = convert(&insn->dest);
2914       Value *tmpH = getSSA();
2915       Value *tmpL = getSSA();
2916
2917       mkCvt(OP_CVT, TYPE_F16, tmpL, TYPE_F32, getSrc(&insn->src[0]));
2918       mkCvt(OP_CVT, TYPE_F16, tmpH, TYPE_F32, getSrc(&insn->src[1]));
2919       mkOp3(OP_INSBF, TYPE_U32, newDefs[0], tmpH, mkImm(0x1010), tmpL);
2920       break;
2921    }
2922    case nir_op_unpack_half_2x16_split_x:
2923    case nir_op_unpack_half_2x16_split_y: {
2924       LValues &newDefs = convert(&insn->dest);
2925       Instruction *cvt = mkCvt(OP_CVT, TYPE_F32, newDefs[0], TYPE_F16, getSrc(&insn->src[0]));
2926       if (op == nir_op_unpack_half_2x16_split_y)
2927          cvt->subOp = 1;
2928       break;
2929    }
2930    case nir_op_unpack_64_2x32: {
2931       LValues &newDefs = convert(&insn->dest);
2932       mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, newDefs[1]);
2933       break;
2934    }
2935    case nir_op_unpack_64_2x32_split_x: {
2936       LValues &newDefs = convert(&insn->dest);
2937       mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, getSSA());
2938       break;
2939    }
2940    case nir_op_unpack_64_2x32_split_y: {
2941       LValues &newDefs = convert(&insn->dest);
2942       mkOp1(OP_SPLIT, dType, getSSA(), getSrc(&insn->src[0]))->setDef(1, newDefs[0]);
2943       break;
2944    }
2945    // special instructions
2946    case nir_op_fsign:
2947    case nir_op_isign: {
2948       DEFAULT_CHECKS;
2949       DataType iType;
2950       if (::isFloatType(dType))
2951          iType = TYPE_F32;
2952       else
2953          iType = TYPE_S32;
2954
2955       LValues &newDefs = convert(&insn->dest);
2956       LValue *val0 = getScratch();
2957       LValue *val1 = getScratch();
2958       mkCmp(OP_SET, CC_GT, iType, val0, dType, getSrc(&insn->src[0]), zero);
2959       mkCmp(OP_SET, CC_LT, iType, val1, dType, getSrc(&insn->src[0]), zero);
2960
2961       if (dType == TYPE_F64) {
2962          mkOp2(OP_SUB, iType, val0, val0, val1);
2963          mkCvt(OP_CVT, TYPE_F64, newDefs[0], iType, val0);
2964       } else if (dType == TYPE_S64 || dType == TYPE_U64) {
2965          mkOp2(OP_SUB, iType, val0, val1, val0);
2966          mkOp2(OP_SHR, iType, val1, val0, loadImm(NULL, 31));
2967          mkOp2(OP_MERGE, dType, newDefs[0], val0, val1);
2968       } else if (::isFloatType(dType))
2969          mkOp2(OP_SUB, iType, newDefs[0], val0, val1);
2970       else
2971          mkOp2(OP_SUB, iType, newDefs[0], val1, val0);
2972       break;
2973    }
2974    case nir_op_fcsel:
2975    case nir_op_b32csel: {
2976       DEFAULT_CHECKS;
2977       LValues &newDefs = convert(&insn->dest);
2978       mkCmp(OP_SLCT, CC_NE, dType, newDefs[0], sTypes[0], getSrc(&insn->src[1]), getSrc(&insn->src[2]), getSrc(&insn->src[0]));
2979       break;
2980    }
2981    case nir_op_ibitfield_extract:
2982    case nir_op_ubitfield_extract: {
2983       DEFAULT_CHECKS;
2984       Value *tmp = getSSA();
2985       LValues &newDefs = convert(&insn->dest);
2986       mkOp3(OP_INSBF, dType, tmp, getSrc(&insn->src[2]), loadImm(NULL, 0x808), getSrc(&insn->src[1]));
2987       mkOp2(OP_EXTBF, dType, newDefs[0], getSrc(&insn->src[0]), tmp);
2988       break;
2989    }
2990    case nir_op_bfm: {
2991       DEFAULT_CHECKS;
2992       LValues &newDefs = convert(&insn->dest);
2993       mkOp3(OP_INSBF, dType, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 0x808), getSrc(&insn->src[1]));
2994       break;
2995    }
2996    case nir_op_bitfield_insert: {
2997       DEFAULT_CHECKS;
2998       LValues &newDefs = convert(&insn->dest);
2999       LValue *temp = getSSA();
3000       mkOp3(OP_INSBF, TYPE_U32, temp, getSrc(&insn->src[3]), mkImm(0x808), getSrc(&insn->src[2]));
3001       mkOp3(OP_INSBF, dType, newDefs[0], getSrc(&insn->src[1]), temp, getSrc(&insn->src[0]));
3002       break;
3003    }
3004    case nir_op_bit_count: {
3005       DEFAULT_CHECKS;
3006       LValues &newDefs = convert(&insn->dest);
3007       mkOp2(OP_POPCNT, dType, newDefs[0], getSrc(&insn->src[0]), getSrc(&insn->src[0]));
3008       break;
3009    }
3010    case nir_op_bitfield_reverse: {
3011       DEFAULT_CHECKS;
3012       LValues &newDefs = convert(&insn->dest);
3013       mkOp2(OP_EXTBF, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), mkImm(0x2000))->subOp = NV50_IR_SUBOP_EXTBF_REV;
3014       break;
3015    }
3016    case nir_op_find_lsb: {
3017       DEFAULT_CHECKS;
3018       LValues &newDefs = convert(&insn->dest);
3019       Value *tmp = getSSA();
3020       mkOp2(OP_EXTBF, TYPE_U32, tmp, getSrc(&insn->src[0]), mkImm(0x2000))->subOp = NV50_IR_SUBOP_EXTBF_REV;
3021       mkOp1(OP_BFIND, TYPE_U32, newDefs[0], tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT;
3022       break;
3023    }
3024    // boolean conversions
3025    case nir_op_b2f32: {
3026       DEFAULT_CHECKS;
3027       LValues &newDefs = convert(&insn->dest);
3028       mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1.0f));
3029       break;
3030    }
3031    case nir_op_b2f64: {
3032       DEFAULT_CHECKS;
3033       LValues &newDefs = convert(&insn->dest);
3034       Value *tmp = getSSA(4);
3035       mkOp2(OP_AND, TYPE_U32, tmp, getSrc(&insn->src[0]), loadImm(NULL, 0x3ff00000));
3036       mkOp2(OP_MERGE, TYPE_U64, newDefs[0], loadImm(NULL, 0), tmp);
3037       break;
3038    }
3039    case nir_op_f2b32:
3040    case nir_op_i2b32: {
3041       DEFAULT_CHECKS;
3042       LValues &newDefs = convert(&insn->dest);
3043       Value *src1;
3044       if (typeSizeof(sTypes[0]) == 8) {
3045          src1 = loadImm(getSSA(8), 0.0);
3046       } else {
3047          src1 = zero;
3048       }
3049       CondCode cc = op == nir_op_f2b32 ? CC_NEU : CC_NE;
3050       mkCmp(OP_SET, cc, TYPE_U32, newDefs[0], sTypes[0], getSrc(&insn->src[0]), src1);
3051       break;
3052    }
3053    case nir_op_b2i32: {
3054       DEFAULT_CHECKS;
3055       LValues &newDefs = convert(&insn->dest);
3056       mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1));
3057       break;
3058    }
3059    case nir_op_b2i64: {
3060       DEFAULT_CHECKS;
3061       LValues &newDefs = convert(&insn->dest);
3062       LValue *def = getScratch();
3063       mkOp2(OP_AND, TYPE_U32, def, getSrc(&insn->src[0]), loadImm(NULL, 1));
3064       mkOp2(OP_MERGE, TYPE_S64, newDefs[0], def, loadImm(NULL, 0));
3065       break;
3066    }
3067    default:
3068       ERROR("unknown nir_op %s\n", info.name);
3069       return false;
3070    }
3071
3072    if (!oldPos) {
3073       oldPos = this->bb->getEntry();
3074       oldPos->precise = insn->exact;
3075    }
3076
3077    if (unlikely(!oldPos))
3078       return true;
3079
3080    while (oldPos->next) {
3081       oldPos = oldPos->next;
3082       oldPos->precise = insn->exact;
3083    }
3084    oldPos->saturate = insn->dest.saturate;
3085
3086    return true;
3087 }
3088 #undef DEFAULT_CHECKS
3089
3090 bool
3091 Converter::visit(nir_ssa_undef_instr *insn)
3092 {
3093    LValues &newDefs = convert(&insn->def);
3094    for (uint8_t i = 0u; i < insn->def.num_components; ++i) {
3095       mkOp(OP_NOP, TYPE_NONE, newDefs[i]);
3096    }
3097    return true;
3098 }
3099
3100 #define CASE_SAMPLER(ty) \
3101    case GLSL_SAMPLER_DIM_ ## ty : \
3102       if (isArray && !isShadow) \
3103          return TEX_TARGET_ ## ty ## _ARRAY; \
3104       else if (!isArray && isShadow) \
3105          return TEX_TARGET_## ty ## _SHADOW; \
3106       else if (isArray && isShadow) \
3107          return TEX_TARGET_## ty ## _ARRAY_SHADOW; \
3108       else \
3109          return TEX_TARGET_ ## ty
3110
3111 TexTarget
3112 Converter::convert(glsl_sampler_dim dim, bool isArray, bool isShadow)
3113 {
3114    switch (dim) {
3115    CASE_SAMPLER(1D);
3116    CASE_SAMPLER(2D);
3117    CASE_SAMPLER(CUBE);
3118    case GLSL_SAMPLER_DIM_3D:
3119       return TEX_TARGET_3D;
3120    case GLSL_SAMPLER_DIM_MS:
3121       if (isArray)
3122          return TEX_TARGET_2D_MS_ARRAY;
3123       return TEX_TARGET_2D_MS;
3124    case GLSL_SAMPLER_DIM_RECT:
3125       if (isShadow)
3126          return TEX_TARGET_RECT_SHADOW;
3127       return TEX_TARGET_RECT;
3128    case GLSL_SAMPLER_DIM_BUF:
3129       return TEX_TARGET_BUFFER;
3130    case GLSL_SAMPLER_DIM_EXTERNAL:
3131       return TEX_TARGET_2D;
3132    default:
3133       ERROR("unknown glsl_sampler_dim %u\n", dim);
3134       assert(false);
3135       return TEX_TARGET_COUNT;
3136    }
3137 }
3138 #undef CASE_SAMPLER
3139
3140 Value*
3141 Converter::applyProjection(Value *src, Value *proj)
3142 {
3143    if (!proj)
3144       return src;
3145    return mkOp2v(OP_MUL, TYPE_F32, getScratch(), src, proj);
3146 }
3147
3148 unsigned int
3149 Converter::getNIRArgCount(TexInstruction::Target& target)
3150 {
3151    unsigned int result = target.getArgCount();
3152    if (target.isCube() && target.isArray())
3153       result--;
3154    if (target.isMS())
3155       result--;
3156    return result;
3157 }
3158
3159 uint16_t
3160 Converter::handleDeref(nir_deref_instr *deref, Value * &indirect, const nir_variable * &tex)
3161 {
3162    typedef std::pair<uint32_t,Value*> DerefPair;
3163    std::list<DerefPair> derefs;
3164
3165    uint16_t result = 0;
3166    while (deref->deref_type != nir_deref_type_var) {
3167       switch (deref->deref_type) {
3168       case nir_deref_type_array: {
3169          Value *indirect;
3170          uint8_t size = type_size(deref->type, true);
3171          result += size * getIndirect(&deref->arr.index, 0, indirect);
3172
3173          if (indirect) {
3174             derefs.push_front(std::make_pair(size, indirect));
3175          }
3176
3177          break;
3178       }
3179       case nir_deref_type_struct: {
3180          result += nir_deref_instr_parent(deref)->type->struct_location_offset(deref->strct.index);
3181          break;
3182       }
3183       case nir_deref_type_var:
3184       default:
3185          unreachable("nir_deref_type_var reached in handleDeref!");
3186          break;
3187       }
3188       deref = nir_deref_instr_parent(deref);
3189    }
3190
3191    indirect = NULL;
3192    for (std::list<DerefPair>::const_iterator it = derefs.begin(); it != derefs.end(); ++it) {
3193       Value *offset = mkOp2v(OP_MUL, TYPE_U32, getSSA(), loadImm(getSSA(), it->first), it->second);
3194       if (indirect)
3195          indirect = mkOp2v(OP_ADD, TYPE_U32, getSSA(), indirect, offset);
3196       else
3197          indirect = offset;
3198    }
3199
3200    tex = nir_deref_instr_get_variable(deref);
3201    assert(tex);
3202
3203    return result + tex->data.driver_location;
3204 }
3205
3206 CacheMode
3207 Converter::convert(enum gl_access_qualifier access)
3208 {
3209    switch (access) {
3210    case ACCESS_VOLATILE:
3211       return CACHE_CV;
3212    case ACCESS_COHERENT:
3213       return CACHE_CG;
3214    default:
3215       return CACHE_CA;
3216    }
3217 }
3218
3219 CacheMode
3220 Converter::getCacheModeFromVar(const nir_variable *var)
3221 {
3222    return convert(var->data.image.access);
3223 }
3224
3225 bool
3226 Converter::visit(nir_tex_instr *insn)
3227 {
3228    switch (insn->op) {
3229    case nir_texop_lod:
3230    case nir_texop_query_levels:
3231    case nir_texop_tex:
3232    case nir_texop_texture_samples:
3233    case nir_texop_tg4:
3234    case nir_texop_txb:
3235    case nir_texop_txd:
3236    case nir_texop_txf:
3237    case nir_texop_txf_ms:
3238    case nir_texop_txl:
3239    case nir_texop_txs: {
3240       LValues &newDefs = convert(&insn->dest);
3241       std::vector<Value*> srcs;
3242       std::vector<Value*> defs;
3243       std::vector<nir_src*> offsets;
3244       uint8_t mask = 0;
3245       bool lz = false;
3246       Value *proj = NULL;
3247       TexInstruction::Target target = convert(insn->sampler_dim, insn->is_array, insn->is_shadow);
3248       operation op = getOperation(insn->op);
3249
3250       int r, s;
3251       int biasIdx = nir_tex_instr_src_index(insn, nir_tex_src_bias);
3252       int compIdx = nir_tex_instr_src_index(insn, nir_tex_src_comparator);
3253       int coordsIdx = nir_tex_instr_src_index(insn, nir_tex_src_coord);
3254       int ddxIdx = nir_tex_instr_src_index(insn, nir_tex_src_ddx);
3255       int ddyIdx = nir_tex_instr_src_index(insn, nir_tex_src_ddy);
3256       int msIdx = nir_tex_instr_src_index(insn, nir_tex_src_ms_index);
3257       int lodIdx = nir_tex_instr_src_index(insn, nir_tex_src_lod);
3258       int offsetIdx = nir_tex_instr_src_index(insn, nir_tex_src_offset);
3259       int projIdx = nir_tex_instr_src_index(insn, nir_tex_src_projector);
3260       int sampOffIdx = nir_tex_instr_src_index(insn, nir_tex_src_sampler_offset);
3261       int texOffIdx = nir_tex_instr_src_index(insn, nir_tex_src_texture_offset);
3262       int sampHandleIdx = nir_tex_instr_src_index(insn, nir_tex_src_sampler_handle);
3263       int texHandleIdx = nir_tex_instr_src_index(insn, nir_tex_src_texture_handle);
3264
3265       bool bindless = sampHandleIdx != -1 || texHandleIdx != -1;
3266       assert((sampHandleIdx != -1) == (texHandleIdx != -1));
3267
3268       if (projIdx != -1)
3269          proj = mkOp1v(OP_RCP, TYPE_F32, getScratch(), getSrc(&insn->src[projIdx].src, 0));
3270
3271       srcs.resize(insn->coord_components);
3272       for (uint8_t i = 0u; i < insn->coord_components; ++i)
3273          srcs[i] = applyProjection(getSrc(&insn->src[coordsIdx].src, i), proj);
3274
3275       // sometimes we get less args than target.getArgCount, but codegen expects the latter
3276       if (insn->coord_components) {
3277          uint32_t argCount = target.getArgCount();
3278
3279          if (target.isMS())
3280             argCount -= 1;
3281
3282          for (uint32_t i = 0u; i < (argCount - insn->coord_components); ++i)
3283             srcs.push_back(getSSA());
3284       }
3285
3286       if (insn->op == nir_texop_texture_samples)
3287          srcs.push_back(zero);
3288       else if (!insn->num_srcs)
3289          srcs.push_back(loadImm(NULL, 0));
3290       if (biasIdx != -1)
3291          srcs.push_back(getSrc(&insn->src[biasIdx].src, 0));
3292       if (lodIdx != -1)
3293          srcs.push_back(getSrc(&insn->src[lodIdx].src, 0));
3294       else if (op == OP_TXF)
3295          lz = true;
3296       if (msIdx != -1)
3297          srcs.push_back(getSrc(&insn->src[msIdx].src, 0));
3298       if (offsetIdx != -1)
3299          offsets.push_back(&insn->src[offsetIdx].src);
3300       if (compIdx != -1)
3301          srcs.push_back(applyProjection(getSrc(&insn->src[compIdx].src, 0), proj));
3302       if (texOffIdx != -1) {
3303          srcs.push_back(getSrc(&insn->src[texOffIdx].src, 0));
3304          texOffIdx = srcs.size() - 1;
3305       }
3306       if (sampOffIdx != -1) {
3307          srcs.push_back(getSrc(&insn->src[sampOffIdx].src, 0));
3308          sampOffIdx = srcs.size() - 1;
3309       }
3310       if (bindless) {
3311          // currently we use the lower bits
3312          Value *split[2];
3313          Value *handle = getSrc(&insn->src[sampHandleIdx].src, 0);
3314
3315          mkSplit(split, 4, handle);
3316
3317          srcs.push_back(split[0]);
3318          texOffIdx = srcs.size() - 1;
3319       }
3320
3321       r = bindless ? 0xff : insn->texture_index;
3322       s = bindless ? 0x1f : insn->sampler_index;
3323
3324       defs.resize(newDefs.size());
3325       for (uint8_t d = 0u; d < newDefs.size(); ++d) {
3326          defs[d] = newDefs[d];
3327          mask |= 1 << d;
3328       }
3329       if (target.isMS() || (op == OP_TEX && prog->getType() != Program::TYPE_FRAGMENT))
3330          lz = true;
3331
3332       TexInstruction *texi = mkTex(op, target.getEnum(), r, s, defs, srcs);
3333       texi->tex.levelZero = lz;
3334       texi->tex.mask = mask;
3335       texi->tex.bindless = bindless;
3336
3337       if (texOffIdx != -1)
3338          texi->tex.rIndirectSrc = texOffIdx;
3339       if (sampOffIdx != -1)
3340          texi->tex.sIndirectSrc = sampOffIdx;
3341
3342       switch (insn->op) {
3343       case nir_texop_tg4:
3344          if (!target.isShadow())
3345             texi->tex.gatherComp = insn->component;
3346          break;
3347       case nir_texop_txs:
3348          texi->tex.query = TXQ_DIMS;
3349          break;
3350       case nir_texop_texture_samples:
3351          texi->tex.mask = 0x4;
3352          texi->tex.query = TXQ_TYPE;
3353          break;
3354       case nir_texop_query_levels:
3355          texi->tex.mask = 0x8;
3356          texi->tex.query = TXQ_DIMS;
3357          break;
3358       default:
3359          break;
3360       }
3361
3362       texi->tex.useOffsets = offsets.size();
3363       if (texi->tex.useOffsets) {
3364          for (uint8_t s = 0; s < texi->tex.useOffsets; ++s) {
3365             for (uint32_t c = 0u; c < 3; ++c) {
3366                uint8_t s2 = std::min(c, target.getDim() - 1);
3367                texi->offset[s][c].set(getSrc(offsets[s], s2));
3368                texi->offset[s][c].setInsn(texi);
3369             }
3370          }
3371       }
3372
3373       if (op == OP_TXG && offsetIdx == -1) {
3374          if (nir_tex_instr_has_explicit_tg4_offsets(insn)) {
3375             texi->tex.useOffsets = 4;
3376             setPosition(texi, false);
3377             for (uint8_t i = 0; i < 4; ++i) {
3378                for (uint8_t j = 0; j < 2; ++j) {
3379                   texi->offset[i][j].set(loadImm(NULL, insn->tg4_offsets[i][j]));
3380                   texi->offset[i][j].setInsn(texi);
3381                }
3382             }
3383             setPosition(texi, true);
3384          }
3385       }
3386
3387       if (ddxIdx != -1 && ddyIdx != -1) {
3388          for (uint8_t c = 0u; c < target.getDim() + target.isCube(); ++c) {
3389             texi->dPdx[c].set(getSrc(&insn->src[ddxIdx].src, c));
3390             texi->dPdy[c].set(getSrc(&insn->src[ddyIdx].src, c));
3391          }
3392       }
3393
3394       break;
3395    }
3396    default:
3397       ERROR("unknown nir_texop %u\n", insn->op);
3398       return false;
3399    }
3400    return true;
3401 }
3402
3403 bool
3404 Converter::visit(nir_deref_instr *deref)
3405 {
3406    // we just ignore those, because images intrinsics are the only place where
3407    // we should end up with deref sources and those have to backtrack anyway
3408    // to get the nir_variable. This code just exists to handle some special
3409    // cases.
3410    switch (deref->deref_type) {
3411    case nir_deref_type_array:
3412    case nir_deref_type_struct:
3413    case nir_deref_type_var:
3414       break;
3415    default:
3416       ERROR("unknown nir_deref_instr %u\n", deref->deref_type);
3417       return false;
3418    }
3419    return true;
3420 }
3421
3422 bool
3423 Converter::run()
3424 {
3425    bool progress;
3426
3427    if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE)
3428       nir_print_shader(nir, stderr);
3429
3430    struct nir_lower_subgroups_options subgroup_options = {
3431       .subgroup_size = 32,
3432       .ballot_bit_size = 32,
3433    };
3434
3435    NIR_PASS_V(nir, nir_lower_io, nir_var_all, type_size, (nir_lower_io_options)0);
3436    NIR_PASS_V(nir, nir_lower_subgroups, &subgroup_options);
3437    NIR_PASS_V(nir, nir_lower_regs_to_ssa);
3438    NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
3439    NIR_PASS_V(nir, nir_lower_vars_to_ssa);
3440    NIR_PASS_V(nir, nir_lower_alu_to_scalar);
3441    NIR_PASS_V(nir, nir_lower_phis_to_scalar);
3442
3443    do {
3444       progress = false;
3445       NIR_PASS(progress, nir, nir_copy_prop);
3446       NIR_PASS(progress, nir, nir_opt_remove_phis);
3447       NIR_PASS(progress, nir, nir_opt_trivial_continues);
3448       NIR_PASS(progress, nir, nir_opt_cse);
3449       NIR_PASS(progress, nir, nir_opt_algebraic);
3450       NIR_PASS(progress, nir, nir_opt_constant_folding);
3451       NIR_PASS(progress, nir, nir_copy_prop);
3452       NIR_PASS(progress, nir, nir_opt_dce);
3453       NIR_PASS(progress, nir, nir_opt_dead_cf);
3454    } while (progress);
3455
3456    NIR_PASS_V(nir, nir_lower_bool_to_int32);
3457    NIR_PASS_V(nir, nir_lower_locals_to_regs);
3458    NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp);
3459    NIR_PASS_V(nir, nir_convert_from_ssa, true);
3460
3461    // Garbage collect dead instructions
3462    nir_sweep(nir);
3463
3464    if (!parseNIR()) {
3465       ERROR("Couldn't prase NIR!\n");
3466       return false;
3467    }
3468
3469    if (!assignSlots()) {
3470       ERROR("Couldn't assign slots!\n");
3471       return false;
3472    }
3473
3474    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
3475       nir_print_shader(nir, stderr);
3476
3477    nir_foreach_function(function, nir) {
3478       if (!visit(function))
3479          return false;
3480    }
3481
3482    return true;
3483 }
3484
3485 } // unnamed namespace
3486
3487 namespace nv50_ir {
3488
3489 bool
3490 Program::makeFromNIR(struct nv50_ir_prog_info *info)
3491 {
3492    nir_shader *nir = (nir_shader*)info->bin.source;
3493    Converter converter(this, nir, info);
3494    bool result = converter.run();
3495    if (!result)
3496       return result;
3497    LoweringHelper lowering;
3498    lowering.run(this);
3499    tlsSize = info->bin.tlsSpace;
3500    return result;
3501 }
3502
3503 } // namespace nv50_ir