2 * Copyright 2017 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Karol Herbst <kherbst@redhat.com>
25 #include "compiler/nir/nir.h"
27 #include "util/u_debug.h"
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_from_common.h"
31 #include "codegen/nv50_ir_lowering_helper.h"
32 #include "codegen/nv50_ir_util.h"
34 #if __cplusplus >= 201103L
35 #include <unordered_map>
37 #include <tr1/unordered_map>
45 #if __cplusplus >= 201103L
47 using std::unordered_map
;
50 using std::tr1::unordered_map
;
53 using namespace nv50_ir
;
56 type_size(const struct glsl_type
*type
, bool bindless
)
58 return glsl_count_attribute_slots(type
, false);
61 class Converter
: public ConverterCommon
64 Converter(Program
*, nir_shader
*, nv50_ir_prog_info
*);
68 typedef std::vector
<LValue
*> LValues
;
69 typedef unordered_map
<unsigned, LValues
> NirDefMap
;
70 typedef unordered_map
<unsigned, nir_load_const_instr
*> ImmediateMap
;
71 typedef unordered_map
<unsigned, uint32_t> NirArrayLMemOffsets
;
72 typedef unordered_map
<unsigned, BasicBlock
*> NirBlockMap
;
74 TexTarget
convert(glsl_sampler_dim
, bool isArray
, bool isShadow
);
75 LValues
& convert(nir_alu_dest
*);
76 BasicBlock
* convert(nir_block
*);
77 LValues
& convert(nir_dest
*);
78 SVSemantic
convert(nir_intrinsic_op
);
79 Value
* convert(nir_load_const_instr
*, uint8_t);
80 LValues
& convert(nir_register
*);
81 LValues
& convert(nir_ssa_def
*);
83 ImgFormat
convertGLImgFormat(GLuint
);
85 Value
* getSrc(nir_alu_src
*, uint8_t component
= 0);
86 Value
* getSrc(nir_register
*, uint8_t);
87 Value
* getSrc(nir_src
*, uint8_t, bool indirect
= false);
88 Value
* getSrc(nir_ssa_def
*, uint8_t);
90 // returned value is the constant part of the given source (either the
91 // nir_src or the selected source component of an intrinsic). Even though
92 // this is mostly an optimization to be able to skip indirects in a few
93 // cases, sometimes we require immediate values or set some fileds on
94 // instructions (e.g. tex) in order for codegen to consume those.
95 // If the found value has not a constant part, the Value gets returned
96 // through the Value parameter.
97 uint32_t getIndirect(nir_src
*, uint8_t, Value
*&);
98 uint32_t getIndirect(nir_intrinsic_instr
*, uint8_t s
, uint8_t c
, Value
*&);
100 uint32_t getSlotAddress(nir_intrinsic_instr
*, uint8_t idx
, uint8_t slot
);
102 void setInterpolate(nv50_ir_varying
*,
107 Instruction
*loadFrom(DataFile
, uint8_t, DataType
, Value
*def
, uint32_t base
,
108 uint8_t c
, Value
*indirect0
= NULL
,
109 Value
*indirect1
= NULL
, bool patch
= false);
110 void storeTo(nir_intrinsic_instr
*, DataFile
, operation
, DataType
,
111 Value
*src
, uint8_t idx
, uint8_t c
, Value
*indirect0
= NULL
,
112 Value
*indirect1
= NULL
);
114 bool isFloatType(nir_alu_type
);
115 bool isSignedType(nir_alu_type
);
116 bool isResultFloat(nir_op
);
117 bool isResultSigned(nir_op
);
119 DataType
getDType(nir_alu_instr
*);
120 DataType
getDType(nir_intrinsic_instr
*);
121 DataType
getDType(nir_intrinsic_instr
*, bool isSigned
);
122 DataType
getDType(nir_op
, uint8_t);
124 std::vector
<DataType
> getSTypes(nir_alu_instr
*);
125 DataType
getSType(nir_src
&, bool isFloat
, bool isSigned
);
127 operation
getOperation(nir_intrinsic_op
);
128 operation
getOperation(nir_op
);
129 operation
getOperation(nir_texop
);
130 operation
preOperationNeeded(nir_op
);
132 int getSubOp(nir_intrinsic_op
);
133 int getSubOp(nir_op
);
135 CondCode
getCondCode(nir_op
);
140 bool visit(nir_alu_instr
*);
141 bool visit(nir_block
*);
142 bool visit(nir_cf_node
*);
143 bool visit(nir_deref_instr
*);
144 bool visit(nir_function
*);
145 bool visit(nir_if
*);
146 bool visit(nir_instr
*);
147 bool visit(nir_intrinsic_instr
*);
148 bool visit(nir_jump_instr
*);
149 bool visit(nir_load_const_instr
*);
150 bool visit(nir_loop
*);
151 bool visit(nir_ssa_undef_instr
*);
152 bool visit(nir_tex_instr
*);
155 Value
* applyProjection(Value
*src
, Value
*proj
);
156 unsigned int getNIRArgCount(TexInstruction::Target
&);
159 uint16_t handleDeref(nir_deref_instr
*, Value
* & indirect
, const nir_variable
* &);
160 CacheMode
getCacheModeFromVar(const nir_variable
*);
166 ImmediateMap immediates
;
167 NirArrayLMemOffsets regToLmemOffset
;
169 unsigned int curLoopDepth
;
173 Instruction
*immInsertPos
;
175 int clipVertexOutput
;
184 Converter::Converter(Program
*prog
, nir_shader
*nir
, nv50_ir_prog_info
*info
)
185 : ConverterCommon(prog
, info
),
190 zero
= mkImm((uint32_t)0);
194 Converter::convert(nir_block
*block
)
196 NirBlockMap::iterator it
= blocks
.find(block
->index
);
197 if (it
!= blocks
.end())
200 BasicBlock
*bb
= new BasicBlock(func
);
201 blocks
[block
->index
] = bb
;
206 Converter::isFloatType(nir_alu_type type
)
208 return nir_alu_type_get_base_type(type
) == nir_type_float
;
212 Converter::isSignedType(nir_alu_type type
)
214 return nir_alu_type_get_base_type(type
) == nir_type_int
;
218 Converter::isResultFloat(nir_op op
)
220 const nir_op_info
&info
= nir_op_infos
[op
];
221 if (info
.output_type
!= nir_type_invalid
)
222 return isFloatType(info
.output_type
);
224 ERROR("isResultFloat not implemented for %s\n", nir_op_infos
[op
].name
);
230 Converter::isResultSigned(nir_op op
)
233 // there is no umul and we get wrong results if we treat all muls as signed
238 const nir_op_info
&info
= nir_op_infos
[op
];
239 if (info
.output_type
!= nir_type_invalid
)
240 return isSignedType(info
.output_type
);
241 ERROR("isResultSigned not implemented for %s\n", nir_op_infos
[op
].name
);
248 Converter::getDType(nir_alu_instr
*insn
)
250 if (insn
->dest
.dest
.is_ssa
)
251 return getDType(insn
->op
, insn
->dest
.dest
.ssa
.bit_size
);
253 return getDType(insn
->op
, insn
->dest
.dest
.reg
.reg
->bit_size
);
257 Converter::getDType(nir_intrinsic_instr
*insn
)
260 switch (insn
->intrinsic
) {
261 case nir_intrinsic_shared_atomic_imax
:
262 case nir_intrinsic_shared_atomic_imin
:
263 case nir_intrinsic_ssbo_atomic_imax
:
264 case nir_intrinsic_ssbo_atomic_imin
:
272 return getDType(insn
, isSigned
);
276 Converter::getDType(nir_intrinsic_instr
*insn
, bool isSigned
)
278 if (insn
->dest
.is_ssa
)
279 return typeOfSize(insn
->dest
.ssa
.bit_size
/ 8, false, isSigned
);
281 return typeOfSize(insn
->dest
.reg
.reg
->bit_size
/ 8, false, isSigned
);
285 Converter::getDType(nir_op op
, uint8_t bitSize
)
287 DataType ty
= typeOfSize(bitSize
/ 8, isResultFloat(op
), isResultSigned(op
));
288 if (ty
== TYPE_NONE
) {
289 ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos
[op
].name
, bitSize
);
295 std::vector
<DataType
>
296 Converter::getSTypes(nir_alu_instr
*insn
)
298 const nir_op_info
&info
= nir_op_infos
[insn
->op
];
299 std::vector
<DataType
> res(info
.num_inputs
);
301 for (uint8_t i
= 0; i
< info
.num_inputs
; ++i
) {
302 if (info
.input_types
[i
] != nir_type_invalid
) {
303 res
[i
] = getSType(insn
->src
[i
].src
, isFloatType(info
.input_types
[i
]), isSignedType(info
.input_types
[i
]));
305 ERROR("getSType not implemented for %s idx %u\n", info
.name
, i
);
316 Converter::getSType(nir_src
&src
, bool isFloat
, bool isSigned
)
320 bitSize
= src
.ssa
->bit_size
;
322 bitSize
= src
.reg
.reg
->bit_size
;
324 DataType ty
= typeOfSize(bitSize
/ 8, isFloat
, isSigned
);
325 if (ty
== TYPE_NONE
) {
333 ERROR("couldn't get Type for %s with bitSize %u\n", str
, bitSize
);
340 Converter::getOperation(nir_op op
)
343 // basic ops with float and int variants
353 case nir_op_ifind_msb
:
354 case nir_op_ufind_msb
:
376 case nir_op_fddx_coarse
:
377 case nir_op_fddx_fine
:
380 case nir_op_fddy_coarse
:
381 case nir_op_fddy_fine
:
399 case nir_op_pack_64_2x32_split
:
413 case nir_op_imul_high
:
414 case nir_op_umul_high
:
462 ERROR("couldn't get operation for op %s\n", nir_op_infos
[op
].name
);
469 Converter::getOperation(nir_texop op
)
481 case nir_texop_txf_ms
:
487 case nir_texop_query_levels
:
488 case nir_texop_texture_samples
:
492 ERROR("couldn't get operation for nir_texop %u\n", op
);
499 Converter::getOperation(nir_intrinsic_op op
)
502 case nir_intrinsic_emit_vertex
:
504 case nir_intrinsic_end_primitive
:
506 case nir_intrinsic_image_deref_atomic_add
:
507 case nir_intrinsic_image_deref_atomic_and
:
508 case nir_intrinsic_image_deref_atomic_comp_swap
:
509 case nir_intrinsic_image_deref_atomic_exchange
:
510 case nir_intrinsic_image_deref_atomic_max
:
511 case nir_intrinsic_image_deref_atomic_min
:
512 case nir_intrinsic_image_deref_atomic_or
:
513 case nir_intrinsic_image_deref_atomic_xor
:
515 case nir_intrinsic_image_deref_load
:
517 case nir_intrinsic_image_deref_samples
:
518 case nir_intrinsic_image_deref_size
:
520 case nir_intrinsic_image_deref_store
:
523 ERROR("couldn't get operation for nir_intrinsic_op %u\n", op
);
530 Converter::preOperationNeeded(nir_op op
)
542 Converter::getSubOp(nir_op op
)
545 case nir_op_imul_high
:
546 case nir_op_umul_high
:
547 return NV50_IR_SUBOP_MUL_HIGH
;
554 Converter::getSubOp(nir_intrinsic_op op
)
557 case nir_intrinsic_image_deref_atomic_add
:
558 case nir_intrinsic_shared_atomic_add
:
559 case nir_intrinsic_ssbo_atomic_add
:
560 return NV50_IR_SUBOP_ATOM_ADD
;
561 case nir_intrinsic_image_deref_atomic_and
:
562 case nir_intrinsic_shared_atomic_and
:
563 case nir_intrinsic_ssbo_atomic_and
:
564 return NV50_IR_SUBOP_ATOM_AND
;
565 case nir_intrinsic_image_deref_atomic_comp_swap
:
566 case nir_intrinsic_shared_atomic_comp_swap
:
567 case nir_intrinsic_ssbo_atomic_comp_swap
:
568 return NV50_IR_SUBOP_ATOM_CAS
;
569 case nir_intrinsic_image_deref_atomic_exchange
:
570 case nir_intrinsic_shared_atomic_exchange
:
571 case nir_intrinsic_ssbo_atomic_exchange
:
572 return NV50_IR_SUBOP_ATOM_EXCH
;
573 case nir_intrinsic_image_deref_atomic_or
:
574 case nir_intrinsic_shared_atomic_or
:
575 case nir_intrinsic_ssbo_atomic_or
:
576 return NV50_IR_SUBOP_ATOM_OR
;
577 case nir_intrinsic_image_deref_atomic_max
:
578 case nir_intrinsic_shared_atomic_imax
:
579 case nir_intrinsic_shared_atomic_umax
:
580 case nir_intrinsic_ssbo_atomic_imax
:
581 case nir_intrinsic_ssbo_atomic_umax
:
582 return NV50_IR_SUBOP_ATOM_MAX
;
583 case nir_intrinsic_image_deref_atomic_min
:
584 case nir_intrinsic_shared_atomic_imin
:
585 case nir_intrinsic_shared_atomic_umin
:
586 case nir_intrinsic_ssbo_atomic_imin
:
587 case nir_intrinsic_ssbo_atomic_umin
:
588 return NV50_IR_SUBOP_ATOM_MIN
;
589 case nir_intrinsic_image_deref_atomic_xor
:
590 case nir_intrinsic_shared_atomic_xor
:
591 case nir_intrinsic_ssbo_atomic_xor
:
592 return NV50_IR_SUBOP_ATOM_XOR
;
594 case nir_intrinsic_group_memory_barrier
:
595 case nir_intrinsic_memory_barrier
:
596 case nir_intrinsic_memory_barrier_atomic_counter
:
597 case nir_intrinsic_memory_barrier_buffer
:
598 case nir_intrinsic_memory_barrier_image
:
599 return NV50_IR_SUBOP_MEMBAR(M
, GL
);
600 case nir_intrinsic_memory_barrier_shared
:
601 return NV50_IR_SUBOP_MEMBAR(M
, CTA
);
603 case nir_intrinsic_vote_all
:
604 return NV50_IR_SUBOP_VOTE_ALL
;
605 case nir_intrinsic_vote_any
:
606 return NV50_IR_SUBOP_VOTE_ANY
;
607 case nir_intrinsic_vote_ieq
:
608 return NV50_IR_SUBOP_VOTE_UNI
;
615 Converter::getCondCode(nir_op op
)
634 ERROR("couldn't get CondCode for op %s\n", nir_op_infos
[op
].name
);
641 Converter::convert(nir_alu_dest
*dest
)
643 return convert(&dest
->dest
);
647 Converter::convert(nir_dest
*dest
)
650 return convert(&dest
->ssa
);
651 if (dest
->reg
.indirect
) {
652 ERROR("no support for indirects.");
655 return convert(dest
->reg
.reg
);
659 Converter::convert(nir_register
*reg
)
661 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
662 if (it
!= regDefs
.end())
665 LValues
newDef(reg
->num_components
);
666 for (uint8_t i
= 0; i
< reg
->num_components
; i
++)
667 newDef
[i
] = getScratch(std::max(4, reg
->bit_size
/ 8));
668 return regDefs
[reg
->index
] = newDef
;
672 Converter::convert(nir_ssa_def
*def
)
674 NirDefMap::iterator it
= ssaDefs
.find(def
->index
);
675 if (it
!= ssaDefs
.end())
678 LValues
newDef(def
->num_components
);
679 for (uint8_t i
= 0; i
< def
->num_components
; i
++)
680 newDef
[i
] = getSSA(std::max(4, def
->bit_size
/ 8));
681 return ssaDefs
[def
->index
] = newDef
;
685 Converter::getSrc(nir_alu_src
*src
, uint8_t component
)
687 if (src
->abs
|| src
->negate
) {
688 ERROR("modifiers currently not supported on nir_alu_src\n");
691 return getSrc(&src
->src
, src
->swizzle
[component
]);
695 Converter::getSrc(nir_register
*reg
, uint8_t idx
)
697 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
698 if (it
== regDefs
.end())
699 return convert(reg
)[idx
];
700 return it
->second
[idx
];
704 Converter::getSrc(nir_src
*src
, uint8_t idx
, bool indirect
)
707 return getSrc(src
->ssa
, idx
);
709 if (src
->reg
.indirect
) {
711 return getSrc(src
->reg
.indirect
, idx
);
712 ERROR("no support for indirects.");
717 return getSrc(src
->reg
.reg
, idx
);
721 Converter::getSrc(nir_ssa_def
*src
, uint8_t idx
)
723 ImmediateMap::iterator iit
= immediates
.find(src
->index
);
724 if (iit
!= immediates
.end())
725 return convert((*iit
).second
, idx
);
727 NirDefMap::iterator it
= ssaDefs
.find(src
->index
);
728 if (it
== ssaDefs
.end()) {
729 ERROR("SSA value %u not found\n", src
->index
);
733 return it
->second
[idx
];
737 Converter::getIndirect(nir_src
*src
, uint8_t idx
, Value
*&indirect
)
739 nir_const_value
*offset
= nir_src_as_const_value(*src
);
743 return offset
->u32
[0];
746 indirect
= getSrc(src
, idx
, true);
751 Converter::getIndirect(nir_intrinsic_instr
*insn
, uint8_t s
, uint8_t c
, Value
*&indirect
)
753 int32_t idx
= nir_intrinsic_base(insn
) + getIndirect(&insn
->src
[s
], c
, indirect
);
755 indirect
= mkOp2v(OP_SHL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), indirect
, loadImm(NULL
, 4));
760 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot
, unsigned *name
, unsigned *index
)
762 assert(name
&& index
);
764 if (slot
>= VERT_ATTRIB_MAX
) {
765 ERROR("invalid varying slot %u\n", slot
);
770 if (slot
>= VERT_ATTRIB_GENERIC0
&&
771 slot
< VERT_ATTRIB_GENERIC0
+ VERT_ATTRIB_GENERIC_MAX
) {
772 *name
= TGSI_SEMANTIC_GENERIC
;
773 *index
= slot
- VERT_ATTRIB_GENERIC0
;
777 if (slot
>= VERT_ATTRIB_TEX0
&&
778 slot
< VERT_ATTRIB_TEX0
+ VERT_ATTRIB_TEX_MAX
) {
779 *name
= TGSI_SEMANTIC_TEXCOORD
;
780 *index
= slot
- VERT_ATTRIB_TEX0
;
785 case VERT_ATTRIB_COLOR0
:
786 *name
= TGSI_SEMANTIC_COLOR
;
789 case VERT_ATTRIB_COLOR1
:
790 *name
= TGSI_SEMANTIC_COLOR
;
793 case VERT_ATTRIB_EDGEFLAG
:
794 *name
= TGSI_SEMANTIC_EDGEFLAG
;
797 case VERT_ATTRIB_FOG
:
798 *name
= TGSI_SEMANTIC_FOG
;
801 case VERT_ATTRIB_NORMAL
:
802 *name
= TGSI_SEMANTIC_NORMAL
;
805 case VERT_ATTRIB_POS
:
806 *name
= TGSI_SEMANTIC_POSITION
;
809 case VERT_ATTRIB_POINT_SIZE
:
810 *name
= TGSI_SEMANTIC_PSIZE
;
814 ERROR("unknown vert attrib slot %u\n", slot
);
821 varying_slot_to_tgsi_semantic(gl_varying_slot slot
, unsigned *name
, unsigned *index
)
823 assert(name
&& index
);
825 if (slot
>= VARYING_SLOT_TESS_MAX
) {
826 ERROR("invalid varying slot %u\n", slot
);
831 if (slot
>= VARYING_SLOT_PATCH0
) {
832 *name
= TGSI_SEMANTIC_PATCH
;
833 *index
= slot
- VARYING_SLOT_PATCH0
;
837 if (slot
>= VARYING_SLOT_VAR0
) {
838 *name
= TGSI_SEMANTIC_GENERIC
;
839 *index
= slot
- VARYING_SLOT_VAR0
;
843 if (slot
>= VARYING_SLOT_TEX0
&& slot
<= VARYING_SLOT_TEX7
) {
844 *name
= TGSI_SEMANTIC_TEXCOORD
;
845 *index
= slot
- VARYING_SLOT_TEX0
;
850 case VARYING_SLOT_BFC0
:
851 *name
= TGSI_SEMANTIC_BCOLOR
;
854 case VARYING_SLOT_BFC1
:
855 *name
= TGSI_SEMANTIC_BCOLOR
;
858 case VARYING_SLOT_CLIP_DIST0
:
859 *name
= TGSI_SEMANTIC_CLIPDIST
;
862 case VARYING_SLOT_CLIP_DIST1
:
863 *name
= TGSI_SEMANTIC_CLIPDIST
;
866 case VARYING_SLOT_CLIP_VERTEX
:
867 *name
= TGSI_SEMANTIC_CLIPVERTEX
;
870 case VARYING_SLOT_COL0
:
871 *name
= TGSI_SEMANTIC_COLOR
;
874 case VARYING_SLOT_COL1
:
875 *name
= TGSI_SEMANTIC_COLOR
;
878 case VARYING_SLOT_EDGE
:
879 *name
= TGSI_SEMANTIC_EDGEFLAG
;
882 case VARYING_SLOT_FACE
:
883 *name
= TGSI_SEMANTIC_FACE
;
886 case VARYING_SLOT_FOGC
:
887 *name
= TGSI_SEMANTIC_FOG
;
890 case VARYING_SLOT_LAYER
:
891 *name
= TGSI_SEMANTIC_LAYER
;
894 case VARYING_SLOT_PNTC
:
895 *name
= TGSI_SEMANTIC_PCOORD
;
898 case VARYING_SLOT_POS
:
899 *name
= TGSI_SEMANTIC_POSITION
;
902 case VARYING_SLOT_PRIMITIVE_ID
:
903 *name
= TGSI_SEMANTIC_PRIMID
;
906 case VARYING_SLOT_PSIZ
:
907 *name
= TGSI_SEMANTIC_PSIZE
;
910 case VARYING_SLOT_TESS_LEVEL_INNER
:
911 *name
= TGSI_SEMANTIC_TESSINNER
;
914 case VARYING_SLOT_TESS_LEVEL_OUTER
:
915 *name
= TGSI_SEMANTIC_TESSOUTER
;
918 case VARYING_SLOT_VIEWPORT
:
919 *name
= TGSI_SEMANTIC_VIEWPORT_INDEX
;
923 ERROR("unknown varying slot %u\n", slot
);
930 frag_result_to_tgsi_semantic(unsigned slot
, unsigned *name
, unsigned *index
)
932 if (slot
>= FRAG_RESULT_DATA0
) {
933 *name
= TGSI_SEMANTIC_COLOR
;
934 *index
= slot
- FRAG_RESULT_COLOR
- 2; // intentional
939 case FRAG_RESULT_COLOR
:
940 *name
= TGSI_SEMANTIC_COLOR
;
943 case FRAG_RESULT_DEPTH
:
944 *name
= TGSI_SEMANTIC_POSITION
;
947 case FRAG_RESULT_SAMPLE_MASK
:
948 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
952 ERROR("unknown frag result slot %u\n", slot
);
958 // copy of _mesa_sysval_to_semantic
960 system_val_to_tgsi_semantic(unsigned val
, unsigned *name
, unsigned *index
)
965 case SYSTEM_VALUE_VERTEX_ID
:
966 *name
= TGSI_SEMANTIC_VERTEXID
;
968 case SYSTEM_VALUE_INSTANCE_ID
:
969 *name
= TGSI_SEMANTIC_INSTANCEID
;
971 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
972 *name
= TGSI_SEMANTIC_VERTEXID_NOBASE
;
974 case SYSTEM_VALUE_BASE_VERTEX
:
975 *name
= TGSI_SEMANTIC_BASEVERTEX
;
977 case SYSTEM_VALUE_BASE_INSTANCE
:
978 *name
= TGSI_SEMANTIC_BASEINSTANCE
;
980 case SYSTEM_VALUE_DRAW_ID
:
981 *name
= TGSI_SEMANTIC_DRAWID
;
985 case SYSTEM_VALUE_INVOCATION_ID
:
986 *name
= TGSI_SEMANTIC_INVOCATIONID
;
990 case SYSTEM_VALUE_FRAG_COORD
:
991 *name
= TGSI_SEMANTIC_POSITION
;
993 case SYSTEM_VALUE_FRONT_FACE
:
994 *name
= TGSI_SEMANTIC_FACE
;
996 case SYSTEM_VALUE_SAMPLE_ID
:
997 *name
= TGSI_SEMANTIC_SAMPLEID
;
999 case SYSTEM_VALUE_SAMPLE_POS
:
1000 *name
= TGSI_SEMANTIC_SAMPLEPOS
;
1002 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
1003 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
1005 case SYSTEM_VALUE_HELPER_INVOCATION
:
1006 *name
= TGSI_SEMANTIC_HELPER_INVOCATION
;
1009 // Tessellation shader
1010 case SYSTEM_VALUE_TESS_COORD
:
1011 *name
= TGSI_SEMANTIC_TESSCOORD
;
1013 case SYSTEM_VALUE_VERTICES_IN
:
1014 *name
= TGSI_SEMANTIC_VERTICESIN
;
1016 case SYSTEM_VALUE_PRIMITIVE_ID
:
1017 *name
= TGSI_SEMANTIC_PRIMID
;
1019 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
1020 *name
= TGSI_SEMANTIC_TESSOUTER
;
1022 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
1023 *name
= TGSI_SEMANTIC_TESSINNER
;
1027 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
1028 *name
= TGSI_SEMANTIC_THREAD_ID
;
1030 case SYSTEM_VALUE_WORK_GROUP_ID
:
1031 *name
= TGSI_SEMANTIC_BLOCK_ID
;
1033 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
1034 *name
= TGSI_SEMANTIC_GRID_SIZE
;
1036 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
1037 *name
= TGSI_SEMANTIC_BLOCK_SIZE
;
1040 // ARB_shader_ballot
1041 case SYSTEM_VALUE_SUBGROUP_SIZE
:
1042 *name
= TGSI_SEMANTIC_SUBGROUP_SIZE
;
1044 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
1045 *name
= TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
1047 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
1048 *name
= TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
1050 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
1051 *name
= TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
1053 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
1054 *name
= TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
1056 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
1057 *name
= TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
1059 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
1060 *name
= TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
1064 ERROR("unknown system value %u\n", val
);
1071 Converter::setInterpolate(nv50_ir_varying
*var
,
1077 case INTERP_MODE_FLAT
:
1080 case INTERP_MODE_NONE
:
1081 if (semantic
== TGSI_SEMANTIC_COLOR
)
1083 else if (semantic
== TGSI_SEMANTIC_POSITION
)
1086 case INTERP_MODE_NOPERSPECTIVE
:
1089 case INTERP_MODE_SMOOTH
:
1092 var
->centroid
= centroid
;
1096 calcSlots(const glsl_type
*type
, Program::Type stage
, const shader_info
&info
,
1097 bool input
, const nir_variable
*var
)
1099 if (!type
->is_array())
1100 return type
->count_attribute_slots(false);
1104 case Program::TYPE_GEOMETRY
:
1105 slots
= type
->uniform_locations();
1107 slots
/= info
.gs
.vertices_in
;
1109 case Program::TYPE_TESSELLATION_CONTROL
:
1110 case Program::TYPE_TESSELLATION_EVAL
:
1111 // remove first dimension
1112 if (var
->data
.patch
|| (!input
&& stage
== Program::TYPE_TESSELLATION_EVAL
))
1113 slots
= type
->uniform_locations();
1115 slots
= type
->fields
.array
->uniform_locations();
1118 slots
= type
->count_attribute_slots(false);
1125 bool Converter::assignSlots() {
1129 info
->io
.viewportId
= -1;
1130 info
->numInputs
= 0;
1132 // we have to fixup the uniform locations for arrays
1133 unsigned numImages
= 0;
1134 nir_foreach_variable(var
, &nir
->uniforms
) {
1135 const glsl_type
*type
= var
->type
;
1136 if (!type
->without_array()->is_image())
1138 var
->data
.driver_location
= numImages
;
1139 numImages
+= type
->is_array() ? type
->arrays_of_arrays_size() : 1;
1142 nir_foreach_variable(var
, &nir
->inputs
) {
1143 const glsl_type
*type
= var
->type
;
1144 int slot
= var
->data
.location
;
1145 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, true, var
);
1146 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
1147 : type
->component_slots();
1148 uint32_t frac
= var
->data
.location_frac
;
1149 uint32_t vary
= var
->data
.driver_location
;
1151 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
1156 assert(vary
+ slots
<= PIPE_MAX_SHADER_INPUTS
);
1158 switch(prog
->getType()) {
1159 case Program::TYPE_FRAGMENT
:
1160 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1161 for (uint16_t i
= 0; i
< slots
; ++i
) {
1162 setInterpolate(&info
->in
[vary
+ i
], var
->data
.interpolation
,
1163 var
->data
.centroid
| var
->data
.sample
, name
);
1166 case Program::TYPE_GEOMETRY
:
1167 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1169 case Program::TYPE_TESSELLATION_CONTROL
:
1170 case Program::TYPE_TESSELLATION_EVAL
:
1171 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1172 if (var
->data
.patch
&& name
== TGSI_SEMANTIC_PATCH
)
1173 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
1175 case Program::TYPE_VERTEX
:
1176 vert_attrib_to_tgsi_semantic((gl_vert_attrib
)slot
, &name
, &index
);
1178 case TGSI_SEMANTIC_EDGEFLAG
:
1179 info
->io
.edgeFlagIn
= vary
;
1186 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1190 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1191 info
->in
[vary
].id
= vary
;
1192 info
->in
[vary
].patch
= var
->data
.patch
;
1193 info
->in
[vary
].sn
= name
;
1194 info
->in
[vary
].si
= index
+ i
;
1195 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1197 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1199 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1201 info
->in
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1203 info
->numInputs
= std::max
<uint8_t>(info
->numInputs
, vary
);
1206 info
->numOutputs
= 0;
1207 nir_foreach_variable(var
, &nir
->outputs
) {
1208 const glsl_type
*type
= var
->type
;
1209 int slot
= var
->data
.location
;
1210 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, false, var
);
1211 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
1212 : type
->component_slots();
1213 uint32_t frac
= var
->data
.location_frac
;
1214 uint32_t vary
= var
->data
.driver_location
;
1216 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
1221 assert(vary
< PIPE_MAX_SHADER_OUTPUTS
);
1223 switch(prog
->getType()) {
1224 case Program::TYPE_FRAGMENT
:
1225 frag_result_to_tgsi_semantic((gl_frag_result
)slot
, &name
, &index
);
1227 case TGSI_SEMANTIC_COLOR
:
1228 if (!var
->data
.fb_fetch_output
)
1229 info
->prop
.fp
.numColourResults
++;
1230 info
->prop
.fp
.separateFragData
= true;
1231 // sometimes we get FRAG_RESULT_DATAX with data.index 0
1232 // sometimes we get FRAG_RESULT_DATA0 with data.index X
1233 index
= index
== 0 ? var
->data
.index
: index
;
1235 case TGSI_SEMANTIC_POSITION
:
1236 info
->io
.fragDepth
= vary
;
1237 info
->prop
.fp
.writesDepth
= true;
1239 case TGSI_SEMANTIC_SAMPLEMASK
:
1240 info
->io
.sampleMask
= vary
;
1246 case Program::TYPE_GEOMETRY
:
1247 case Program::TYPE_TESSELLATION_CONTROL
:
1248 case Program::TYPE_TESSELLATION_EVAL
:
1249 case Program::TYPE_VERTEX
:
1250 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1252 if (var
->data
.patch
&& name
!= TGSI_SEMANTIC_TESSINNER
&&
1253 name
!= TGSI_SEMANTIC_TESSOUTER
)
1254 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
1257 case TGSI_SEMANTIC_CLIPDIST
:
1258 info
->io
.genUserClip
= -1;
1260 case TGSI_SEMANTIC_CLIPVERTEX
:
1261 clipVertexOutput
= vary
;
1263 case TGSI_SEMANTIC_EDGEFLAG
:
1264 info
->io
.edgeFlagOut
= vary
;
1266 case TGSI_SEMANTIC_POSITION
:
1267 if (clipVertexOutput
< 0)
1268 clipVertexOutput
= vary
;
1275 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1279 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1280 info
->out
[vary
].id
= vary
;
1281 info
->out
[vary
].patch
= var
->data
.patch
;
1282 info
->out
[vary
].sn
= name
;
1283 info
->out
[vary
].si
= index
+ i
;
1284 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1286 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1288 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1290 info
->out
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1292 if (nir
->info
.outputs_read
& 1ll << slot
)
1293 info
->out
[vary
].oread
= 1;
1295 info
->numOutputs
= std::max
<uint8_t>(info
->numOutputs
, vary
);
1298 info
->numSysVals
= 0;
1299 for (uint8_t i
= 0; i
< 64; ++i
) {
1300 if (!(nir
->info
.system_values_read
& 1ll << i
))
1303 system_val_to_tgsi_semantic(i
, &name
, &index
);
1304 info
->sv
[info
->numSysVals
].sn
= name
;
1305 info
->sv
[info
->numSysVals
].si
= index
;
1306 info
->sv
[info
->numSysVals
].input
= 0; // TODO inferSysValDirection(sn);
1309 case SYSTEM_VALUE_INSTANCE_ID
:
1310 info
->io
.instanceId
= info
->numSysVals
;
1312 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
1313 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
1314 info
->sv
[info
->numSysVals
].patch
= 1;
1316 case SYSTEM_VALUE_VERTEX_ID
:
1317 info
->io
.vertexId
= info
->numSysVals
;
1323 info
->numSysVals
+= 1;
1326 if (info
->io
.genUserClip
> 0) {
1327 info
->io
.clipDistances
= info
->io
.genUserClip
;
1329 const unsigned int nOut
= (info
->io
.genUserClip
+ 3) / 4;
1331 for (unsigned int n
= 0; n
< nOut
; ++n
) {
1332 unsigned int i
= info
->numOutputs
++;
1333 info
->out
[i
].id
= i
;
1334 info
->out
[i
].sn
= TGSI_SEMANTIC_CLIPDIST
;
1335 info
->out
[i
].si
= n
;
1336 info
->out
[i
].mask
= ((1 << info
->io
.clipDistances
) - 1) >> (n
* 4);
1340 return info
->assignSlots(info
) == 0;
1344 Converter::getSlotAddress(nir_intrinsic_instr
*insn
, uint8_t idx
, uint8_t slot
)
1347 int offset
= nir_intrinsic_component(insn
);
1350 if (nir_intrinsic_infos
[insn
->intrinsic
].has_dest
)
1351 ty
= getDType(insn
);
1353 ty
= getSType(insn
->src
[0], false, false);
1355 switch (insn
->intrinsic
) {
1356 case nir_intrinsic_load_input
:
1357 case nir_intrinsic_load_interpolated_input
:
1358 case nir_intrinsic_load_per_vertex_input
:
1361 case nir_intrinsic_load_output
:
1362 case nir_intrinsic_load_per_vertex_output
:
1363 case nir_intrinsic_store_output
:
1364 case nir_intrinsic_store_per_vertex_output
:
1368 ERROR("unknown intrinsic in getSlotAddress %s",
1369 nir_intrinsic_infos
[insn
->intrinsic
].name
);
1375 if (typeSizeof(ty
) == 8) {
1387 assert(!input
|| idx
< PIPE_MAX_SHADER_INPUTS
);
1388 assert(input
|| idx
< PIPE_MAX_SHADER_OUTPUTS
);
1390 const nv50_ir_varying
*vary
= input
? info
->in
: info
->out
;
1391 return vary
[idx
].slot
[slot
] * 4;
1395 Converter::loadFrom(DataFile file
, uint8_t i
, DataType ty
, Value
*def
,
1396 uint32_t base
, uint8_t c
, Value
*indirect0
,
1397 Value
*indirect1
, bool patch
)
1399 unsigned int tySize
= typeSizeof(ty
);
1402 (file
== FILE_MEMORY_CONST
|| file
== FILE_MEMORY_BUFFER
|| indirect0
)) {
1403 Value
*lo
= getSSA();
1404 Value
*hi
= getSSA();
1407 mkLoad(TYPE_U32
, lo
,
1408 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
),
1410 loi
->setIndirect(0, 1, indirect1
);
1411 loi
->perPatch
= patch
;
1414 mkLoad(TYPE_U32
, hi
,
1415 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
+ 4),
1417 hii
->setIndirect(0, 1, indirect1
);
1418 hii
->perPatch
= patch
;
1420 return mkOp2(OP_MERGE
, ty
, def
, lo
, hi
);
1423 mkLoad(ty
, def
, mkSymbol(file
, i
, ty
, base
+ c
* tySize
), indirect0
);
1424 ld
->setIndirect(0, 1, indirect1
);
1425 ld
->perPatch
= patch
;
1431 Converter::storeTo(nir_intrinsic_instr
*insn
, DataFile file
, operation op
,
1432 DataType ty
, Value
*src
, uint8_t idx
, uint8_t c
,
1433 Value
*indirect0
, Value
*indirect1
)
1435 uint8_t size
= typeSizeof(ty
);
1436 uint32_t address
= getSlotAddress(insn
, idx
, c
);
1438 if (size
== 8 && indirect0
) {
1440 mkSplit(split
, 4, src
);
1442 if (op
== OP_EXPORT
) {
1443 split
[0] = mkMov(getSSA(), split
[0], ty
)->getDef(0);
1444 split
[1] = mkMov(getSSA(), split
[1], ty
)->getDef(0);
1447 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
), indirect0
,
1448 split
[0])->perPatch
= info
->out
[idx
].patch
;
1449 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
+ 4), indirect0
,
1450 split
[1])->perPatch
= info
->out
[idx
].patch
;
1452 if (op
== OP_EXPORT
)
1453 src
= mkMov(getSSA(size
), src
, ty
)->getDef(0);
1454 mkStore(op
, ty
, mkSymbol(file
, 0, ty
, address
), indirect0
,
1455 src
)->perPatch
= info
->out
[idx
].patch
;
1460 Converter::parseNIR()
1462 info
->bin
.tlsSpace
= 0;
1463 info
->io
.clipDistances
= nir
->info
.clip_distance_array_size
;
1464 info
->io
.cullDistances
= nir
->info
.cull_distance_array_size
;
1466 switch(prog
->getType()) {
1467 case Program::TYPE_COMPUTE
:
1468 info
->prop
.cp
.numThreads
[0] = nir
->info
.cs
.local_size
[0];
1469 info
->prop
.cp
.numThreads
[1] = nir
->info
.cs
.local_size
[1];
1470 info
->prop
.cp
.numThreads
[2] = nir
->info
.cs
.local_size
[2];
1471 info
->bin
.smemSize
= nir
->info
.cs
.shared_size
;
1473 case Program::TYPE_FRAGMENT
:
1474 info
->prop
.fp
.earlyFragTests
= nir
->info
.fs
.early_fragment_tests
;
1475 info
->prop
.fp
.persampleInvocation
=
1476 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_ID
) ||
1477 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1478 info
->prop
.fp
.postDepthCoverage
= nir
->info
.fs
.post_depth_coverage
;
1479 info
->prop
.fp
.readsSampleLocations
=
1480 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1481 info
->prop
.fp
.usesDiscard
= nir
->info
.fs
.uses_discard
;
1482 info
->prop
.fp
.usesSampleMaskIn
=
1483 !!(nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
);
1485 case Program::TYPE_GEOMETRY
:
1486 info
->prop
.gp
.inputPrim
= nir
->info
.gs
.input_primitive
;
1487 info
->prop
.gp
.instanceCount
= nir
->info
.gs
.invocations
;
1488 info
->prop
.gp
.maxVertices
= nir
->info
.gs
.vertices_out
;
1489 info
->prop
.gp
.outputPrim
= nir
->info
.gs
.output_primitive
;
1491 case Program::TYPE_TESSELLATION_CONTROL
:
1492 case Program::TYPE_TESSELLATION_EVAL
:
1493 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1494 info
->prop
.tp
.domain
= GL_LINES
;
1496 info
->prop
.tp
.domain
= nir
->info
.tess
.primitive_mode
;
1497 info
->prop
.tp
.outputPatchSize
= nir
->info
.tess
.tcs_vertices_out
;
1498 info
->prop
.tp
.outputPrim
=
1499 nir
->info
.tess
.point_mode
? PIPE_PRIM_POINTS
: PIPE_PRIM_TRIANGLES
;
1500 info
->prop
.tp
.partitioning
= (nir
->info
.tess
.spacing
+ 1) % 3;
1501 info
->prop
.tp
.winding
= !nir
->info
.tess
.ccw
;
1503 case Program::TYPE_VERTEX
:
1504 info
->prop
.vp
.usesDrawParameters
=
1505 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
)) ||
1506 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
)) ||
1507 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
));
1517 Converter::visit(nir_function
*function
)
1519 // we only support emiting the main function for now
1520 assert(!strcmp(function
->name
, "main"));
1521 assert(function
->impl
);
1523 // usually the blocks will set everything up, but main is special
1524 BasicBlock
*entry
= new BasicBlock(prog
->main
);
1525 exit
= new BasicBlock(prog
->main
);
1526 blocks
[nir_start_block(function
->impl
)->index
] = entry
;
1527 prog
->main
->setEntry(entry
);
1528 prog
->main
->setExit(exit
);
1530 setPosition(entry
, true);
1532 if (info
->io
.genUserClip
> 0) {
1533 for (int c
= 0; c
< 4; ++c
)
1534 clipVtx
[c
] = getScratch();
1537 switch (prog
->getType()) {
1538 case Program::TYPE_TESSELLATION_CONTROL
:
1540 OP_SUB
, TYPE_U32
, getSSA(),
1541 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LANEID
, 0)),
1542 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_INVOCATION_ID
, 0)));
1544 case Program::TYPE_FRAGMENT
: {
1545 Symbol
*sv
= mkSysVal(SV_POSITION
, 3);
1546 fragCoord
[3] = mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), sv
);
1547 fp
.position
= mkOp1v(OP_RCP
, TYPE_F32
, fragCoord
[3], fragCoord
[3]);
1554 nir_foreach_register(reg
, &function
->impl
->registers
) {
1555 if (reg
->num_array_elems
) {
1556 // TODO: packed variables would be nice, but MemoryOpt fails
1557 // replace 4 with reg->num_components
1558 uint32_t size
= 4 * reg
->num_array_elems
* (reg
->bit_size
/ 8);
1559 regToLmemOffset
[reg
->index
] = info
->bin
.tlsSpace
;
1560 info
->bin
.tlsSpace
+= size
;
1564 nir_index_ssa_defs(function
->impl
);
1565 foreach_list_typed(nir_cf_node
, node
, node
, &function
->impl
->body
) {
1570 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::TREE
);
1571 setPosition(exit
, true);
1573 if ((prog
->getType() == Program::TYPE_VERTEX
||
1574 prog
->getType() == Program::TYPE_TESSELLATION_EVAL
)
1575 && info
->io
.genUserClip
> 0)
1576 handleUserClipPlanes();
1578 // TODO: for non main function this needs to be a OP_RETURN
1579 mkOp(OP_EXIT
, TYPE_NONE
, NULL
)->terminator
= 1;
1584 Converter::visit(nir_cf_node
*node
)
1586 switch (node
->type
) {
1587 case nir_cf_node_block
:
1588 return visit(nir_cf_node_as_block(node
));
1589 case nir_cf_node_if
:
1590 return visit(nir_cf_node_as_if(node
));
1591 case nir_cf_node_loop
:
1592 return visit(nir_cf_node_as_loop(node
));
1594 ERROR("unknown nir_cf_node type %u\n", node
->type
);
1600 Converter::visit(nir_block
*block
)
1602 if (!block
->predecessors
->entries
&& block
->instr_list
.is_empty())
1605 BasicBlock
*bb
= convert(block
);
1607 setPosition(bb
, true);
1608 nir_foreach_instr(insn
, block
) {
1616 Converter::visit(nir_if
*nif
)
1618 DataType sType
= getSType(nif
->condition
, false, false);
1619 Value
*src
= getSrc(&nif
->condition
, 0);
1621 nir_block
*lastThen
= nir_if_last_then_block(nif
);
1622 nir_block
*lastElse
= nir_if_last_else_block(nif
);
1624 assert(!lastThen
->successors
[1]);
1625 assert(!lastElse
->successors
[1]);
1627 BasicBlock
*ifBB
= convert(nir_if_first_then_block(nif
));
1628 BasicBlock
*elseBB
= convert(nir_if_first_else_block(nif
));
1630 bb
->cfg
.attach(&ifBB
->cfg
, Graph::Edge::TREE
);
1631 bb
->cfg
.attach(&elseBB
->cfg
, Graph::Edge::TREE
);
1633 // we only insert joinats, if both nodes end up at the end of the if again.
1634 // the reason for this to not happens are breaks/continues/ret/... which
1635 // have their own handling
1636 if (lastThen
->successors
[0] == lastElse
->successors
[0])
1637 bb
->joinAt
= mkFlow(OP_JOINAT
, convert(lastThen
->successors
[0]),
1640 mkFlow(OP_BRA
, elseBB
, CC_EQ
, src
)->setType(sType
);
1642 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->then_list
) {
1646 setPosition(convert(lastThen
), true);
1647 if (!bb
->getExit() ||
1648 !bb
->getExit()->asFlow() ||
1649 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1650 BasicBlock
*tailBB
= convert(lastThen
->successors
[0]);
1651 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1652 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1655 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->else_list
) {
1659 setPosition(convert(lastElse
), true);
1660 if (!bb
->getExit() ||
1661 !bb
->getExit()->asFlow() ||
1662 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1663 BasicBlock
*tailBB
= convert(lastElse
->successors
[0]);
1664 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1665 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1668 if (lastThen
->successors
[0] == lastElse
->successors
[0]) {
1669 setPosition(convert(lastThen
->successors
[0]), true);
1670 mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1677 Converter::visit(nir_loop
*loop
)
1680 func
->loopNestingBound
= std::max(func
->loopNestingBound
, curLoopDepth
);
1682 BasicBlock
*loopBB
= convert(nir_loop_first_block(loop
));
1683 BasicBlock
*tailBB
=
1684 convert(nir_cf_node_as_block(nir_cf_node_next(&loop
->cf_node
)));
1685 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::TREE
);
1687 mkFlow(OP_PREBREAK
, tailBB
, CC_ALWAYS
, NULL
);
1688 setPosition(loopBB
, false);
1689 mkFlow(OP_PRECONT
, loopBB
, CC_ALWAYS
, NULL
);
1691 foreach_list_typed(nir_cf_node
, node
, node
, &loop
->body
) {
1695 Instruction
*insn
= bb
->getExit();
1696 if (bb
->cfg
.incidentCount() != 0) {
1697 if (!insn
|| !insn
->asFlow()) {
1698 mkFlow(OP_CONT
, loopBB
, CC_ALWAYS
, NULL
);
1699 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::BACK
);
1700 } else if (insn
&& insn
->op
== OP_BRA
&& !insn
->getPredicate() &&
1701 tailBB
->cfg
.incidentCount() == 0) {
1702 // RA doesn't like having blocks around with no incident edge,
1703 // so we create a fake one to make it happy
1704 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::TREE
);
1714 Converter::visit(nir_instr
*insn
)
1716 // we need an insertion point for on the fly generated immediate loads
1717 immInsertPos
= bb
->getExit();
1718 switch (insn
->type
) {
1719 case nir_instr_type_alu
:
1720 return visit(nir_instr_as_alu(insn
));
1721 case nir_instr_type_deref
:
1722 return visit(nir_instr_as_deref(insn
));
1723 case nir_instr_type_intrinsic
:
1724 return visit(nir_instr_as_intrinsic(insn
));
1725 case nir_instr_type_jump
:
1726 return visit(nir_instr_as_jump(insn
));
1727 case nir_instr_type_load_const
:
1728 return visit(nir_instr_as_load_const(insn
));
1729 case nir_instr_type_ssa_undef
:
1730 return visit(nir_instr_as_ssa_undef(insn
));
1731 case nir_instr_type_tex
:
1732 return visit(nir_instr_as_tex(insn
));
1734 ERROR("unknown nir_instr type %u\n", insn
->type
);
1741 Converter::convert(nir_intrinsic_op intr
)
1744 case nir_intrinsic_load_base_vertex
:
1745 return SV_BASEVERTEX
;
1746 case nir_intrinsic_load_base_instance
:
1747 return SV_BASEINSTANCE
;
1748 case nir_intrinsic_load_draw_id
:
1750 case nir_intrinsic_load_front_face
:
1752 case nir_intrinsic_load_helper_invocation
:
1753 return SV_THREAD_KILL
;
1754 case nir_intrinsic_load_instance_id
:
1755 return SV_INSTANCE_ID
;
1756 case nir_intrinsic_load_invocation_id
:
1757 return SV_INVOCATION_ID
;
1758 case nir_intrinsic_load_local_group_size
:
1760 case nir_intrinsic_load_local_invocation_id
:
1762 case nir_intrinsic_load_num_work_groups
:
1764 case nir_intrinsic_load_patch_vertices_in
:
1765 return SV_VERTEX_COUNT
;
1766 case nir_intrinsic_load_primitive_id
:
1767 return SV_PRIMITIVE_ID
;
1768 case nir_intrinsic_load_sample_id
:
1769 return SV_SAMPLE_INDEX
;
1770 case nir_intrinsic_load_sample_mask_in
:
1771 return SV_SAMPLE_MASK
;
1772 case nir_intrinsic_load_sample_pos
:
1773 return SV_SAMPLE_POS
;
1774 case nir_intrinsic_load_subgroup_eq_mask
:
1775 return SV_LANEMASK_EQ
;
1776 case nir_intrinsic_load_subgroup_ge_mask
:
1777 return SV_LANEMASK_GE
;
1778 case nir_intrinsic_load_subgroup_gt_mask
:
1779 return SV_LANEMASK_GT
;
1780 case nir_intrinsic_load_subgroup_le_mask
:
1781 return SV_LANEMASK_LE
;
1782 case nir_intrinsic_load_subgroup_lt_mask
:
1783 return SV_LANEMASK_LT
;
1784 case nir_intrinsic_load_subgroup_invocation
:
1786 case nir_intrinsic_load_tess_coord
:
1787 return SV_TESS_COORD
;
1788 case nir_intrinsic_load_tess_level_inner
:
1789 return SV_TESS_INNER
;
1790 case nir_intrinsic_load_tess_level_outer
:
1791 return SV_TESS_OUTER
;
1792 case nir_intrinsic_load_vertex_id
:
1793 return SV_VERTEX_ID
;
1794 case nir_intrinsic_load_work_group_id
:
1797 ERROR("unknown SVSemantic for nir_intrinsic_op %s\n",
1798 nir_intrinsic_infos
[intr
].name
);
1805 Converter::convertGLImgFormat(GLuint format
)
1807 #define FMT_CASE(a, b) \
1808 case GL_ ## a: return nv50_ir::FMT_ ## b
1811 FMT_CASE(NONE
, NONE
);
1813 FMT_CASE(RGBA32F
, RGBA32F
);
1814 FMT_CASE(RGBA16F
, RGBA16F
);
1815 FMT_CASE(RG32F
, RG32F
);
1816 FMT_CASE(RG16F
, RG16F
);
1817 FMT_CASE(R11F_G11F_B10F
, R11G11B10F
);
1818 FMT_CASE(R32F
, R32F
);
1819 FMT_CASE(R16F
, R16F
);
1821 FMT_CASE(RGBA32UI
, RGBA32UI
);
1822 FMT_CASE(RGBA16UI
, RGBA16UI
);
1823 FMT_CASE(RGB10_A2UI
, RGB10A2UI
);
1824 FMT_CASE(RGBA8UI
, RGBA8UI
);
1825 FMT_CASE(RG32UI
, RG32UI
);
1826 FMT_CASE(RG16UI
, RG16UI
);
1827 FMT_CASE(RG8UI
, RG8UI
);
1828 FMT_CASE(R32UI
, R32UI
);
1829 FMT_CASE(R16UI
, R16UI
);
1830 FMT_CASE(R8UI
, R8UI
);
1832 FMT_CASE(RGBA32I
, RGBA32I
);
1833 FMT_CASE(RGBA16I
, RGBA16I
);
1834 FMT_CASE(RGBA8I
, RGBA8I
);
1835 FMT_CASE(RG32I
, RG32I
);
1836 FMT_CASE(RG16I
, RG16I
);
1837 FMT_CASE(RG8I
, RG8I
);
1838 FMT_CASE(R32I
, R32I
);
1839 FMT_CASE(R16I
, R16I
);
1842 FMT_CASE(RGBA16
, RGBA16
);
1843 FMT_CASE(RGB10_A2
, RGB10A2
);
1844 FMT_CASE(RGBA8
, RGBA8
);
1845 FMT_CASE(RG16
, RG16
);
1850 FMT_CASE(RGBA16_SNORM
, RGBA16_SNORM
);
1851 FMT_CASE(RGBA8_SNORM
, RGBA8_SNORM
);
1852 FMT_CASE(RG16_SNORM
, RG16_SNORM
);
1853 FMT_CASE(RG8_SNORM
, RG8_SNORM
);
1854 FMT_CASE(R16_SNORM
, R16_SNORM
);
1855 FMT_CASE(R8_SNORM
, R8_SNORM
);
1857 FMT_CASE(BGRA_INTEGER
, BGRA8
);
1859 ERROR("unknown format %x\n", format
);
1861 return nv50_ir::FMT_NONE
;
1867 Converter::visit(nir_intrinsic_instr
*insn
)
1869 nir_intrinsic_op op
= insn
->intrinsic
;
1870 const nir_intrinsic_info
&opInfo
= nir_intrinsic_infos
[op
];
1873 case nir_intrinsic_load_uniform
: {
1874 LValues
&newDefs
= convert(&insn
->dest
);
1875 const DataType dType
= getDType(insn
);
1877 uint32_t coffset
= getIndirect(insn
, 0, 0, indirect
);
1878 for (uint8_t i
= 0; i
< insn
->num_components
; ++i
) {
1879 loadFrom(FILE_MEMORY_CONST
, 0, dType
, newDefs
[i
], 16 * coffset
, i
, indirect
);
1883 case nir_intrinsic_store_output
:
1884 case nir_intrinsic_store_per_vertex_output
: {
1886 DataType dType
= getSType(insn
->src
[0], false, false);
1887 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_store_output
? 1 : 2, 0, indirect
);
1889 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1890 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
1894 Value
*src
= getSrc(&insn
->src
[0], i
);
1895 switch (prog
->getType()) {
1896 case Program::TYPE_FRAGMENT
: {
1897 if (info
->out
[idx
].sn
== TGSI_SEMANTIC_POSITION
) {
1898 // TGSI uses a different interface than NIR, TGSI stores that
1899 // value in the z component, NIR in X
1901 src
= mkOp1v(OP_SAT
, TYPE_F32
, getScratch(), src
);
1905 case Program::TYPE_GEOMETRY
:
1906 case Program::TYPE_VERTEX
: {
1907 if (info
->io
.genUserClip
> 0 && idx
== clipVertexOutput
) {
1908 mkMov(clipVtx
[i
], src
);
1917 storeTo(insn
, FILE_SHADER_OUTPUT
, OP_EXPORT
, dType
, src
, idx
, i
+ offset
, indirect
);
1921 case nir_intrinsic_load_input
:
1922 case nir_intrinsic_load_interpolated_input
:
1923 case nir_intrinsic_load_output
: {
1924 LValues
&newDefs
= convert(&insn
->dest
);
1927 if (prog
->getType() == Program::TYPE_FRAGMENT
&&
1928 op
== nir_intrinsic_load_output
) {
1929 std::vector
<Value
*> defs
, srcs
;
1932 srcs
.push_back(getSSA());
1933 srcs
.push_back(getSSA());
1934 Value
*x
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 0));
1935 Value
*y
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 1));
1936 mkCvt(OP_CVT
, TYPE_U32
, srcs
[0], TYPE_F32
, x
)->rnd
= ROUND_Z
;
1937 mkCvt(OP_CVT
, TYPE_U32
, srcs
[1], TYPE_F32
, y
)->rnd
= ROUND_Z
;
1939 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LAYER
, 0)));
1940 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_SAMPLE_INDEX
, 0)));
1942 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1943 defs
.push_back(newDefs
[i
]);
1947 TexInstruction
*texi
= mkTex(OP_TXF
, TEX_TARGET_2D_MS_ARRAY
, 0, 0, defs
, srcs
);
1948 texi
->tex
.levelZero
= 1;
1949 texi
->tex
.mask
= mask
;
1950 texi
->tex
.useOffsets
= 0;
1951 texi
->tex
.r
= 0xffff;
1952 texi
->tex
.s
= 0xffff;
1954 info
->prop
.fp
.readsFramebuffer
= true;
1958 const DataType dType
= getDType(insn
);
1960 bool input
= op
!= nir_intrinsic_load_output
;
1964 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_load_interpolated_input
? 1 : 0, 0, indirect
);
1965 nv50_ir_varying
& vary
= input
? info
->in
[idx
] : info
->out
[idx
];
1967 // see load_barycentric_* handling
1968 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1969 mode
= translateInterpMode(&vary
, nvirOp
);
1970 if (op
== nir_intrinsic_load_interpolated_input
) {
1971 ImmediateValue immMode
;
1972 if (getSrc(&insn
->src
[0], 1)->getUniqueInsn()->src(0).getImmediate(immMode
))
1973 mode
|= immMode
.reg
.data
.u32
;
1977 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1978 uint32_t address
= getSlotAddress(insn
, idx
, i
);
1979 Symbol
*sym
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
);
1980 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1982 if (typeSizeof(dType
) == 8) {
1983 Value
*lo
= getSSA();
1984 Value
*hi
= getSSA();
1985 Instruction
*interp
;
1987 interp
= mkOp1(nvirOp
, TYPE_U32
, lo
, sym
);
1988 if (nvirOp
== OP_PINTERP
)
1989 interp
->setSrc(s
++, fp
.position
);
1990 if (mode
& NV50_IR_INTERP_OFFSET
)
1991 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1992 interp
->setInterpolate(mode
);
1993 interp
->setIndirect(0, 0, indirect
);
1995 Symbol
*sym1
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
+ 4);
1996 interp
= mkOp1(nvirOp
, TYPE_U32
, hi
, sym1
);
1997 if (nvirOp
== OP_PINTERP
)
1998 interp
->setSrc(s
++, fp
.position
);
1999 if (mode
& NV50_IR_INTERP_OFFSET
)
2000 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
2001 interp
->setInterpolate(mode
);
2002 interp
->setIndirect(0, 0, indirect
);
2004 mkOp2(OP_MERGE
, dType
, newDefs
[i
], lo
, hi
);
2006 Instruction
*interp
= mkOp1(nvirOp
, dType
, newDefs
[i
], sym
);
2007 if (nvirOp
== OP_PINTERP
)
2008 interp
->setSrc(s
++, fp
.position
);
2009 if (mode
& NV50_IR_INTERP_OFFSET
)
2010 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
2011 interp
->setInterpolate(mode
);
2012 interp
->setIndirect(0, 0, indirect
);
2015 mkLoad(dType
, newDefs
[i
], sym
, indirect
)->perPatch
= vary
.patch
;
2020 case nir_intrinsic_load_barycentric_at_offset
:
2021 case nir_intrinsic_load_barycentric_at_sample
:
2022 case nir_intrinsic_load_barycentric_centroid
:
2023 case nir_intrinsic_load_barycentric_pixel
:
2024 case nir_intrinsic_load_barycentric_sample
: {
2025 LValues
&newDefs
= convert(&insn
->dest
);
2028 if (op
== nir_intrinsic_load_barycentric_centroid
||
2029 op
== nir_intrinsic_load_barycentric_sample
) {
2030 mode
= NV50_IR_INTERP_CENTROID
;
2031 } else if (op
== nir_intrinsic_load_barycentric_at_offset
) {
2033 for (uint8_t c
= 0; c
< 2; c
++) {
2034 offs
[c
] = getScratch();
2035 mkOp2(OP_MIN
, TYPE_F32
, offs
[c
], getSrc(&insn
->src
[0], c
), loadImm(NULL
, 0.4375f
));
2036 mkOp2(OP_MAX
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, -0.5f
));
2037 mkOp2(OP_MUL
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, 4096.0f
));
2038 mkCvt(OP_CVT
, TYPE_S32
, offs
[c
], TYPE_F32
, offs
[c
]);
2040 mkOp3v(OP_INSBF
, TYPE_U32
, newDefs
[0], offs
[1], mkImm(0x1010), offs
[0]);
2042 mode
= NV50_IR_INTERP_OFFSET
;
2043 } else if (op
== nir_intrinsic_load_barycentric_pixel
) {
2044 mode
= NV50_IR_INTERP_DEFAULT
;
2045 } else if (op
== nir_intrinsic_load_barycentric_at_sample
) {
2046 info
->prop
.fp
.readsSampleLocations
= true;
2047 mkOp1(OP_PIXLD
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0], 0))->subOp
= NV50_IR_SUBOP_PIXLD_OFFSET
;
2048 mode
= NV50_IR_INTERP_OFFSET
;
2050 unreachable("all intrinsics already handled above");
2053 loadImm(newDefs
[1], mode
);
2056 case nir_intrinsic_discard
:
2057 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
);
2059 case nir_intrinsic_discard_if
: {
2060 Value
*pred
= getSSA(1, FILE_PREDICATE
);
2061 if (insn
->num_components
> 1) {
2062 ERROR("nir_intrinsic_discard_if only with 1 component supported!\n");
2066 mkCmp(OP_SET
, CC_NE
, TYPE_U8
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
2067 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
)->setPredicate(CC_P
, pred
);
2070 case nir_intrinsic_load_base_vertex
:
2071 case nir_intrinsic_load_base_instance
:
2072 case nir_intrinsic_load_draw_id
:
2073 case nir_intrinsic_load_front_face
:
2074 case nir_intrinsic_load_helper_invocation
:
2075 case nir_intrinsic_load_instance_id
:
2076 case nir_intrinsic_load_invocation_id
:
2077 case nir_intrinsic_load_local_group_size
:
2078 case nir_intrinsic_load_local_invocation_id
:
2079 case nir_intrinsic_load_num_work_groups
:
2080 case nir_intrinsic_load_patch_vertices_in
:
2081 case nir_intrinsic_load_primitive_id
:
2082 case nir_intrinsic_load_sample_id
:
2083 case nir_intrinsic_load_sample_mask_in
:
2084 case nir_intrinsic_load_sample_pos
:
2085 case nir_intrinsic_load_subgroup_eq_mask
:
2086 case nir_intrinsic_load_subgroup_ge_mask
:
2087 case nir_intrinsic_load_subgroup_gt_mask
:
2088 case nir_intrinsic_load_subgroup_le_mask
:
2089 case nir_intrinsic_load_subgroup_lt_mask
:
2090 case nir_intrinsic_load_subgroup_invocation
:
2091 case nir_intrinsic_load_tess_coord
:
2092 case nir_intrinsic_load_tess_level_inner
:
2093 case nir_intrinsic_load_tess_level_outer
:
2094 case nir_intrinsic_load_vertex_id
:
2095 case nir_intrinsic_load_work_group_id
: {
2096 const DataType dType
= getDType(insn
);
2097 SVSemantic sv
= convert(op
);
2098 LValues
&newDefs
= convert(&insn
->dest
);
2100 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2102 if (typeSizeof(dType
) == 8)
2107 if (sv
== SV_TID
&& info
->prop
.cp
.numThreads
[i
] == 1) {
2110 Symbol
*sym
= mkSysVal(sv
, i
);
2111 Instruction
*rdsv
= mkOp1(OP_RDSV
, TYPE_U32
, def
, sym
);
2112 if (sv
== SV_TESS_OUTER
|| sv
== SV_TESS_INNER
)
2116 if (typeSizeof(dType
) == 8)
2117 mkOp2(OP_MERGE
, dType
, newDefs
[i
], def
, loadImm(getSSA(), 0u));
2122 case nir_intrinsic_load_subgroup_size
: {
2123 LValues
&newDefs
= convert(&insn
->dest
);
2124 loadImm(newDefs
[0], 32u);
2127 case nir_intrinsic_vote_all
:
2128 case nir_intrinsic_vote_any
:
2129 case nir_intrinsic_vote_ieq
: {
2130 LValues
&newDefs
= convert(&insn
->dest
);
2131 Value
*pred
= getScratch(1, FILE_PREDICATE
);
2132 mkCmp(OP_SET
, CC_NE
, TYPE_U32
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
2133 mkOp1(OP_VOTE
, TYPE_U32
, pred
, pred
)->subOp
= getSubOp(op
);
2134 mkCvt(OP_CVT
, TYPE_U32
, newDefs
[0], TYPE_U8
, pred
);
2137 case nir_intrinsic_ballot
: {
2138 LValues
&newDefs
= convert(&insn
->dest
);
2139 Value
*pred
= getSSA(1, FILE_PREDICATE
);
2140 mkCmp(OP_SET
, CC_NE
, TYPE_U32
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
2141 mkOp1(OP_VOTE
, TYPE_U32
, newDefs
[0], pred
)->subOp
= NV50_IR_SUBOP_VOTE_ANY
;
2144 case nir_intrinsic_read_first_invocation
:
2145 case nir_intrinsic_read_invocation
: {
2146 LValues
&newDefs
= convert(&insn
->dest
);
2147 const DataType dType
= getDType(insn
);
2148 Value
*tmp
= getScratch();
2150 if (op
== nir_intrinsic_read_first_invocation
) {
2151 mkOp1(OP_VOTE
, TYPE_U32
, tmp
, mkImm(1))->subOp
= NV50_IR_SUBOP_VOTE_ANY
;
2152 mkOp2(OP_EXTBF
, TYPE_U32
, tmp
, tmp
, mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2153 mkOp1(OP_BFIND
, TYPE_U32
, tmp
, tmp
)->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
2155 tmp
= getSrc(&insn
->src
[1], 0);
2157 for (uint8_t i
= 0; i
< insn
->num_components
; ++i
) {
2158 mkOp3(OP_SHFL
, dType
, newDefs
[i
], getSrc(&insn
->src
[0], i
), tmp
, mkImm(0x1f))
2159 ->subOp
= NV50_IR_SUBOP_SHFL_IDX
;
2163 case nir_intrinsic_load_per_vertex_input
: {
2164 const DataType dType
= getDType(insn
);
2165 LValues
&newDefs
= convert(&insn
->dest
);
2166 Value
*indirectVertex
;
2167 Value
*indirectOffset
;
2168 uint32_t baseVertex
= getIndirect(&insn
->src
[0], 0, indirectVertex
);
2169 uint32_t idx
= getIndirect(insn
, 1, 0, indirectOffset
);
2171 Value
*vtxBase
= mkOp2v(OP_PFETCH
, TYPE_U32
, getSSA(4, FILE_ADDRESS
),
2172 mkImm(baseVertex
), indirectVertex
);
2173 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2174 uint32_t address
= getSlotAddress(insn
, idx
, i
);
2175 loadFrom(FILE_SHADER_INPUT
, 0, dType
, newDefs
[i
], address
, 0,
2176 indirectOffset
, vtxBase
, info
->in
[idx
].patch
);
2180 case nir_intrinsic_load_per_vertex_output
: {
2181 const DataType dType
= getDType(insn
);
2182 LValues
&newDefs
= convert(&insn
->dest
);
2183 Value
*indirectVertex
;
2184 Value
*indirectOffset
;
2185 uint32_t baseVertex
= getIndirect(&insn
->src
[0], 0, indirectVertex
);
2186 uint32_t idx
= getIndirect(insn
, 1, 0, indirectOffset
);
2187 Value
*vtxBase
= NULL
;
2190 vtxBase
= indirectVertex
;
2192 vtxBase
= loadImm(NULL
, baseVertex
);
2194 vtxBase
= mkOp2v(OP_ADD
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), outBase
, vtxBase
);
2196 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2197 uint32_t address
= getSlotAddress(insn
, idx
, i
);
2198 loadFrom(FILE_SHADER_OUTPUT
, 0, dType
, newDefs
[i
], address
, 0,
2199 indirectOffset
, vtxBase
, info
->in
[idx
].patch
);
2203 case nir_intrinsic_emit_vertex
:
2204 if (info
->io
.genUserClip
> 0)
2205 handleUserClipPlanes();
2207 case nir_intrinsic_end_primitive
: {
2208 uint32_t idx
= nir_intrinsic_stream_id(insn
);
2209 mkOp1(getOperation(op
), TYPE_U32
, NULL
, mkImm(idx
))->fixed
= 1;
2212 case nir_intrinsic_load_ubo
: {
2213 const DataType dType
= getDType(insn
);
2214 LValues
&newDefs
= convert(&insn
->dest
);
2215 Value
*indirectIndex
;
2216 Value
*indirectOffset
;
2217 uint32_t index
= getIndirect(&insn
->src
[0], 0, indirectIndex
) + 1;
2218 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2220 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2221 loadFrom(FILE_MEMORY_CONST
, index
, dType
, newDefs
[i
], offset
, i
,
2222 indirectOffset
, indirectIndex
);
2226 case nir_intrinsic_get_buffer_size
: {
2227 LValues
&newDefs
= convert(&insn
->dest
);
2228 const DataType dType
= getDType(insn
);
2229 Value
*indirectBuffer
;
2230 uint32_t buffer
= getIndirect(&insn
->src
[0], 0, indirectBuffer
);
2232 Symbol
*sym
= mkSymbol(FILE_MEMORY_BUFFER
, buffer
, dType
, 0);
2233 mkOp1(OP_BUFQ
, dType
, newDefs
[0], sym
)->setIndirect(0, 0, indirectBuffer
);
2236 case nir_intrinsic_store_ssbo
: {
2237 DataType sType
= getSType(insn
->src
[0], false, false);
2238 Value
*indirectBuffer
;
2239 Value
*indirectOffset
;
2240 uint32_t buffer
= getIndirect(&insn
->src
[1], 0, indirectBuffer
);
2241 uint32_t offset
= getIndirect(&insn
->src
[2], 0, indirectOffset
);
2243 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2244 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
2246 Symbol
*sym
= mkSymbol(FILE_MEMORY_BUFFER
, buffer
, sType
,
2247 offset
+ i
* typeSizeof(sType
));
2248 mkStore(OP_STORE
, sType
, sym
, indirectOffset
, getSrc(&insn
->src
[0], i
))
2249 ->setIndirect(0, 1, indirectBuffer
);
2251 info
->io
.globalAccess
|= 0x2;
2254 case nir_intrinsic_load_ssbo
: {
2255 const DataType dType
= getDType(insn
);
2256 LValues
&newDefs
= convert(&insn
->dest
);
2257 Value
*indirectBuffer
;
2258 Value
*indirectOffset
;
2259 uint32_t buffer
= getIndirect(&insn
->src
[0], 0, indirectBuffer
);
2260 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2262 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
)
2263 loadFrom(FILE_MEMORY_BUFFER
, buffer
, dType
, newDefs
[i
], offset
, i
,
2264 indirectOffset
, indirectBuffer
);
2266 info
->io
.globalAccess
|= 0x1;
2269 case nir_intrinsic_shared_atomic_add
:
2270 case nir_intrinsic_shared_atomic_and
:
2271 case nir_intrinsic_shared_atomic_comp_swap
:
2272 case nir_intrinsic_shared_atomic_exchange
:
2273 case nir_intrinsic_shared_atomic_or
:
2274 case nir_intrinsic_shared_atomic_imax
:
2275 case nir_intrinsic_shared_atomic_imin
:
2276 case nir_intrinsic_shared_atomic_umax
:
2277 case nir_intrinsic_shared_atomic_umin
:
2278 case nir_intrinsic_shared_atomic_xor
: {
2279 const DataType dType
= getDType(insn
);
2280 LValues
&newDefs
= convert(&insn
->dest
);
2281 Value
*indirectOffset
;
2282 uint32_t offset
= getIndirect(&insn
->src
[0], 0, indirectOffset
);
2283 Symbol
*sym
= mkSymbol(FILE_MEMORY_SHARED
, 0, dType
, offset
);
2284 Instruction
*atom
= mkOp2(OP_ATOM
, dType
, newDefs
[0], sym
, getSrc(&insn
->src
[1], 0));
2285 if (op
== nir_intrinsic_shared_atomic_comp_swap
)
2286 atom
->setSrc(2, getSrc(&insn
->src
[2], 0));
2287 atom
->setIndirect(0, 0, indirectOffset
);
2288 atom
->subOp
= getSubOp(op
);
2291 case nir_intrinsic_ssbo_atomic_add
:
2292 case nir_intrinsic_ssbo_atomic_and
:
2293 case nir_intrinsic_ssbo_atomic_comp_swap
:
2294 case nir_intrinsic_ssbo_atomic_exchange
:
2295 case nir_intrinsic_ssbo_atomic_or
:
2296 case nir_intrinsic_ssbo_atomic_imax
:
2297 case nir_intrinsic_ssbo_atomic_imin
:
2298 case nir_intrinsic_ssbo_atomic_umax
:
2299 case nir_intrinsic_ssbo_atomic_umin
:
2300 case nir_intrinsic_ssbo_atomic_xor
: {
2301 const DataType dType
= getDType(insn
);
2302 LValues
&newDefs
= convert(&insn
->dest
);
2303 Value
*indirectBuffer
;
2304 Value
*indirectOffset
;
2305 uint32_t buffer
= getIndirect(&insn
->src
[0], 0, indirectBuffer
);
2306 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2308 Symbol
*sym
= mkSymbol(FILE_MEMORY_BUFFER
, buffer
, dType
, offset
);
2309 Instruction
*atom
= mkOp2(OP_ATOM
, dType
, newDefs
[0], sym
,
2310 getSrc(&insn
->src
[2], 0));
2311 if (op
== nir_intrinsic_ssbo_atomic_comp_swap
)
2312 atom
->setSrc(2, getSrc(&insn
->src
[3], 0));
2313 atom
->setIndirect(0, 0, indirectOffset
);
2314 atom
->setIndirect(0, 1, indirectBuffer
);
2315 atom
->subOp
= getSubOp(op
);
2317 info
->io
.globalAccess
|= 0x2;
2320 case nir_intrinsic_image_deref_atomic_add
:
2321 case nir_intrinsic_image_deref_atomic_and
:
2322 case nir_intrinsic_image_deref_atomic_comp_swap
:
2323 case nir_intrinsic_image_deref_atomic_exchange
:
2324 case nir_intrinsic_image_deref_atomic_max
:
2325 case nir_intrinsic_image_deref_atomic_min
:
2326 case nir_intrinsic_image_deref_atomic_or
:
2327 case nir_intrinsic_image_deref_atomic_xor
:
2328 case nir_intrinsic_image_deref_load
:
2329 case nir_intrinsic_image_deref_samples
:
2330 case nir_intrinsic_image_deref_size
:
2331 case nir_intrinsic_image_deref_store
: {
2332 const nir_variable
*tex
;
2333 std::vector
<Value
*> srcs
, defs
;
2338 nir_deref_instr
*deref
= nir_src_as_deref(insn
->src
[0]);
2339 const glsl_type
*type
= deref
->type
;
2340 TexInstruction::Target target
=
2341 convert((glsl_sampler_dim
)type
->sampler_dimensionality
,
2342 type
->sampler_array
, type
->sampler_shadow
);
2343 unsigned int argCount
= getNIRArgCount(target
);
2344 uint16_t location
= handleDeref(deref
, indirect
, tex
);
2346 if (opInfo
.has_dest
) {
2347 LValues
&newDefs
= convert(&insn
->dest
);
2348 for (uint8_t i
= 0u; i
< newDefs
.size(); ++i
) {
2349 defs
.push_back(newDefs
[i
]);
2355 case nir_intrinsic_image_deref_atomic_add
:
2356 case nir_intrinsic_image_deref_atomic_and
:
2357 case nir_intrinsic_image_deref_atomic_comp_swap
:
2358 case nir_intrinsic_image_deref_atomic_exchange
:
2359 case nir_intrinsic_image_deref_atomic_max
:
2360 case nir_intrinsic_image_deref_atomic_min
:
2361 case nir_intrinsic_image_deref_atomic_or
:
2362 case nir_intrinsic_image_deref_atomic_xor
:
2363 ty
= getDType(insn
);
2365 info
->io
.globalAccess
|= 0x2;
2367 case nir_intrinsic_image_deref_load
:
2369 info
->io
.globalAccess
|= 0x1;
2371 case nir_intrinsic_image_deref_store
:
2374 info
->io
.globalAccess
|= 0x2;
2376 case nir_intrinsic_image_deref_samples
:
2380 case nir_intrinsic_image_deref_size
:
2384 unreachable("unhandled image opcode");
2389 if (opInfo
.num_srcs
>= 2)
2390 for (unsigned int i
= 0u; i
< argCount
; ++i
)
2391 srcs
.push_back(getSrc(&insn
->src
[1], i
));
2393 // the sampler is just another src added after coords
2394 if (opInfo
.num_srcs
>= 3 && target
.isMS())
2395 srcs
.push_back(getSrc(&insn
->src
[2], 0));
2397 if (opInfo
.num_srcs
>= 4) {
2398 unsigned components
= opInfo
.src_components
[3] ? opInfo
.src_components
[3] : insn
->num_components
;
2399 for (uint8_t i
= 0u; i
< components
; ++i
)
2400 srcs
.push_back(getSrc(&insn
->src
[3], i
));
2403 if (opInfo
.num_srcs
>= 5)
2404 // 1 for aotmic swap
2405 for (uint8_t i
= 0u; i
< opInfo
.src_components
[4]; ++i
)
2406 srcs
.push_back(getSrc(&insn
->src
[4], i
));
2408 TexInstruction
*texi
= mkTex(getOperation(op
), target
.getEnum(), location
, 0, defs
, srcs
);
2409 texi
->tex
.bindless
= false;
2410 texi
->tex
.format
= &nv50_ir::TexInstruction::formatTable
[convertGLImgFormat(tex
->data
.image
.format
)];
2411 texi
->tex
.mask
= mask
;
2412 texi
->cache
= getCacheModeFromVar(tex
);
2414 texi
->subOp
= getSubOp(op
);
2417 texi
->setIndirectR(indirect
);
2421 case nir_intrinsic_store_shared
: {
2422 DataType sType
= getSType(insn
->src
[0], false, false);
2423 Value
*indirectOffset
;
2424 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2426 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2427 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
2429 Symbol
*sym
= mkSymbol(FILE_MEMORY_SHARED
, 0, sType
, offset
+ i
* typeSizeof(sType
));
2430 mkStore(OP_STORE
, sType
, sym
, indirectOffset
, getSrc(&insn
->src
[0], i
));
2434 case nir_intrinsic_load_shared
: {
2435 const DataType dType
= getDType(insn
);
2436 LValues
&newDefs
= convert(&insn
->dest
);
2437 Value
*indirectOffset
;
2438 uint32_t offset
= getIndirect(&insn
->src
[0], 0, indirectOffset
);
2440 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
)
2441 loadFrom(FILE_MEMORY_SHARED
, 0, dType
, newDefs
[i
], offset
, i
, indirectOffset
);
2445 case nir_intrinsic_barrier
: {
2446 // TODO: add flag to shader_info
2447 info
->numBarriers
= 1;
2448 Instruction
*bar
= mkOp2(OP_BAR
, TYPE_U32
, NULL
, mkImm(0), mkImm(0));
2450 bar
->subOp
= NV50_IR_SUBOP_BAR_SYNC
;
2453 case nir_intrinsic_group_memory_barrier
:
2454 case nir_intrinsic_memory_barrier
:
2455 case nir_intrinsic_memory_barrier_atomic_counter
:
2456 case nir_intrinsic_memory_barrier_buffer
:
2457 case nir_intrinsic_memory_barrier_image
:
2458 case nir_intrinsic_memory_barrier_shared
: {
2459 Instruction
*bar
= mkOp(OP_MEMBAR
, TYPE_NONE
, NULL
);
2461 bar
->subOp
= getSubOp(op
);
2464 case nir_intrinsic_shader_clock
: {
2465 const DataType dType
= getDType(insn
);
2466 LValues
&newDefs
= convert(&insn
->dest
);
2468 loadImm(newDefs
[0], 0u);
2469 mkOp1(OP_RDSV
, dType
, newDefs
[1], mkSysVal(SV_CLOCK
, 0))->fixed
= 1;
2473 ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos
[op
].name
);
2481 Converter::visit(nir_jump_instr
*insn
)
2483 switch (insn
->type
) {
2484 case nir_jump_return
:
2485 // TODO: this only works in the main function
2486 mkFlow(OP_BRA
, exit
, CC_ALWAYS
, NULL
);
2487 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::CROSS
);
2489 case nir_jump_break
:
2490 case nir_jump_continue
: {
2491 bool isBreak
= insn
->type
== nir_jump_break
;
2492 nir_block
*block
= insn
->instr
.block
;
2493 assert(!block
->successors
[1]);
2494 BasicBlock
*target
= convert(block
->successors
[0]);
2495 mkFlow(isBreak
? OP_BREAK
: OP_CONT
, target
, CC_ALWAYS
, NULL
);
2496 bb
->cfg
.attach(&target
->cfg
, isBreak
? Graph::Edge::CROSS
: Graph::Edge::BACK
);
2500 ERROR("unknown nir_jump_type %u\n", insn
->type
);
2508 Converter::convert(nir_load_const_instr
*insn
, uint8_t idx
)
2513 setPosition(immInsertPos
, true);
2515 setPosition(bb
, false);
2517 switch (insn
->def
.bit_size
) {
2519 val
= loadImm(getSSA(8), insn
->value
.u64
[idx
]);
2522 val
= loadImm(getSSA(4), insn
->value
.u32
[idx
]);
2525 val
= loadImm(getSSA(2), insn
->value
.u16
[idx
]);
2528 val
= loadImm(getSSA(1), insn
->value
.u8
[idx
]);
2531 unreachable("unhandled bit size!\n");
2533 setPosition(bb
, true);
2538 Converter::visit(nir_load_const_instr
*insn
)
2540 assert(insn
->def
.bit_size
<= 64);
2541 immediates
[insn
->def
.index
] = insn
;
2545 #define DEFAULT_CHECKS \
2546 if (insn->dest.dest.ssa.num_components > 1) { \
2547 ERROR("nir_alu_instr only supported with 1 component!\n"); \
2550 if (insn->dest.write_mask != 1) { \
2551 ERROR("nir_alu_instr only with write_mask of 1 supported!\n"); \
2555 Converter::visit(nir_alu_instr
*insn
)
2557 const nir_op op
= insn
->op
;
2558 const nir_op_info
&info
= nir_op_infos
[op
];
2559 DataType dType
= getDType(insn
);
2560 const std::vector
<DataType
> sTypes
= getSTypes(insn
);
2562 Instruction
*oldPos
= this->bb
->getExit();
2574 case nir_op_fddx_coarse
:
2575 case nir_op_fddx_fine
:
2577 case nir_op_fddy_coarse
:
2578 case nir_op_fddy_fine
:
2597 case nir_op_imul_high
:
2598 case nir_op_umul_high
:
2605 case nir_op_pack_64_2x32_split
:
2623 LValues
&newDefs
= convert(&insn
->dest
);
2624 operation preOp
= preOperationNeeded(op
);
2625 if (preOp
!= OP_NOP
) {
2626 assert(info
.num_inputs
< 2);
2627 Value
*tmp
= getSSA(typeSizeof(dType
));
2628 Instruction
*i0
= mkOp(preOp
, dType
, tmp
);
2629 Instruction
*i1
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2630 if (info
.num_inputs
) {
2631 i0
->setSrc(0, getSrc(&insn
->src
[0]));
2634 i1
->subOp
= getSubOp(op
);
2636 Instruction
*i
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2637 for (unsigned s
= 0u; s
< info
.num_inputs
; ++s
) {
2638 i
->setSrc(s
, getSrc(&insn
->src
[s
]));
2640 i
->subOp
= getSubOp(op
);
2644 case nir_op_ifind_msb
:
2645 case nir_op_ufind_msb
: {
2647 LValues
&newDefs
= convert(&insn
->dest
);
2649 mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2652 case nir_op_fround_even
: {
2654 LValues
&newDefs
= convert(&insn
->dest
);
2655 mkCvt(OP_CVT
, dType
, newDefs
[0], dType
, getSrc(&insn
->src
[0]))->rnd
= ROUND_NI
;
2658 // convert instructions
2672 case nir_op_u2u64
: {
2674 LValues
&newDefs
= convert(&insn
->dest
);
2675 Instruction
*i
= mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2676 if (op
== nir_op_f2i32
|| op
== nir_op_f2i64
|| op
== nir_op_f2u32
|| op
== nir_op_f2u64
)
2678 i
->sType
= sTypes
[0];
2681 // compare instructions
2691 case nir_op_ine32
: {
2693 LValues
&newDefs
= convert(&insn
->dest
);
2694 Instruction
*i
= mkCmp(getOperation(op
),
2699 getSrc(&insn
->src
[0]),
2700 getSrc(&insn
->src
[1]));
2701 if (info
.num_inputs
== 3)
2702 i
->setSrc(2, getSrc(&insn
->src
[2]));
2703 i
->sType
= sTypes
[0];
2706 // those are weird ALU ops and need special handling, because
2707 // 1. they are always componend based
2708 // 2. they basically just merge multiple values into one data type
2711 if (!insn
->dest
.dest
.is_ssa
&& insn
->dest
.dest
.reg
.reg
->num_array_elems
) {
2712 nir_reg_dest
& reg
= insn
->dest
.dest
.reg
;
2713 uint32_t goffset
= regToLmemOffset
[reg
.reg
->index
];
2714 uint8_t comps
= reg
.reg
->num_components
;
2715 uint8_t size
= reg
.reg
->bit_size
/ 8;
2716 uint8_t csize
= 4 * size
; // TODO after fixing MemoryOpts: comps * size;
2717 uint32_t aoffset
= csize
* reg
.base_offset
;
2718 Value
*indirect
= NULL
;
2721 indirect
= mkOp2v(OP_MUL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
),
2722 getSrc(reg
.indirect
, 0), mkImm(csize
));
2724 for (uint8_t i
= 0u; i
< comps
; ++i
) {
2725 if (!((1u << i
) & insn
->dest
.write_mask
))
2728 Symbol
*sym
= mkSymbol(FILE_MEMORY_LOCAL
, 0, dType
, goffset
+ aoffset
+ i
* size
);
2729 mkStore(OP_STORE
, dType
, sym
, indirect
, getSrc(&insn
->src
[0], i
));
2732 } else if (!insn
->src
[0].src
.is_ssa
&& insn
->src
[0].src
.reg
.reg
->num_array_elems
) {
2733 LValues
&newDefs
= convert(&insn
->dest
);
2734 nir_reg_src
& reg
= insn
->src
[0].src
.reg
;
2735 uint32_t goffset
= regToLmemOffset
[reg
.reg
->index
];
2736 // uint8_t comps = reg.reg->num_components;
2737 uint8_t size
= reg
.reg
->bit_size
/ 8;
2738 uint8_t csize
= 4 * size
; // TODO after fixing MemoryOpts: comps * size;
2739 uint32_t aoffset
= csize
* reg
.base_offset
;
2740 Value
*indirect
= NULL
;
2743 indirect
= mkOp2v(OP_MUL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), getSrc(reg
.indirect
, 0), mkImm(csize
));
2745 for (uint8_t i
= 0u; i
< newDefs
.size(); ++i
)
2746 loadFrom(FILE_MEMORY_LOCAL
, 0, dType
, newDefs
[i
], goffset
+ aoffset
, i
, indirect
);
2750 LValues
&newDefs
= convert(&insn
->dest
);
2751 for (LValues::size_type c
= 0u; c
< newDefs
.size(); ++c
) {
2752 mkMov(newDefs
[c
], getSrc(&insn
->src
[0], c
), dType
);
2759 LValues
&newDefs
= convert(&insn
->dest
);
2760 for (LValues::size_type c
= 0u; c
< newDefs
.size(); ++c
) {
2761 mkMov(newDefs
[c
], getSrc(&insn
->src
[c
]), dType
);
2766 case nir_op_pack_64_2x32
: {
2767 LValues
&newDefs
= convert(&insn
->dest
);
2768 Instruction
*merge
= mkOp(OP_MERGE
, dType
, newDefs
[0]);
2769 merge
->setSrc(0, getSrc(&insn
->src
[0], 0));
2770 merge
->setSrc(1, getSrc(&insn
->src
[0], 1));
2773 case nir_op_pack_half_2x16_split
: {
2774 LValues
&newDefs
= convert(&insn
->dest
);
2775 Value
*tmpH
= getSSA();
2776 Value
*tmpL
= getSSA();
2778 mkCvt(OP_CVT
, TYPE_F16
, tmpL
, TYPE_F32
, getSrc(&insn
->src
[0]));
2779 mkCvt(OP_CVT
, TYPE_F16
, tmpH
, TYPE_F32
, getSrc(&insn
->src
[1]));
2780 mkOp3(OP_INSBF
, TYPE_U32
, newDefs
[0], tmpH
, mkImm(0x1010), tmpL
);
2783 case nir_op_unpack_half_2x16_split_x
:
2784 case nir_op_unpack_half_2x16_split_y
: {
2785 LValues
&newDefs
= convert(&insn
->dest
);
2786 Instruction
*cvt
= mkCvt(OP_CVT
, TYPE_F32
, newDefs
[0], TYPE_F16
, getSrc(&insn
->src
[0]));
2787 if (op
== nir_op_unpack_half_2x16_split_y
)
2791 case nir_op_unpack_64_2x32
: {
2792 LValues
&newDefs
= convert(&insn
->dest
);
2793 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, newDefs
[1]);
2796 case nir_op_unpack_64_2x32_split_x
: {
2797 LValues
&newDefs
= convert(&insn
->dest
);
2798 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, getSSA());
2801 case nir_op_unpack_64_2x32_split_y
: {
2802 LValues
&newDefs
= convert(&insn
->dest
);
2803 mkOp1(OP_SPLIT
, dType
, getSSA(), getSrc(&insn
->src
[0]))->setDef(1, newDefs
[0]);
2806 // special instructions
2808 case nir_op_isign
: {
2811 if (::isFloatType(dType
))
2816 LValues
&newDefs
= convert(&insn
->dest
);
2817 LValue
*val0
= getScratch();
2818 LValue
*val1
= getScratch();
2819 mkCmp(OP_SET
, CC_GT
, iType
, val0
, dType
, getSrc(&insn
->src
[0]), zero
);
2820 mkCmp(OP_SET
, CC_LT
, iType
, val1
, dType
, getSrc(&insn
->src
[0]), zero
);
2822 if (dType
== TYPE_F64
) {
2823 mkOp2(OP_SUB
, iType
, val0
, val0
, val1
);
2824 mkCvt(OP_CVT
, TYPE_F64
, newDefs
[0], iType
, val0
);
2825 } else if (dType
== TYPE_S64
|| dType
== TYPE_U64
) {
2826 mkOp2(OP_SUB
, iType
, val0
, val1
, val0
);
2827 mkOp2(OP_SHR
, iType
, val1
, val0
, loadImm(NULL
, 31));
2828 mkOp2(OP_MERGE
, dType
, newDefs
[0], val0
, val1
);
2829 } else if (::isFloatType(dType
))
2830 mkOp2(OP_SUB
, iType
, newDefs
[0], val0
, val1
);
2832 mkOp2(OP_SUB
, iType
, newDefs
[0], val1
, val0
);
2836 case nir_op_b32csel
: {
2838 LValues
&newDefs
= convert(&insn
->dest
);
2839 mkCmp(OP_SLCT
, CC_NE
, dType
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[1]), getSrc(&insn
->src
[2]), getSrc(&insn
->src
[0]));
2842 case nir_op_ibitfield_extract
:
2843 case nir_op_ubitfield_extract
: {
2845 Value
*tmp
= getSSA();
2846 LValues
&newDefs
= convert(&insn
->dest
);
2847 mkOp3(OP_INSBF
, dType
, tmp
, getSrc(&insn
->src
[2]), loadImm(NULL
, 0x808), getSrc(&insn
->src
[1]));
2848 mkOp2(OP_EXTBF
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), tmp
);
2853 LValues
&newDefs
= convert(&insn
->dest
);
2854 mkOp3(OP_INSBF
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 0x808), getSrc(&insn
->src
[1]));
2857 case nir_op_bitfield_insert
: {
2859 LValues
&newDefs
= convert(&insn
->dest
);
2860 LValue
*temp
= getSSA();
2861 mkOp3(OP_INSBF
, TYPE_U32
, temp
, getSrc(&insn
->src
[3]), mkImm(0x808), getSrc(&insn
->src
[2]));
2862 mkOp3(OP_INSBF
, dType
, newDefs
[0], getSrc(&insn
->src
[1]), temp
, getSrc(&insn
->src
[0]));
2865 case nir_op_bit_count
: {
2867 LValues
&newDefs
= convert(&insn
->dest
);
2868 mkOp2(OP_POPCNT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), getSrc(&insn
->src
[0]));
2871 case nir_op_bitfield_reverse
: {
2873 LValues
&newDefs
= convert(&insn
->dest
);
2874 mkOp2(OP_EXTBF
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2877 case nir_op_find_lsb
: {
2879 LValues
&newDefs
= convert(&insn
->dest
);
2880 Value
*tmp
= getSSA();
2881 mkOp2(OP_EXTBF
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]), mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2882 mkOp1(OP_BFIND
, TYPE_U32
, newDefs
[0], tmp
)->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
2885 // boolean conversions
2886 case nir_op_b2f32
: {
2888 LValues
&newDefs
= convert(&insn
->dest
);
2889 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1.0f
));
2892 case nir_op_b2f64
: {
2894 LValues
&newDefs
= convert(&insn
->dest
);
2895 Value
*tmp
= getSSA(4);
2896 mkOp2(OP_AND
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]), loadImm(NULL
, 0x3ff00000));
2897 mkOp2(OP_MERGE
, TYPE_U64
, newDefs
[0], loadImm(NULL
, 0), tmp
);
2901 case nir_op_i2b32
: {
2903 LValues
&newDefs
= convert(&insn
->dest
);
2905 if (typeSizeof(sTypes
[0]) == 8) {
2906 src1
= loadImm(getSSA(8), 0.0);
2910 CondCode cc
= op
== nir_op_f2b32
? CC_NEU
: CC_NE
;
2911 mkCmp(OP_SET
, cc
, TYPE_U32
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[0]), src1
);
2914 case nir_op_b2i32
: {
2916 LValues
&newDefs
= convert(&insn
->dest
);
2917 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2920 case nir_op_b2i64
: {
2922 LValues
&newDefs
= convert(&insn
->dest
);
2923 LValue
*def
= getScratch();
2924 mkOp2(OP_AND
, TYPE_U32
, def
, getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2925 mkOp2(OP_MERGE
, TYPE_S64
, newDefs
[0], def
, loadImm(NULL
, 0));
2929 ERROR("unknown nir_op %s\n", info
.name
);
2934 oldPos
= this->bb
->getEntry();
2935 oldPos
->precise
= insn
->exact
;
2938 if (unlikely(!oldPos
))
2941 while (oldPos
->next
) {
2942 oldPos
= oldPos
->next
;
2943 oldPos
->precise
= insn
->exact
;
2945 oldPos
->saturate
= insn
->dest
.saturate
;
2949 #undef DEFAULT_CHECKS
2952 Converter::visit(nir_ssa_undef_instr
*insn
)
2954 LValues
&newDefs
= convert(&insn
->def
);
2955 for (uint8_t i
= 0u; i
< insn
->def
.num_components
; ++i
) {
2956 mkOp(OP_NOP
, TYPE_NONE
, newDefs
[i
]);
2961 #define CASE_SAMPLER(ty) \
2962 case GLSL_SAMPLER_DIM_ ## ty : \
2963 if (isArray && !isShadow) \
2964 return TEX_TARGET_ ## ty ## _ARRAY; \
2965 else if (!isArray && isShadow) \
2966 return TEX_TARGET_## ty ## _SHADOW; \
2967 else if (isArray && isShadow) \
2968 return TEX_TARGET_## ty ## _ARRAY_SHADOW; \
2970 return TEX_TARGET_ ## ty
2973 Converter::convert(glsl_sampler_dim dim
, bool isArray
, bool isShadow
)
2979 case GLSL_SAMPLER_DIM_3D
:
2980 return TEX_TARGET_3D
;
2981 case GLSL_SAMPLER_DIM_MS
:
2983 return TEX_TARGET_2D_MS_ARRAY
;
2984 return TEX_TARGET_2D_MS
;
2985 case GLSL_SAMPLER_DIM_RECT
:
2987 return TEX_TARGET_RECT_SHADOW
;
2988 return TEX_TARGET_RECT
;
2989 case GLSL_SAMPLER_DIM_BUF
:
2990 return TEX_TARGET_BUFFER
;
2991 case GLSL_SAMPLER_DIM_EXTERNAL
:
2992 return TEX_TARGET_2D
;
2994 ERROR("unknown glsl_sampler_dim %u\n", dim
);
2996 return TEX_TARGET_COUNT
;
3002 Converter::applyProjection(Value
*src
, Value
*proj
)
3006 return mkOp2v(OP_MUL
, TYPE_F32
, getScratch(), src
, proj
);
3010 Converter::getNIRArgCount(TexInstruction::Target
& target
)
3012 unsigned int result
= target
.getArgCount();
3013 if (target
.isCube() && target
.isArray())
3021 Converter::handleDeref(nir_deref_instr
*deref
, Value
* &indirect
, const nir_variable
* &tex
)
3023 typedef std::pair
<uint32_t,Value
*> DerefPair
;
3024 std::list
<DerefPair
> derefs
;
3026 uint16_t result
= 0;
3027 while (deref
->deref_type
!= nir_deref_type_var
) {
3028 switch (deref
->deref_type
) {
3029 case nir_deref_type_array
: {
3031 uint8_t size
= type_size(deref
->type
, true);
3032 result
+= size
* getIndirect(&deref
->arr
.index
, 0, indirect
);
3035 derefs
.push_front(std::make_pair(size
, indirect
));
3040 case nir_deref_type_struct
: {
3041 result
+= nir_deref_instr_parent(deref
)->type
->struct_location_offset(deref
->strct
.index
);
3044 case nir_deref_type_var
:
3046 unreachable("nir_deref_type_var reached in handleDeref!");
3049 deref
= nir_deref_instr_parent(deref
);
3053 for (std::list
<DerefPair
>::const_iterator it
= derefs
.begin(); it
!= derefs
.end(); ++it
) {
3054 Value
*offset
= mkOp2v(OP_MUL
, TYPE_U32
, getSSA(), loadImm(getSSA(), it
->first
), it
->second
);
3056 indirect
= mkOp2v(OP_ADD
, TYPE_U32
, getSSA(), indirect
, offset
);
3061 tex
= nir_deref_instr_get_variable(deref
);
3064 return result
+ tex
->data
.driver_location
;
3068 Converter::getCacheModeFromVar(const nir_variable
*var
)
3070 if (var
->data
.image
.access
== ACCESS_VOLATILE
)
3072 if (var
->data
.image
.access
== ACCESS_COHERENT
)
3078 Converter::visit(nir_tex_instr
*insn
)
3082 case nir_texop_query_levels
:
3084 case nir_texop_texture_samples
:
3089 case nir_texop_txf_ms
:
3091 case nir_texop_txs
: {
3092 LValues
&newDefs
= convert(&insn
->dest
);
3093 std::vector
<Value
*> srcs
;
3094 std::vector
<Value
*> defs
;
3095 std::vector
<nir_src
*> offsets
;
3099 TexInstruction::Target target
= convert(insn
->sampler_dim
, insn
->is_array
, insn
->is_shadow
);
3100 operation op
= getOperation(insn
->op
);
3103 int biasIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_bias
);
3104 int compIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_comparator
);
3105 int coordsIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_coord
);
3106 int ddxIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddx
);
3107 int ddyIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddy
);
3108 int msIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ms_index
);
3109 int lodIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_lod
);
3110 int offsetIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_offset
);
3111 int projIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_projector
);
3112 int sampOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_sampler_offset
);
3113 int texOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_texture_offset
);
3116 proj
= mkOp1v(OP_RCP
, TYPE_F32
, getScratch(), getSrc(&insn
->src
[projIdx
].src
, 0));
3118 srcs
.resize(insn
->coord_components
);
3119 for (uint8_t i
= 0u; i
< insn
->coord_components
; ++i
)
3120 srcs
[i
] = applyProjection(getSrc(&insn
->src
[coordsIdx
].src
, i
), proj
);
3122 // sometimes we get less args than target.getArgCount, but codegen expects the latter
3123 if (insn
->coord_components
) {
3124 uint32_t argCount
= target
.getArgCount();
3129 for (uint32_t i
= 0u; i
< (argCount
- insn
->coord_components
); ++i
)
3130 srcs
.push_back(getSSA());
3133 if (insn
->op
== nir_texop_texture_samples
)
3134 srcs
.push_back(zero
);
3135 else if (!insn
->num_srcs
)
3136 srcs
.push_back(loadImm(NULL
, 0));
3138 srcs
.push_back(getSrc(&insn
->src
[biasIdx
].src
, 0));
3140 srcs
.push_back(getSrc(&insn
->src
[lodIdx
].src
, 0));
3141 else if (op
== OP_TXF
)
3144 srcs
.push_back(getSrc(&insn
->src
[msIdx
].src
, 0));
3145 if (offsetIdx
!= -1)
3146 offsets
.push_back(&insn
->src
[offsetIdx
].src
);
3148 srcs
.push_back(applyProjection(getSrc(&insn
->src
[compIdx
].src
, 0), proj
));
3149 if (texOffIdx
!= -1) {
3150 srcs
.push_back(getSrc(&insn
->src
[texOffIdx
].src
, 0));
3151 texOffIdx
= srcs
.size() - 1;
3153 if (sampOffIdx
!= -1) {
3154 srcs
.push_back(getSrc(&insn
->src
[sampOffIdx
].src
, 0));
3155 sampOffIdx
= srcs
.size() - 1;
3158 r
= insn
->texture_index
;
3159 s
= insn
->sampler_index
;
3161 defs
.resize(newDefs
.size());
3162 for (uint8_t d
= 0u; d
< newDefs
.size(); ++d
) {
3163 defs
[d
] = newDefs
[d
];
3166 if (target
.isMS() || (op
== OP_TEX
&& prog
->getType() != Program::TYPE_FRAGMENT
))
3169 TexInstruction
*texi
= mkTex(op
, target
.getEnum(), r
, s
, defs
, srcs
);
3170 texi
->tex
.levelZero
= lz
;
3171 texi
->tex
.mask
= mask
;
3173 if (texOffIdx
!= -1)
3174 texi
->tex
.rIndirectSrc
= texOffIdx
;
3175 if (sampOffIdx
!= -1)
3176 texi
->tex
.sIndirectSrc
= sampOffIdx
;
3180 if (!target
.isShadow())
3181 texi
->tex
.gatherComp
= insn
->component
;
3184 texi
->tex
.query
= TXQ_DIMS
;
3186 case nir_texop_texture_samples
:
3187 texi
->tex
.mask
= 0x4;
3188 texi
->tex
.query
= TXQ_TYPE
;
3190 case nir_texop_query_levels
:
3191 texi
->tex
.mask
= 0x8;
3192 texi
->tex
.query
= TXQ_DIMS
;
3198 texi
->tex
.useOffsets
= offsets
.size();
3199 if (texi
->tex
.useOffsets
) {
3200 for (uint8_t s
= 0; s
< texi
->tex
.useOffsets
; ++s
) {
3201 for (uint32_t c
= 0u; c
< 3; ++c
) {
3202 uint8_t s2
= std::min(c
, target
.getDim() - 1);
3203 texi
->offset
[s
][c
].set(getSrc(offsets
[s
], s2
));
3204 texi
->offset
[s
][c
].setInsn(texi
);
3209 if (op
== OP_TXG
&& offsetIdx
== -1) {
3210 if (nir_tex_instr_has_explicit_tg4_offsets(insn
)) {
3211 texi
->tex
.useOffsets
= 4;
3212 setPosition(texi
, false);
3213 for (uint8_t i
= 0; i
< 4; ++i
) {
3214 for (uint8_t j
= 0; j
< 2; ++j
) {
3215 texi
->offset
[i
][j
].set(loadImm(NULL
, insn
->tg4_offsets
[i
][j
]));
3216 texi
->offset
[i
][j
].setInsn(texi
);
3219 setPosition(texi
, true);
3223 if (ddxIdx
!= -1 && ddyIdx
!= -1) {
3224 for (uint8_t c
= 0u; c
< target
.getDim() + target
.isCube(); ++c
) {
3225 texi
->dPdx
[c
].set(getSrc(&insn
->src
[ddxIdx
].src
, c
));
3226 texi
->dPdy
[c
].set(getSrc(&insn
->src
[ddyIdx
].src
, c
));
3233 ERROR("unknown nir_texop %u\n", insn
->op
);
3240 Converter::visit(nir_deref_instr
*deref
)
3242 // we just ignore those, because images intrinsics are the only place where
3243 // we should end up with deref sources and those have to backtrack anyway
3244 // to get the nir_variable. This code just exists to handle some special
3246 switch (deref
->deref_type
) {
3247 case nir_deref_type_array
:
3248 case nir_deref_type_struct
:
3249 case nir_deref_type_var
:
3252 ERROR("unknown nir_deref_instr %u\n", deref
->deref_type
);
3263 if (prog
->dbgFlags
& NV50_IR_DEBUG_VERBOSE
)
3264 nir_print_shader(nir
, stderr
);
3266 struct nir_lower_subgroups_options subgroup_options
= {
3267 .subgroup_size
= 32,
3268 .ballot_bit_size
= 32,
3271 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, type_size
, (nir_lower_io_options
)0);
3272 NIR_PASS_V(nir
, nir_lower_subgroups
, &subgroup_options
);
3273 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
);
3274 NIR_PASS_V(nir
, nir_lower_load_const_to_scalar
);
3275 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3276 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
);
3277 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
3281 NIR_PASS(progress
, nir
, nir_copy_prop
);
3282 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
3283 NIR_PASS(progress
, nir
, nir_opt_trivial_continues
);
3284 NIR_PASS(progress
, nir
, nir_opt_cse
);
3285 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
3286 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
3287 NIR_PASS(progress
, nir
, nir_copy_prop
);
3288 NIR_PASS(progress
, nir
, nir_opt_dce
);
3289 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
3292 NIR_PASS_V(nir
, nir_lower_bool_to_int32
);
3293 NIR_PASS_V(nir
, nir_lower_locals_to_regs
);
3294 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
);
3295 NIR_PASS_V(nir
, nir_convert_from_ssa
, true);
3297 // Garbage collect dead instructions
3301 ERROR("Couldn't prase NIR!\n");
3305 if (!assignSlots()) {
3306 ERROR("Couldn't assign slots!\n");
3310 if (prog
->dbgFlags
& NV50_IR_DEBUG_BASIC
)
3311 nir_print_shader(nir
, stderr
);
3313 nir_foreach_function(function
, nir
) {
3314 if (!visit(function
))
3321 } // unnamed namespace
3326 Program::makeFromNIR(struct nv50_ir_prog_info
*info
)
3328 nir_shader
*nir
= (nir_shader
*)info
->bin
.source
;
3329 Converter
converter(this, nir
, info
);
3330 bool result
= converter
.run();
3333 LoweringHelper lowering
;
3335 tlsSize
= info
->bin
.tlsSpace
;
3339 } // namespace nv50_ir