2 * Copyright 2017 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Karol Herbst <kherbst@redhat.com>
25 #include "compiler/nir/nir.h"
27 #include "util/u_debug.h"
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_from_common.h"
31 #include "codegen/nv50_ir_lowering_helper.h"
32 #include "codegen/nv50_ir_util.h"
33 #include "tgsi/tgsi_from_mesa.h"
35 #if __cplusplus >= 201103L
36 #include <unordered_map>
38 #include <tr1/unordered_map>
46 #if __cplusplus >= 201103L
48 using std::unordered_map
;
51 using std::tr1::unordered_map
;
54 using namespace nv50_ir
;
57 type_size(const struct glsl_type
*type
, bool bindless
)
59 return glsl_count_attribute_slots(type
, false);
62 class Converter
: public ConverterCommon
65 Converter(Program
*, nir_shader
*, nv50_ir_prog_info
*);
69 typedef std::vector
<LValue
*> LValues
;
70 typedef unordered_map
<unsigned, LValues
> NirDefMap
;
71 typedef unordered_map
<unsigned, nir_load_const_instr
*> ImmediateMap
;
72 typedef unordered_map
<unsigned, uint32_t> NirArrayLMemOffsets
;
73 typedef unordered_map
<unsigned, BasicBlock
*> NirBlockMap
;
75 CacheMode
convert(enum gl_access_qualifier
);
76 TexTarget
convert(glsl_sampler_dim
, bool isArray
, bool isShadow
);
77 LValues
& convert(nir_alu_dest
*);
78 BasicBlock
* convert(nir_block
*);
79 LValues
& convert(nir_dest
*);
80 SVSemantic
convert(nir_intrinsic_op
);
81 Value
* convert(nir_load_const_instr
*, uint8_t);
82 LValues
& convert(nir_register
*);
83 LValues
& convert(nir_ssa_def
*);
85 Value
* getSrc(nir_alu_src
*, uint8_t component
= 0);
86 Value
* getSrc(nir_register
*, uint8_t);
87 Value
* getSrc(nir_src
*, uint8_t, bool indirect
= false);
88 Value
* getSrc(nir_ssa_def
*, uint8_t);
90 // returned value is the constant part of the given source (either the
91 // nir_src or the selected source component of an intrinsic). Even though
92 // this is mostly an optimization to be able to skip indirects in a few
93 // cases, sometimes we require immediate values or set some fileds on
94 // instructions (e.g. tex) in order for codegen to consume those.
95 // If the found value has not a constant part, the Value gets returned
96 // through the Value parameter.
97 uint32_t getIndirect(nir_src
*, uint8_t, Value
*&);
98 // isScalar indicates that the addressing is scalar, vec4 addressing is
100 uint32_t getIndirect(nir_intrinsic_instr
*, uint8_t s
, uint8_t c
, Value
*&,
101 bool isScalar
= false);
103 uint32_t getSlotAddress(nir_intrinsic_instr
*, uint8_t idx
, uint8_t slot
);
105 void setInterpolate(nv50_ir_varying
*,
110 Instruction
*loadFrom(DataFile
, uint8_t, DataType
, Value
*def
, uint32_t base
,
111 uint8_t c
, Value
*indirect0
= NULL
,
112 Value
*indirect1
= NULL
, bool patch
= false);
113 void storeTo(nir_intrinsic_instr
*, DataFile
, operation
, DataType
,
114 Value
*src
, uint8_t idx
, uint8_t c
, Value
*indirect0
= NULL
,
115 Value
*indirect1
= NULL
);
117 bool isFloatType(nir_alu_type
);
118 bool isSignedType(nir_alu_type
);
119 bool isResultFloat(nir_op
);
120 bool isResultSigned(nir_op
);
122 DataType
getDType(nir_alu_instr
*);
123 DataType
getDType(nir_intrinsic_instr
*);
124 DataType
getDType(nir_intrinsic_instr
*, bool isSigned
);
125 DataType
getDType(nir_op
, uint8_t);
127 std::vector
<DataType
> getSTypes(nir_alu_instr
*);
128 DataType
getSType(nir_src
&, bool isFloat
, bool isSigned
);
130 operation
getOperation(nir_intrinsic_op
);
131 operation
getOperation(nir_op
);
132 operation
getOperation(nir_texop
);
133 operation
preOperationNeeded(nir_op
);
135 int getSubOp(nir_intrinsic_op
);
136 int getSubOp(nir_op
);
138 CondCode
getCondCode(nir_op
);
143 bool visit(nir_alu_instr
*);
144 bool visit(nir_block
*);
145 bool visit(nir_cf_node
*);
146 bool visit(nir_function
*);
147 bool visit(nir_if
*);
148 bool visit(nir_instr
*);
149 bool visit(nir_intrinsic_instr
*);
150 bool visit(nir_jump_instr
*);
151 bool visit(nir_load_const_instr
*);
152 bool visit(nir_loop
*);
153 bool visit(nir_ssa_undef_instr
*);
154 bool visit(nir_tex_instr
*);
157 Value
* applyProjection(Value
*src
, Value
*proj
);
158 unsigned int getNIRArgCount(TexInstruction::Target
&);
164 ImmediateMap immediates
;
165 NirArrayLMemOffsets regToLmemOffset
;
167 unsigned int curLoopDepth
;
171 Instruction
*immInsertPos
;
173 int clipVertexOutput
;
182 Converter::Converter(Program
*prog
, nir_shader
*nir
, nv50_ir_prog_info
*info
)
183 : ConverterCommon(prog
, info
),
188 zero
= mkImm((uint32_t)0);
192 Converter::convert(nir_block
*block
)
194 NirBlockMap::iterator it
= blocks
.find(block
->index
);
195 if (it
!= blocks
.end())
198 BasicBlock
*bb
= new BasicBlock(func
);
199 blocks
[block
->index
] = bb
;
204 Converter::isFloatType(nir_alu_type type
)
206 return nir_alu_type_get_base_type(type
) == nir_type_float
;
210 Converter::isSignedType(nir_alu_type type
)
212 return nir_alu_type_get_base_type(type
) == nir_type_int
;
216 Converter::isResultFloat(nir_op op
)
218 const nir_op_info
&info
= nir_op_infos
[op
];
219 if (info
.output_type
!= nir_type_invalid
)
220 return isFloatType(info
.output_type
);
222 ERROR("isResultFloat not implemented for %s\n", nir_op_infos
[op
].name
);
228 Converter::isResultSigned(nir_op op
)
231 // there is no umul and we get wrong results if we treat all muls as signed
236 const nir_op_info
&info
= nir_op_infos
[op
];
237 if (info
.output_type
!= nir_type_invalid
)
238 return isSignedType(info
.output_type
);
239 ERROR("isResultSigned not implemented for %s\n", nir_op_infos
[op
].name
);
246 Converter::getDType(nir_alu_instr
*insn
)
248 if (insn
->dest
.dest
.is_ssa
)
249 return getDType(insn
->op
, insn
->dest
.dest
.ssa
.bit_size
);
251 return getDType(insn
->op
, insn
->dest
.dest
.reg
.reg
->bit_size
);
255 Converter::getDType(nir_intrinsic_instr
*insn
)
258 switch (insn
->intrinsic
) {
259 case nir_intrinsic_shared_atomic_imax
:
260 case nir_intrinsic_shared_atomic_imin
:
261 case nir_intrinsic_ssbo_atomic_imax
:
262 case nir_intrinsic_ssbo_atomic_imin
:
270 return getDType(insn
, isSigned
);
274 Converter::getDType(nir_intrinsic_instr
*insn
, bool isSigned
)
276 if (insn
->dest
.is_ssa
)
277 return typeOfSize(insn
->dest
.ssa
.bit_size
/ 8, false, isSigned
);
279 return typeOfSize(insn
->dest
.reg
.reg
->bit_size
/ 8, false, isSigned
);
283 Converter::getDType(nir_op op
, uint8_t bitSize
)
285 DataType ty
= typeOfSize(bitSize
/ 8, isResultFloat(op
), isResultSigned(op
));
286 if (ty
== TYPE_NONE
) {
287 ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos
[op
].name
, bitSize
);
293 std::vector
<DataType
>
294 Converter::getSTypes(nir_alu_instr
*insn
)
296 const nir_op_info
&info
= nir_op_infos
[insn
->op
];
297 std::vector
<DataType
> res(info
.num_inputs
);
299 for (uint8_t i
= 0; i
< info
.num_inputs
; ++i
) {
300 if (info
.input_types
[i
] != nir_type_invalid
) {
301 res
[i
] = getSType(insn
->src
[i
].src
, isFloatType(info
.input_types
[i
]), isSignedType(info
.input_types
[i
]));
303 ERROR("getSType not implemented for %s idx %u\n", info
.name
, i
);
314 Converter::getSType(nir_src
&src
, bool isFloat
, bool isSigned
)
318 bitSize
= src
.ssa
->bit_size
;
320 bitSize
= src
.reg
.reg
->bit_size
;
322 DataType ty
= typeOfSize(bitSize
/ 8, isFloat
, isSigned
);
323 if (ty
== TYPE_NONE
) {
331 ERROR("couldn't get Type for %s with bitSize %u\n", str
, bitSize
);
338 Converter::getOperation(nir_op op
)
341 // basic ops with float and int variants
350 case nir_op_ifind_msb
:
351 case nir_op_ufind_msb
:
373 case nir_op_fddx_coarse
:
374 case nir_op_fddx_fine
:
377 case nir_op_fddy_coarse
:
378 case nir_op_fddy_fine
:
396 case nir_op_pack_64_2x32_split
:
410 case nir_op_imul_high
:
411 case nir_op_umul_high
:
453 ERROR("couldn't get operation for op %s\n", nir_op_infos
[op
].name
);
460 Converter::getOperation(nir_texop op
)
472 case nir_texop_txf_ms
:
478 case nir_texop_query_levels
:
479 case nir_texop_texture_samples
:
483 ERROR("couldn't get operation for nir_texop %u\n", op
);
490 Converter::getOperation(nir_intrinsic_op op
)
493 case nir_intrinsic_emit_vertex
:
495 case nir_intrinsic_end_primitive
:
497 case nir_intrinsic_bindless_image_atomic_add
:
498 case nir_intrinsic_image_atomic_add
:
499 case nir_intrinsic_bindless_image_atomic_and
:
500 case nir_intrinsic_image_atomic_and
:
501 case nir_intrinsic_bindless_image_atomic_comp_swap
:
502 case nir_intrinsic_image_atomic_comp_swap
:
503 case nir_intrinsic_bindless_image_atomic_exchange
:
504 case nir_intrinsic_image_atomic_exchange
:
505 case nir_intrinsic_bindless_image_atomic_imax
:
506 case nir_intrinsic_image_atomic_imax
:
507 case nir_intrinsic_bindless_image_atomic_umax
:
508 case nir_intrinsic_image_atomic_umax
:
509 case nir_intrinsic_bindless_image_atomic_imin
:
510 case nir_intrinsic_image_atomic_imin
:
511 case nir_intrinsic_bindless_image_atomic_umin
:
512 case nir_intrinsic_image_atomic_umin
:
513 case nir_intrinsic_bindless_image_atomic_or
:
514 case nir_intrinsic_image_atomic_or
:
515 case nir_intrinsic_bindless_image_atomic_xor
:
516 case nir_intrinsic_image_atomic_xor
:
518 case nir_intrinsic_bindless_image_load
:
519 case nir_intrinsic_image_load
:
521 case nir_intrinsic_bindless_image_samples
:
522 case nir_intrinsic_image_samples
:
523 case nir_intrinsic_bindless_image_size
:
524 case nir_intrinsic_image_size
:
526 case nir_intrinsic_bindless_image_store
:
527 case nir_intrinsic_image_store
:
530 ERROR("couldn't get operation for nir_intrinsic_op %u\n", op
);
537 Converter::preOperationNeeded(nir_op op
)
549 Converter::getSubOp(nir_op op
)
552 case nir_op_imul_high
:
553 case nir_op_umul_high
:
554 return NV50_IR_SUBOP_MUL_HIGH
;
558 return NV50_IR_SUBOP_SHIFT_WRAP
;
565 Converter::getSubOp(nir_intrinsic_op op
)
568 case nir_intrinsic_bindless_image_atomic_add
:
569 case nir_intrinsic_global_atomic_add
:
570 case nir_intrinsic_image_atomic_add
:
571 case nir_intrinsic_shared_atomic_add
:
572 case nir_intrinsic_ssbo_atomic_add
:
573 return NV50_IR_SUBOP_ATOM_ADD
;
574 case nir_intrinsic_bindless_image_atomic_and
:
575 case nir_intrinsic_global_atomic_and
:
576 case nir_intrinsic_image_atomic_and
:
577 case nir_intrinsic_shared_atomic_and
:
578 case nir_intrinsic_ssbo_atomic_and
:
579 return NV50_IR_SUBOP_ATOM_AND
;
580 case nir_intrinsic_bindless_image_atomic_comp_swap
:
581 case nir_intrinsic_global_atomic_comp_swap
:
582 case nir_intrinsic_image_atomic_comp_swap
:
583 case nir_intrinsic_shared_atomic_comp_swap
:
584 case nir_intrinsic_ssbo_atomic_comp_swap
:
585 return NV50_IR_SUBOP_ATOM_CAS
;
586 case nir_intrinsic_bindless_image_atomic_exchange
:
587 case nir_intrinsic_global_atomic_exchange
:
588 case nir_intrinsic_image_atomic_exchange
:
589 case nir_intrinsic_shared_atomic_exchange
:
590 case nir_intrinsic_ssbo_atomic_exchange
:
591 return NV50_IR_SUBOP_ATOM_EXCH
;
592 case nir_intrinsic_bindless_image_atomic_or
:
593 case nir_intrinsic_global_atomic_or
:
594 case nir_intrinsic_image_atomic_or
:
595 case nir_intrinsic_shared_atomic_or
:
596 case nir_intrinsic_ssbo_atomic_or
:
597 return NV50_IR_SUBOP_ATOM_OR
;
598 case nir_intrinsic_bindless_image_atomic_imax
:
599 case nir_intrinsic_bindless_image_atomic_umax
:
600 case nir_intrinsic_global_atomic_imax
:
601 case nir_intrinsic_global_atomic_umax
:
602 case nir_intrinsic_image_atomic_imax
:
603 case nir_intrinsic_image_atomic_umax
:
604 case nir_intrinsic_shared_atomic_imax
:
605 case nir_intrinsic_shared_atomic_umax
:
606 case nir_intrinsic_ssbo_atomic_imax
:
607 case nir_intrinsic_ssbo_atomic_umax
:
608 return NV50_IR_SUBOP_ATOM_MAX
;
609 case nir_intrinsic_bindless_image_atomic_imin
:
610 case nir_intrinsic_bindless_image_atomic_umin
:
611 case nir_intrinsic_global_atomic_imin
:
612 case nir_intrinsic_global_atomic_umin
:
613 case nir_intrinsic_image_atomic_imin
:
614 case nir_intrinsic_image_atomic_umin
:
615 case nir_intrinsic_shared_atomic_imin
:
616 case nir_intrinsic_shared_atomic_umin
:
617 case nir_intrinsic_ssbo_atomic_imin
:
618 case nir_intrinsic_ssbo_atomic_umin
:
619 return NV50_IR_SUBOP_ATOM_MIN
;
620 case nir_intrinsic_bindless_image_atomic_xor
:
621 case nir_intrinsic_global_atomic_xor
:
622 case nir_intrinsic_image_atomic_xor
:
623 case nir_intrinsic_shared_atomic_xor
:
624 case nir_intrinsic_ssbo_atomic_xor
:
625 return NV50_IR_SUBOP_ATOM_XOR
;
627 case nir_intrinsic_group_memory_barrier
:
628 case nir_intrinsic_memory_barrier
:
629 case nir_intrinsic_memory_barrier_buffer
:
630 case nir_intrinsic_memory_barrier_image
:
631 return NV50_IR_SUBOP_MEMBAR(M
, GL
);
632 case nir_intrinsic_memory_barrier_shared
:
633 return NV50_IR_SUBOP_MEMBAR(M
, CTA
);
635 case nir_intrinsic_vote_all
:
636 return NV50_IR_SUBOP_VOTE_ALL
;
637 case nir_intrinsic_vote_any
:
638 return NV50_IR_SUBOP_VOTE_ANY
;
639 case nir_intrinsic_vote_ieq
:
640 return NV50_IR_SUBOP_VOTE_UNI
;
647 Converter::getCondCode(nir_op op
)
666 ERROR("couldn't get CondCode for op %s\n", nir_op_infos
[op
].name
);
673 Converter::convert(nir_alu_dest
*dest
)
675 return convert(&dest
->dest
);
679 Converter::convert(nir_dest
*dest
)
682 return convert(&dest
->ssa
);
683 if (dest
->reg
.indirect
) {
684 ERROR("no support for indirects.");
687 return convert(dest
->reg
.reg
);
691 Converter::convert(nir_register
*reg
)
693 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
694 if (it
!= regDefs
.end())
697 LValues
newDef(reg
->num_components
);
698 for (uint8_t i
= 0; i
< reg
->num_components
; i
++)
699 newDef
[i
] = getScratch(std::max(4, reg
->bit_size
/ 8));
700 return regDefs
[reg
->index
] = newDef
;
704 Converter::convert(nir_ssa_def
*def
)
706 NirDefMap::iterator it
= ssaDefs
.find(def
->index
);
707 if (it
!= ssaDefs
.end())
710 LValues
newDef(def
->num_components
);
711 for (uint8_t i
= 0; i
< def
->num_components
; i
++)
712 newDef
[i
] = getSSA(std::max(4, def
->bit_size
/ 8));
713 return ssaDefs
[def
->index
] = newDef
;
717 Converter::getSrc(nir_alu_src
*src
, uint8_t component
)
719 if (src
->abs
|| src
->negate
) {
720 ERROR("modifiers currently not supported on nir_alu_src\n");
723 return getSrc(&src
->src
, src
->swizzle
[component
]);
727 Converter::getSrc(nir_register
*reg
, uint8_t idx
)
729 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
730 if (it
== regDefs
.end())
731 return convert(reg
)[idx
];
732 return it
->second
[idx
];
736 Converter::getSrc(nir_src
*src
, uint8_t idx
, bool indirect
)
739 return getSrc(src
->ssa
, idx
);
741 if (src
->reg
.indirect
) {
743 return getSrc(src
->reg
.indirect
, idx
);
744 ERROR("no support for indirects.");
749 return getSrc(src
->reg
.reg
, idx
);
753 Converter::getSrc(nir_ssa_def
*src
, uint8_t idx
)
755 ImmediateMap::iterator iit
= immediates
.find(src
->index
);
756 if (iit
!= immediates
.end())
757 return convert((*iit
).second
, idx
);
759 NirDefMap::iterator it
= ssaDefs
.find(src
->index
);
760 if (it
== ssaDefs
.end()) {
761 ERROR("SSA value %u not found\n", src
->index
);
765 return it
->second
[idx
];
769 Converter::getIndirect(nir_src
*src
, uint8_t idx
, Value
*&indirect
)
771 nir_const_value
*offset
= nir_src_as_const_value(*src
);
775 return offset
[0].u32
;
778 indirect
= getSrc(src
, idx
, true);
783 Converter::getIndirect(nir_intrinsic_instr
*insn
, uint8_t s
, uint8_t c
, Value
*&indirect
, bool isScalar
)
785 int32_t idx
= nir_intrinsic_base(insn
) + getIndirect(&insn
->src
[s
], c
, indirect
);
786 if (indirect
&& !isScalar
)
787 indirect
= mkOp2v(OP_SHL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), indirect
, loadImm(NULL
, 4));
792 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot
, unsigned *name
, unsigned *index
)
794 assert(name
&& index
);
796 if (slot
>= VERT_ATTRIB_MAX
) {
797 ERROR("invalid varying slot %u\n", slot
);
802 if (slot
>= VERT_ATTRIB_GENERIC0
&&
803 slot
< VERT_ATTRIB_GENERIC0
+ VERT_ATTRIB_GENERIC_MAX
) {
804 *name
= TGSI_SEMANTIC_GENERIC
;
805 *index
= slot
- VERT_ATTRIB_GENERIC0
;
809 if (slot
>= VERT_ATTRIB_TEX0
&&
810 slot
< VERT_ATTRIB_TEX0
+ VERT_ATTRIB_TEX_MAX
) {
811 *name
= TGSI_SEMANTIC_TEXCOORD
;
812 *index
= slot
- VERT_ATTRIB_TEX0
;
817 case VERT_ATTRIB_COLOR0
:
818 *name
= TGSI_SEMANTIC_COLOR
;
821 case VERT_ATTRIB_COLOR1
:
822 *name
= TGSI_SEMANTIC_COLOR
;
825 case VERT_ATTRIB_EDGEFLAG
:
826 *name
= TGSI_SEMANTIC_EDGEFLAG
;
829 case VERT_ATTRIB_FOG
:
830 *name
= TGSI_SEMANTIC_FOG
;
833 case VERT_ATTRIB_NORMAL
:
834 *name
= TGSI_SEMANTIC_NORMAL
;
837 case VERT_ATTRIB_POS
:
838 *name
= TGSI_SEMANTIC_POSITION
;
841 case VERT_ATTRIB_POINT_SIZE
:
842 *name
= TGSI_SEMANTIC_PSIZE
;
846 ERROR("unknown vert attrib slot %u\n", slot
);
853 Converter::setInterpolate(nv50_ir_varying
*var
,
859 case INTERP_MODE_FLAT
:
862 case INTERP_MODE_NONE
:
863 if (semantic
== TGSI_SEMANTIC_COLOR
)
865 else if (semantic
== TGSI_SEMANTIC_POSITION
)
868 case INTERP_MODE_NOPERSPECTIVE
:
871 case INTERP_MODE_SMOOTH
:
874 var
->centroid
= centroid
;
878 calcSlots(const glsl_type
*type
, Program::Type stage
, const shader_info
&info
,
879 bool input
, const nir_variable
*var
)
881 if (!type
->is_array())
882 return type
->count_attribute_slots(false);
886 case Program::TYPE_GEOMETRY
:
887 slots
= type
->uniform_locations();
889 slots
/= info
.gs
.vertices_in
;
891 case Program::TYPE_TESSELLATION_CONTROL
:
892 case Program::TYPE_TESSELLATION_EVAL
:
893 // remove first dimension
894 if (var
->data
.patch
|| (!input
&& stage
== Program::TYPE_TESSELLATION_EVAL
))
895 slots
= type
->uniform_locations();
897 slots
= type
->fields
.array
->uniform_locations();
900 slots
= type
->count_attribute_slots(false);
907 bool Converter::assignSlots() {
911 info
->io
.viewportId
= -1;
913 info
->numOutputs
= 0;
915 // we have to fixup the uniform locations for arrays
916 unsigned numImages
= 0;
917 nir_foreach_variable(var
, &nir
->uniforms
) {
918 const glsl_type
*type
= var
->type
;
919 if (!type
->without_array()->is_image())
921 var
->data
.driver_location
= numImages
;
922 numImages
+= type
->is_array() ? type
->arrays_of_arrays_size() : 1;
925 info
->numSysVals
= 0;
926 for (uint8_t i
= 0; i
< SYSTEM_VALUE_MAX
; ++i
) {
927 if (!(nir
->info
.system_values_read
& 1ull << i
))
930 info
->sv
[info
->numSysVals
].sn
= tgsi_get_sysval_semantic(i
);
931 info
->sv
[info
->numSysVals
].si
= 0;
932 info
->sv
[info
->numSysVals
].input
= 0; // TODO inferSysValDirection(sn);
935 case SYSTEM_VALUE_INSTANCE_ID
:
936 info
->io
.instanceId
= info
->numSysVals
;
938 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
939 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
940 info
->sv
[info
->numSysVals
].patch
= 1;
942 case SYSTEM_VALUE_VERTEX_ID
:
943 info
->io
.vertexId
= info
->numSysVals
;
949 info
->numSysVals
+= 1;
952 if (prog
->getType() == Program::TYPE_COMPUTE
)
955 nir_foreach_variable(var
, &nir
->inputs
) {
956 const glsl_type
*type
= var
->type
;
957 int slot
= var
->data
.location
;
958 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, true, var
);
959 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
960 : type
->component_slots();
961 uint32_t frac
= var
->data
.location_frac
;
962 uint32_t vary
= var
->data
.driver_location
;
964 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
969 assert(vary
+ slots
<= PIPE_MAX_SHADER_INPUTS
);
971 switch(prog
->getType()) {
972 case Program::TYPE_FRAGMENT
:
973 tgsi_get_gl_varying_semantic((gl_varying_slot
)slot
, true,
975 for (uint16_t i
= 0; i
< slots
; ++i
) {
976 setInterpolate(&info
->in
[vary
+ i
], var
->data
.interpolation
,
977 var
->data
.centroid
| var
->data
.sample
, name
);
980 case Program::TYPE_GEOMETRY
:
981 tgsi_get_gl_varying_semantic((gl_varying_slot
)slot
, true,
984 case Program::TYPE_TESSELLATION_CONTROL
:
985 case Program::TYPE_TESSELLATION_EVAL
:
986 tgsi_get_gl_varying_semantic((gl_varying_slot
)slot
, true,
988 if (var
->data
.patch
&& name
== TGSI_SEMANTIC_PATCH
)
989 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
991 case Program::TYPE_VERTEX
:
992 vert_attrib_to_tgsi_semantic((gl_vert_attrib
)slot
, &name
, &index
);
994 case TGSI_SEMANTIC_EDGEFLAG
:
995 info
->io
.edgeFlagIn
= vary
;
1002 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1006 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1007 info
->in
[vary
].id
= vary
;
1008 info
->in
[vary
].patch
= var
->data
.patch
;
1009 info
->in
[vary
].sn
= name
;
1010 info
->in
[vary
].si
= index
+ i
;
1011 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1013 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1015 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1017 info
->in
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1019 info
->numInputs
= std::max
<uint8_t>(info
->numInputs
, vary
);
1022 nir_foreach_variable(var
, &nir
->outputs
) {
1023 const glsl_type
*type
= var
->type
;
1024 int slot
= var
->data
.location
;
1025 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, false, var
);
1026 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
1027 : type
->component_slots();
1028 uint32_t frac
= var
->data
.location_frac
;
1029 uint32_t vary
= var
->data
.driver_location
;
1031 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
1036 assert(vary
< PIPE_MAX_SHADER_OUTPUTS
);
1038 switch(prog
->getType()) {
1039 case Program::TYPE_FRAGMENT
:
1040 tgsi_get_gl_frag_result_semantic((gl_frag_result
)slot
, &name
, &index
);
1042 case TGSI_SEMANTIC_COLOR
:
1043 if (!var
->data
.fb_fetch_output
)
1044 info
->prop
.fp
.numColourResults
++;
1046 if (var
->data
.location
== FRAG_RESULT_COLOR
&&
1047 nir
->info
.outputs_written
& BITFIELD64_BIT(var
->data
.location
))
1048 info
->prop
.fp
.separateFragData
= true;
1050 // sometimes we get FRAG_RESULT_DATAX with data.index 0
1051 // sometimes we get FRAG_RESULT_DATA0 with data.index X
1052 index
= index
== 0 ? var
->data
.index
: index
;
1054 case TGSI_SEMANTIC_POSITION
:
1055 info
->io
.fragDepth
= vary
;
1056 info
->prop
.fp
.writesDepth
= true;
1058 case TGSI_SEMANTIC_SAMPLEMASK
:
1059 info
->io
.sampleMask
= vary
;
1065 case Program::TYPE_GEOMETRY
:
1066 case Program::TYPE_TESSELLATION_CONTROL
:
1067 case Program::TYPE_TESSELLATION_EVAL
:
1068 case Program::TYPE_VERTEX
:
1069 tgsi_get_gl_varying_semantic((gl_varying_slot
)slot
, true,
1072 if (var
->data
.patch
&& name
!= TGSI_SEMANTIC_TESSINNER
&&
1073 name
!= TGSI_SEMANTIC_TESSOUTER
)
1074 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
1077 case TGSI_SEMANTIC_CLIPDIST
:
1078 info
->io
.genUserClip
= -1;
1080 case TGSI_SEMANTIC_CLIPVERTEX
:
1081 clipVertexOutput
= vary
;
1083 case TGSI_SEMANTIC_EDGEFLAG
:
1084 info
->io
.edgeFlagOut
= vary
;
1086 case TGSI_SEMANTIC_POSITION
:
1087 if (clipVertexOutput
< 0)
1088 clipVertexOutput
= vary
;
1095 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1099 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1100 info
->out
[vary
].id
= vary
;
1101 info
->out
[vary
].patch
= var
->data
.patch
;
1102 info
->out
[vary
].sn
= name
;
1103 info
->out
[vary
].si
= index
+ i
;
1104 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1106 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1108 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1110 info
->out
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1112 if (nir
->info
.outputs_read
& 1ull << slot
)
1113 info
->out
[vary
].oread
= 1;
1115 info
->numOutputs
= std::max
<uint8_t>(info
->numOutputs
, vary
);
1118 if (info
->io
.genUserClip
> 0) {
1119 info
->io
.clipDistances
= info
->io
.genUserClip
;
1121 const unsigned int nOut
= (info
->io
.genUserClip
+ 3) / 4;
1123 for (unsigned int n
= 0; n
< nOut
; ++n
) {
1124 unsigned int i
= info
->numOutputs
++;
1125 info
->out
[i
].id
= i
;
1126 info
->out
[i
].sn
= TGSI_SEMANTIC_CLIPDIST
;
1127 info
->out
[i
].si
= n
;
1128 info
->out
[i
].mask
= ((1 << info
->io
.clipDistances
) - 1) >> (n
* 4);
1132 return info
->assignSlots(info
) == 0;
1136 Converter::getSlotAddress(nir_intrinsic_instr
*insn
, uint8_t idx
, uint8_t slot
)
1139 int offset
= nir_intrinsic_component(insn
);
1142 if (nir_intrinsic_infos
[insn
->intrinsic
].has_dest
)
1143 ty
= getDType(insn
);
1145 ty
= getSType(insn
->src
[0], false, false);
1147 switch (insn
->intrinsic
) {
1148 case nir_intrinsic_load_input
:
1149 case nir_intrinsic_load_interpolated_input
:
1150 case nir_intrinsic_load_per_vertex_input
:
1153 case nir_intrinsic_load_output
:
1154 case nir_intrinsic_load_per_vertex_output
:
1155 case nir_intrinsic_store_output
:
1156 case nir_intrinsic_store_per_vertex_output
:
1160 ERROR("unknown intrinsic in getSlotAddress %s",
1161 nir_intrinsic_infos
[insn
->intrinsic
].name
);
1167 if (typeSizeof(ty
) == 8) {
1179 assert(!input
|| idx
< PIPE_MAX_SHADER_INPUTS
);
1180 assert(input
|| idx
< PIPE_MAX_SHADER_OUTPUTS
);
1182 const nv50_ir_varying
*vary
= input
? info
->in
: info
->out
;
1183 return vary
[idx
].slot
[slot
] * 4;
1187 Converter::loadFrom(DataFile file
, uint8_t i
, DataType ty
, Value
*def
,
1188 uint32_t base
, uint8_t c
, Value
*indirect0
,
1189 Value
*indirect1
, bool patch
)
1191 unsigned int tySize
= typeSizeof(ty
);
1194 (file
== FILE_MEMORY_CONST
|| file
== FILE_MEMORY_BUFFER
|| indirect0
)) {
1195 Value
*lo
= getSSA();
1196 Value
*hi
= getSSA();
1199 mkLoad(TYPE_U32
, lo
,
1200 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
),
1202 loi
->setIndirect(0, 1, indirect1
);
1203 loi
->perPatch
= patch
;
1206 mkLoad(TYPE_U32
, hi
,
1207 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
+ 4),
1209 hii
->setIndirect(0, 1, indirect1
);
1210 hii
->perPatch
= patch
;
1212 return mkOp2(OP_MERGE
, ty
, def
, lo
, hi
);
1215 mkLoad(ty
, def
, mkSymbol(file
, i
, ty
, base
+ c
* tySize
), indirect0
);
1216 ld
->setIndirect(0, 1, indirect1
);
1217 ld
->perPatch
= patch
;
1223 Converter::storeTo(nir_intrinsic_instr
*insn
, DataFile file
, operation op
,
1224 DataType ty
, Value
*src
, uint8_t idx
, uint8_t c
,
1225 Value
*indirect0
, Value
*indirect1
)
1227 uint8_t size
= typeSizeof(ty
);
1228 uint32_t address
= getSlotAddress(insn
, idx
, c
);
1230 if (size
== 8 && indirect0
) {
1232 mkSplit(split
, 4, src
);
1234 if (op
== OP_EXPORT
) {
1235 split
[0] = mkMov(getSSA(), split
[0], ty
)->getDef(0);
1236 split
[1] = mkMov(getSSA(), split
[1], ty
)->getDef(0);
1239 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
), indirect0
,
1240 split
[0])->perPatch
= info
->out
[idx
].patch
;
1241 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
+ 4), indirect0
,
1242 split
[1])->perPatch
= info
->out
[idx
].patch
;
1244 if (op
== OP_EXPORT
)
1245 src
= mkMov(getSSA(size
), src
, ty
)->getDef(0);
1246 mkStore(op
, ty
, mkSymbol(file
, 0, ty
, address
), indirect0
,
1247 src
)->perPatch
= info
->out
[idx
].patch
;
1252 Converter::parseNIR()
1254 info
->bin
.tlsSpace
= 0;
1255 info
->io
.clipDistances
= nir
->info
.clip_distance_array_size
;
1256 info
->io
.cullDistances
= nir
->info
.cull_distance_array_size
;
1258 switch(prog
->getType()) {
1259 case Program::TYPE_COMPUTE
:
1260 info
->prop
.cp
.numThreads
[0] = nir
->info
.cs
.local_size
[0];
1261 info
->prop
.cp
.numThreads
[1] = nir
->info
.cs
.local_size
[1];
1262 info
->prop
.cp
.numThreads
[2] = nir
->info
.cs
.local_size
[2];
1263 info
->bin
.smemSize
= nir
->info
.cs
.shared_size
;
1265 case Program::TYPE_FRAGMENT
:
1266 info
->prop
.fp
.earlyFragTests
= nir
->info
.fs
.early_fragment_tests
;
1267 info
->prop
.fp
.persampleInvocation
=
1268 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_ID
) ||
1269 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1270 info
->prop
.fp
.postDepthCoverage
= nir
->info
.fs
.post_depth_coverage
;
1271 info
->prop
.fp
.readsSampleLocations
=
1272 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1273 info
->prop
.fp
.usesDiscard
= nir
->info
.fs
.uses_discard
;
1274 info
->prop
.fp
.usesSampleMaskIn
=
1275 !!(nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
);
1277 case Program::TYPE_GEOMETRY
:
1278 info
->prop
.gp
.inputPrim
= nir
->info
.gs
.input_primitive
;
1279 info
->prop
.gp
.instanceCount
= nir
->info
.gs
.invocations
;
1280 info
->prop
.gp
.maxVertices
= nir
->info
.gs
.vertices_out
;
1281 info
->prop
.gp
.outputPrim
= nir
->info
.gs
.output_primitive
;
1283 case Program::TYPE_TESSELLATION_CONTROL
:
1284 case Program::TYPE_TESSELLATION_EVAL
:
1285 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1286 info
->prop
.tp
.domain
= GL_LINES
;
1288 info
->prop
.tp
.domain
= nir
->info
.tess
.primitive_mode
;
1289 info
->prop
.tp
.outputPatchSize
= nir
->info
.tess
.tcs_vertices_out
;
1290 info
->prop
.tp
.outputPrim
=
1291 nir
->info
.tess
.point_mode
? PIPE_PRIM_POINTS
: PIPE_PRIM_TRIANGLES
;
1292 info
->prop
.tp
.partitioning
= (nir
->info
.tess
.spacing
+ 1) % 3;
1293 info
->prop
.tp
.winding
= !nir
->info
.tess
.ccw
;
1295 case Program::TYPE_VERTEX
:
1296 info
->prop
.vp
.usesDrawParameters
=
1297 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
)) ||
1298 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
)) ||
1299 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
));
1309 Converter::visit(nir_function
*function
)
1311 assert(function
->impl
);
1313 // usually the blocks will set everything up, but main is special
1314 BasicBlock
*entry
= new BasicBlock(prog
->main
);
1315 exit
= new BasicBlock(prog
->main
);
1316 blocks
[nir_start_block(function
->impl
)->index
] = entry
;
1317 prog
->main
->setEntry(entry
);
1318 prog
->main
->setExit(exit
);
1320 setPosition(entry
, true);
1322 if (info
->io
.genUserClip
> 0) {
1323 for (int c
= 0; c
< 4; ++c
)
1324 clipVtx
[c
] = getScratch();
1327 switch (prog
->getType()) {
1328 case Program::TYPE_TESSELLATION_CONTROL
:
1330 OP_SUB
, TYPE_U32
, getSSA(),
1331 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LANEID
, 0)),
1332 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_INVOCATION_ID
, 0)));
1334 case Program::TYPE_FRAGMENT
: {
1335 Symbol
*sv
= mkSysVal(SV_POSITION
, 3);
1336 fragCoord
[3] = mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), sv
);
1337 fp
.position
= mkOp1v(OP_RCP
, TYPE_F32
, fragCoord
[3], fragCoord
[3]);
1344 nir_foreach_register(reg
, &function
->impl
->registers
) {
1345 if (reg
->num_array_elems
) {
1346 // TODO: packed variables would be nice, but MemoryOpt fails
1347 // replace 4 with reg->num_components
1348 uint32_t size
= 4 * reg
->num_array_elems
* (reg
->bit_size
/ 8);
1349 regToLmemOffset
[reg
->index
] = info
->bin
.tlsSpace
;
1350 info
->bin
.tlsSpace
+= size
;
1354 nir_index_ssa_defs(function
->impl
);
1355 foreach_list_typed(nir_cf_node
, node
, node
, &function
->impl
->body
) {
1360 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::TREE
);
1361 setPosition(exit
, true);
1363 if ((prog
->getType() == Program::TYPE_VERTEX
||
1364 prog
->getType() == Program::TYPE_TESSELLATION_EVAL
)
1365 && info
->io
.genUserClip
> 0)
1366 handleUserClipPlanes();
1368 // TODO: for non main function this needs to be a OP_RETURN
1369 mkOp(OP_EXIT
, TYPE_NONE
, NULL
)->terminator
= 1;
1374 Converter::visit(nir_cf_node
*node
)
1376 switch (node
->type
) {
1377 case nir_cf_node_block
:
1378 return visit(nir_cf_node_as_block(node
));
1379 case nir_cf_node_if
:
1380 return visit(nir_cf_node_as_if(node
));
1381 case nir_cf_node_loop
:
1382 return visit(nir_cf_node_as_loop(node
));
1384 ERROR("unknown nir_cf_node type %u\n", node
->type
);
1390 Converter::visit(nir_block
*block
)
1392 if (!block
->predecessors
->entries
&& block
->instr_list
.is_empty())
1395 BasicBlock
*bb
= convert(block
);
1397 setPosition(bb
, true);
1398 nir_foreach_instr(insn
, block
) {
1406 Converter::visit(nir_if
*nif
)
1408 DataType sType
= getSType(nif
->condition
, false, false);
1409 Value
*src
= getSrc(&nif
->condition
, 0);
1411 nir_block
*lastThen
= nir_if_last_then_block(nif
);
1412 nir_block
*lastElse
= nir_if_last_else_block(nif
);
1414 assert(!lastThen
->successors
[1]);
1415 assert(!lastElse
->successors
[1]);
1417 BasicBlock
*ifBB
= convert(nir_if_first_then_block(nif
));
1418 BasicBlock
*elseBB
= convert(nir_if_first_else_block(nif
));
1420 bb
->cfg
.attach(&ifBB
->cfg
, Graph::Edge::TREE
);
1421 bb
->cfg
.attach(&elseBB
->cfg
, Graph::Edge::TREE
);
1423 // we only insert joinats, if both nodes end up at the end of the if again.
1424 // the reason for this to not happens are breaks/continues/ret/... which
1425 // have their own handling
1426 if (lastThen
->successors
[0] == lastElse
->successors
[0])
1427 bb
->joinAt
= mkFlow(OP_JOINAT
, convert(lastThen
->successors
[0]),
1430 mkFlow(OP_BRA
, elseBB
, CC_EQ
, src
)->setType(sType
);
1432 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->then_list
) {
1436 setPosition(convert(lastThen
), true);
1437 if (!bb
->getExit() ||
1438 !bb
->getExit()->asFlow() ||
1439 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1440 BasicBlock
*tailBB
= convert(lastThen
->successors
[0]);
1441 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1442 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1445 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->else_list
) {
1449 setPosition(convert(lastElse
), true);
1450 if (!bb
->getExit() ||
1451 !bb
->getExit()->asFlow() ||
1452 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1453 BasicBlock
*tailBB
= convert(lastElse
->successors
[0]);
1454 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1455 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1458 if (lastThen
->successors
[0] == lastElse
->successors
[0]) {
1459 setPosition(convert(lastThen
->successors
[0]), true);
1460 mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1467 Converter::visit(nir_loop
*loop
)
1470 func
->loopNestingBound
= std::max(func
->loopNestingBound
, curLoopDepth
);
1472 BasicBlock
*loopBB
= convert(nir_loop_first_block(loop
));
1473 BasicBlock
*tailBB
=
1474 convert(nir_cf_node_as_block(nir_cf_node_next(&loop
->cf_node
)));
1475 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::TREE
);
1477 mkFlow(OP_PREBREAK
, tailBB
, CC_ALWAYS
, NULL
);
1478 setPosition(loopBB
, false);
1479 mkFlow(OP_PRECONT
, loopBB
, CC_ALWAYS
, NULL
);
1481 foreach_list_typed(nir_cf_node
, node
, node
, &loop
->body
) {
1485 Instruction
*insn
= bb
->getExit();
1486 if (bb
->cfg
.incidentCount() != 0) {
1487 if (!insn
|| !insn
->asFlow()) {
1488 mkFlow(OP_CONT
, loopBB
, CC_ALWAYS
, NULL
);
1489 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::BACK
);
1490 } else if (insn
&& insn
->op
== OP_BRA
&& !insn
->getPredicate() &&
1491 tailBB
->cfg
.incidentCount() == 0) {
1492 // RA doesn't like having blocks around with no incident edge,
1493 // so we create a fake one to make it happy
1494 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::TREE
);
1504 Converter::visit(nir_instr
*insn
)
1506 // we need an insertion point for on the fly generated immediate loads
1507 immInsertPos
= bb
->getExit();
1508 switch (insn
->type
) {
1509 case nir_instr_type_alu
:
1510 return visit(nir_instr_as_alu(insn
));
1511 case nir_instr_type_intrinsic
:
1512 return visit(nir_instr_as_intrinsic(insn
));
1513 case nir_instr_type_jump
:
1514 return visit(nir_instr_as_jump(insn
));
1515 case nir_instr_type_load_const
:
1516 return visit(nir_instr_as_load_const(insn
));
1517 case nir_instr_type_ssa_undef
:
1518 return visit(nir_instr_as_ssa_undef(insn
));
1519 case nir_instr_type_tex
:
1520 return visit(nir_instr_as_tex(insn
));
1522 ERROR("unknown nir_instr type %u\n", insn
->type
);
1529 Converter::convert(nir_intrinsic_op intr
)
1532 case nir_intrinsic_load_base_vertex
:
1533 return SV_BASEVERTEX
;
1534 case nir_intrinsic_load_base_instance
:
1535 return SV_BASEINSTANCE
;
1536 case nir_intrinsic_load_draw_id
:
1538 case nir_intrinsic_load_front_face
:
1540 case nir_intrinsic_load_helper_invocation
:
1541 return SV_THREAD_KILL
;
1542 case nir_intrinsic_load_instance_id
:
1543 return SV_INSTANCE_ID
;
1544 case nir_intrinsic_load_invocation_id
:
1545 return SV_INVOCATION_ID
;
1546 case nir_intrinsic_load_local_group_size
:
1548 case nir_intrinsic_load_local_invocation_id
:
1550 case nir_intrinsic_load_num_work_groups
:
1552 case nir_intrinsic_load_patch_vertices_in
:
1553 return SV_VERTEX_COUNT
;
1554 case nir_intrinsic_load_primitive_id
:
1555 return SV_PRIMITIVE_ID
;
1556 case nir_intrinsic_load_sample_id
:
1557 return SV_SAMPLE_INDEX
;
1558 case nir_intrinsic_load_sample_mask_in
:
1559 return SV_SAMPLE_MASK
;
1560 case nir_intrinsic_load_sample_pos
:
1561 return SV_SAMPLE_POS
;
1562 case nir_intrinsic_load_subgroup_eq_mask
:
1563 return SV_LANEMASK_EQ
;
1564 case nir_intrinsic_load_subgroup_ge_mask
:
1565 return SV_LANEMASK_GE
;
1566 case nir_intrinsic_load_subgroup_gt_mask
:
1567 return SV_LANEMASK_GT
;
1568 case nir_intrinsic_load_subgroup_le_mask
:
1569 return SV_LANEMASK_LE
;
1570 case nir_intrinsic_load_subgroup_lt_mask
:
1571 return SV_LANEMASK_LT
;
1572 case nir_intrinsic_load_subgroup_invocation
:
1574 case nir_intrinsic_load_tess_coord
:
1575 return SV_TESS_COORD
;
1576 case nir_intrinsic_load_tess_level_inner
:
1577 return SV_TESS_INNER
;
1578 case nir_intrinsic_load_tess_level_outer
:
1579 return SV_TESS_OUTER
;
1580 case nir_intrinsic_load_vertex_id
:
1581 return SV_VERTEX_ID
;
1582 case nir_intrinsic_load_work_group_id
:
1585 ERROR("unknown SVSemantic for nir_intrinsic_op %s\n",
1586 nir_intrinsic_infos
[intr
].name
);
1593 Converter::visit(nir_intrinsic_instr
*insn
)
1595 nir_intrinsic_op op
= insn
->intrinsic
;
1596 const nir_intrinsic_info
&opInfo
= nir_intrinsic_infos
[op
];
1597 unsigned dest_components
= nir_intrinsic_dest_components(insn
);
1600 case nir_intrinsic_load_uniform
: {
1601 LValues
&newDefs
= convert(&insn
->dest
);
1602 const DataType dType
= getDType(insn
);
1604 uint32_t coffset
= getIndirect(insn
, 0, 0, indirect
);
1605 for (uint8_t i
= 0; i
< dest_components
; ++i
) {
1606 loadFrom(FILE_MEMORY_CONST
, 0, dType
, newDefs
[i
], 16 * coffset
, i
, indirect
);
1610 case nir_intrinsic_store_output
:
1611 case nir_intrinsic_store_per_vertex_output
: {
1613 DataType dType
= getSType(insn
->src
[0], false, false);
1614 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_store_output
? 1 : 2, 0, indirect
);
1616 for (uint8_t i
= 0u; i
< nir_intrinsic_src_components(insn
, 0); ++i
) {
1617 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
1621 Value
*src
= getSrc(&insn
->src
[0], i
);
1622 switch (prog
->getType()) {
1623 case Program::TYPE_FRAGMENT
: {
1624 if (info
->out
[idx
].sn
== TGSI_SEMANTIC_POSITION
) {
1625 // TGSI uses a different interface than NIR, TGSI stores that
1626 // value in the z component, NIR in X
1628 src
= mkOp1v(OP_SAT
, TYPE_F32
, getScratch(), src
);
1632 case Program::TYPE_GEOMETRY
:
1633 case Program::TYPE_VERTEX
: {
1634 if (info
->io
.genUserClip
> 0 && idx
== (uint32_t)clipVertexOutput
) {
1635 mkMov(clipVtx
[i
], src
);
1644 storeTo(insn
, FILE_SHADER_OUTPUT
, OP_EXPORT
, dType
, src
, idx
, i
+ offset
, indirect
);
1648 case nir_intrinsic_load_input
:
1649 case nir_intrinsic_load_interpolated_input
:
1650 case nir_intrinsic_load_output
: {
1651 LValues
&newDefs
= convert(&insn
->dest
);
1654 if (prog
->getType() == Program::TYPE_FRAGMENT
&&
1655 op
== nir_intrinsic_load_output
) {
1656 std::vector
<Value
*> defs
, srcs
;
1659 srcs
.push_back(getSSA());
1660 srcs
.push_back(getSSA());
1661 Value
*x
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 0));
1662 Value
*y
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 1));
1663 mkCvt(OP_CVT
, TYPE_U32
, srcs
[0], TYPE_F32
, x
)->rnd
= ROUND_Z
;
1664 mkCvt(OP_CVT
, TYPE_U32
, srcs
[1], TYPE_F32
, y
)->rnd
= ROUND_Z
;
1666 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LAYER
, 0)));
1667 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_SAMPLE_INDEX
, 0)));
1669 for (uint8_t i
= 0u; i
< dest_components
; ++i
) {
1670 defs
.push_back(newDefs
[i
]);
1674 TexInstruction
*texi
= mkTex(OP_TXF
, TEX_TARGET_2D_MS_ARRAY
, 0, 0, defs
, srcs
);
1675 texi
->tex
.levelZero
= 1;
1676 texi
->tex
.mask
= mask
;
1677 texi
->tex
.useOffsets
= 0;
1678 texi
->tex
.r
= 0xffff;
1679 texi
->tex
.s
= 0xffff;
1681 info
->prop
.fp
.readsFramebuffer
= true;
1685 const DataType dType
= getDType(insn
);
1687 bool input
= op
!= nir_intrinsic_load_output
;
1691 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_load_interpolated_input
? 1 : 0, 0, indirect
);
1692 nv50_ir_varying
& vary
= input
? info
->in
[idx
] : info
->out
[idx
];
1694 // see load_barycentric_* handling
1695 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1696 mode
= translateInterpMode(&vary
, nvirOp
);
1697 if (op
== nir_intrinsic_load_interpolated_input
) {
1698 ImmediateValue immMode
;
1699 if (getSrc(&insn
->src
[0], 1)->getUniqueInsn()->src(0).getImmediate(immMode
))
1700 mode
|= immMode
.reg
.data
.u32
;
1704 for (uint8_t i
= 0u; i
< dest_components
; ++i
) {
1705 uint32_t address
= getSlotAddress(insn
, idx
, i
);
1706 Symbol
*sym
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
);
1707 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1709 if (typeSizeof(dType
) == 8) {
1710 Value
*lo
= getSSA();
1711 Value
*hi
= getSSA();
1712 Instruction
*interp
;
1714 interp
= mkOp1(nvirOp
, TYPE_U32
, lo
, sym
);
1715 if (nvirOp
== OP_PINTERP
)
1716 interp
->setSrc(s
++, fp
.position
);
1717 if (mode
& NV50_IR_INTERP_OFFSET
)
1718 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1719 interp
->setInterpolate(mode
);
1720 interp
->setIndirect(0, 0, indirect
);
1722 Symbol
*sym1
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
+ 4);
1723 interp
= mkOp1(nvirOp
, TYPE_U32
, hi
, sym1
);
1724 if (nvirOp
== OP_PINTERP
)
1725 interp
->setSrc(s
++, fp
.position
);
1726 if (mode
& NV50_IR_INTERP_OFFSET
)
1727 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1728 interp
->setInterpolate(mode
);
1729 interp
->setIndirect(0, 0, indirect
);
1731 mkOp2(OP_MERGE
, dType
, newDefs
[i
], lo
, hi
);
1733 Instruction
*interp
= mkOp1(nvirOp
, dType
, newDefs
[i
], sym
);
1734 if (nvirOp
== OP_PINTERP
)
1735 interp
->setSrc(s
++, fp
.position
);
1736 if (mode
& NV50_IR_INTERP_OFFSET
)
1737 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1738 interp
->setInterpolate(mode
);
1739 interp
->setIndirect(0, 0, indirect
);
1742 mkLoad(dType
, newDefs
[i
], sym
, indirect
)->perPatch
= vary
.patch
;
1747 case nir_intrinsic_load_kernel_input
: {
1748 assert(prog
->getType() == Program::TYPE_COMPUTE
);
1749 assert(insn
->num_components
== 1);
1751 LValues
&newDefs
= convert(&insn
->dest
);
1752 const DataType dType
= getDType(insn
);
1754 uint32_t idx
= getIndirect(insn
, 0, 0, indirect
, true);
1756 mkLoad(dType
, newDefs
[0], mkSymbol(FILE_SHADER_INPUT
, 0, dType
, idx
), indirect
);
1759 case nir_intrinsic_load_barycentric_at_offset
:
1760 case nir_intrinsic_load_barycentric_at_sample
:
1761 case nir_intrinsic_load_barycentric_centroid
:
1762 case nir_intrinsic_load_barycentric_pixel
:
1763 case nir_intrinsic_load_barycentric_sample
: {
1764 LValues
&newDefs
= convert(&insn
->dest
);
1767 if (op
== nir_intrinsic_load_barycentric_centroid
||
1768 op
== nir_intrinsic_load_barycentric_sample
) {
1769 mode
= NV50_IR_INTERP_CENTROID
;
1770 } else if (op
== nir_intrinsic_load_barycentric_at_offset
) {
1772 for (uint8_t c
= 0; c
< 2; c
++) {
1773 offs
[c
] = getScratch();
1774 mkOp2(OP_MIN
, TYPE_F32
, offs
[c
], getSrc(&insn
->src
[0], c
), loadImm(NULL
, 0.4375f
));
1775 mkOp2(OP_MAX
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, -0.5f
));
1776 mkOp2(OP_MUL
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, 4096.0f
));
1777 mkCvt(OP_CVT
, TYPE_S32
, offs
[c
], TYPE_F32
, offs
[c
]);
1779 mkOp3v(OP_INSBF
, TYPE_U32
, newDefs
[0], offs
[1], mkImm(0x1010), offs
[0]);
1781 mode
= NV50_IR_INTERP_OFFSET
;
1782 } else if (op
== nir_intrinsic_load_barycentric_pixel
) {
1783 mode
= NV50_IR_INTERP_DEFAULT
;
1784 } else if (op
== nir_intrinsic_load_barycentric_at_sample
) {
1785 info
->prop
.fp
.readsSampleLocations
= true;
1786 mkOp1(OP_PIXLD
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0], 0))->subOp
= NV50_IR_SUBOP_PIXLD_OFFSET
;
1787 mode
= NV50_IR_INTERP_OFFSET
;
1789 unreachable("all intrinsics already handled above");
1792 loadImm(newDefs
[1], mode
);
1795 case nir_intrinsic_discard
:
1796 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
);
1798 case nir_intrinsic_discard_if
: {
1799 Value
*pred
= getSSA(1, FILE_PREDICATE
);
1800 if (insn
->num_components
> 1) {
1801 ERROR("nir_intrinsic_discard_if only with 1 component supported!\n");
1805 mkCmp(OP_SET
, CC_NE
, TYPE_U8
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
1806 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
)->setPredicate(CC_P
, pred
);
1809 case nir_intrinsic_load_base_vertex
:
1810 case nir_intrinsic_load_base_instance
:
1811 case nir_intrinsic_load_draw_id
:
1812 case nir_intrinsic_load_front_face
:
1813 case nir_intrinsic_load_helper_invocation
:
1814 case nir_intrinsic_load_instance_id
:
1815 case nir_intrinsic_load_invocation_id
:
1816 case nir_intrinsic_load_local_group_size
:
1817 case nir_intrinsic_load_local_invocation_id
:
1818 case nir_intrinsic_load_num_work_groups
:
1819 case nir_intrinsic_load_patch_vertices_in
:
1820 case nir_intrinsic_load_primitive_id
:
1821 case nir_intrinsic_load_sample_id
:
1822 case nir_intrinsic_load_sample_mask_in
:
1823 case nir_intrinsic_load_sample_pos
:
1824 case nir_intrinsic_load_subgroup_eq_mask
:
1825 case nir_intrinsic_load_subgroup_ge_mask
:
1826 case nir_intrinsic_load_subgroup_gt_mask
:
1827 case nir_intrinsic_load_subgroup_le_mask
:
1828 case nir_intrinsic_load_subgroup_lt_mask
:
1829 case nir_intrinsic_load_subgroup_invocation
:
1830 case nir_intrinsic_load_tess_coord
:
1831 case nir_intrinsic_load_tess_level_inner
:
1832 case nir_intrinsic_load_tess_level_outer
:
1833 case nir_intrinsic_load_vertex_id
:
1834 case nir_intrinsic_load_work_group_id
: {
1835 const DataType dType
= getDType(insn
);
1836 SVSemantic sv
= convert(op
);
1837 LValues
&newDefs
= convert(&insn
->dest
);
1839 for (uint8_t i
= 0u; i
< nir_intrinsic_dest_components(insn
); ++i
) {
1841 if (typeSizeof(dType
) == 8)
1846 if (sv
== SV_TID
&& info
->prop
.cp
.numThreads
[i
] == 1) {
1849 Symbol
*sym
= mkSysVal(sv
, i
);
1850 Instruction
*rdsv
= mkOp1(OP_RDSV
, TYPE_U32
, def
, sym
);
1851 if (sv
== SV_TESS_OUTER
|| sv
== SV_TESS_INNER
)
1855 if (typeSizeof(dType
) == 8)
1856 mkOp2(OP_MERGE
, dType
, newDefs
[i
], def
, loadImm(getSSA(), 0u));
1861 case nir_intrinsic_load_subgroup_size
: {
1862 LValues
&newDefs
= convert(&insn
->dest
);
1863 loadImm(newDefs
[0], 32u);
1866 case nir_intrinsic_vote_all
:
1867 case nir_intrinsic_vote_any
:
1868 case nir_intrinsic_vote_ieq
: {
1869 LValues
&newDefs
= convert(&insn
->dest
);
1870 Value
*pred
= getScratch(1, FILE_PREDICATE
);
1871 mkCmp(OP_SET
, CC_NE
, TYPE_U32
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
1872 mkOp1(OP_VOTE
, TYPE_U32
, pred
, pred
)->subOp
= getSubOp(op
);
1873 mkCvt(OP_CVT
, TYPE_U32
, newDefs
[0], TYPE_U8
, pred
);
1876 case nir_intrinsic_ballot
: {
1877 LValues
&newDefs
= convert(&insn
->dest
);
1878 Value
*pred
= getSSA(1, FILE_PREDICATE
);
1879 mkCmp(OP_SET
, CC_NE
, TYPE_U32
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
1880 mkOp1(OP_VOTE
, TYPE_U32
, newDefs
[0], pred
)->subOp
= NV50_IR_SUBOP_VOTE_ANY
;
1883 case nir_intrinsic_read_first_invocation
:
1884 case nir_intrinsic_read_invocation
: {
1885 LValues
&newDefs
= convert(&insn
->dest
);
1886 const DataType dType
= getDType(insn
);
1887 Value
*tmp
= getScratch();
1889 if (op
== nir_intrinsic_read_first_invocation
) {
1890 mkOp1(OP_VOTE
, TYPE_U32
, tmp
, mkImm(1))->subOp
= NV50_IR_SUBOP_VOTE_ANY
;
1891 mkOp1(OP_BREV
, TYPE_U32
, tmp
, tmp
);
1892 mkOp1(OP_BFIND
, TYPE_U32
, tmp
, tmp
)->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
1894 tmp
= getSrc(&insn
->src
[1], 0);
1896 for (uint8_t i
= 0; i
< dest_components
; ++i
) {
1897 mkOp3(OP_SHFL
, dType
, newDefs
[i
], getSrc(&insn
->src
[0], i
), tmp
, mkImm(0x1f))
1898 ->subOp
= NV50_IR_SUBOP_SHFL_IDX
;
1902 case nir_intrinsic_load_per_vertex_input
: {
1903 const DataType dType
= getDType(insn
);
1904 LValues
&newDefs
= convert(&insn
->dest
);
1905 Value
*indirectVertex
;
1906 Value
*indirectOffset
;
1907 uint32_t baseVertex
= getIndirect(&insn
->src
[0], 0, indirectVertex
);
1908 uint32_t idx
= getIndirect(insn
, 1, 0, indirectOffset
);
1910 Value
*vtxBase
= mkOp2v(OP_PFETCH
, TYPE_U32
, getSSA(4, FILE_ADDRESS
),
1911 mkImm(baseVertex
), indirectVertex
);
1912 for (uint8_t i
= 0u; i
< dest_components
; ++i
) {
1913 uint32_t address
= getSlotAddress(insn
, idx
, i
);
1914 loadFrom(FILE_SHADER_INPUT
, 0, dType
, newDefs
[i
], address
, 0,
1915 indirectOffset
, vtxBase
, info
->in
[idx
].patch
);
1919 case nir_intrinsic_load_per_vertex_output
: {
1920 const DataType dType
= getDType(insn
);
1921 LValues
&newDefs
= convert(&insn
->dest
);
1922 Value
*indirectVertex
;
1923 Value
*indirectOffset
;
1924 uint32_t baseVertex
= getIndirect(&insn
->src
[0], 0, indirectVertex
);
1925 uint32_t idx
= getIndirect(insn
, 1, 0, indirectOffset
);
1926 Value
*vtxBase
= NULL
;
1929 vtxBase
= indirectVertex
;
1931 vtxBase
= loadImm(NULL
, baseVertex
);
1933 vtxBase
= mkOp2v(OP_ADD
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), outBase
, vtxBase
);
1935 for (uint8_t i
= 0u; i
< dest_components
; ++i
) {
1936 uint32_t address
= getSlotAddress(insn
, idx
, i
);
1937 loadFrom(FILE_SHADER_OUTPUT
, 0, dType
, newDefs
[i
], address
, 0,
1938 indirectOffset
, vtxBase
, info
->in
[idx
].patch
);
1942 case nir_intrinsic_emit_vertex
:
1943 if (info
->io
.genUserClip
> 0)
1944 handleUserClipPlanes();
1946 case nir_intrinsic_end_primitive
: {
1947 uint32_t idx
= nir_intrinsic_stream_id(insn
);
1948 mkOp1(getOperation(op
), TYPE_U32
, NULL
, mkImm(idx
))->fixed
= 1;
1951 case nir_intrinsic_load_ubo
: {
1952 const DataType dType
= getDType(insn
);
1953 LValues
&newDefs
= convert(&insn
->dest
);
1954 Value
*indirectIndex
;
1955 Value
*indirectOffset
;
1956 uint32_t index
= getIndirect(&insn
->src
[0], 0, indirectIndex
) + 1;
1957 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
1959 for (uint8_t i
= 0u; i
< dest_components
; ++i
) {
1960 loadFrom(FILE_MEMORY_CONST
, index
, dType
, newDefs
[i
], offset
, i
,
1961 indirectOffset
, indirectIndex
);
1965 case nir_intrinsic_get_buffer_size
: {
1966 LValues
&newDefs
= convert(&insn
->dest
);
1967 const DataType dType
= getDType(insn
);
1968 Value
*indirectBuffer
;
1969 uint32_t buffer
= getIndirect(&insn
->src
[0], 0, indirectBuffer
);
1971 Symbol
*sym
= mkSymbol(FILE_MEMORY_BUFFER
, buffer
, dType
, 0);
1972 mkOp1(OP_BUFQ
, dType
, newDefs
[0], sym
)->setIndirect(0, 0, indirectBuffer
);
1975 case nir_intrinsic_store_ssbo
: {
1976 DataType sType
= getSType(insn
->src
[0], false, false);
1977 Value
*indirectBuffer
;
1978 Value
*indirectOffset
;
1979 uint32_t buffer
= getIndirect(&insn
->src
[1], 0, indirectBuffer
);
1980 uint32_t offset
= getIndirect(&insn
->src
[2], 0, indirectOffset
);
1982 for (uint8_t i
= 0u; i
< nir_intrinsic_src_components(insn
, 0); ++i
) {
1983 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
1985 Symbol
*sym
= mkSymbol(FILE_MEMORY_BUFFER
, buffer
, sType
,
1986 offset
+ i
* typeSizeof(sType
));
1987 mkStore(OP_STORE
, sType
, sym
, indirectOffset
, getSrc(&insn
->src
[0], i
))
1988 ->setIndirect(0, 1, indirectBuffer
);
1990 info
->io
.globalAccess
|= 0x2;
1993 case nir_intrinsic_load_ssbo
: {
1994 const DataType dType
= getDType(insn
);
1995 LValues
&newDefs
= convert(&insn
->dest
);
1996 Value
*indirectBuffer
;
1997 Value
*indirectOffset
;
1998 uint32_t buffer
= getIndirect(&insn
->src
[0], 0, indirectBuffer
);
1999 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2001 for (uint8_t i
= 0u; i
< dest_components
; ++i
)
2002 loadFrom(FILE_MEMORY_BUFFER
, buffer
, dType
, newDefs
[i
], offset
, i
,
2003 indirectOffset
, indirectBuffer
);
2005 info
->io
.globalAccess
|= 0x1;
2008 case nir_intrinsic_shared_atomic_add
:
2009 case nir_intrinsic_shared_atomic_and
:
2010 case nir_intrinsic_shared_atomic_comp_swap
:
2011 case nir_intrinsic_shared_atomic_exchange
:
2012 case nir_intrinsic_shared_atomic_or
:
2013 case nir_intrinsic_shared_atomic_imax
:
2014 case nir_intrinsic_shared_atomic_imin
:
2015 case nir_intrinsic_shared_atomic_umax
:
2016 case nir_intrinsic_shared_atomic_umin
:
2017 case nir_intrinsic_shared_atomic_xor
: {
2018 const DataType dType
= getDType(insn
);
2019 LValues
&newDefs
= convert(&insn
->dest
);
2020 Value
*indirectOffset
;
2021 uint32_t offset
= getIndirect(&insn
->src
[0], 0, indirectOffset
);
2022 Symbol
*sym
= mkSymbol(FILE_MEMORY_SHARED
, 0, dType
, offset
);
2023 Instruction
*atom
= mkOp2(OP_ATOM
, dType
, newDefs
[0], sym
, getSrc(&insn
->src
[1], 0));
2024 if (op
== nir_intrinsic_shared_atomic_comp_swap
)
2025 atom
->setSrc(2, getSrc(&insn
->src
[2], 0));
2026 atom
->setIndirect(0, 0, indirectOffset
);
2027 atom
->subOp
= getSubOp(op
);
2030 case nir_intrinsic_ssbo_atomic_add
:
2031 case nir_intrinsic_ssbo_atomic_and
:
2032 case nir_intrinsic_ssbo_atomic_comp_swap
:
2033 case nir_intrinsic_ssbo_atomic_exchange
:
2034 case nir_intrinsic_ssbo_atomic_or
:
2035 case nir_intrinsic_ssbo_atomic_imax
:
2036 case nir_intrinsic_ssbo_atomic_imin
:
2037 case nir_intrinsic_ssbo_atomic_umax
:
2038 case nir_intrinsic_ssbo_atomic_umin
:
2039 case nir_intrinsic_ssbo_atomic_xor
: {
2040 const DataType dType
= getDType(insn
);
2041 LValues
&newDefs
= convert(&insn
->dest
);
2042 Value
*indirectBuffer
;
2043 Value
*indirectOffset
;
2044 uint32_t buffer
= getIndirect(&insn
->src
[0], 0, indirectBuffer
);
2045 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2047 Symbol
*sym
= mkSymbol(FILE_MEMORY_BUFFER
, buffer
, dType
, offset
);
2048 Instruction
*atom
= mkOp2(OP_ATOM
, dType
, newDefs
[0], sym
,
2049 getSrc(&insn
->src
[2], 0));
2050 if (op
== nir_intrinsic_ssbo_atomic_comp_swap
)
2051 atom
->setSrc(2, getSrc(&insn
->src
[3], 0));
2052 atom
->setIndirect(0, 0, indirectOffset
);
2053 atom
->setIndirect(0, 1, indirectBuffer
);
2054 atom
->subOp
= getSubOp(op
);
2056 info
->io
.globalAccess
|= 0x2;
2059 case nir_intrinsic_global_atomic_add
:
2060 case nir_intrinsic_global_atomic_and
:
2061 case nir_intrinsic_global_atomic_comp_swap
:
2062 case nir_intrinsic_global_atomic_exchange
:
2063 case nir_intrinsic_global_atomic_or
:
2064 case nir_intrinsic_global_atomic_imax
:
2065 case nir_intrinsic_global_atomic_imin
:
2066 case nir_intrinsic_global_atomic_umax
:
2067 case nir_intrinsic_global_atomic_umin
:
2068 case nir_intrinsic_global_atomic_xor
: {
2069 const DataType dType
= getDType(insn
);
2070 LValues
&newDefs
= convert(&insn
->dest
);
2072 uint32_t offset
= getIndirect(&insn
->src
[0], 0, address
);
2074 Symbol
*sym
= mkSymbol(FILE_MEMORY_GLOBAL
, 0, dType
, offset
);
2076 mkOp2(OP_ATOM
, dType
, newDefs
[0], sym
, getSrc(&insn
->src
[1], 0));
2077 atom
->setIndirect(0, 0, address
);
2078 atom
->subOp
= getSubOp(op
);
2080 info
->io
.globalAccess
|= 0x2;
2083 case nir_intrinsic_bindless_image_atomic_add
:
2084 case nir_intrinsic_bindless_image_atomic_and
:
2085 case nir_intrinsic_bindless_image_atomic_comp_swap
:
2086 case nir_intrinsic_bindless_image_atomic_exchange
:
2087 case nir_intrinsic_bindless_image_atomic_imax
:
2088 case nir_intrinsic_bindless_image_atomic_umax
:
2089 case nir_intrinsic_bindless_image_atomic_imin
:
2090 case nir_intrinsic_bindless_image_atomic_umin
:
2091 case nir_intrinsic_bindless_image_atomic_or
:
2092 case nir_intrinsic_bindless_image_atomic_xor
:
2093 case nir_intrinsic_bindless_image_load
:
2094 case nir_intrinsic_bindless_image_samples
:
2095 case nir_intrinsic_bindless_image_size
:
2096 case nir_intrinsic_bindless_image_store
:
2097 case nir_intrinsic_image_atomic_add
:
2098 case nir_intrinsic_image_atomic_and
:
2099 case nir_intrinsic_image_atomic_comp_swap
:
2100 case nir_intrinsic_image_atomic_exchange
:
2101 case nir_intrinsic_image_atomic_imax
:
2102 case nir_intrinsic_image_atomic_umax
:
2103 case nir_intrinsic_image_atomic_imin
:
2104 case nir_intrinsic_image_atomic_umin
:
2105 case nir_intrinsic_image_atomic_or
:
2106 case nir_intrinsic_image_atomic_xor
:
2107 case nir_intrinsic_image_load
:
2108 case nir_intrinsic_image_samples
:
2109 case nir_intrinsic_image_size
:
2110 case nir_intrinsic_image_store
: {
2111 std::vector
<Value
*> srcs
, defs
;
2116 TexInstruction::Target target
=
2117 convert(nir_intrinsic_image_dim(insn
), !!nir_intrinsic_image_array(insn
), false);
2118 unsigned int argCount
= getNIRArgCount(target
);
2119 uint16_t location
= 0;
2121 if (opInfo
.has_dest
) {
2122 LValues
&newDefs
= convert(&insn
->dest
);
2123 for (uint8_t i
= 0u; i
< newDefs
.size(); ++i
) {
2124 defs
.push_back(newDefs
[i
]);
2130 bool bindless
= false;
2132 case nir_intrinsic_bindless_image_atomic_add
:
2133 case nir_intrinsic_bindless_image_atomic_and
:
2134 case nir_intrinsic_bindless_image_atomic_comp_swap
:
2135 case nir_intrinsic_bindless_image_atomic_exchange
:
2136 case nir_intrinsic_bindless_image_atomic_imax
:
2137 case nir_intrinsic_bindless_image_atomic_umax
:
2138 case nir_intrinsic_bindless_image_atomic_imin
:
2139 case nir_intrinsic_bindless_image_atomic_umin
:
2140 case nir_intrinsic_bindless_image_atomic_or
:
2141 case nir_intrinsic_bindless_image_atomic_xor
:
2142 ty
= getDType(insn
);
2144 info
->io
.globalAccess
|= 0x2;
2147 case nir_intrinsic_image_atomic_add
:
2148 case nir_intrinsic_image_atomic_and
:
2149 case nir_intrinsic_image_atomic_comp_swap
:
2150 case nir_intrinsic_image_atomic_exchange
:
2151 case nir_intrinsic_image_atomic_imax
:
2152 case nir_intrinsic_image_atomic_umax
:
2153 case nir_intrinsic_image_atomic_imin
:
2154 case nir_intrinsic_image_atomic_umin
:
2155 case nir_intrinsic_image_atomic_or
:
2156 case nir_intrinsic_image_atomic_xor
:
2157 ty
= getDType(insn
);
2159 info
->io
.globalAccess
|= 0x2;
2162 case nir_intrinsic_bindless_image_load
:
2163 case nir_intrinsic_image_load
:
2165 bindless
= op
== nir_intrinsic_bindless_image_load
;
2166 info
->io
.globalAccess
|= 0x1;
2169 case nir_intrinsic_bindless_image_store
:
2170 case nir_intrinsic_image_store
:
2172 bindless
= op
== nir_intrinsic_bindless_image_store
;
2173 info
->io
.globalAccess
|= 0x2;
2177 case nir_intrinsic_bindless_image_samples
:
2178 case nir_intrinsic_image_samples
:
2180 bindless
= op
== nir_intrinsic_bindless_image_samples
;
2183 case nir_intrinsic_bindless_image_size
:
2184 case nir_intrinsic_image_size
:
2186 bindless
= op
== nir_intrinsic_bindless_image_size
;
2189 unreachable("unhandled image opcode");
2194 indirect
= getSrc(&insn
->src
[0], 0);
2196 location
= getIndirect(&insn
->src
[0], 0, indirect
);
2199 if (opInfo
.num_srcs
>= 2)
2200 for (unsigned int i
= 0u; i
< argCount
; ++i
)
2201 srcs
.push_back(getSrc(&insn
->src
[1], i
));
2203 // the sampler is just another src added after coords
2204 if (opInfo
.num_srcs
>= 3 && target
.isMS())
2205 srcs
.push_back(getSrc(&insn
->src
[2], 0));
2207 if (opInfo
.num_srcs
>= 4 && lod_src
!= 4) {
2208 unsigned components
= opInfo
.src_components
[3] ? opInfo
.src_components
[3] : insn
->num_components
;
2209 for (uint8_t i
= 0u; i
< components
; ++i
)
2210 srcs
.push_back(getSrc(&insn
->src
[3], i
));
2213 if (opInfo
.num_srcs
>= 5 && lod_src
!= 5)
2214 // 1 for aotmic swap
2215 for (uint8_t i
= 0u; i
< opInfo
.src_components
[4]; ++i
)
2216 srcs
.push_back(getSrc(&insn
->src
[4], i
));
2218 TexInstruction
*texi
= mkTex(getOperation(op
), target
.getEnum(), location
, 0, defs
, srcs
);
2219 texi
->tex
.bindless
= bindless
;
2220 texi
->tex
.format
= nv50_ir::TexInstruction::translateImgFormat(nir_intrinsic_format(insn
));
2221 texi
->tex
.mask
= mask
;
2222 texi
->cache
= convert(nir_intrinsic_access(insn
));
2224 texi
->subOp
= getSubOp(op
);
2227 texi
->setIndirectR(indirect
);
2231 case nir_intrinsic_store_shared
: {
2232 DataType sType
= getSType(insn
->src
[0], false, false);
2233 Value
*indirectOffset
;
2234 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2236 for (uint8_t i
= 0u; i
< nir_intrinsic_src_components(insn
, 0); ++i
) {
2237 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
2239 Symbol
*sym
= mkSymbol(FILE_MEMORY_SHARED
, 0, sType
, offset
+ i
* typeSizeof(sType
));
2240 mkStore(OP_STORE
, sType
, sym
, indirectOffset
, getSrc(&insn
->src
[0], i
));
2244 case nir_intrinsic_load_shared
: {
2245 const DataType dType
= getDType(insn
);
2246 LValues
&newDefs
= convert(&insn
->dest
);
2247 Value
*indirectOffset
;
2248 uint32_t offset
= getIndirect(&insn
->src
[0], 0, indirectOffset
);
2250 for (uint8_t i
= 0u; i
< dest_components
; ++i
)
2251 loadFrom(FILE_MEMORY_SHARED
, 0, dType
, newDefs
[i
], offset
, i
, indirectOffset
);
2255 case nir_intrinsic_control_barrier
: {
2256 // TODO: add flag to shader_info
2257 info
->numBarriers
= 1;
2258 Instruction
*bar
= mkOp2(OP_BAR
, TYPE_U32
, NULL
, mkImm(0), mkImm(0));
2260 bar
->subOp
= NV50_IR_SUBOP_BAR_SYNC
;
2263 case nir_intrinsic_group_memory_barrier
:
2264 case nir_intrinsic_memory_barrier
:
2265 case nir_intrinsic_memory_barrier_buffer
:
2266 case nir_intrinsic_memory_barrier_image
:
2267 case nir_intrinsic_memory_barrier_shared
: {
2268 Instruction
*bar
= mkOp(OP_MEMBAR
, TYPE_NONE
, NULL
);
2270 bar
->subOp
= getSubOp(op
);
2273 case nir_intrinsic_memory_barrier_tcs_patch
:
2275 case nir_intrinsic_shader_clock
: {
2276 const DataType dType
= getDType(insn
);
2277 LValues
&newDefs
= convert(&insn
->dest
);
2279 loadImm(newDefs
[0], 0u);
2280 mkOp1(OP_RDSV
, dType
, newDefs
[1], mkSysVal(SV_CLOCK
, 0))->fixed
= 1;
2283 case nir_intrinsic_load_global
: {
2284 const DataType dType
= getDType(insn
);
2285 LValues
&newDefs
= convert(&insn
->dest
);
2286 Value
*indirectOffset
;
2287 uint32_t offset
= getIndirect(&insn
->src
[0], 0, indirectOffset
);
2289 for (auto i
= 0u; i
< dest_components
; ++i
)
2290 loadFrom(FILE_MEMORY_GLOBAL
, 0, dType
, newDefs
[i
], offset
, i
, indirectOffset
);
2292 info
->io
.globalAccess
|= 0x1;
2295 case nir_intrinsic_store_global
: {
2296 DataType sType
= getSType(insn
->src
[0], false, false);
2298 for (auto i
= 0u; i
< nir_intrinsic_src_components(insn
, 0); ++i
) {
2299 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
2301 if (typeSizeof(sType
) == 8) {
2303 mkSplit(split
, 4, getSrc(&insn
->src
[0], i
));
2305 Symbol
*sym
= mkSymbol(FILE_MEMORY_GLOBAL
, 0, TYPE_U32
, i
* typeSizeof(sType
));
2306 mkStore(OP_STORE
, TYPE_U32
, sym
, getSrc(&insn
->src
[1], 0), split
[0]);
2308 sym
= mkSymbol(FILE_MEMORY_GLOBAL
, 0, TYPE_U32
, i
* typeSizeof(sType
) + 4);
2309 mkStore(OP_STORE
, TYPE_U32
, sym
, getSrc(&insn
->src
[1], 0), split
[1]);
2311 Symbol
*sym
= mkSymbol(FILE_MEMORY_GLOBAL
, 0, sType
, i
* typeSizeof(sType
));
2312 mkStore(OP_STORE
, sType
, sym
, getSrc(&insn
->src
[1], 0), getSrc(&insn
->src
[0], i
));
2316 info
->io
.globalAccess
|= 0x2;
2320 ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos
[op
].name
);
2328 Converter::visit(nir_jump_instr
*insn
)
2330 switch (insn
->type
) {
2331 case nir_jump_return
:
2332 // TODO: this only works in the main function
2333 mkFlow(OP_BRA
, exit
, CC_ALWAYS
, NULL
);
2334 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::CROSS
);
2336 case nir_jump_break
:
2337 case nir_jump_continue
: {
2338 bool isBreak
= insn
->type
== nir_jump_break
;
2339 nir_block
*block
= insn
->instr
.block
;
2340 assert(!block
->successors
[1]);
2341 BasicBlock
*target
= convert(block
->successors
[0]);
2342 mkFlow(isBreak
? OP_BREAK
: OP_CONT
, target
, CC_ALWAYS
, NULL
);
2343 bb
->cfg
.attach(&target
->cfg
, isBreak
? Graph::Edge::CROSS
: Graph::Edge::BACK
);
2347 ERROR("unknown nir_jump_type %u\n", insn
->type
);
2355 Converter::convert(nir_load_const_instr
*insn
, uint8_t idx
)
2360 setPosition(immInsertPos
, true);
2362 setPosition(bb
, false);
2364 switch (insn
->def
.bit_size
) {
2366 val
= loadImm(getSSA(8), insn
->value
[idx
].u64
);
2369 val
= loadImm(getSSA(4), insn
->value
[idx
].u32
);
2372 val
= loadImm(getSSA(2), insn
->value
[idx
].u16
);
2375 val
= loadImm(getSSA(1), insn
->value
[idx
].u8
);
2378 unreachable("unhandled bit size!\n");
2380 setPosition(bb
, true);
2385 Converter::visit(nir_load_const_instr
*insn
)
2387 assert(insn
->def
.bit_size
<= 64);
2388 immediates
[insn
->def
.index
] = insn
;
2392 #define DEFAULT_CHECKS \
2393 if (insn->dest.dest.ssa.num_components > 1) { \
2394 ERROR("nir_alu_instr only supported with 1 component!\n"); \
2397 if (insn->dest.write_mask != 1) { \
2398 ERROR("nir_alu_instr only with write_mask of 1 supported!\n"); \
2402 Converter::visit(nir_alu_instr
*insn
)
2404 const nir_op op
= insn
->op
;
2405 const nir_op_info
&info
= nir_op_infos
[op
];
2406 DataType dType
= getDType(insn
);
2407 const std::vector
<DataType
> sTypes
= getSTypes(insn
);
2409 Instruction
*oldPos
= this->bb
->getExit();
2420 case nir_op_fddx_coarse
:
2421 case nir_op_fddx_fine
:
2423 case nir_op_fddy_coarse
:
2424 case nir_op_fddy_fine
:
2443 case nir_op_imul_high
:
2444 case nir_op_umul_high
:
2449 case nir_op_pack_64_2x32_split
:
2464 LValues
&newDefs
= convert(&insn
->dest
);
2465 operation preOp
= preOperationNeeded(op
);
2466 if (preOp
!= OP_NOP
) {
2467 assert(info
.num_inputs
< 2);
2468 Value
*tmp
= getSSA(typeSizeof(dType
));
2469 Instruction
*i0
= mkOp(preOp
, dType
, tmp
);
2470 Instruction
*i1
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2471 if (info
.num_inputs
) {
2472 i0
->setSrc(0, getSrc(&insn
->src
[0]));
2475 i1
->subOp
= getSubOp(op
);
2477 Instruction
*i
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2478 for (unsigned s
= 0u; s
< info
.num_inputs
; ++s
) {
2479 i
->setSrc(s
, getSrc(&insn
->src
[s
]));
2481 i
->subOp
= getSubOp(op
);
2485 case nir_op_ifind_msb
:
2486 case nir_op_ufind_msb
: {
2488 LValues
&newDefs
= convert(&insn
->dest
);
2490 mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2493 case nir_op_fround_even
: {
2495 LValues
&newDefs
= convert(&insn
->dest
);
2496 mkCvt(OP_CVT
, dType
, newDefs
[0], dType
, getSrc(&insn
->src
[0]))->rnd
= ROUND_NI
;
2499 // convert instructions
2513 case nir_op_u2u64
: {
2515 LValues
&newDefs
= convert(&insn
->dest
);
2516 Instruction
*i
= mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2517 if (op
== nir_op_f2i32
|| op
== nir_op_f2i64
|| op
== nir_op_f2u32
|| op
== nir_op_f2u64
)
2519 i
->sType
= sTypes
[0];
2522 // compare instructions
2532 case nir_op_ine32
: {
2534 LValues
&newDefs
= convert(&insn
->dest
);
2535 Instruction
*i
= mkCmp(getOperation(op
),
2540 getSrc(&insn
->src
[0]),
2541 getSrc(&insn
->src
[1]));
2542 if (info
.num_inputs
== 3)
2543 i
->setSrc(2, getSrc(&insn
->src
[2]));
2544 i
->sType
= sTypes
[0];
2547 // those are weird ALU ops and need special handling, because
2548 // 1. they are always componend based
2549 // 2. they basically just merge multiple values into one data type
2551 if (!insn
->dest
.dest
.is_ssa
&& insn
->dest
.dest
.reg
.reg
->num_array_elems
) {
2552 nir_reg_dest
& reg
= insn
->dest
.dest
.reg
;
2553 uint32_t goffset
= regToLmemOffset
[reg
.reg
->index
];
2554 uint8_t comps
= reg
.reg
->num_components
;
2555 uint8_t size
= reg
.reg
->bit_size
/ 8;
2556 uint8_t csize
= 4 * size
; // TODO after fixing MemoryOpts: comps * size;
2557 uint32_t aoffset
= csize
* reg
.base_offset
;
2558 Value
*indirect
= NULL
;
2561 indirect
= mkOp2v(OP_MUL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
),
2562 getSrc(reg
.indirect
, 0), mkImm(csize
));
2564 for (uint8_t i
= 0u; i
< comps
; ++i
) {
2565 if (!((1u << i
) & insn
->dest
.write_mask
))
2568 Symbol
*sym
= mkSymbol(FILE_MEMORY_LOCAL
, 0, dType
, goffset
+ aoffset
+ i
* size
);
2569 mkStore(OP_STORE
, dType
, sym
, indirect
, getSrc(&insn
->src
[0], i
));
2572 } else if (!insn
->src
[0].src
.is_ssa
&& insn
->src
[0].src
.reg
.reg
->num_array_elems
) {
2573 LValues
&newDefs
= convert(&insn
->dest
);
2574 nir_reg_src
& reg
= insn
->src
[0].src
.reg
;
2575 uint32_t goffset
= regToLmemOffset
[reg
.reg
->index
];
2576 // uint8_t comps = reg.reg->num_components;
2577 uint8_t size
= reg
.reg
->bit_size
/ 8;
2578 uint8_t csize
= 4 * size
; // TODO after fixing MemoryOpts: comps * size;
2579 uint32_t aoffset
= csize
* reg
.base_offset
;
2580 Value
*indirect
= NULL
;
2583 indirect
= mkOp2v(OP_MUL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), getSrc(reg
.indirect
, 0), mkImm(csize
));
2585 for (uint8_t i
= 0u; i
< newDefs
.size(); ++i
)
2586 loadFrom(FILE_MEMORY_LOCAL
, 0, dType
, newDefs
[i
], goffset
+ aoffset
, i
, indirect
);
2590 LValues
&newDefs
= convert(&insn
->dest
);
2591 for (LValues::size_type c
= 0u; c
< newDefs
.size(); ++c
) {
2592 mkMov(newDefs
[c
], getSrc(&insn
->src
[0], c
), dType
);
2600 case nir_op_vec16
: {
2601 LValues
&newDefs
= convert(&insn
->dest
);
2602 for (LValues::size_type c
= 0u; c
< newDefs
.size(); ++c
) {
2603 mkMov(newDefs
[c
], getSrc(&insn
->src
[c
]), dType
);
2608 case nir_op_pack_64_2x32
: {
2609 LValues
&newDefs
= convert(&insn
->dest
);
2610 Instruction
*merge
= mkOp(OP_MERGE
, dType
, newDefs
[0]);
2611 merge
->setSrc(0, getSrc(&insn
->src
[0], 0));
2612 merge
->setSrc(1, getSrc(&insn
->src
[0], 1));
2615 case nir_op_pack_half_2x16_split
: {
2616 LValues
&newDefs
= convert(&insn
->dest
);
2617 Value
*tmpH
= getSSA();
2618 Value
*tmpL
= getSSA();
2620 mkCvt(OP_CVT
, TYPE_F16
, tmpL
, TYPE_F32
, getSrc(&insn
->src
[0]));
2621 mkCvt(OP_CVT
, TYPE_F16
, tmpH
, TYPE_F32
, getSrc(&insn
->src
[1]));
2622 mkOp3(OP_INSBF
, TYPE_U32
, newDefs
[0], tmpH
, mkImm(0x1010), tmpL
);
2625 case nir_op_unpack_half_2x16_split_x
:
2626 case nir_op_unpack_half_2x16_split_y
: {
2627 LValues
&newDefs
= convert(&insn
->dest
);
2628 Instruction
*cvt
= mkCvt(OP_CVT
, TYPE_F32
, newDefs
[0], TYPE_F16
, getSrc(&insn
->src
[0]));
2629 if (op
== nir_op_unpack_half_2x16_split_y
)
2633 case nir_op_unpack_64_2x32
: {
2634 LValues
&newDefs
= convert(&insn
->dest
);
2635 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, newDefs
[1]);
2638 case nir_op_unpack_64_2x32_split_x
: {
2639 LValues
&newDefs
= convert(&insn
->dest
);
2640 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, getSSA());
2643 case nir_op_unpack_64_2x32_split_y
: {
2644 LValues
&newDefs
= convert(&insn
->dest
);
2645 mkOp1(OP_SPLIT
, dType
, getSSA(), getSrc(&insn
->src
[0]))->setDef(1, newDefs
[0]);
2648 // special instructions
2650 case nir_op_isign
: {
2653 if (::isFloatType(dType
))
2658 LValues
&newDefs
= convert(&insn
->dest
);
2659 LValue
*val0
= getScratch();
2660 LValue
*val1
= getScratch();
2661 mkCmp(OP_SET
, CC_GT
, iType
, val0
, dType
, getSrc(&insn
->src
[0]), zero
);
2662 mkCmp(OP_SET
, CC_LT
, iType
, val1
, dType
, getSrc(&insn
->src
[0]), zero
);
2664 if (dType
== TYPE_F64
) {
2665 mkOp2(OP_SUB
, iType
, val0
, val0
, val1
);
2666 mkCvt(OP_CVT
, TYPE_F64
, newDefs
[0], iType
, val0
);
2667 } else if (dType
== TYPE_S64
|| dType
== TYPE_U64
) {
2668 mkOp2(OP_SUB
, iType
, val0
, val1
, val0
);
2669 mkOp2(OP_SHR
, iType
, val1
, val0
, loadImm(NULL
, 31));
2670 mkOp2(OP_MERGE
, dType
, newDefs
[0], val0
, val1
);
2671 } else if (::isFloatType(dType
))
2672 mkOp2(OP_SUB
, iType
, newDefs
[0], val0
, val1
);
2674 mkOp2(OP_SUB
, iType
, newDefs
[0], val1
, val0
);
2678 case nir_op_b32csel
: {
2680 LValues
&newDefs
= convert(&insn
->dest
);
2681 mkCmp(OP_SLCT
, CC_NE
, dType
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[1]), getSrc(&insn
->src
[2]), getSrc(&insn
->src
[0]));
2684 case nir_op_ibitfield_extract
:
2685 case nir_op_ubitfield_extract
: {
2687 Value
*tmp
= getSSA();
2688 LValues
&newDefs
= convert(&insn
->dest
);
2689 mkOp3(OP_INSBF
, dType
, tmp
, getSrc(&insn
->src
[2]), loadImm(NULL
, 0x808), getSrc(&insn
->src
[1]));
2690 mkOp2(OP_EXTBF
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), tmp
);
2695 LValues
&newDefs
= convert(&insn
->dest
);
2696 mkOp2(OP_BMSK
, dType
, newDefs
[0], getSrc(&insn
->src
[1]), getSrc(&insn
->src
[0]))->subOp
= NV50_IR_SUBOP_BMSK_W
;
2699 case nir_op_bitfield_insert
: {
2701 LValues
&newDefs
= convert(&insn
->dest
);
2702 LValue
*temp
= getSSA();
2703 mkOp3(OP_INSBF
, TYPE_U32
, temp
, getSrc(&insn
->src
[3]), mkImm(0x808), getSrc(&insn
->src
[2]));
2704 mkOp3(OP_INSBF
, dType
, newDefs
[0], getSrc(&insn
->src
[1]), temp
, getSrc(&insn
->src
[0]));
2707 case nir_op_bit_count
: {
2709 LValues
&newDefs
= convert(&insn
->dest
);
2710 mkOp2(OP_POPCNT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), getSrc(&insn
->src
[0]));
2713 case nir_op_bitfield_reverse
: {
2715 LValues
&newDefs
= convert(&insn
->dest
);
2716 mkOp1(OP_BREV
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]));
2719 case nir_op_find_lsb
: {
2721 LValues
&newDefs
= convert(&insn
->dest
);
2722 Value
*tmp
= getSSA();
2723 mkOp1(OP_BREV
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]));
2724 mkOp1(OP_BFIND
, TYPE_U32
, newDefs
[0], tmp
)->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
2727 case nir_op_extract_u8
: {
2729 LValues
&newDefs
= convert(&insn
->dest
);
2730 Value
*prmt
= getSSA();
2731 mkOp2(OP_OR
, TYPE_U32
, prmt
, getSrc(&insn
->src
[1]), loadImm(NULL
, 0x4440));
2732 mkOp3(OP_PERMT
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), prmt
, loadImm(NULL
, 0));
2735 case nir_op_extract_i8
: {
2737 LValues
&newDefs
= convert(&insn
->dest
);
2738 Value
*prmt
= getSSA();
2739 mkOp3(OP_MAD
, TYPE_U32
, prmt
, getSrc(&insn
->src
[1]), loadImm(NULL
, 0x1111), loadImm(NULL
, 0x8880));
2740 mkOp3(OP_PERMT
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), prmt
, loadImm(NULL
, 0));
2743 case nir_op_extract_u16
: {
2745 LValues
&newDefs
= convert(&insn
->dest
);
2746 Value
*prmt
= getSSA();
2747 mkOp3(OP_MAD
, TYPE_U32
, prmt
, getSrc(&insn
->src
[1]), loadImm(NULL
, 0x22), loadImm(NULL
, 0x4410));
2748 mkOp3(OP_PERMT
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), prmt
, loadImm(NULL
, 0));
2751 case nir_op_extract_i16
: {
2753 LValues
&newDefs
= convert(&insn
->dest
);
2754 Value
*prmt
= getSSA();
2755 mkOp3(OP_MAD
, TYPE_U32
, prmt
, getSrc(&insn
->src
[1]), loadImm(NULL
, 0x2222), loadImm(NULL
, 0x9910));
2756 mkOp3(OP_PERMT
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), prmt
, loadImm(NULL
, 0));
2761 LValues
&newDefs
= convert(&insn
->dest
);
2762 mkOp3(OP_SHF
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]),
2763 getSrc(&insn
->src
[1]), getSrc(&insn
->src
[0]))
2764 ->subOp
= NV50_IR_SUBOP_SHF_L
|
2765 NV50_IR_SUBOP_SHF_W
|
2766 NV50_IR_SUBOP_SHF_HI
;
2771 LValues
&newDefs
= convert(&insn
->dest
);
2772 mkOp3(OP_SHF
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]),
2773 getSrc(&insn
->src
[1]), getSrc(&insn
->src
[0]))
2774 ->subOp
= NV50_IR_SUBOP_SHF_R
|
2775 NV50_IR_SUBOP_SHF_W
|
2776 NV50_IR_SUBOP_SHF_LO
;
2779 // boolean conversions
2780 case nir_op_b2f32
: {
2782 LValues
&newDefs
= convert(&insn
->dest
);
2783 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1.0f
));
2786 case nir_op_b2f64
: {
2788 LValues
&newDefs
= convert(&insn
->dest
);
2789 Value
*tmp
= getSSA(4);
2790 mkOp2(OP_AND
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]), loadImm(NULL
, 0x3ff00000));
2791 mkOp2(OP_MERGE
, TYPE_U64
, newDefs
[0], loadImm(NULL
, 0), tmp
);
2795 case nir_op_i2b32
: {
2797 LValues
&newDefs
= convert(&insn
->dest
);
2799 if (typeSizeof(sTypes
[0]) == 8) {
2800 src1
= loadImm(getSSA(8), 0.0);
2804 CondCode cc
= op
== nir_op_f2b32
? CC_NEU
: CC_NE
;
2805 mkCmp(OP_SET
, cc
, TYPE_U32
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[0]), src1
);
2808 case nir_op_b2i32
: {
2810 LValues
&newDefs
= convert(&insn
->dest
);
2811 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2814 case nir_op_b2i64
: {
2816 LValues
&newDefs
= convert(&insn
->dest
);
2817 LValue
*def
= getScratch();
2818 mkOp2(OP_AND
, TYPE_U32
, def
, getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2819 mkOp2(OP_MERGE
, TYPE_S64
, newDefs
[0], def
, loadImm(NULL
, 0));
2823 ERROR("unknown nir_op %s\n", info
.name
);
2828 oldPos
= this->bb
->getEntry();
2829 oldPos
->precise
= insn
->exact
;
2832 if (unlikely(!oldPos
))
2835 while (oldPos
->next
) {
2836 oldPos
= oldPos
->next
;
2837 oldPos
->precise
= insn
->exact
;
2839 oldPos
->saturate
= insn
->dest
.saturate
;
2843 #undef DEFAULT_CHECKS
2846 Converter::visit(nir_ssa_undef_instr
*insn
)
2848 LValues
&newDefs
= convert(&insn
->def
);
2849 for (uint8_t i
= 0u; i
< insn
->def
.num_components
; ++i
) {
2850 mkOp(OP_NOP
, TYPE_NONE
, newDefs
[i
]);
2855 #define CASE_SAMPLER(ty) \
2856 case GLSL_SAMPLER_DIM_ ## ty : \
2857 if (isArray && !isShadow) \
2858 return TEX_TARGET_ ## ty ## _ARRAY; \
2859 else if (!isArray && isShadow) \
2860 return TEX_TARGET_## ty ## _SHADOW; \
2861 else if (isArray && isShadow) \
2862 return TEX_TARGET_## ty ## _ARRAY_SHADOW; \
2864 return TEX_TARGET_ ## ty
2867 Converter::convert(glsl_sampler_dim dim
, bool isArray
, bool isShadow
)
2873 case GLSL_SAMPLER_DIM_3D
:
2874 return TEX_TARGET_3D
;
2875 case GLSL_SAMPLER_DIM_MS
:
2877 return TEX_TARGET_2D_MS_ARRAY
;
2878 return TEX_TARGET_2D_MS
;
2879 case GLSL_SAMPLER_DIM_RECT
:
2881 return TEX_TARGET_RECT_SHADOW
;
2882 return TEX_TARGET_RECT
;
2883 case GLSL_SAMPLER_DIM_BUF
:
2884 return TEX_TARGET_BUFFER
;
2885 case GLSL_SAMPLER_DIM_EXTERNAL
:
2886 return TEX_TARGET_2D
;
2888 ERROR("unknown glsl_sampler_dim %u\n", dim
);
2890 return TEX_TARGET_COUNT
;
2896 Converter::applyProjection(Value
*src
, Value
*proj
)
2900 return mkOp2v(OP_MUL
, TYPE_F32
, getScratch(), src
, proj
);
2904 Converter::getNIRArgCount(TexInstruction::Target
& target
)
2906 unsigned int result
= target
.getArgCount();
2907 if (target
.isCube() && target
.isArray())
2915 Converter::convert(enum gl_access_qualifier access
)
2918 case ACCESS_VOLATILE
:
2920 case ACCESS_COHERENT
:
2928 Converter::visit(nir_tex_instr
*insn
)
2932 case nir_texop_query_levels
:
2934 case nir_texop_texture_samples
:
2939 case nir_texop_txf_ms
:
2941 case nir_texop_txs
: {
2942 LValues
&newDefs
= convert(&insn
->dest
);
2943 std::vector
<Value
*> srcs
;
2944 std::vector
<Value
*> defs
;
2945 std::vector
<nir_src
*> offsets
;
2949 TexInstruction::Target target
= convert(insn
->sampler_dim
, insn
->is_array
, insn
->is_shadow
);
2950 operation op
= getOperation(insn
->op
);
2953 int biasIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_bias
);
2954 int compIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_comparator
);
2955 int coordsIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_coord
);
2956 int ddxIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddx
);
2957 int ddyIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddy
);
2958 int msIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ms_index
);
2959 int lodIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_lod
);
2960 int offsetIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_offset
);
2961 int projIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_projector
);
2962 int sampOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_sampler_offset
);
2963 int texOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_texture_offset
);
2964 int sampHandleIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_sampler_handle
);
2965 int texHandleIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_texture_handle
);
2967 bool bindless
= sampHandleIdx
!= -1 || texHandleIdx
!= -1;
2968 assert((sampHandleIdx
!= -1) == (texHandleIdx
!= -1));
2971 proj
= mkOp1v(OP_RCP
, TYPE_F32
, getScratch(), getSrc(&insn
->src
[projIdx
].src
, 0));
2973 srcs
.resize(insn
->coord_components
);
2974 for (uint8_t i
= 0u; i
< insn
->coord_components
; ++i
)
2975 srcs
[i
] = applyProjection(getSrc(&insn
->src
[coordsIdx
].src
, i
), proj
);
2977 // sometimes we get less args than target.getArgCount, but codegen expects the latter
2978 if (insn
->coord_components
) {
2979 uint32_t argCount
= target
.getArgCount();
2984 for (uint32_t i
= 0u; i
< (argCount
- insn
->coord_components
); ++i
)
2985 srcs
.push_back(getSSA());
2988 if (insn
->op
== nir_texop_texture_samples
)
2989 srcs
.push_back(zero
);
2990 else if (!insn
->num_srcs
)
2991 srcs
.push_back(loadImm(NULL
, 0));
2993 srcs
.push_back(getSrc(&insn
->src
[biasIdx
].src
, 0));
2995 srcs
.push_back(getSrc(&insn
->src
[lodIdx
].src
, 0));
2996 else if (op
== OP_TXF
)
2999 srcs
.push_back(getSrc(&insn
->src
[msIdx
].src
, 0));
3000 if (offsetIdx
!= -1)
3001 offsets
.push_back(&insn
->src
[offsetIdx
].src
);
3003 srcs
.push_back(applyProjection(getSrc(&insn
->src
[compIdx
].src
, 0), proj
));
3004 if (texOffIdx
!= -1) {
3005 srcs
.push_back(getSrc(&insn
->src
[texOffIdx
].src
, 0));
3006 texOffIdx
= srcs
.size() - 1;
3008 if (sampOffIdx
!= -1) {
3009 srcs
.push_back(getSrc(&insn
->src
[sampOffIdx
].src
, 0));
3010 sampOffIdx
= srcs
.size() - 1;
3013 // currently we use the lower bits
3015 Value
*handle
= getSrc(&insn
->src
[sampHandleIdx
].src
, 0);
3017 mkSplit(split
, 4, handle
);
3019 srcs
.push_back(split
[0]);
3020 texOffIdx
= srcs
.size() - 1;
3023 r
= bindless
? 0xff : insn
->texture_index
;
3024 s
= bindless
? 0x1f : insn
->sampler_index
;
3026 defs
.resize(newDefs
.size());
3027 for (uint8_t d
= 0u; d
< newDefs
.size(); ++d
) {
3028 defs
[d
] = newDefs
[d
];
3031 if (target
.isMS() || (op
== OP_TEX
&& prog
->getType() != Program::TYPE_FRAGMENT
))
3034 TexInstruction
*texi
= mkTex(op
, target
.getEnum(), r
, s
, defs
, srcs
);
3035 texi
->tex
.levelZero
= lz
;
3036 texi
->tex
.mask
= mask
;
3037 texi
->tex
.bindless
= bindless
;
3039 if (texOffIdx
!= -1)
3040 texi
->tex
.rIndirectSrc
= texOffIdx
;
3041 if (sampOffIdx
!= -1)
3042 texi
->tex
.sIndirectSrc
= sampOffIdx
;
3046 if (!target
.isShadow())
3047 texi
->tex
.gatherComp
= insn
->component
;
3050 texi
->tex
.query
= TXQ_DIMS
;
3052 case nir_texop_texture_samples
:
3053 texi
->tex
.mask
= 0x4;
3054 texi
->tex
.query
= TXQ_TYPE
;
3056 case nir_texop_query_levels
:
3057 texi
->tex
.mask
= 0x8;
3058 texi
->tex
.query
= TXQ_DIMS
;
3064 texi
->tex
.useOffsets
= offsets
.size();
3065 if (texi
->tex
.useOffsets
) {
3066 for (uint8_t s
= 0; s
< texi
->tex
.useOffsets
; ++s
) {
3067 for (uint32_t c
= 0u; c
< 3; ++c
) {
3068 uint8_t s2
= std::min(c
, target
.getDim() - 1);
3069 texi
->offset
[s
][c
].set(getSrc(offsets
[s
], s2
));
3070 texi
->offset
[s
][c
].setInsn(texi
);
3075 if (op
== OP_TXG
&& offsetIdx
== -1) {
3076 if (nir_tex_instr_has_explicit_tg4_offsets(insn
)) {
3077 texi
->tex
.useOffsets
= 4;
3078 setPosition(texi
, false);
3079 for (uint8_t i
= 0; i
< 4; ++i
) {
3080 for (uint8_t j
= 0; j
< 2; ++j
) {
3081 texi
->offset
[i
][j
].set(loadImm(NULL
, insn
->tg4_offsets
[i
][j
]));
3082 texi
->offset
[i
][j
].setInsn(texi
);
3085 setPosition(texi
, true);
3089 if (ddxIdx
!= -1 && ddyIdx
!= -1) {
3090 for (uint8_t c
= 0u; c
< target
.getDim() + target
.isCube(); ++c
) {
3091 texi
->dPdx
[c
].set(getSrc(&insn
->src
[ddxIdx
].src
, c
));
3092 texi
->dPdy
[c
].set(getSrc(&insn
->src
[ddyIdx
].src
, c
));
3099 ERROR("unknown nir_texop %u\n", insn
->op
);
3110 if (prog
->dbgFlags
& NV50_IR_DEBUG_VERBOSE
)
3111 nir_print_shader(nir
, stderr
);
3113 struct nir_lower_subgroups_options subgroup_options
= {
3114 .subgroup_size
= 32,
3115 .ballot_bit_size
= 32,
3118 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, type_size
, (nir_lower_io_options
)0);
3119 NIR_PASS_V(nir
, nir_lower_subgroups
, &subgroup_options
);
3120 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
);
3121 NIR_PASS_V(nir
, nir_lower_load_const_to_scalar
);
3122 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3123 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
3124 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
3126 /*TODO: improve this lowering/optimisation loop so that we can use
3127 * nir_opt_idiv_const effectively before this.
3129 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_precise
);
3133 NIR_PASS(progress
, nir
, nir_copy_prop
);
3134 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
3135 NIR_PASS(progress
, nir
, nir_opt_trivial_continues
);
3136 NIR_PASS(progress
, nir
, nir_opt_cse
);
3137 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
3138 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
3139 NIR_PASS(progress
, nir
, nir_copy_prop
);
3140 NIR_PASS(progress
, nir
, nir_opt_dce
);
3141 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
3144 NIR_PASS_V(nir
, nir_lower_bool_to_int32
);
3145 NIR_PASS_V(nir
, nir_lower_locals_to_regs
);
3146 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
, NULL
);
3147 NIR_PASS_V(nir
, nir_convert_from_ssa
, true);
3149 // Garbage collect dead instructions
3153 ERROR("Couldn't prase NIR!\n");
3157 if (!assignSlots()) {
3158 ERROR("Couldn't assign slots!\n");
3162 if (prog
->dbgFlags
& NV50_IR_DEBUG_BASIC
)
3163 nir_print_shader(nir
, stderr
);
3165 nir_foreach_function(function
, nir
) {
3166 if (!visit(function
))
3173 } // unnamed namespace
3178 Program::makeFromNIR(struct nv50_ir_prog_info
*info
)
3180 nir_shader
*nir
= (nir_shader
*)info
->bin
.source
;
3181 Converter
converter(this, nir
, info
);
3182 bool result
= converter
.run();
3185 LoweringHelper lowering
;
3187 tlsSize
= info
->bin
.tlsSpace
;
3191 } // namespace nv50_ir
3193 static nir_shader_compiler_options
3194 nvir_nir_shader_compiler_options(int chipset
)
3196 nir_shader_compiler_options op
= {};
3197 op
.lower_fdiv
= (chipset
>= NVISA_GV100_CHIPSET
);
3198 op
.lower_ffma
= false;
3199 op
.fuse_ffma
= false; /* nir doesn't track mad vs fma */
3200 op
.lower_flrp16
= (chipset
>= NVISA_GV100_CHIPSET
);
3201 op
.lower_flrp32
= true;
3202 op
.lower_flrp64
= true;
3203 op
.lower_fpow
= false; // TODO: nir's lowering is broken, or we could use it
3204 op
.lower_fsat
= false;
3205 op
.lower_fsqrt
= false; // TODO: only before gm200
3206 op
.lower_sincos
= false;
3207 op
.lower_fmod
= true;
3208 op
.lower_bitfield_extract
= false;
3209 op
.lower_bitfield_extract_to_shifts
= (chipset
>= NVISA_GV100_CHIPSET
);
3210 op
.lower_bitfield_insert
= false;
3211 op
.lower_bitfield_insert_to_shifts
= (chipset
>= NVISA_GV100_CHIPSET
);
3212 op
.lower_bitfield_insert_to_bitfield_select
= false;
3213 op
.lower_bitfield_reverse
= false;
3214 op
.lower_bit_count
= false;
3215 op
.lower_ifind_msb
= false;
3216 op
.lower_find_lsb
= false;
3217 op
.lower_uadd_carry
= true; // TODO
3218 op
.lower_usub_borrow
= true; // TODO
3219 op
.lower_mul_high
= false;
3220 op
.lower_negate
= false;
3221 op
.lower_sub
= true;
3222 op
.lower_scmp
= true; // TODO: not implemented yet
3223 op
.lower_vector_cmp
= false;
3224 op
.lower_idiv
= true;
3225 op
.lower_bitops
= false;
3226 op
.lower_isign
= (chipset
>= NVISA_GV100_CHIPSET
);
3227 op
.lower_fsign
= (chipset
>= NVISA_GV100_CHIPSET
);
3228 op
.lower_fdph
= false;
3229 op
.lower_fdot
= false;
3230 op
.fdot_replicates
= false; // TODO
3231 op
.lower_ffloor
= false; // TODO
3232 op
.lower_ffract
= true;
3233 op
.lower_fceil
= false; // TODO
3234 op
.lower_ftrunc
= false;
3235 op
.lower_ldexp
= true;
3236 op
.lower_pack_half_2x16
= true;
3237 op
.lower_pack_unorm_2x16
= true;
3238 op
.lower_pack_snorm_2x16
= true;
3239 op
.lower_pack_unorm_4x8
= true;
3240 op
.lower_pack_snorm_4x8
= true;
3241 op
.lower_unpack_half_2x16
= true;
3242 op
.lower_unpack_unorm_2x16
= true;
3243 op
.lower_unpack_snorm_2x16
= true;
3244 op
.lower_unpack_unorm_4x8
= true;
3245 op
.lower_unpack_snorm_4x8
= true;
3246 op
.lower_pack_split
= false;
3247 op
.lower_extract_byte
= (chipset
< NVISA_GM107_CHIPSET
);
3248 op
.lower_extract_word
= (chipset
< NVISA_GM107_CHIPSET
);
3249 op
.lower_all_io_to_temps
= false;
3250 op
.lower_all_io_to_elements
= false;
3251 op
.vertex_id_zero_based
= false;
3252 op
.lower_base_vertex
= false;
3253 op
.lower_helper_invocation
= false;
3254 op
.optimize_sample_mask_in
= false;
3255 op
.lower_cs_local_index_from_id
= true;
3256 op
.lower_cs_local_id_from_index
= false;
3257 op
.lower_device_index_to_zero
= false; // TODO
3258 op
.lower_wpos_pntc
= false; // TODO
3259 op
.lower_hadd
= true; // TODO
3260 op
.lower_add_sat
= true; // TODO
3261 op
.vectorize_io
= false;
3262 op
.lower_to_scalar
= true;
3263 op
.unify_interfaces
= false;
3264 op
.use_interpolated_input_intrinsics
= true;
3265 op
.lower_mul_2x32_64
= true; // TODO
3266 op
.lower_rotate
= (chipset
< NVISA_GV100_CHIPSET
);
3267 op
.has_imul24
= false;
3268 op
.intel_vec4
= false;
3269 op
.max_unroll_iterations
= 32;
3270 op
.lower_int64_options
= (nir_lower_int64_options
) (
3271 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_imul64
: 0) |
3272 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_isign64
: 0) |
3273 nir_lower_divmod64
|
3274 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_imul_high64
: 0) |
3275 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_mov64
: 0) |
3276 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_icmp64
: 0) |
3277 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_iabs64
: 0) |
3278 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_ineg64
: 0) |
3279 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_logic64
: 0) |
3280 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_minmax64
: 0) |
3281 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_shift64
: 0) |
3282 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_imul_2x32_64
: 0) |
3283 ((chipset
>= NVISA_GM107_CHIPSET
) ? nir_lower_extract64
: 0) |
3284 nir_lower_ufind_msb64
3286 op
.lower_doubles_options
= (nir_lower_doubles_options
) (
3287 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_drcp
: 0) |
3288 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_dsqrt
: 0) |
3289 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_drsq
: 0) |
3290 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_dfract
: 0) |
3292 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_dsub
: 0) |
3293 ((chipset
>= NVISA_GV100_CHIPSET
) ? nir_lower_ddiv
: 0)
3298 static const nir_shader_compiler_options gf100_nir_shader_compiler_options
=
3299 nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET
);
3300 static const nir_shader_compiler_options gm107_nir_shader_compiler_options
=
3301 nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET
);
3302 static const nir_shader_compiler_options gv100_nir_shader_compiler_options
=
3303 nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET
);
3305 const nir_shader_compiler_options
*
3306 nv50_ir_nir_shader_compiler_options(int chipset
)
3308 if (chipset
>= NVISA_GV100_CHIPSET
)
3309 return &gv100_nir_shader_compiler_options
;
3310 if (chipset
>= NVISA_GM107_CHIPSET
)
3311 return &gm107_nir_shader_compiler_options
;
3312 return &gf100_nir_shader_compiler_options
;