2 * Copyright 2017 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Karol Herbst <kherbst@redhat.com>
25 #include "compiler/nir/nir.h"
27 #include "util/u_debug.h"
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_from_common.h"
31 #include "codegen/nv50_ir_lowering_helper.h"
32 #include "codegen/nv50_ir_util.h"
34 #if __cplusplus >= 201103L
35 #include <unordered_map>
37 #include <tr1/unordered_map>
43 #if __cplusplus >= 201103L
45 using std::unordered_map
;
48 using std::tr1::unordered_map
;
51 using namespace nv50_ir
;
54 type_size(const struct glsl_type
*type
)
56 return glsl_count_attribute_slots(type
, false);
59 class Converter
: public ConverterCommon
62 Converter(Program
*, nir_shader
*, nv50_ir_prog_info
*);
66 typedef std::vector
<LValue
*> LValues
;
67 typedef unordered_map
<unsigned, LValues
> NirDefMap
;
68 typedef unordered_map
<unsigned, BasicBlock
*> NirBlockMap
;
70 TexTarget
convert(glsl_sampler_dim
, bool isArray
, bool isShadow
);
71 LValues
& convert(nir_alu_dest
*);
72 BasicBlock
* convert(nir_block
*);
73 LValues
& convert(nir_dest
*);
74 SVSemantic
convert(nir_intrinsic_op
);
75 LValues
& convert(nir_register
*);
76 LValues
& convert(nir_ssa_def
*);
78 Value
* getSrc(nir_alu_src
*, uint8_t component
= 0);
79 Value
* getSrc(nir_register
*, uint8_t);
80 Value
* getSrc(nir_src
*, uint8_t, bool indirect
= false);
81 Value
* getSrc(nir_ssa_def
*, uint8_t);
83 // returned value is the constant part of the given source (either the
84 // nir_src or the selected source component of an intrinsic). Even though
85 // this is mostly an optimization to be able to skip indirects in a few
86 // cases, sometimes we require immediate values or set some fileds on
87 // instructions (e.g. tex) in order for codegen to consume those.
88 // If the found value has not a constant part, the Value gets returned
89 // through the Value parameter.
90 uint32_t getIndirect(nir_src
*, uint8_t, Value
*&);
91 uint32_t getIndirect(nir_intrinsic_instr
*, uint8_t s
, uint8_t c
, Value
*&);
93 uint32_t getSlotAddress(nir_intrinsic_instr
*, uint8_t idx
, uint8_t slot
);
95 void setInterpolate(nv50_ir_varying
*,
100 Instruction
*loadFrom(DataFile
, uint8_t, DataType
, Value
*def
, uint32_t base
,
101 uint8_t c
, Value
*indirect0
= NULL
,
102 Value
*indirect1
= NULL
, bool patch
= false);
103 void storeTo(nir_intrinsic_instr
*, DataFile
, operation
, DataType
,
104 Value
*src
, uint8_t idx
, uint8_t c
, Value
*indirect0
= NULL
,
105 Value
*indirect1
= NULL
);
107 bool isFloatType(nir_alu_type
);
108 bool isSignedType(nir_alu_type
);
109 bool isResultFloat(nir_op
);
110 bool isResultSigned(nir_op
);
112 DataType
getDType(nir_alu_instr
*);
113 DataType
getDType(nir_intrinsic_instr
*);
114 DataType
getDType(nir_op
, uint8_t);
116 std::vector
<DataType
> getSTypes(nir_alu_instr
*);
117 DataType
getSType(nir_src
&, bool isFloat
, bool isSigned
);
119 operation
getOperation(nir_intrinsic_op
);
120 operation
getOperation(nir_op
);
121 operation
getOperation(nir_texop
);
122 operation
preOperationNeeded(nir_op
);
124 int getSubOp(nir_intrinsic_op
);
125 int getSubOp(nir_op
);
127 CondCode
getCondCode(nir_op
);
132 bool visit(nir_alu_instr
*);
133 bool visit(nir_block
*);
134 bool visit(nir_cf_node
*);
135 bool visit(nir_function
*);
136 bool visit(nir_if
*);
137 bool visit(nir_instr
*);
138 bool visit(nir_intrinsic_instr
*);
139 bool visit(nir_jump_instr
*);
140 bool visit(nir_load_const_instr
*);
141 bool visit(nir_loop
*);
142 bool visit(nir_ssa_undef_instr
*);
143 bool visit(nir_tex_instr
*);
146 Value
* applyProjection(Value
*src
, Value
*proj
);
153 unsigned int curLoopDepth
;
158 int clipVertexOutput
;
167 Converter::Converter(Program
*prog
, nir_shader
*nir
, nv50_ir_prog_info
*info
)
168 : ConverterCommon(prog
, info
),
173 zero
= mkImm((uint32_t)0);
177 Converter::convert(nir_block
*block
)
179 NirBlockMap::iterator it
= blocks
.find(block
->index
);
180 if (it
!= blocks
.end())
183 BasicBlock
*bb
= new BasicBlock(func
);
184 blocks
[block
->index
] = bb
;
189 Converter::isFloatType(nir_alu_type type
)
191 return nir_alu_type_get_base_type(type
) == nir_type_float
;
195 Converter::isSignedType(nir_alu_type type
)
197 return nir_alu_type_get_base_type(type
) == nir_type_int
;
201 Converter::isResultFloat(nir_op op
)
203 const nir_op_info
&info
= nir_op_infos
[op
];
204 if (info
.output_type
!= nir_type_invalid
)
205 return isFloatType(info
.output_type
);
207 ERROR("isResultFloat not implemented for %s\n", nir_op_infos
[op
].name
);
213 Converter::isResultSigned(nir_op op
)
216 // there is no umul and we get wrong results if we treat all muls as signed
221 const nir_op_info
&info
= nir_op_infos
[op
];
222 if (info
.output_type
!= nir_type_invalid
)
223 return isSignedType(info
.output_type
);
224 ERROR("isResultSigned not implemented for %s\n", nir_op_infos
[op
].name
);
231 Converter::getDType(nir_alu_instr
*insn
)
233 if (insn
->dest
.dest
.is_ssa
)
234 return getDType(insn
->op
, insn
->dest
.dest
.ssa
.bit_size
);
236 return getDType(insn
->op
, insn
->dest
.dest
.reg
.reg
->bit_size
);
240 Converter::getDType(nir_intrinsic_instr
*insn
)
242 if (insn
->dest
.is_ssa
)
243 return typeOfSize(insn
->dest
.ssa
.bit_size
/ 8, false, false);
245 return typeOfSize(insn
->dest
.reg
.reg
->bit_size
/ 8, false, false);
249 Converter::getDType(nir_op op
, uint8_t bitSize
)
251 DataType ty
= typeOfSize(bitSize
/ 8, isResultFloat(op
), isResultSigned(op
));
252 if (ty
== TYPE_NONE
) {
253 ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos
[op
].name
, bitSize
);
259 std::vector
<DataType
>
260 Converter::getSTypes(nir_alu_instr
*insn
)
262 const nir_op_info
&info
= nir_op_infos
[insn
->op
];
263 std::vector
<DataType
> res(info
.num_inputs
);
265 for (uint8_t i
= 0; i
< info
.num_inputs
; ++i
) {
266 if (info
.input_types
[i
] != nir_type_invalid
) {
267 res
[i
] = getSType(insn
->src
[i
].src
, isFloatType(info
.input_types
[i
]), isSignedType(info
.input_types
[i
]));
269 ERROR("getSType not implemented for %s idx %u\n", info
.name
, i
);
280 Converter::getSType(nir_src
&src
, bool isFloat
, bool isSigned
)
284 bitSize
= src
.ssa
->bit_size
;
286 bitSize
= src
.reg
.reg
->bit_size
;
288 DataType ty
= typeOfSize(bitSize
/ 8, isFloat
, isSigned
);
289 if (ty
== TYPE_NONE
) {
297 ERROR("couldn't get Type for %s with bitSize %u\n", str
, bitSize
);
304 Converter::getOperation(nir_op op
)
307 // basic ops with float and int variants
317 case nir_op_ifind_msb
:
318 case nir_op_ufind_msb
:
340 case nir_op_fddx_coarse
:
341 case nir_op_fddx_fine
:
344 case nir_op_fddy_coarse
:
345 case nir_op_fddy_fine
:
363 case nir_op_pack_64_2x32_split
:
377 case nir_op_imul_high
:
378 case nir_op_umul_high
:
426 ERROR("couldn't get operation for op %s\n", nir_op_infos
[op
].name
);
433 Converter::getOperation(nir_texop op
)
445 case nir_texop_txf_ms
:
451 case nir_texop_query_levels
:
452 case nir_texop_texture_samples
:
456 ERROR("couldn't get operation for nir_texop %u\n", op
);
463 Converter::getOperation(nir_intrinsic_op op
)
467 ERROR("couldn't get operation for nir_intrinsic_op %u\n", op
);
474 Converter::preOperationNeeded(nir_op op
)
486 Converter::getSubOp(nir_op op
)
489 case nir_op_imul_high
:
490 case nir_op_umul_high
:
491 return NV50_IR_SUBOP_MUL_HIGH
;
498 Converter::getSubOp(nir_intrinsic_op op
)
507 Converter::getCondCode(nir_op op
)
526 ERROR("couldn't get CondCode for op %s\n", nir_op_infos
[op
].name
);
533 Converter::convert(nir_alu_dest
*dest
)
535 return convert(&dest
->dest
);
539 Converter::convert(nir_dest
*dest
)
542 return convert(&dest
->ssa
);
543 if (dest
->reg
.indirect
) {
544 ERROR("no support for indirects.");
547 return convert(dest
->reg
.reg
);
551 Converter::convert(nir_register
*reg
)
553 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
554 if (it
!= regDefs
.end())
557 LValues
newDef(reg
->num_components
);
558 for (uint8_t i
= 0; i
< reg
->num_components
; i
++)
559 newDef
[i
] = getScratch(std::max(4, reg
->bit_size
/ 8));
560 return regDefs
[reg
->index
] = newDef
;
564 Converter::convert(nir_ssa_def
*def
)
566 NirDefMap::iterator it
= ssaDefs
.find(def
->index
);
567 if (it
!= ssaDefs
.end())
570 LValues
newDef(def
->num_components
);
571 for (uint8_t i
= 0; i
< def
->num_components
; i
++)
572 newDef
[i
] = getSSA(std::max(4, def
->bit_size
/ 8));
573 return ssaDefs
[def
->index
] = newDef
;
577 Converter::getSrc(nir_alu_src
*src
, uint8_t component
)
579 if (src
->abs
|| src
->negate
) {
580 ERROR("modifiers currently not supported on nir_alu_src\n");
583 return getSrc(&src
->src
, src
->swizzle
[component
]);
587 Converter::getSrc(nir_register
*reg
, uint8_t idx
)
589 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
590 if (it
== regDefs
.end())
591 return convert(reg
)[idx
];
592 return it
->second
[idx
];
596 Converter::getSrc(nir_src
*src
, uint8_t idx
, bool indirect
)
599 return getSrc(src
->ssa
, idx
);
601 if (src
->reg
.indirect
) {
603 return getSrc(src
->reg
.indirect
, idx
);
604 ERROR("no support for indirects.");
609 return getSrc(src
->reg
.reg
, idx
);
613 Converter::getSrc(nir_ssa_def
*src
, uint8_t idx
)
615 NirDefMap::iterator it
= ssaDefs
.find(src
->index
);
616 if (it
== ssaDefs
.end()) {
617 ERROR("SSA value %u not found\n", src
->index
);
621 return it
->second
[idx
];
625 Converter::getIndirect(nir_src
*src
, uint8_t idx
, Value
*&indirect
)
627 nir_const_value
*offset
= nir_src_as_const_value(*src
);
631 return offset
->u32
[0];
634 indirect
= getSrc(src
, idx
, true);
639 Converter::getIndirect(nir_intrinsic_instr
*insn
, uint8_t s
, uint8_t c
, Value
*&indirect
)
641 int32_t idx
= nir_intrinsic_base(insn
) + getIndirect(&insn
->src
[s
], c
, indirect
);
643 indirect
= mkOp2v(OP_SHL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), indirect
, loadImm(NULL
, 4));
648 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot
, unsigned *name
, unsigned *index
)
650 assert(name
&& index
);
652 if (slot
>= VERT_ATTRIB_MAX
) {
653 ERROR("invalid varying slot %u\n", slot
);
658 if (slot
>= VERT_ATTRIB_GENERIC0
&&
659 slot
< VERT_ATTRIB_GENERIC0
+ VERT_ATTRIB_GENERIC_MAX
) {
660 *name
= TGSI_SEMANTIC_GENERIC
;
661 *index
= slot
- VERT_ATTRIB_GENERIC0
;
665 if (slot
>= VERT_ATTRIB_TEX0
&&
666 slot
< VERT_ATTRIB_TEX0
+ VERT_ATTRIB_TEX_MAX
) {
667 *name
= TGSI_SEMANTIC_TEXCOORD
;
668 *index
= slot
- VERT_ATTRIB_TEX0
;
673 case VERT_ATTRIB_COLOR0
:
674 *name
= TGSI_SEMANTIC_COLOR
;
677 case VERT_ATTRIB_COLOR1
:
678 *name
= TGSI_SEMANTIC_COLOR
;
681 case VERT_ATTRIB_EDGEFLAG
:
682 *name
= TGSI_SEMANTIC_EDGEFLAG
;
685 case VERT_ATTRIB_FOG
:
686 *name
= TGSI_SEMANTIC_FOG
;
689 case VERT_ATTRIB_NORMAL
:
690 *name
= TGSI_SEMANTIC_NORMAL
;
693 case VERT_ATTRIB_POS
:
694 *name
= TGSI_SEMANTIC_POSITION
;
697 case VERT_ATTRIB_POINT_SIZE
:
698 *name
= TGSI_SEMANTIC_PSIZE
;
702 ERROR("unknown vert attrib slot %u\n", slot
);
709 varying_slot_to_tgsi_semantic(gl_varying_slot slot
, unsigned *name
, unsigned *index
)
711 assert(name
&& index
);
713 if (slot
>= VARYING_SLOT_TESS_MAX
) {
714 ERROR("invalid varying slot %u\n", slot
);
719 if (slot
>= VARYING_SLOT_PATCH0
) {
720 *name
= TGSI_SEMANTIC_PATCH
;
721 *index
= slot
- VARYING_SLOT_PATCH0
;
725 if (slot
>= VARYING_SLOT_VAR0
) {
726 *name
= TGSI_SEMANTIC_GENERIC
;
727 *index
= slot
- VARYING_SLOT_VAR0
;
731 if (slot
>= VARYING_SLOT_TEX0
&& slot
<= VARYING_SLOT_TEX7
) {
732 *name
= TGSI_SEMANTIC_TEXCOORD
;
733 *index
= slot
- VARYING_SLOT_TEX0
;
738 case VARYING_SLOT_BFC0
:
739 *name
= TGSI_SEMANTIC_BCOLOR
;
742 case VARYING_SLOT_BFC1
:
743 *name
= TGSI_SEMANTIC_BCOLOR
;
746 case VARYING_SLOT_CLIP_DIST0
:
747 *name
= TGSI_SEMANTIC_CLIPDIST
;
750 case VARYING_SLOT_CLIP_DIST1
:
751 *name
= TGSI_SEMANTIC_CLIPDIST
;
754 case VARYING_SLOT_CLIP_VERTEX
:
755 *name
= TGSI_SEMANTIC_CLIPVERTEX
;
758 case VARYING_SLOT_COL0
:
759 *name
= TGSI_SEMANTIC_COLOR
;
762 case VARYING_SLOT_COL1
:
763 *name
= TGSI_SEMANTIC_COLOR
;
766 case VARYING_SLOT_EDGE
:
767 *name
= TGSI_SEMANTIC_EDGEFLAG
;
770 case VARYING_SLOT_FACE
:
771 *name
= TGSI_SEMANTIC_FACE
;
774 case VARYING_SLOT_FOGC
:
775 *name
= TGSI_SEMANTIC_FOG
;
778 case VARYING_SLOT_LAYER
:
779 *name
= TGSI_SEMANTIC_LAYER
;
782 case VARYING_SLOT_PNTC
:
783 *name
= TGSI_SEMANTIC_PCOORD
;
786 case VARYING_SLOT_POS
:
787 *name
= TGSI_SEMANTIC_POSITION
;
790 case VARYING_SLOT_PRIMITIVE_ID
:
791 *name
= TGSI_SEMANTIC_PRIMID
;
794 case VARYING_SLOT_PSIZ
:
795 *name
= TGSI_SEMANTIC_PSIZE
;
798 case VARYING_SLOT_TESS_LEVEL_INNER
:
799 *name
= TGSI_SEMANTIC_TESSINNER
;
802 case VARYING_SLOT_TESS_LEVEL_OUTER
:
803 *name
= TGSI_SEMANTIC_TESSOUTER
;
806 case VARYING_SLOT_VIEWPORT
:
807 *name
= TGSI_SEMANTIC_VIEWPORT_INDEX
;
811 ERROR("unknown varying slot %u\n", slot
);
818 frag_result_to_tgsi_semantic(unsigned slot
, unsigned *name
, unsigned *index
)
820 if (slot
>= FRAG_RESULT_DATA0
) {
821 *name
= TGSI_SEMANTIC_COLOR
;
822 *index
= slot
- FRAG_RESULT_COLOR
- 2; // intentional
827 case FRAG_RESULT_COLOR
:
828 *name
= TGSI_SEMANTIC_COLOR
;
831 case FRAG_RESULT_DEPTH
:
832 *name
= TGSI_SEMANTIC_POSITION
;
835 case FRAG_RESULT_SAMPLE_MASK
:
836 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
840 ERROR("unknown frag result slot %u\n", slot
);
846 // copy of _mesa_sysval_to_semantic
848 system_val_to_tgsi_semantic(unsigned val
, unsigned *name
, unsigned *index
)
853 case SYSTEM_VALUE_VERTEX_ID
:
854 *name
= TGSI_SEMANTIC_VERTEXID
;
856 case SYSTEM_VALUE_INSTANCE_ID
:
857 *name
= TGSI_SEMANTIC_INSTANCEID
;
859 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
860 *name
= TGSI_SEMANTIC_VERTEXID_NOBASE
;
862 case SYSTEM_VALUE_BASE_VERTEX
:
863 *name
= TGSI_SEMANTIC_BASEVERTEX
;
865 case SYSTEM_VALUE_BASE_INSTANCE
:
866 *name
= TGSI_SEMANTIC_BASEINSTANCE
;
868 case SYSTEM_VALUE_DRAW_ID
:
869 *name
= TGSI_SEMANTIC_DRAWID
;
873 case SYSTEM_VALUE_INVOCATION_ID
:
874 *name
= TGSI_SEMANTIC_INVOCATIONID
;
878 case SYSTEM_VALUE_FRAG_COORD
:
879 *name
= TGSI_SEMANTIC_POSITION
;
881 case SYSTEM_VALUE_FRONT_FACE
:
882 *name
= TGSI_SEMANTIC_FACE
;
884 case SYSTEM_VALUE_SAMPLE_ID
:
885 *name
= TGSI_SEMANTIC_SAMPLEID
;
887 case SYSTEM_VALUE_SAMPLE_POS
:
888 *name
= TGSI_SEMANTIC_SAMPLEPOS
;
890 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
891 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
893 case SYSTEM_VALUE_HELPER_INVOCATION
:
894 *name
= TGSI_SEMANTIC_HELPER_INVOCATION
;
897 // Tessellation shader
898 case SYSTEM_VALUE_TESS_COORD
:
899 *name
= TGSI_SEMANTIC_TESSCOORD
;
901 case SYSTEM_VALUE_VERTICES_IN
:
902 *name
= TGSI_SEMANTIC_VERTICESIN
;
904 case SYSTEM_VALUE_PRIMITIVE_ID
:
905 *name
= TGSI_SEMANTIC_PRIMID
;
907 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
908 *name
= TGSI_SEMANTIC_TESSOUTER
;
910 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
911 *name
= TGSI_SEMANTIC_TESSINNER
;
915 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
916 *name
= TGSI_SEMANTIC_THREAD_ID
;
918 case SYSTEM_VALUE_WORK_GROUP_ID
:
919 *name
= TGSI_SEMANTIC_BLOCK_ID
;
921 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
922 *name
= TGSI_SEMANTIC_GRID_SIZE
;
924 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
925 *name
= TGSI_SEMANTIC_BLOCK_SIZE
;
929 case SYSTEM_VALUE_SUBGROUP_SIZE
:
930 *name
= TGSI_SEMANTIC_SUBGROUP_SIZE
;
932 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
933 *name
= TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
935 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
936 *name
= TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
938 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
939 *name
= TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
941 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
942 *name
= TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
944 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
945 *name
= TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
947 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
948 *name
= TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
952 ERROR("unknown system value %u\n", val
);
959 Converter::setInterpolate(nv50_ir_varying
*var
,
965 case INTERP_MODE_FLAT
:
968 case INTERP_MODE_NONE
:
969 if (semantic
== TGSI_SEMANTIC_COLOR
)
971 else if (semantic
== TGSI_SEMANTIC_POSITION
)
974 case INTERP_MODE_NOPERSPECTIVE
:
977 case INTERP_MODE_SMOOTH
:
980 var
->centroid
= centroid
;
984 calcSlots(const glsl_type
*type
, Program::Type stage
, const shader_info
&info
,
985 bool input
, const nir_variable
*var
)
987 if (!type
->is_array())
988 return type
->count_attribute_slots(false);
992 case Program::TYPE_GEOMETRY
:
993 slots
= type
->uniform_locations();
995 slots
/= info
.gs
.vertices_in
;
997 case Program::TYPE_TESSELLATION_CONTROL
:
998 case Program::TYPE_TESSELLATION_EVAL
:
999 // remove first dimension
1000 if (var
->data
.patch
|| (!input
&& stage
== Program::TYPE_TESSELLATION_EVAL
))
1001 slots
= type
->uniform_locations();
1003 slots
= type
->fields
.array
->uniform_locations();
1006 slots
= type
->count_attribute_slots(false);
1013 bool Converter::assignSlots() {
1017 info
->io
.viewportId
= -1;
1018 info
->numInputs
= 0;
1020 // we have to fixup the uniform locations for arrays
1021 unsigned numImages
= 0;
1022 nir_foreach_variable(var
, &nir
->uniforms
) {
1023 const glsl_type
*type
= var
->type
;
1024 if (!type
->without_array()->is_image())
1026 var
->data
.driver_location
= numImages
;
1027 numImages
+= type
->is_array() ? type
->arrays_of_arrays_size() : 1;
1030 nir_foreach_variable(var
, &nir
->inputs
) {
1031 const glsl_type
*type
= var
->type
;
1032 int slot
= var
->data
.location
;
1033 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, true, var
);
1034 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
1035 : type
->component_slots();
1036 uint32_t frac
= var
->data
.location_frac
;
1037 uint32_t vary
= var
->data
.driver_location
;
1039 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
1044 assert(vary
+ slots
<= PIPE_MAX_SHADER_INPUTS
);
1046 switch(prog
->getType()) {
1047 case Program::TYPE_FRAGMENT
:
1048 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1049 for (uint16_t i
= 0; i
< slots
; ++i
) {
1050 setInterpolate(&info
->in
[vary
+ i
], var
->data
.interpolation
,
1051 var
->data
.centroid
| var
->data
.sample
, name
);
1054 case Program::TYPE_GEOMETRY
:
1055 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1057 case Program::TYPE_TESSELLATION_CONTROL
:
1058 case Program::TYPE_TESSELLATION_EVAL
:
1059 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1060 if (var
->data
.patch
&& name
== TGSI_SEMANTIC_PATCH
)
1061 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
1063 case Program::TYPE_VERTEX
:
1064 vert_attrib_to_tgsi_semantic((gl_vert_attrib
)slot
, &name
, &index
);
1066 case TGSI_SEMANTIC_EDGEFLAG
:
1067 info
->io
.edgeFlagIn
= vary
;
1074 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1078 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1079 info
->in
[vary
].id
= vary
;
1080 info
->in
[vary
].patch
= var
->data
.patch
;
1081 info
->in
[vary
].sn
= name
;
1082 info
->in
[vary
].si
= index
+ i
;
1083 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1085 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1087 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1089 info
->in
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1091 info
->numInputs
= std::max
<uint8_t>(info
->numInputs
, vary
);
1094 info
->numOutputs
= 0;
1095 nir_foreach_variable(var
, &nir
->outputs
) {
1096 const glsl_type
*type
= var
->type
;
1097 int slot
= var
->data
.location
;
1098 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, false, var
);
1099 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
1100 : type
->component_slots();
1101 uint32_t frac
= var
->data
.location_frac
;
1102 uint32_t vary
= var
->data
.driver_location
;
1104 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
1109 assert(vary
< PIPE_MAX_SHADER_OUTPUTS
);
1111 switch(prog
->getType()) {
1112 case Program::TYPE_FRAGMENT
:
1113 frag_result_to_tgsi_semantic((gl_frag_result
)slot
, &name
, &index
);
1115 case TGSI_SEMANTIC_COLOR
:
1116 if (!var
->data
.fb_fetch_output
)
1117 info
->prop
.fp
.numColourResults
++;
1118 info
->prop
.fp
.separateFragData
= true;
1119 // sometimes we get FRAG_RESULT_DATAX with data.index 0
1120 // sometimes we get FRAG_RESULT_DATA0 with data.index X
1121 index
= index
== 0 ? var
->data
.index
: index
;
1123 case TGSI_SEMANTIC_POSITION
:
1124 info
->io
.fragDepth
= vary
;
1125 info
->prop
.fp
.writesDepth
= true;
1127 case TGSI_SEMANTIC_SAMPLEMASK
:
1128 info
->io
.sampleMask
= vary
;
1134 case Program::TYPE_GEOMETRY
:
1135 case Program::TYPE_TESSELLATION_CONTROL
:
1136 case Program::TYPE_TESSELLATION_EVAL
:
1137 case Program::TYPE_VERTEX
:
1138 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1140 if (var
->data
.patch
&& name
!= TGSI_SEMANTIC_TESSINNER
&&
1141 name
!= TGSI_SEMANTIC_TESSOUTER
)
1142 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
1145 case TGSI_SEMANTIC_CLIPDIST
:
1146 info
->io
.genUserClip
= -1;
1148 case TGSI_SEMANTIC_CLIPVERTEX
:
1149 clipVertexOutput
= vary
;
1151 case TGSI_SEMANTIC_EDGEFLAG
:
1152 info
->io
.edgeFlagOut
= vary
;
1154 case TGSI_SEMANTIC_POSITION
:
1155 if (clipVertexOutput
< 0)
1156 clipVertexOutput
= vary
;
1163 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1167 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1168 info
->out
[vary
].id
= vary
;
1169 info
->out
[vary
].patch
= var
->data
.patch
;
1170 info
->out
[vary
].sn
= name
;
1171 info
->out
[vary
].si
= index
+ i
;
1172 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1174 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1176 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1178 info
->out
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1180 if (nir
->info
.outputs_read
& 1ll << slot
)
1181 info
->out
[vary
].oread
= 1;
1183 info
->numOutputs
= std::max
<uint8_t>(info
->numOutputs
, vary
);
1186 info
->numSysVals
= 0;
1187 for (uint8_t i
= 0; i
< 64; ++i
) {
1188 if (!(nir
->info
.system_values_read
& 1ll << i
))
1191 system_val_to_tgsi_semantic(i
, &name
, &index
);
1192 info
->sv
[info
->numSysVals
].sn
= name
;
1193 info
->sv
[info
->numSysVals
].si
= index
;
1194 info
->sv
[info
->numSysVals
].input
= 0; // TODO inferSysValDirection(sn);
1197 case SYSTEM_VALUE_INSTANCE_ID
:
1198 info
->io
.instanceId
= info
->numSysVals
;
1200 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
1201 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
1202 info
->sv
[info
->numSysVals
].patch
= 1;
1204 case SYSTEM_VALUE_VERTEX_ID
:
1205 info
->io
.vertexId
= info
->numSysVals
;
1211 info
->numSysVals
+= 1;
1214 if (info
->io
.genUserClip
> 0) {
1215 info
->io
.clipDistances
= info
->io
.genUserClip
;
1217 const unsigned int nOut
= (info
->io
.genUserClip
+ 3) / 4;
1219 for (unsigned int n
= 0; n
< nOut
; ++n
) {
1220 unsigned int i
= info
->numOutputs
++;
1221 info
->out
[i
].id
= i
;
1222 info
->out
[i
].sn
= TGSI_SEMANTIC_CLIPDIST
;
1223 info
->out
[i
].si
= n
;
1224 info
->out
[i
].mask
= ((1 << info
->io
.clipDistances
) - 1) >> (n
* 4);
1228 return info
->assignSlots(info
) == 0;
1232 Converter::getSlotAddress(nir_intrinsic_instr
*insn
, uint8_t idx
, uint8_t slot
)
1235 int offset
= nir_intrinsic_component(insn
);
1238 if (nir_intrinsic_infos
[insn
->intrinsic
].has_dest
)
1239 ty
= getDType(insn
);
1241 ty
= getSType(insn
->src
[0], false, false);
1243 switch (insn
->intrinsic
) {
1244 case nir_intrinsic_load_input
:
1245 case nir_intrinsic_load_interpolated_input
:
1246 case nir_intrinsic_load_per_vertex_input
:
1249 case nir_intrinsic_load_output
:
1250 case nir_intrinsic_load_per_vertex_output
:
1251 case nir_intrinsic_store_output
:
1252 case nir_intrinsic_store_per_vertex_output
:
1256 ERROR("unknown intrinsic in getSlotAddress %s",
1257 nir_intrinsic_infos
[insn
->intrinsic
].name
);
1263 if (typeSizeof(ty
) == 8) {
1275 assert(!input
|| idx
< PIPE_MAX_SHADER_INPUTS
);
1276 assert(input
|| idx
< PIPE_MAX_SHADER_OUTPUTS
);
1278 const nv50_ir_varying
*vary
= input
? info
->in
: info
->out
;
1279 return vary
[idx
].slot
[slot
] * 4;
1283 Converter::loadFrom(DataFile file
, uint8_t i
, DataType ty
, Value
*def
,
1284 uint32_t base
, uint8_t c
, Value
*indirect0
,
1285 Value
*indirect1
, bool patch
)
1287 unsigned int tySize
= typeSizeof(ty
);
1290 (file
== FILE_MEMORY_CONST
|| file
== FILE_MEMORY_BUFFER
|| indirect0
)) {
1291 Value
*lo
= getSSA();
1292 Value
*hi
= getSSA();
1295 mkLoad(TYPE_U32
, lo
,
1296 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
),
1298 loi
->setIndirect(0, 1, indirect1
);
1299 loi
->perPatch
= patch
;
1302 mkLoad(TYPE_U32
, hi
,
1303 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
+ 4),
1305 hii
->setIndirect(0, 1, indirect1
);
1306 hii
->perPatch
= patch
;
1308 return mkOp2(OP_MERGE
, ty
, def
, lo
, hi
);
1311 mkLoad(ty
, def
, mkSymbol(file
, i
, ty
, base
+ c
* tySize
), indirect0
);
1312 ld
->setIndirect(0, 1, indirect1
);
1313 ld
->perPatch
= patch
;
1319 Converter::storeTo(nir_intrinsic_instr
*insn
, DataFile file
, operation op
,
1320 DataType ty
, Value
*src
, uint8_t idx
, uint8_t c
,
1321 Value
*indirect0
, Value
*indirect1
)
1323 uint8_t size
= typeSizeof(ty
);
1324 uint32_t address
= getSlotAddress(insn
, idx
, c
);
1326 if (size
== 8 && indirect0
) {
1328 mkSplit(split
, 4, src
);
1330 if (op
== OP_EXPORT
) {
1331 split
[0] = mkMov(getSSA(), split
[0], ty
)->getDef(0);
1332 split
[1] = mkMov(getSSA(), split
[1], ty
)->getDef(0);
1335 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
), indirect0
,
1336 split
[0])->perPatch
= info
->out
[idx
].patch
;
1337 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
+ 4), indirect0
,
1338 split
[1])->perPatch
= info
->out
[idx
].patch
;
1340 if (op
== OP_EXPORT
)
1341 src
= mkMov(getSSA(size
), src
, ty
)->getDef(0);
1342 mkStore(op
, ty
, mkSymbol(file
, 0, ty
, address
), indirect0
,
1343 src
)->perPatch
= info
->out
[idx
].patch
;
1348 Converter::parseNIR()
1350 info
->io
.clipDistances
= nir
->info
.clip_distance_array_size
;
1351 info
->io
.cullDistances
= nir
->info
.cull_distance_array_size
;
1353 switch(prog
->getType()) {
1354 case Program::TYPE_COMPUTE
:
1355 info
->prop
.cp
.numThreads
[0] = nir
->info
.cs
.local_size
[0];
1356 info
->prop
.cp
.numThreads
[1] = nir
->info
.cs
.local_size
[1];
1357 info
->prop
.cp
.numThreads
[2] = nir
->info
.cs
.local_size
[2];
1358 info
->bin
.smemSize
= nir
->info
.cs
.shared_size
;
1360 case Program::TYPE_FRAGMENT
:
1361 info
->prop
.fp
.earlyFragTests
= nir
->info
.fs
.early_fragment_tests
;
1362 info
->prop
.fp
.persampleInvocation
=
1363 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_ID
) ||
1364 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1365 info
->prop
.fp
.postDepthCoverage
= nir
->info
.fs
.post_depth_coverage
;
1366 info
->prop
.fp
.readsSampleLocations
=
1367 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1368 info
->prop
.fp
.usesDiscard
= nir
->info
.fs
.uses_discard
;
1369 info
->prop
.fp
.usesSampleMaskIn
=
1370 !!(nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
);
1372 case Program::TYPE_GEOMETRY
:
1373 info
->prop
.gp
.inputPrim
= nir
->info
.gs
.input_primitive
;
1374 info
->prop
.gp
.instanceCount
= nir
->info
.gs
.invocations
;
1375 info
->prop
.gp
.maxVertices
= nir
->info
.gs
.vertices_out
;
1376 info
->prop
.gp
.outputPrim
= nir
->info
.gs
.output_primitive
;
1378 case Program::TYPE_TESSELLATION_CONTROL
:
1379 case Program::TYPE_TESSELLATION_EVAL
:
1380 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1381 info
->prop
.tp
.domain
= GL_LINES
;
1383 info
->prop
.tp
.domain
= nir
->info
.tess
.primitive_mode
;
1384 info
->prop
.tp
.outputPatchSize
= nir
->info
.tess
.tcs_vertices_out
;
1385 info
->prop
.tp
.outputPrim
=
1386 nir
->info
.tess
.point_mode
? PIPE_PRIM_POINTS
: PIPE_PRIM_TRIANGLES
;
1387 info
->prop
.tp
.partitioning
= (nir
->info
.tess
.spacing
+ 1) % 3;
1388 info
->prop
.tp
.winding
= !nir
->info
.tess
.ccw
;
1390 case Program::TYPE_VERTEX
:
1391 info
->prop
.vp
.usesDrawParameters
=
1392 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
)) ||
1393 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
)) ||
1394 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
));
1404 Converter::visit(nir_function
*function
)
1406 // we only support emiting the main function for now
1407 assert(!strcmp(function
->name
, "main"));
1408 assert(function
->impl
);
1410 // usually the blocks will set everything up, but main is special
1411 BasicBlock
*entry
= new BasicBlock(prog
->main
);
1412 exit
= new BasicBlock(prog
->main
);
1413 blocks
[nir_start_block(function
->impl
)->index
] = entry
;
1414 prog
->main
->setEntry(entry
);
1415 prog
->main
->setExit(exit
);
1417 setPosition(entry
, true);
1419 if (info
->io
.genUserClip
> 0) {
1420 for (int c
= 0; c
< 4; ++c
)
1421 clipVtx
[c
] = getScratch();
1424 switch (prog
->getType()) {
1425 case Program::TYPE_TESSELLATION_CONTROL
:
1427 OP_SUB
, TYPE_U32
, getSSA(),
1428 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LANEID
, 0)),
1429 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_INVOCATION_ID
, 0)));
1431 case Program::TYPE_FRAGMENT
: {
1432 Symbol
*sv
= mkSysVal(SV_POSITION
, 3);
1433 fragCoord
[3] = mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), sv
);
1434 fp
.position
= mkOp1v(OP_RCP
, TYPE_F32
, fragCoord
[3], fragCoord
[3]);
1441 nir_index_ssa_defs(function
->impl
);
1442 foreach_list_typed(nir_cf_node
, node
, node
, &function
->impl
->body
) {
1447 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::TREE
);
1448 setPosition(exit
, true);
1450 if (info
->io
.genUserClip
> 0)
1451 handleUserClipPlanes();
1453 // TODO: for non main function this needs to be a OP_RETURN
1454 mkOp(OP_EXIT
, TYPE_NONE
, NULL
)->terminator
= 1;
1459 Converter::visit(nir_cf_node
*node
)
1461 switch (node
->type
) {
1462 case nir_cf_node_block
:
1463 return visit(nir_cf_node_as_block(node
));
1464 case nir_cf_node_if
:
1465 return visit(nir_cf_node_as_if(node
));
1466 case nir_cf_node_loop
:
1467 return visit(nir_cf_node_as_loop(node
));
1469 ERROR("unknown nir_cf_node type %u\n", node
->type
);
1475 Converter::visit(nir_block
*block
)
1477 if (!block
->predecessors
->entries
&& block
->instr_list
.is_empty())
1480 BasicBlock
*bb
= convert(block
);
1482 setPosition(bb
, true);
1483 nir_foreach_instr(insn
, block
) {
1491 Converter::visit(nir_if
*nif
)
1493 DataType sType
= getSType(nif
->condition
, false, false);
1494 Value
*src
= getSrc(&nif
->condition
, 0);
1496 nir_block
*lastThen
= nir_if_last_then_block(nif
);
1497 nir_block
*lastElse
= nir_if_last_else_block(nif
);
1499 assert(!lastThen
->successors
[1]);
1500 assert(!lastElse
->successors
[1]);
1502 BasicBlock
*ifBB
= convert(nir_if_first_then_block(nif
));
1503 BasicBlock
*elseBB
= convert(nir_if_first_else_block(nif
));
1505 bb
->cfg
.attach(&ifBB
->cfg
, Graph::Edge::TREE
);
1506 bb
->cfg
.attach(&elseBB
->cfg
, Graph::Edge::TREE
);
1508 // we only insert joinats, if both nodes end up at the end of the if again.
1509 // the reason for this to not happens are breaks/continues/ret/... which
1510 // have their own handling
1511 if (lastThen
->successors
[0] == lastElse
->successors
[0])
1512 bb
->joinAt
= mkFlow(OP_JOINAT
, convert(lastThen
->successors
[0]),
1515 mkFlow(OP_BRA
, elseBB
, CC_EQ
, src
)->setType(sType
);
1517 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->then_list
) {
1521 setPosition(convert(lastThen
), true);
1522 if (!bb
->getExit() ||
1523 !bb
->getExit()->asFlow() ||
1524 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1525 BasicBlock
*tailBB
= convert(lastThen
->successors
[0]);
1526 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1527 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1530 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->else_list
) {
1534 setPosition(convert(lastElse
), true);
1535 if (!bb
->getExit() ||
1536 !bb
->getExit()->asFlow() ||
1537 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1538 BasicBlock
*tailBB
= convert(lastElse
->successors
[0]);
1539 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1540 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1543 if (lastThen
->successors
[0] == lastElse
->successors
[0]) {
1544 setPosition(convert(lastThen
->successors
[0]), true);
1545 mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1552 Converter::visit(nir_loop
*loop
)
1555 func
->loopNestingBound
= std::max(func
->loopNestingBound
, curLoopDepth
);
1557 BasicBlock
*loopBB
= convert(nir_loop_first_block(loop
));
1558 BasicBlock
*tailBB
=
1559 convert(nir_cf_node_as_block(nir_cf_node_next(&loop
->cf_node
)));
1560 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::TREE
);
1562 mkFlow(OP_PREBREAK
, tailBB
, CC_ALWAYS
, NULL
);
1563 setPosition(loopBB
, false);
1564 mkFlow(OP_PRECONT
, loopBB
, CC_ALWAYS
, NULL
);
1566 foreach_list_typed(nir_cf_node
, node
, node
, &loop
->body
) {
1570 Instruction
*insn
= bb
->getExit();
1571 if (bb
->cfg
.incidentCount() != 0) {
1572 if (!insn
|| !insn
->asFlow()) {
1573 mkFlow(OP_CONT
, loopBB
, CC_ALWAYS
, NULL
);
1574 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::BACK
);
1575 } else if (insn
&& insn
->op
== OP_BRA
&& !insn
->getPredicate() &&
1576 tailBB
->cfg
.incidentCount() == 0) {
1577 // RA doesn't like having blocks around with no incident edge,
1578 // so we create a fake one to make it happy
1579 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::TREE
);
1589 Converter::visit(nir_instr
*insn
)
1591 switch (insn
->type
) {
1592 case nir_instr_type_alu
:
1593 return visit(nir_instr_as_alu(insn
));
1594 case nir_instr_type_intrinsic
:
1595 return visit(nir_instr_as_intrinsic(insn
));
1596 case nir_instr_type_jump
:
1597 return visit(nir_instr_as_jump(insn
));
1598 case nir_instr_type_load_const
:
1599 return visit(nir_instr_as_load_const(insn
));
1600 case nir_instr_type_ssa_undef
:
1601 return visit(nir_instr_as_ssa_undef(insn
));
1602 case nir_instr_type_tex
:
1603 return visit(nir_instr_as_tex(insn
));
1605 ERROR("unknown nir_instr type %u\n", insn
->type
);
1612 Converter::convert(nir_intrinsic_op intr
)
1615 case nir_intrinsic_load_base_vertex
:
1616 return SV_BASEVERTEX
;
1617 case nir_intrinsic_load_base_instance
:
1618 return SV_BASEINSTANCE
;
1619 case nir_intrinsic_load_draw_id
:
1621 case nir_intrinsic_load_front_face
:
1623 case nir_intrinsic_load_helper_invocation
:
1624 return SV_THREAD_KILL
;
1625 case nir_intrinsic_load_instance_id
:
1626 return SV_INSTANCE_ID
;
1627 case nir_intrinsic_load_invocation_id
:
1628 return SV_INVOCATION_ID
;
1629 case nir_intrinsic_load_local_group_size
:
1631 case nir_intrinsic_load_local_invocation_id
:
1633 case nir_intrinsic_load_num_work_groups
:
1635 case nir_intrinsic_load_patch_vertices_in
:
1636 return SV_VERTEX_COUNT
;
1637 case nir_intrinsic_load_primitive_id
:
1638 return SV_PRIMITIVE_ID
;
1639 case nir_intrinsic_load_sample_id
:
1640 return SV_SAMPLE_INDEX
;
1641 case nir_intrinsic_load_sample_mask_in
:
1642 return SV_SAMPLE_MASK
;
1643 case nir_intrinsic_load_sample_pos
:
1644 return SV_SAMPLE_POS
;
1645 case nir_intrinsic_load_subgroup_eq_mask
:
1646 return SV_LANEMASK_EQ
;
1647 case nir_intrinsic_load_subgroup_ge_mask
:
1648 return SV_LANEMASK_GE
;
1649 case nir_intrinsic_load_subgroup_gt_mask
:
1650 return SV_LANEMASK_GT
;
1651 case nir_intrinsic_load_subgroup_le_mask
:
1652 return SV_LANEMASK_LE
;
1653 case nir_intrinsic_load_subgroup_lt_mask
:
1654 return SV_LANEMASK_LT
;
1655 case nir_intrinsic_load_subgroup_invocation
:
1657 case nir_intrinsic_load_tess_coord
:
1658 return SV_TESS_COORD
;
1659 case nir_intrinsic_load_tess_level_inner
:
1660 return SV_TESS_INNER
;
1661 case nir_intrinsic_load_tess_level_outer
:
1662 return SV_TESS_OUTER
;
1663 case nir_intrinsic_load_vertex_id
:
1664 return SV_VERTEX_ID
;
1665 case nir_intrinsic_load_work_group_id
:
1668 ERROR("unknown SVSemantic for nir_intrinsic_op %s\n",
1669 nir_intrinsic_infos
[intr
].name
);
1676 Converter::visit(nir_intrinsic_instr
*insn
)
1678 nir_intrinsic_op op
= insn
->intrinsic
;
1681 case nir_intrinsic_load_uniform
: {
1682 LValues
&newDefs
= convert(&insn
->dest
);
1683 const DataType dType
= getDType(insn
);
1685 uint32_t coffset
= getIndirect(insn
, 0, 0, indirect
);
1686 for (uint8_t i
= 0; i
< insn
->num_components
; ++i
) {
1687 loadFrom(FILE_MEMORY_CONST
, 0, dType
, newDefs
[i
], 16 * coffset
, i
, indirect
);
1691 case nir_intrinsic_store_output
:
1692 case nir_intrinsic_store_per_vertex_output
: {
1694 DataType dType
= getSType(insn
->src
[0], false, false);
1695 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_store_output
? 1 : 2, 0, indirect
);
1697 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1698 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
1702 Value
*src
= getSrc(&insn
->src
[0], i
);
1703 switch (prog
->getType()) {
1704 case Program::TYPE_FRAGMENT
: {
1705 if (info
->out
[idx
].sn
== TGSI_SEMANTIC_POSITION
) {
1706 // TGSI uses a different interface than NIR, TGSI stores that
1707 // value in the z component, NIR in X
1709 src
= mkOp1v(OP_SAT
, TYPE_F32
, getScratch(), src
);
1713 case Program::TYPE_VERTEX
: {
1714 if (info
->io
.genUserClip
> 0 && idx
== clipVertexOutput
) {
1715 mkMov(clipVtx
[i
], src
);
1724 storeTo(insn
, FILE_SHADER_OUTPUT
, OP_EXPORT
, dType
, src
, idx
, i
+ offset
, indirect
);
1728 case nir_intrinsic_load_input
:
1729 case nir_intrinsic_load_interpolated_input
:
1730 case nir_intrinsic_load_output
: {
1731 LValues
&newDefs
= convert(&insn
->dest
);
1734 if (prog
->getType() == Program::TYPE_FRAGMENT
&&
1735 op
== nir_intrinsic_load_output
) {
1736 std::vector
<Value
*> defs
, srcs
;
1739 srcs
.push_back(getSSA());
1740 srcs
.push_back(getSSA());
1741 Value
*x
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 0));
1742 Value
*y
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 1));
1743 mkCvt(OP_CVT
, TYPE_U32
, srcs
[0], TYPE_F32
, x
)->rnd
= ROUND_Z
;
1744 mkCvt(OP_CVT
, TYPE_U32
, srcs
[1], TYPE_F32
, y
)->rnd
= ROUND_Z
;
1746 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LAYER
, 0)));
1747 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_SAMPLE_INDEX
, 0)));
1749 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1750 defs
.push_back(newDefs
[i
]);
1754 TexInstruction
*texi
= mkTex(OP_TXF
, TEX_TARGET_2D_MS_ARRAY
, 0, 0, defs
, srcs
);
1755 texi
->tex
.levelZero
= 1;
1756 texi
->tex
.mask
= mask
;
1757 texi
->tex
.useOffsets
= 0;
1758 texi
->tex
.r
= 0xffff;
1759 texi
->tex
.s
= 0xffff;
1761 info
->prop
.fp
.readsFramebuffer
= true;
1765 const DataType dType
= getDType(insn
);
1767 bool input
= op
!= nir_intrinsic_load_output
;
1771 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_load_interpolated_input
? 1 : 0, 0, indirect
);
1772 nv50_ir_varying
& vary
= input
? info
->in
[idx
] : info
->out
[idx
];
1774 // see load_barycentric_* handling
1775 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1776 mode
= translateInterpMode(&vary
, nvirOp
);
1777 if (op
== nir_intrinsic_load_interpolated_input
) {
1778 ImmediateValue immMode
;
1779 if (getSrc(&insn
->src
[0], 1)->getUniqueInsn()->src(0).getImmediate(immMode
))
1780 mode
|= immMode
.reg
.data
.u32
;
1784 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1785 uint32_t address
= getSlotAddress(insn
, idx
, i
);
1786 Symbol
*sym
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
);
1787 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1789 if (typeSizeof(dType
) == 8) {
1790 Value
*lo
= getSSA();
1791 Value
*hi
= getSSA();
1792 Instruction
*interp
;
1794 interp
= mkOp1(nvirOp
, TYPE_U32
, lo
, sym
);
1795 if (nvirOp
== OP_PINTERP
)
1796 interp
->setSrc(s
++, fp
.position
);
1797 if (mode
& NV50_IR_INTERP_OFFSET
)
1798 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1799 interp
->setInterpolate(mode
);
1800 interp
->setIndirect(0, 0, indirect
);
1802 Symbol
*sym1
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
+ 4);
1803 interp
= mkOp1(nvirOp
, TYPE_U32
, hi
, sym1
);
1804 if (nvirOp
== OP_PINTERP
)
1805 interp
->setSrc(s
++, fp
.position
);
1806 if (mode
& NV50_IR_INTERP_OFFSET
)
1807 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1808 interp
->setInterpolate(mode
);
1809 interp
->setIndirect(0, 0, indirect
);
1811 mkOp2(OP_MERGE
, dType
, newDefs
[i
], lo
, hi
);
1813 Instruction
*interp
= mkOp1(nvirOp
, dType
, newDefs
[i
], sym
);
1814 if (nvirOp
== OP_PINTERP
)
1815 interp
->setSrc(s
++, fp
.position
);
1816 if (mode
& NV50_IR_INTERP_OFFSET
)
1817 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1818 interp
->setInterpolate(mode
);
1819 interp
->setIndirect(0, 0, indirect
);
1822 mkLoad(dType
, newDefs
[i
], sym
, indirect
)->perPatch
= vary
.patch
;
1827 case nir_intrinsic_load_barycentric_at_offset
:
1828 case nir_intrinsic_load_barycentric_at_sample
:
1829 case nir_intrinsic_load_barycentric_centroid
:
1830 case nir_intrinsic_load_barycentric_pixel
:
1831 case nir_intrinsic_load_barycentric_sample
: {
1832 LValues
&newDefs
= convert(&insn
->dest
);
1835 if (op
== nir_intrinsic_load_barycentric_centroid
||
1836 op
== nir_intrinsic_load_barycentric_sample
) {
1837 mode
= NV50_IR_INTERP_CENTROID
;
1838 } else if (op
== nir_intrinsic_load_barycentric_at_offset
) {
1840 for (uint8_t c
= 0; c
< 2; c
++) {
1841 offs
[c
] = getScratch();
1842 mkOp2(OP_MIN
, TYPE_F32
, offs
[c
], getSrc(&insn
->src
[0], c
), loadImm(NULL
, 0.4375f
));
1843 mkOp2(OP_MAX
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, -0.5f
));
1844 mkOp2(OP_MUL
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, 4096.0f
));
1845 mkCvt(OP_CVT
, TYPE_S32
, offs
[c
], TYPE_F32
, offs
[c
]);
1847 mkOp3v(OP_INSBF
, TYPE_U32
, newDefs
[0], offs
[1], mkImm(0x1010), offs
[0]);
1849 mode
= NV50_IR_INTERP_OFFSET
;
1850 } else if (op
== nir_intrinsic_load_barycentric_pixel
) {
1851 mode
= NV50_IR_INTERP_DEFAULT
;
1852 } else if (op
== nir_intrinsic_load_barycentric_at_sample
) {
1853 info
->prop
.fp
.readsSampleLocations
= true;
1854 mkOp1(OP_PIXLD
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0], 0))->subOp
= NV50_IR_SUBOP_PIXLD_OFFSET
;
1855 mode
= NV50_IR_INTERP_OFFSET
;
1857 unreachable("all intrinsics already handled above");
1860 loadImm(newDefs
[1], mode
);
1863 case nir_intrinsic_discard
:
1864 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
);
1866 case nir_intrinsic_discard_if
: {
1867 Value
*pred
= getSSA(1, FILE_PREDICATE
);
1868 if (insn
->num_components
> 1) {
1869 ERROR("nir_intrinsic_discard_if only with 1 component supported!\n");
1873 mkCmp(OP_SET
, CC_NE
, TYPE_U8
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
1874 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
)->setPredicate(CC_P
, pred
);
1877 case nir_intrinsic_load_base_vertex
:
1878 case nir_intrinsic_load_base_instance
:
1879 case nir_intrinsic_load_draw_id
:
1880 case nir_intrinsic_load_front_face
:
1881 case nir_intrinsic_load_helper_invocation
:
1882 case nir_intrinsic_load_instance_id
:
1883 case nir_intrinsic_load_invocation_id
:
1884 case nir_intrinsic_load_local_group_size
:
1885 case nir_intrinsic_load_local_invocation_id
:
1886 case nir_intrinsic_load_num_work_groups
:
1887 case nir_intrinsic_load_patch_vertices_in
:
1888 case nir_intrinsic_load_primitive_id
:
1889 case nir_intrinsic_load_sample_id
:
1890 case nir_intrinsic_load_sample_mask_in
:
1891 case nir_intrinsic_load_sample_pos
:
1892 case nir_intrinsic_load_subgroup_eq_mask
:
1893 case nir_intrinsic_load_subgroup_ge_mask
:
1894 case nir_intrinsic_load_subgroup_gt_mask
:
1895 case nir_intrinsic_load_subgroup_le_mask
:
1896 case nir_intrinsic_load_subgroup_lt_mask
:
1897 case nir_intrinsic_load_subgroup_invocation
:
1898 case nir_intrinsic_load_tess_coord
:
1899 case nir_intrinsic_load_tess_level_inner
:
1900 case nir_intrinsic_load_tess_level_outer
:
1901 case nir_intrinsic_load_vertex_id
:
1902 case nir_intrinsic_load_work_group_id
: {
1903 const DataType dType
= getDType(insn
);
1904 SVSemantic sv
= convert(op
);
1905 LValues
&newDefs
= convert(&insn
->dest
);
1907 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1909 if (typeSizeof(dType
) == 8)
1914 if (sv
== SV_TID
&& info
->prop
.cp
.numThreads
[i
] == 1) {
1917 Symbol
*sym
= mkSysVal(sv
, i
);
1918 Instruction
*rdsv
= mkOp1(OP_RDSV
, TYPE_U32
, def
, sym
);
1919 if (sv
== SV_TESS_OUTER
|| sv
== SV_TESS_INNER
)
1923 if (typeSizeof(dType
) == 8)
1924 mkOp2(OP_MERGE
, dType
, newDefs
[i
], def
, loadImm(getSSA(), 0u));
1929 case nir_intrinsic_load_subgroup_size
: {
1930 LValues
&newDefs
= convert(&insn
->dest
);
1931 loadImm(newDefs
[0], 32u);
1935 ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos
[op
].name
);
1943 Converter::visit(nir_jump_instr
*insn
)
1945 switch (insn
->type
) {
1946 case nir_jump_return
:
1947 // TODO: this only works in the main function
1948 mkFlow(OP_BRA
, exit
, CC_ALWAYS
, NULL
);
1949 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::CROSS
);
1951 case nir_jump_break
:
1952 case nir_jump_continue
: {
1953 bool isBreak
= insn
->type
== nir_jump_break
;
1954 nir_block
*block
= insn
->instr
.block
;
1955 assert(!block
->successors
[1]);
1956 BasicBlock
*target
= convert(block
->successors
[0]);
1957 mkFlow(isBreak
? OP_BREAK
: OP_CONT
, target
, CC_ALWAYS
, NULL
);
1958 bb
->cfg
.attach(&target
->cfg
, isBreak
? Graph::Edge::CROSS
: Graph::Edge::BACK
);
1962 ERROR("unknown nir_jump_type %u\n", insn
->type
);
1970 Converter::visit(nir_load_const_instr
*insn
)
1972 assert(insn
->def
.bit_size
<= 64);
1974 LValues
&newDefs
= convert(&insn
->def
);
1975 for (int i
= 0; i
< insn
->def
.num_components
; i
++) {
1976 switch (insn
->def
.bit_size
) {
1978 loadImm(newDefs
[i
], insn
->value
.u64
[i
]);
1981 loadImm(newDefs
[i
], insn
->value
.u32
[i
]);
1984 loadImm(newDefs
[i
], insn
->value
.u16
[i
]);
1987 loadImm(newDefs
[i
], insn
->value
.u8
[i
]);
1994 #define DEFAULT_CHECKS \
1995 if (insn->dest.dest.ssa.num_components > 1) { \
1996 ERROR("nir_alu_instr only supported with 1 component!\n"); \
1999 if (insn->dest.write_mask != 1) { \
2000 ERROR("nir_alu_instr only with write_mask of 1 supported!\n"); \
2004 Converter::visit(nir_alu_instr
*insn
)
2006 const nir_op op
= insn
->op
;
2007 const nir_op_info
&info
= nir_op_infos
[op
];
2008 DataType dType
= getDType(insn
);
2009 const std::vector
<DataType
> sTypes
= getSTypes(insn
);
2011 Instruction
*oldPos
= this->bb
->getExit();
2023 case nir_op_fddx_coarse
:
2024 case nir_op_fddx_fine
:
2026 case nir_op_fddy_coarse
:
2027 case nir_op_fddy_fine
:
2046 case nir_op_imul_high
:
2047 case nir_op_umul_high
:
2054 case nir_op_pack_64_2x32_split
:
2072 LValues
&newDefs
= convert(&insn
->dest
);
2073 operation preOp
= preOperationNeeded(op
);
2074 if (preOp
!= OP_NOP
) {
2075 assert(info
.num_inputs
< 2);
2076 Value
*tmp
= getSSA(typeSizeof(dType
));
2077 Instruction
*i0
= mkOp(preOp
, dType
, tmp
);
2078 Instruction
*i1
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2079 if (info
.num_inputs
) {
2080 i0
->setSrc(0, getSrc(&insn
->src
[0]));
2083 i1
->subOp
= getSubOp(op
);
2085 Instruction
*i
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2086 for (unsigned s
= 0u; s
< info
.num_inputs
; ++s
) {
2087 i
->setSrc(s
, getSrc(&insn
->src
[s
]));
2089 i
->subOp
= getSubOp(op
);
2093 case nir_op_ifind_msb
:
2094 case nir_op_ufind_msb
: {
2096 LValues
&newDefs
= convert(&insn
->dest
);
2098 mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2101 case nir_op_fround_even
: {
2103 LValues
&newDefs
= convert(&insn
->dest
);
2104 mkCvt(OP_CVT
, dType
, newDefs
[0], dType
, getSrc(&insn
->src
[0]))->rnd
= ROUND_NI
;
2107 // convert instructions
2121 case nir_op_u2u64
: {
2123 LValues
&newDefs
= convert(&insn
->dest
);
2124 Instruction
*i
= mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2125 if (op
== nir_op_f2i32
|| op
== nir_op_f2i64
|| op
== nir_op_f2u32
|| op
== nir_op_f2u64
)
2127 i
->sType
= sTypes
[0];
2130 // compare instructions
2140 case nir_op_ine32
: {
2142 LValues
&newDefs
= convert(&insn
->dest
);
2143 Instruction
*i
= mkCmp(getOperation(op
),
2148 getSrc(&insn
->src
[0]),
2149 getSrc(&insn
->src
[1]));
2150 if (info
.num_inputs
== 3)
2151 i
->setSrc(2, getSrc(&insn
->src
[2]));
2152 i
->sType
= sTypes
[0];
2155 // those are weird ALU ops and need special handling, because
2156 // 1. they are always componend based
2157 // 2. they basically just merge multiple values into one data type
2163 LValues
&newDefs
= convert(&insn
->dest
);
2164 for (LValues::size_type c
= 0u; c
< newDefs
.size(); ++c
) {
2165 mkMov(newDefs
[c
], getSrc(&insn
->src
[c
]), dType
);
2170 case nir_op_pack_64_2x32
: {
2171 LValues
&newDefs
= convert(&insn
->dest
);
2172 Instruction
*merge
= mkOp(OP_MERGE
, dType
, newDefs
[0]);
2173 merge
->setSrc(0, getSrc(&insn
->src
[0], 0));
2174 merge
->setSrc(1, getSrc(&insn
->src
[0], 1));
2177 case nir_op_pack_half_2x16_split
: {
2178 LValues
&newDefs
= convert(&insn
->dest
);
2179 Value
*tmpH
= getSSA();
2180 Value
*tmpL
= getSSA();
2182 mkCvt(OP_CVT
, TYPE_F16
, tmpL
, TYPE_F32
, getSrc(&insn
->src
[0]));
2183 mkCvt(OP_CVT
, TYPE_F16
, tmpH
, TYPE_F32
, getSrc(&insn
->src
[1]));
2184 mkOp3(OP_INSBF
, TYPE_U32
, newDefs
[0], tmpH
, mkImm(0x1010), tmpL
);
2187 case nir_op_unpack_half_2x16_split_x
:
2188 case nir_op_unpack_half_2x16_split_y
: {
2189 LValues
&newDefs
= convert(&insn
->dest
);
2190 Instruction
*cvt
= mkCvt(OP_CVT
, TYPE_F32
, newDefs
[0], TYPE_F16
, getSrc(&insn
->src
[0]));
2191 if (op
== nir_op_unpack_half_2x16_split_y
)
2195 case nir_op_unpack_64_2x32
: {
2196 LValues
&newDefs
= convert(&insn
->dest
);
2197 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, newDefs
[1]);
2200 case nir_op_unpack_64_2x32_split_x
: {
2201 LValues
&newDefs
= convert(&insn
->dest
);
2202 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, getSSA());
2205 case nir_op_unpack_64_2x32_split_y
: {
2206 LValues
&newDefs
= convert(&insn
->dest
);
2207 mkOp1(OP_SPLIT
, dType
, getSSA(), getSrc(&insn
->src
[0]))->setDef(1, newDefs
[0]);
2210 // special instructions
2212 case nir_op_isign
: {
2215 if (::isFloatType(dType
))
2220 LValues
&newDefs
= convert(&insn
->dest
);
2221 LValue
*val0
= getScratch();
2222 LValue
*val1
= getScratch();
2223 mkCmp(OP_SET
, CC_GT
, iType
, val0
, dType
, getSrc(&insn
->src
[0]), zero
);
2224 mkCmp(OP_SET
, CC_LT
, iType
, val1
, dType
, getSrc(&insn
->src
[0]), zero
);
2226 if (dType
== TYPE_F64
) {
2227 mkOp2(OP_SUB
, iType
, val0
, val0
, val1
);
2228 mkCvt(OP_CVT
, TYPE_F64
, newDefs
[0], iType
, val0
);
2229 } else if (dType
== TYPE_S64
|| dType
== TYPE_U64
) {
2230 mkOp2(OP_SUB
, iType
, val0
, val1
, val0
);
2231 mkOp2(OP_SHR
, iType
, val1
, val0
, loadImm(NULL
, 31));
2232 mkOp2(OP_MERGE
, dType
, newDefs
[0], val0
, val1
);
2233 } else if (::isFloatType(dType
))
2234 mkOp2(OP_SUB
, iType
, newDefs
[0], val0
, val1
);
2236 mkOp2(OP_SUB
, iType
, newDefs
[0], val1
, val0
);
2240 case nir_op_b32csel
: {
2242 LValues
&newDefs
= convert(&insn
->dest
);
2243 mkCmp(OP_SLCT
, CC_NE
, dType
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[1]), getSrc(&insn
->src
[2]), getSrc(&insn
->src
[0]));
2246 case nir_op_ibitfield_extract
:
2247 case nir_op_ubitfield_extract
: {
2249 Value
*tmp
= getSSA();
2250 LValues
&newDefs
= convert(&insn
->dest
);
2251 mkOp3(OP_INSBF
, dType
, tmp
, getSrc(&insn
->src
[2]), loadImm(NULL
, 0x808), getSrc(&insn
->src
[1]));
2252 mkOp2(OP_EXTBF
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), tmp
);
2257 LValues
&newDefs
= convert(&insn
->dest
);
2258 mkOp3(OP_INSBF
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 0x808), getSrc(&insn
->src
[1]));
2261 case nir_op_bitfield_insert
: {
2263 LValues
&newDefs
= convert(&insn
->dest
);
2264 LValue
*temp
= getSSA();
2265 mkOp3(OP_INSBF
, TYPE_U32
, temp
, getSrc(&insn
->src
[3]), mkImm(0x808), getSrc(&insn
->src
[2]));
2266 mkOp3(OP_INSBF
, dType
, newDefs
[0], getSrc(&insn
->src
[1]), temp
, getSrc(&insn
->src
[0]));
2269 case nir_op_bit_count
: {
2271 LValues
&newDefs
= convert(&insn
->dest
);
2272 mkOp2(OP_POPCNT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), getSrc(&insn
->src
[0]));
2275 case nir_op_bitfield_reverse
: {
2277 LValues
&newDefs
= convert(&insn
->dest
);
2278 mkOp2(OP_EXTBF
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2281 case nir_op_find_lsb
: {
2283 LValues
&newDefs
= convert(&insn
->dest
);
2284 Value
*tmp
= getSSA();
2285 mkOp2(OP_EXTBF
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]), mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2286 mkOp1(OP_BFIND
, TYPE_U32
, newDefs
[0], tmp
)->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
2289 // boolean conversions
2290 case nir_op_b2f32
: {
2292 LValues
&newDefs
= convert(&insn
->dest
);
2293 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1.0f
));
2296 case nir_op_b2f64
: {
2298 LValues
&newDefs
= convert(&insn
->dest
);
2299 Value
*tmp
= getSSA(4);
2300 mkOp2(OP_AND
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]), loadImm(NULL
, 0x3ff00000));
2301 mkOp2(OP_MERGE
, TYPE_U64
, newDefs
[0], loadImm(NULL
, 0), tmp
);
2305 case nir_op_i2b32
: {
2307 LValues
&newDefs
= convert(&insn
->dest
);
2309 if (typeSizeof(sTypes
[0]) == 8) {
2310 src1
= loadImm(getSSA(8), 0.0);
2314 CondCode cc
= op
== nir_op_f2b32
? CC_NEU
: CC_NE
;
2315 mkCmp(OP_SET
, cc
, TYPE_U32
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[0]), src1
);
2318 case nir_op_b2i32
: {
2320 LValues
&newDefs
= convert(&insn
->dest
);
2321 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2324 case nir_op_b2i64
: {
2326 LValues
&newDefs
= convert(&insn
->dest
);
2327 LValue
*def
= getScratch();
2328 mkOp2(OP_AND
, TYPE_U32
, def
, getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2329 mkOp2(OP_MERGE
, TYPE_S64
, newDefs
[0], def
, loadImm(NULL
, 0));
2333 ERROR("unknown nir_op %s\n", info
.name
);
2338 oldPos
= this->bb
->getEntry();
2339 oldPos
->precise
= insn
->exact
;
2342 if (unlikely(!oldPos
))
2345 while (oldPos
->next
) {
2346 oldPos
= oldPos
->next
;
2347 oldPos
->precise
= insn
->exact
;
2349 oldPos
->saturate
= insn
->dest
.saturate
;
2353 #undef DEFAULT_CHECKS
2356 Converter::visit(nir_ssa_undef_instr
*insn
)
2358 LValues
&newDefs
= convert(&insn
->def
);
2359 for (uint8_t i
= 0u; i
< insn
->def
.num_components
; ++i
) {
2360 mkOp(OP_NOP
, TYPE_NONE
, newDefs
[i
]);
2365 #define CASE_SAMPLER(ty) \
2366 case GLSL_SAMPLER_DIM_ ## ty : \
2367 if (isArray && !isShadow) \
2368 return TEX_TARGET_ ## ty ## _ARRAY; \
2369 else if (!isArray && isShadow) \
2370 return TEX_TARGET_## ty ## _SHADOW; \
2371 else if (isArray && isShadow) \
2372 return TEX_TARGET_## ty ## _ARRAY_SHADOW; \
2374 return TEX_TARGET_ ## ty
2377 Converter::convert(glsl_sampler_dim dim
, bool isArray
, bool isShadow
)
2383 case GLSL_SAMPLER_DIM_3D
:
2384 return TEX_TARGET_3D
;
2385 case GLSL_SAMPLER_DIM_MS
:
2387 return TEX_TARGET_2D_MS_ARRAY
;
2388 return TEX_TARGET_2D_MS
;
2389 case GLSL_SAMPLER_DIM_RECT
:
2391 return TEX_TARGET_RECT_SHADOW
;
2392 return TEX_TARGET_RECT
;
2393 case GLSL_SAMPLER_DIM_BUF
:
2394 return TEX_TARGET_BUFFER
;
2395 case GLSL_SAMPLER_DIM_EXTERNAL
:
2396 return TEX_TARGET_2D
;
2398 ERROR("unknown glsl_sampler_dim %u\n", dim
);
2400 return TEX_TARGET_COUNT
;
2406 Converter::applyProjection(Value
*src
, Value
*proj
)
2410 return mkOp2v(OP_MUL
, TYPE_F32
, getScratch(), src
, proj
);
2414 Converter::visit(nir_tex_instr
*insn
)
2418 case nir_texop_query_levels
:
2420 case nir_texop_texture_samples
:
2425 case nir_texop_txf_ms
:
2427 case nir_texop_txs
: {
2428 LValues
&newDefs
= convert(&insn
->dest
);
2429 std::vector
<Value
*> srcs
;
2430 std::vector
<Value
*> defs
;
2431 std::vector
<nir_src
*> offsets
;
2435 TexInstruction::Target target
= convert(insn
->sampler_dim
, insn
->is_array
, insn
->is_shadow
);
2436 operation op
= getOperation(insn
->op
);
2439 int biasIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_bias
);
2440 int compIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_comparator
);
2441 int coordsIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_coord
);
2442 int ddxIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddx
);
2443 int ddyIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddy
);
2444 int msIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ms_index
);
2445 int lodIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_lod
);
2446 int offsetIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_offset
);
2447 int projIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_projector
);
2448 int sampOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_sampler_offset
);
2449 int texOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_texture_offset
);
2452 proj
= mkOp1v(OP_RCP
, TYPE_F32
, getScratch(), getSrc(&insn
->src
[projIdx
].src
, 0));
2454 srcs
.resize(insn
->coord_components
);
2455 for (uint8_t i
= 0u; i
< insn
->coord_components
; ++i
)
2456 srcs
[i
] = applyProjection(getSrc(&insn
->src
[coordsIdx
].src
, i
), proj
);
2458 // sometimes we get less args than target.getArgCount, but codegen expects the latter
2459 if (insn
->coord_components
) {
2460 uint32_t argCount
= target
.getArgCount();
2465 for (uint32_t i
= 0u; i
< (argCount
- insn
->coord_components
); ++i
)
2466 srcs
.push_back(getSSA());
2469 if (insn
->op
== nir_texop_texture_samples
)
2470 srcs
.push_back(zero
);
2471 else if (!insn
->num_srcs
)
2472 srcs
.push_back(loadImm(NULL
, 0));
2474 srcs
.push_back(getSrc(&insn
->src
[biasIdx
].src
, 0));
2476 srcs
.push_back(getSrc(&insn
->src
[lodIdx
].src
, 0));
2477 else if (op
== OP_TXF
)
2480 srcs
.push_back(getSrc(&insn
->src
[msIdx
].src
, 0));
2481 if (offsetIdx
!= -1)
2482 offsets
.push_back(&insn
->src
[offsetIdx
].src
);
2484 srcs
.push_back(applyProjection(getSrc(&insn
->src
[compIdx
].src
, 0), proj
));
2485 if (texOffIdx
!= -1) {
2486 srcs
.push_back(getSrc(&insn
->src
[texOffIdx
].src
, 0));
2487 texOffIdx
= srcs
.size() - 1;
2489 if (sampOffIdx
!= -1) {
2490 srcs
.push_back(getSrc(&insn
->src
[sampOffIdx
].src
, 0));
2491 sampOffIdx
= srcs
.size() - 1;
2494 r
= insn
->texture_index
;
2495 s
= insn
->sampler_index
;
2497 defs
.resize(newDefs
.size());
2498 for (uint8_t d
= 0u; d
< newDefs
.size(); ++d
) {
2499 defs
[d
] = newDefs
[d
];
2502 if (target
.isMS() || (op
== OP_TEX
&& prog
->getType() != Program::TYPE_FRAGMENT
))
2505 TexInstruction
*texi
= mkTex(op
, target
.getEnum(), r
, s
, defs
, srcs
);
2506 texi
->tex
.levelZero
= lz
;
2507 texi
->tex
.mask
= mask
;
2509 if (texOffIdx
!= -1)
2510 texi
->tex
.rIndirectSrc
= texOffIdx
;
2511 if (sampOffIdx
!= -1)
2512 texi
->tex
.sIndirectSrc
= sampOffIdx
;
2516 if (!target
.isShadow())
2517 texi
->tex
.gatherComp
= insn
->component
;
2520 texi
->tex
.query
= TXQ_DIMS
;
2522 case nir_texop_texture_samples
:
2523 texi
->tex
.mask
= 0x4;
2524 texi
->tex
.query
= TXQ_TYPE
;
2526 case nir_texop_query_levels
:
2527 texi
->tex
.mask
= 0x8;
2528 texi
->tex
.query
= TXQ_DIMS
;
2534 texi
->tex
.useOffsets
= offsets
.size();
2535 if (texi
->tex
.useOffsets
) {
2536 for (uint8_t s
= 0; s
< texi
->tex
.useOffsets
; ++s
) {
2537 for (uint32_t c
= 0u; c
< 3; ++c
) {
2538 uint8_t s2
= std::min(c
, target
.getDim() - 1);
2539 texi
->offset
[s
][c
].set(getSrc(offsets
[s
], s2
));
2540 texi
->offset
[s
][c
].setInsn(texi
);
2545 if (ddxIdx
!= -1 && ddyIdx
!= -1) {
2546 for (uint8_t c
= 0u; c
< target
.getDim() + target
.isCube(); ++c
) {
2547 texi
->dPdx
[c
].set(getSrc(&insn
->src
[ddxIdx
].src
, c
));
2548 texi
->dPdy
[c
].set(getSrc(&insn
->src
[ddyIdx
].src
, c
));
2555 ERROR("unknown nir_texop %u\n", insn
->op
);
2566 if (prog
->dbgFlags
& NV50_IR_DEBUG_VERBOSE
)
2567 nir_print_shader(nir
, stderr
);
2569 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, type_size
, (nir_lower_io_options
)0);
2570 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
);
2571 NIR_PASS_V(nir
, nir_lower_load_const_to_scalar
);
2572 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2573 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
);
2574 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
2578 NIR_PASS(progress
, nir
, nir_copy_prop
);
2579 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
2580 NIR_PASS(progress
, nir
, nir_opt_trivial_continues
);
2581 NIR_PASS(progress
, nir
, nir_opt_cse
);
2582 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
2583 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
2584 NIR_PASS(progress
, nir
, nir_copy_prop
);
2585 NIR_PASS(progress
, nir
, nir_opt_dce
);
2586 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
2589 NIR_PASS_V(nir
, nir_lower_bool_to_int32
);
2590 NIR_PASS_V(nir
, nir_lower_locals_to_regs
);
2591 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
);
2592 NIR_PASS_V(nir
, nir_convert_from_ssa
, true);
2594 // Garbage collect dead instructions
2598 ERROR("Couldn't prase NIR!\n");
2602 if (!assignSlots()) {
2603 ERROR("Couldn't assign slots!\n");
2607 if (prog
->dbgFlags
& NV50_IR_DEBUG_BASIC
)
2608 nir_print_shader(nir
, stderr
);
2610 nir_foreach_function(function
, nir
) {
2611 if (!visit(function
))
2618 } // unnamed namespace
2623 Program::makeFromNIR(struct nv50_ir_prog_info
*info
)
2625 nir_shader
*nir
= (nir_shader
*)info
->bin
.source
;
2626 Converter
converter(this, nir
, info
);
2627 bool result
= converter
.run();
2630 LoweringHelper lowering
;
2632 tlsSize
= info
->bin
.tlsSpace
;
2636 } // namespace nv50_ir