2 * Copyright 2017 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Karol Herbst <kherbst@redhat.com>
25 #include "compiler/nir/nir.h"
27 #include "util/u_debug.h"
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_from_common.h"
31 #include "codegen/nv50_ir_lowering_helper.h"
32 #include "codegen/nv50_ir_util.h"
34 #if __cplusplus >= 201103L
35 #include <unordered_map>
37 #include <tr1/unordered_map>
43 #if __cplusplus >= 201103L
45 using std::unordered_map
;
48 using std::tr1::unordered_map
;
51 using namespace nv50_ir
;
54 type_size(const struct glsl_type
*type
)
56 return glsl_count_attribute_slots(type
, false);
59 class Converter
: public ConverterCommon
62 Converter(Program
*, nir_shader
*, nv50_ir_prog_info
*);
66 typedef std::vector
<LValue
*> LValues
;
67 typedef unordered_map
<unsigned, LValues
> NirDefMap
;
68 typedef unordered_map
<unsigned, BasicBlock
*> NirBlockMap
;
70 LValues
& convert(nir_alu_dest
*);
71 BasicBlock
* convert(nir_block
*);
72 LValues
& convert(nir_dest
*);
73 LValues
& convert(nir_register
*);
74 LValues
& convert(nir_ssa_def
*);
76 Value
* getSrc(nir_alu_src
*, uint8_t component
= 0);
77 Value
* getSrc(nir_register
*, uint8_t);
78 Value
* getSrc(nir_src
*, uint8_t, bool indirect
= false);
79 Value
* getSrc(nir_ssa_def
*, uint8_t);
81 // returned value is the constant part of the given source (either the
82 // nir_src or the selected source component of an intrinsic). Even though
83 // this is mostly an optimization to be able to skip indirects in a few
84 // cases, sometimes we require immediate values or set some fileds on
85 // instructions (e.g. tex) in order for codegen to consume those.
86 // If the found value has not a constant part, the Value gets returned
87 // through the Value parameter.
88 uint32_t getIndirect(nir_src
*, uint8_t, Value
*&);
89 uint32_t getIndirect(nir_intrinsic_instr
*, uint8_t s
, uint8_t c
, Value
*&);
91 uint32_t getSlotAddress(nir_intrinsic_instr
*, uint8_t idx
, uint8_t slot
);
93 void setInterpolate(nv50_ir_varying
*,
98 Instruction
*loadFrom(DataFile
, uint8_t, DataType
, Value
*def
, uint32_t base
,
99 uint8_t c
, Value
*indirect0
= NULL
,
100 Value
*indirect1
= NULL
, bool patch
= false);
101 void storeTo(nir_intrinsic_instr
*, DataFile
, operation
, DataType
,
102 Value
*src
, uint8_t idx
, uint8_t c
, Value
*indirect0
= NULL
,
103 Value
*indirect1
= NULL
);
105 bool isFloatType(nir_alu_type
);
106 bool isSignedType(nir_alu_type
);
107 bool isResultFloat(nir_op
);
108 bool isResultSigned(nir_op
);
110 DataType
getDType(nir_alu_instr
*);
111 DataType
getDType(nir_intrinsic_instr
*);
112 DataType
getDType(nir_op
, uint8_t);
114 std::vector
<DataType
> getSTypes(nir_alu_instr
*);
115 DataType
getSType(nir_src
&, bool isFloat
, bool isSigned
);
120 bool visit(nir_block
*);
121 bool visit(nir_cf_node
*);
122 bool visit(nir_function
*);
123 bool visit(nir_if
*);
124 bool visit(nir_instr
*);
125 bool visit(nir_jump_instr
*);
126 bool visit(nir_loop
*);
133 unsigned int curLoopDepth
;
144 Converter::Converter(Program
*prog
, nir_shader
*nir
, nv50_ir_prog_info
*info
)
145 : ConverterCommon(prog
, info
),
150 Converter::convert(nir_block
*block
)
152 NirBlockMap::iterator it
= blocks
.find(block
->index
);
153 if (it
!= blocks
.end())
156 BasicBlock
*bb
= new BasicBlock(func
);
157 blocks
[block
->index
] = bb
;
162 Converter::isFloatType(nir_alu_type type
)
164 return nir_alu_type_get_base_type(type
) == nir_type_float
;
168 Converter::isSignedType(nir_alu_type type
)
170 return nir_alu_type_get_base_type(type
) == nir_type_int
;
174 Converter::isResultFloat(nir_op op
)
176 const nir_op_info
&info
= nir_op_infos
[op
];
177 if (info
.output_type
!= nir_type_invalid
)
178 return isFloatType(info
.output_type
);
180 ERROR("isResultFloat not implemented for %s\n", nir_op_infos
[op
].name
);
186 Converter::isResultSigned(nir_op op
)
189 // there is no umul and we get wrong results if we treat all muls as signed
194 const nir_op_info
&info
= nir_op_infos
[op
];
195 if (info
.output_type
!= nir_type_invalid
)
196 return isSignedType(info
.output_type
);
197 ERROR("isResultSigned not implemented for %s\n", nir_op_infos
[op
].name
);
204 Converter::getDType(nir_alu_instr
*insn
)
206 if (insn
->dest
.dest
.is_ssa
)
207 return getDType(insn
->op
, insn
->dest
.dest
.ssa
.bit_size
);
209 return getDType(insn
->op
, insn
->dest
.dest
.reg
.reg
->bit_size
);
213 Converter::getDType(nir_intrinsic_instr
*insn
)
215 if (insn
->dest
.is_ssa
)
216 return typeOfSize(insn
->dest
.ssa
.bit_size
/ 8, false, false);
218 return typeOfSize(insn
->dest
.reg
.reg
->bit_size
/ 8, false, false);
222 Converter::getDType(nir_op op
, uint8_t bitSize
)
224 DataType ty
= typeOfSize(bitSize
/ 8, isResultFloat(op
), isResultSigned(op
));
225 if (ty
== TYPE_NONE
) {
226 ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos
[op
].name
, bitSize
);
232 std::vector
<DataType
>
233 Converter::getSTypes(nir_alu_instr
*insn
)
235 const nir_op_info
&info
= nir_op_infos
[insn
->op
];
236 std::vector
<DataType
> res(info
.num_inputs
);
238 for (uint8_t i
= 0; i
< info
.num_inputs
; ++i
) {
239 if (info
.input_types
[i
] != nir_type_invalid
) {
240 res
[i
] = getSType(insn
->src
[i
].src
, isFloatType(info
.input_types
[i
]), isSignedType(info
.input_types
[i
]));
242 ERROR("getSType not implemented for %s idx %u\n", info
.name
, i
);
253 Converter::getSType(nir_src
&src
, bool isFloat
, bool isSigned
)
257 bitSize
= src
.ssa
->bit_size
;
259 bitSize
= src
.reg
.reg
->bit_size
;
261 DataType ty
= typeOfSize(bitSize
/ 8, isFloat
, isSigned
);
262 if (ty
== TYPE_NONE
) {
270 ERROR("couldn't get Type for %s with bitSize %u\n", str
, bitSize
);
277 Converter::convert(nir_dest
*dest
)
280 return convert(&dest
->ssa
);
281 if (dest
->reg
.indirect
) {
282 ERROR("no support for indirects.");
285 return convert(dest
->reg
.reg
);
289 Converter::convert(nir_register
*reg
)
291 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
292 if (it
!= regDefs
.end())
295 LValues
newDef(reg
->num_components
);
296 for (uint8_t i
= 0; i
< reg
->num_components
; i
++)
297 newDef
[i
] = getScratch(std::max(4, reg
->bit_size
/ 8));
298 return regDefs
[reg
->index
] = newDef
;
302 Converter::convert(nir_ssa_def
*def
)
304 NirDefMap::iterator it
= ssaDefs
.find(def
->index
);
305 if (it
!= ssaDefs
.end())
308 LValues
newDef(def
->num_components
);
309 for (uint8_t i
= 0; i
< def
->num_components
; i
++)
310 newDef
[i
] = getSSA(std::max(4, def
->bit_size
/ 8));
311 return ssaDefs
[def
->index
] = newDef
;
315 Converter::getSrc(nir_alu_src
*src
, uint8_t component
)
317 if (src
->abs
|| src
->negate
) {
318 ERROR("modifiers currently not supported on nir_alu_src\n");
321 return getSrc(&src
->src
, src
->swizzle
[component
]);
325 Converter::getSrc(nir_register
*reg
, uint8_t idx
)
327 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
328 if (it
== regDefs
.end())
329 return convert(reg
)[idx
];
330 return it
->second
[idx
];
334 Converter::getSrc(nir_src
*src
, uint8_t idx
, bool indirect
)
337 return getSrc(src
->ssa
, idx
);
339 if (src
->reg
.indirect
) {
341 return getSrc(src
->reg
.indirect
, idx
);
342 ERROR("no support for indirects.");
347 return getSrc(src
->reg
.reg
, idx
);
351 Converter::getSrc(nir_ssa_def
*src
, uint8_t idx
)
353 NirDefMap::iterator it
= ssaDefs
.find(src
->index
);
354 if (it
== ssaDefs
.end()) {
355 ERROR("SSA value %u not found\n", src
->index
);
359 return it
->second
[idx
];
363 Converter::getIndirect(nir_src
*src
, uint8_t idx
, Value
*&indirect
)
365 nir_const_value
*offset
= nir_src_as_const_value(*src
);
369 return offset
->u32
[0];
372 indirect
= getSrc(src
, idx
, true);
377 Converter::getIndirect(nir_intrinsic_instr
*insn
, uint8_t s
, uint8_t c
, Value
*&indirect
)
379 int32_t idx
= nir_intrinsic_base(insn
) + getIndirect(&insn
->src
[s
], c
, indirect
);
381 indirect
= mkOp2v(OP_SHL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), indirect
, loadImm(NULL
, 4));
386 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot
, unsigned *name
, unsigned *index
)
388 assert(name
&& index
);
390 if (slot
>= VERT_ATTRIB_MAX
) {
391 ERROR("invalid varying slot %u\n", slot
);
396 if (slot
>= VERT_ATTRIB_GENERIC0
&&
397 slot
< VERT_ATTRIB_GENERIC0
+ VERT_ATTRIB_GENERIC_MAX
) {
398 *name
= TGSI_SEMANTIC_GENERIC
;
399 *index
= slot
- VERT_ATTRIB_GENERIC0
;
403 if (slot
>= VERT_ATTRIB_TEX0
&&
404 slot
< VERT_ATTRIB_TEX0
+ VERT_ATTRIB_TEX_MAX
) {
405 *name
= TGSI_SEMANTIC_TEXCOORD
;
406 *index
= slot
- VERT_ATTRIB_TEX0
;
411 case VERT_ATTRIB_COLOR0
:
412 *name
= TGSI_SEMANTIC_COLOR
;
415 case VERT_ATTRIB_COLOR1
:
416 *name
= TGSI_SEMANTIC_COLOR
;
419 case VERT_ATTRIB_EDGEFLAG
:
420 *name
= TGSI_SEMANTIC_EDGEFLAG
;
423 case VERT_ATTRIB_FOG
:
424 *name
= TGSI_SEMANTIC_FOG
;
427 case VERT_ATTRIB_NORMAL
:
428 *name
= TGSI_SEMANTIC_NORMAL
;
431 case VERT_ATTRIB_POS
:
432 *name
= TGSI_SEMANTIC_POSITION
;
435 case VERT_ATTRIB_POINT_SIZE
:
436 *name
= TGSI_SEMANTIC_PSIZE
;
440 ERROR("unknown vert attrib slot %u\n", slot
);
447 varying_slot_to_tgsi_semantic(gl_varying_slot slot
, unsigned *name
, unsigned *index
)
449 assert(name
&& index
);
451 if (slot
>= VARYING_SLOT_TESS_MAX
) {
452 ERROR("invalid varying slot %u\n", slot
);
457 if (slot
>= VARYING_SLOT_PATCH0
) {
458 *name
= TGSI_SEMANTIC_PATCH
;
459 *index
= slot
- VARYING_SLOT_PATCH0
;
463 if (slot
>= VARYING_SLOT_VAR0
) {
464 *name
= TGSI_SEMANTIC_GENERIC
;
465 *index
= slot
- VARYING_SLOT_VAR0
;
469 if (slot
>= VARYING_SLOT_TEX0
&& slot
<= VARYING_SLOT_TEX7
) {
470 *name
= TGSI_SEMANTIC_TEXCOORD
;
471 *index
= slot
- VARYING_SLOT_TEX0
;
476 case VARYING_SLOT_BFC0
:
477 *name
= TGSI_SEMANTIC_BCOLOR
;
480 case VARYING_SLOT_BFC1
:
481 *name
= TGSI_SEMANTIC_BCOLOR
;
484 case VARYING_SLOT_CLIP_DIST0
:
485 *name
= TGSI_SEMANTIC_CLIPDIST
;
488 case VARYING_SLOT_CLIP_DIST1
:
489 *name
= TGSI_SEMANTIC_CLIPDIST
;
492 case VARYING_SLOT_CLIP_VERTEX
:
493 *name
= TGSI_SEMANTIC_CLIPVERTEX
;
496 case VARYING_SLOT_COL0
:
497 *name
= TGSI_SEMANTIC_COLOR
;
500 case VARYING_SLOT_COL1
:
501 *name
= TGSI_SEMANTIC_COLOR
;
504 case VARYING_SLOT_EDGE
:
505 *name
= TGSI_SEMANTIC_EDGEFLAG
;
508 case VARYING_SLOT_FACE
:
509 *name
= TGSI_SEMANTIC_FACE
;
512 case VARYING_SLOT_FOGC
:
513 *name
= TGSI_SEMANTIC_FOG
;
516 case VARYING_SLOT_LAYER
:
517 *name
= TGSI_SEMANTIC_LAYER
;
520 case VARYING_SLOT_PNTC
:
521 *name
= TGSI_SEMANTIC_PCOORD
;
524 case VARYING_SLOT_POS
:
525 *name
= TGSI_SEMANTIC_POSITION
;
528 case VARYING_SLOT_PRIMITIVE_ID
:
529 *name
= TGSI_SEMANTIC_PRIMID
;
532 case VARYING_SLOT_PSIZ
:
533 *name
= TGSI_SEMANTIC_PSIZE
;
536 case VARYING_SLOT_TESS_LEVEL_INNER
:
537 *name
= TGSI_SEMANTIC_TESSINNER
;
540 case VARYING_SLOT_TESS_LEVEL_OUTER
:
541 *name
= TGSI_SEMANTIC_TESSOUTER
;
544 case VARYING_SLOT_VIEWPORT
:
545 *name
= TGSI_SEMANTIC_VIEWPORT_INDEX
;
549 ERROR("unknown varying slot %u\n", slot
);
556 frag_result_to_tgsi_semantic(unsigned slot
, unsigned *name
, unsigned *index
)
558 if (slot
>= FRAG_RESULT_DATA0
) {
559 *name
= TGSI_SEMANTIC_COLOR
;
560 *index
= slot
- FRAG_RESULT_COLOR
- 2; // intentional
565 case FRAG_RESULT_COLOR
:
566 *name
= TGSI_SEMANTIC_COLOR
;
569 case FRAG_RESULT_DEPTH
:
570 *name
= TGSI_SEMANTIC_POSITION
;
573 case FRAG_RESULT_SAMPLE_MASK
:
574 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
578 ERROR("unknown frag result slot %u\n", slot
);
584 // copy of _mesa_sysval_to_semantic
586 system_val_to_tgsi_semantic(unsigned val
, unsigned *name
, unsigned *index
)
591 case SYSTEM_VALUE_VERTEX_ID
:
592 *name
= TGSI_SEMANTIC_VERTEXID
;
594 case SYSTEM_VALUE_INSTANCE_ID
:
595 *name
= TGSI_SEMANTIC_INSTANCEID
;
597 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
598 *name
= TGSI_SEMANTIC_VERTEXID_NOBASE
;
600 case SYSTEM_VALUE_BASE_VERTEX
:
601 *name
= TGSI_SEMANTIC_BASEVERTEX
;
603 case SYSTEM_VALUE_BASE_INSTANCE
:
604 *name
= TGSI_SEMANTIC_BASEINSTANCE
;
606 case SYSTEM_VALUE_DRAW_ID
:
607 *name
= TGSI_SEMANTIC_DRAWID
;
611 case SYSTEM_VALUE_INVOCATION_ID
:
612 *name
= TGSI_SEMANTIC_INVOCATIONID
;
616 case SYSTEM_VALUE_FRAG_COORD
:
617 *name
= TGSI_SEMANTIC_POSITION
;
619 case SYSTEM_VALUE_FRONT_FACE
:
620 *name
= TGSI_SEMANTIC_FACE
;
622 case SYSTEM_VALUE_SAMPLE_ID
:
623 *name
= TGSI_SEMANTIC_SAMPLEID
;
625 case SYSTEM_VALUE_SAMPLE_POS
:
626 *name
= TGSI_SEMANTIC_SAMPLEPOS
;
628 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
629 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
631 case SYSTEM_VALUE_HELPER_INVOCATION
:
632 *name
= TGSI_SEMANTIC_HELPER_INVOCATION
;
635 // Tessellation shader
636 case SYSTEM_VALUE_TESS_COORD
:
637 *name
= TGSI_SEMANTIC_TESSCOORD
;
639 case SYSTEM_VALUE_VERTICES_IN
:
640 *name
= TGSI_SEMANTIC_VERTICESIN
;
642 case SYSTEM_VALUE_PRIMITIVE_ID
:
643 *name
= TGSI_SEMANTIC_PRIMID
;
645 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
646 *name
= TGSI_SEMANTIC_TESSOUTER
;
648 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
649 *name
= TGSI_SEMANTIC_TESSINNER
;
653 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
654 *name
= TGSI_SEMANTIC_THREAD_ID
;
656 case SYSTEM_VALUE_WORK_GROUP_ID
:
657 *name
= TGSI_SEMANTIC_BLOCK_ID
;
659 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
660 *name
= TGSI_SEMANTIC_GRID_SIZE
;
662 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
663 *name
= TGSI_SEMANTIC_BLOCK_SIZE
;
667 case SYSTEM_VALUE_SUBGROUP_SIZE
:
668 *name
= TGSI_SEMANTIC_SUBGROUP_SIZE
;
670 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
671 *name
= TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
673 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
674 *name
= TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
676 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
677 *name
= TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
679 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
680 *name
= TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
682 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
683 *name
= TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
685 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
686 *name
= TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
690 ERROR("unknown system value %u\n", val
);
697 Converter::setInterpolate(nv50_ir_varying
*var
,
703 case INTERP_MODE_FLAT
:
706 case INTERP_MODE_NONE
:
707 if (semantic
== TGSI_SEMANTIC_COLOR
)
709 else if (semantic
== TGSI_SEMANTIC_POSITION
)
712 case INTERP_MODE_NOPERSPECTIVE
:
715 case INTERP_MODE_SMOOTH
:
718 var
->centroid
= centroid
;
722 calcSlots(const glsl_type
*type
, Program::Type stage
, const shader_info
&info
,
723 bool input
, const nir_variable
*var
)
725 if (!type
->is_array())
726 return type
->count_attribute_slots(false);
730 case Program::TYPE_GEOMETRY
:
731 slots
= type
->uniform_locations();
733 slots
/= info
.gs
.vertices_in
;
735 case Program::TYPE_TESSELLATION_CONTROL
:
736 case Program::TYPE_TESSELLATION_EVAL
:
737 // remove first dimension
738 if (var
->data
.patch
|| (!input
&& stage
== Program::TYPE_TESSELLATION_EVAL
))
739 slots
= type
->uniform_locations();
741 slots
= type
->fields
.array
->uniform_locations();
744 slots
= type
->count_attribute_slots(false);
751 bool Converter::assignSlots() {
755 info
->io
.viewportId
= -1;
758 // we have to fixup the uniform locations for arrays
759 unsigned numImages
= 0;
760 nir_foreach_variable(var
, &nir
->uniforms
) {
761 const glsl_type
*type
= var
->type
;
762 if (!type
->without_array()->is_image())
764 var
->data
.driver_location
= numImages
;
765 numImages
+= type
->is_array() ? type
->arrays_of_arrays_size() : 1;
768 nir_foreach_variable(var
, &nir
->inputs
) {
769 const glsl_type
*type
= var
->type
;
770 int slot
= var
->data
.location
;
771 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, true, var
);
772 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
773 : type
->component_slots();
774 uint32_t frac
= var
->data
.location_frac
;
775 uint32_t vary
= var
->data
.driver_location
;
777 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
782 assert(vary
+ slots
<= PIPE_MAX_SHADER_INPUTS
);
784 switch(prog
->getType()) {
785 case Program::TYPE_FRAGMENT
:
786 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
787 for (uint16_t i
= 0; i
< slots
; ++i
) {
788 setInterpolate(&info
->in
[vary
+ i
], var
->data
.interpolation
,
789 var
->data
.centroid
| var
->data
.sample
, name
);
792 case Program::TYPE_GEOMETRY
:
793 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
795 case Program::TYPE_TESSELLATION_CONTROL
:
796 case Program::TYPE_TESSELLATION_EVAL
:
797 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
798 if (var
->data
.patch
&& name
== TGSI_SEMANTIC_PATCH
)
799 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
801 case Program::TYPE_VERTEX
:
802 vert_attrib_to_tgsi_semantic((gl_vert_attrib
)slot
, &name
, &index
);
804 case TGSI_SEMANTIC_EDGEFLAG
:
805 info
->io
.edgeFlagIn
= vary
;
812 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
816 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
817 info
->in
[vary
].id
= vary
;
818 info
->in
[vary
].patch
= var
->data
.patch
;
819 info
->in
[vary
].sn
= name
;
820 info
->in
[vary
].si
= index
+ i
;
821 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
823 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
825 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
827 info
->in
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
829 info
->numInputs
= std::max
<uint8_t>(info
->numInputs
, vary
);
832 info
->numOutputs
= 0;
833 nir_foreach_variable(var
, &nir
->outputs
) {
834 const glsl_type
*type
= var
->type
;
835 int slot
= var
->data
.location
;
836 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, false, var
);
837 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
838 : type
->component_slots();
839 uint32_t frac
= var
->data
.location_frac
;
840 uint32_t vary
= var
->data
.driver_location
;
842 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
847 assert(vary
< PIPE_MAX_SHADER_OUTPUTS
);
849 switch(prog
->getType()) {
850 case Program::TYPE_FRAGMENT
:
851 frag_result_to_tgsi_semantic((gl_frag_result
)slot
, &name
, &index
);
853 case TGSI_SEMANTIC_COLOR
:
854 if (!var
->data
.fb_fetch_output
)
855 info
->prop
.fp
.numColourResults
++;
856 info
->prop
.fp
.separateFragData
= true;
857 // sometimes we get FRAG_RESULT_DATAX with data.index 0
858 // sometimes we get FRAG_RESULT_DATA0 with data.index X
859 index
= index
== 0 ? var
->data
.index
: index
;
861 case TGSI_SEMANTIC_POSITION
:
862 info
->io
.fragDepth
= vary
;
863 info
->prop
.fp
.writesDepth
= true;
865 case TGSI_SEMANTIC_SAMPLEMASK
:
866 info
->io
.sampleMask
= vary
;
872 case Program::TYPE_GEOMETRY
:
873 case Program::TYPE_TESSELLATION_CONTROL
:
874 case Program::TYPE_TESSELLATION_EVAL
:
875 case Program::TYPE_VERTEX
:
876 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
878 if (var
->data
.patch
&& name
!= TGSI_SEMANTIC_TESSINNER
&&
879 name
!= TGSI_SEMANTIC_TESSOUTER
)
880 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
883 case TGSI_SEMANTIC_CLIPDIST
:
884 info
->io
.genUserClip
= -1;
886 case TGSI_SEMANTIC_EDGEFLAG
:
887 info
->io
.edgeFlagOut
= vary
;
894 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
898 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
899 info
->out
[vary
].id
= vary
;
900 info
->out
[vary
].patch
= var
->data
.patch
;
901 info
->out
[vary
].sn
= name
;
902 info
->out
[vary
].si
= index
+ i
;
903 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
905 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
907 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
909 info
->out
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
911 if (nir
->info
.outputs_read
& 1ll << slot
)
912 info
->out
[vary
].oread
= 1;
914 info
->numOutputs
= std::max
<uint8_t>(info
->numOutputs
, vary
);
917 info
->numSysVals
= 0;
918 for (uint8_t i
= 0; i
< 64; ++i
) {
919 if (!(nir
->info
.system_values_read
& 1ll << i
))
922 system_val_to_tgsi_semantic(i
, &name
, &index
);
923 info
->sv
[info
->numSysVals
].sn
= name
;
924 info
->sv
[info
->numSysVals
].si
= index
;
925 info
->sv
[info
->numSysVals
].input
= 0; // TODO inferSysValDirection(sn);
928 case SYSTEM_VALUE_INSTANCE_ID
:
929 info
->io
.instanceId
= info
->numSysVals
;
931 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
932 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
933 info
->sv
[info
->numSysVals
].patch
= 1;
935 case SYSTEM_VALUE_VERTEX_ID
:
936 info
->io
.vertexId
= info
->numSysVals
;
942 info
->numSysVals
+= 1;
945 if (info
->io
.genUserClip
> 0) {
946 info
->io
.clipDistances
= info
->io
.genUserClip
;
948 const unsigned int nOut
= (info
->io
.genUserClip
+ 3) / 4;
950 for (unsigned int n
= 0; n
< nOut
; ++n
) {
951 unsigned int i
= info
->numOutputs
++;
953 info
->out
[i
].sn
= TGSI_SEMANTIC_CLIPDIST
;
955 info
->out
[i
].mask
= ((1 << info
->io
.clipDistances
) - 1) >> (n
* 4);
959 return info
->assignSlots(info
) == 0;
963 Converter::getSlotAddress(nir_intrinsic_instr
*insn
, uint8_t idx
, uint8_t slot
)
966 int offset
= nir_intrinsic_component(insn
);
969 if (nir_intrinsic_infos
[insn
->intrinsic
].has_dest
)
972 ty
= getSType(insn
->src
[0], false, false);
974 switch (insn
->intrinsic
) {
975 case nir_intrinsic_load_input
:
976 case nir_intrinsic_load_interpolated_input
:
977 case nir_intrinsic_load_per_vertex_input
:
980 case nir_intrinsic_load_output
:
981 case nir_intrinsic_load_per_vertex_output
:
982 case nir_intrinsic_store_output
:
983 case nir_intrinsic_store_per_vertex_output
:
987 ERROR("unknown intrinsic in getSlotAddress %s",
988 nir_intrinsic_infos
[insn
->intrinsic
].name
);
994 if (typeSizeof(ty
) == 8) {
1006 assert(!input
|| idx
< PIPE_MAX_SHADER_INPUTS
);
1007 assert(input
|| idx
< PIPE_MAX_SHADER_OUTPUTS
);
1009 const nv50_ir_varying
*vary
= input
? info
->in
: info
->out
;
1010 return vary
[idx
].slot
[slot
] * 4;
1014 Converter::loadFrom(DataFile file
, uint8_t i
, DataType ty
, Value
*def
,
1015 uint32_t base
, uint8_t c
, Value
*indirect0
,
1016 Value
*indirect1
, bool patch
)
1018 unsigned int tySize
= typeSizeof(ty
);
1021 (file
== FILE_MEMORY_CONST
|| file
== FILE_MEMORY_BUFFER
|| indirect0
)) {
1022 Value
*lo
= getSSA();
1023 Value
*hi
= getSSA();
1026 mkLoad(TYPE_U32
, lo
,
1027 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
),
1029 loi
->setIndirect(0, 1, indirect1
);
1030 loi
->perPatch
= patch
;
1033 mkLoad(TYPE_U32
, hi
,
1034 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
+ 4),
1036 hii
->setIndirect(0, 1, indirect1
);
1037 hii
->perPatch
= patch
;
1039 return mkOp2(OP_MERGE
, ty
, def
, lo
, hi
);
1042 mkLoad(ty
, def
, mkSymbol(file
, i
, ty
, base
+ c
* tySize
), indirect0
);
1043 ld
->setIndirect(0, 1, indirect1
);
1044 ld
->perPatch
= patch
;
1050 Converter::storeTo(nir_intrinsic_instr
*insn
, DataFile file
, operation op
,
1051 DataType ty
, Value
*src
, uint8_t idx
, uint8_t c
,
1052 Value
*indirect0
, Value
*indirect1
)
1054 uint8_t size
= typeSizeof(ty
);
1055 uint32_t address
= getSlotAddress(insn
, idx
, c
);
1057 if (size
== 8 && indirect0
) {
1059 mkSplit(split
, 4, src
);
1061 if (op
== OP_EXPORT
) {
1062 split
[0] = mkMov(getSSA(), split
[0], ty
)->getDef(0);
1063 split
[1] = mkMov(getSSA(), split
[1], ty
)->getDef(0);
1066 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
), indirect0
,
1067 split
[0])->perPatch
= info
->out
[idx
].patch
;
1068 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
+ 4), indirect0
,
1069 split
[1])->perPatch
= info
->out
[idx
].patch
;
1071 if (op
== OP_EXPORT
)
1072 src
= mkMov(getSSA(size
), src
, ty
)->getDef(0);
1073 mkStore(op
, ty
, mkSymbol(file
, 0, ty
, address
), indirect0
,
1074 src
)->perPatch
= info
->out
[idx
].patch
;
1079 Converter::parseNIR()
1081 info
->io
.clipDistances
= nir
->info
.clip_distance_array_size
;
1082 info
->io
.cullDistances
= nir
->info
.cull_distance_array_size
;
1084 switch(prog
->getType()) {
1085 case Program::TYPE_COMPUTE
:
1086 info
->prop
.cp
.numThreads
[0] = nir
->info
.cs
.local_size
[0];
1087 info
->prop
.cp
.numThreads
[1] = nir
->info
.cs
.local_size
[1];
1088 info
->prop
.cp
.numThreads
[2] = nir
->info
.cs
.local_size
[2];
1089 info
->bin
.smemSize
= nir
->info
.cs
.shared_size
;
1091 case Program::TYPE_FRAGMENT
:
1092 info
->prop
.fp
.earlyFragTests
= nir
->info
.fs
.early_fragment_tests
;
1093 info
->prop
.fp
.persampleInvocation
=
1094 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_ID
) ||
1095 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1096 info
->prop
.fp
.postDepthCoverage
= nir
->info
.fs
.post_depth_coverage
;
1097 info
->prop
.fp
.readsSampleLocations
=
1098 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1099 info
->prop
.fp
.usesDiscard
= nir
->info
.fs
.uses_discard
;
1100 info
->prop
.fp
.usesSampleMaskIn
=
1101 !!(nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
);
1103 case Program::TYPE_GEOMETRY
:
1104 info
->prop
.gp
.inputPrim
= nir
->info
.gs
.input_primitive
;
1105 info
->prop
.gp
.instanceCount
= nir
->info
.gs
.invocations
;
1106 info
->prop
.gp
.maxVertices
= nir
->info
.gs
.vertices_out
;
1107 info
->prop
.gp
.outputPrim
= nir
->info
.gs
.output_primitive
;
1109 case Program::TYPE_TESSELLATION_CONTROL
:
1110 case Program::TYPE_TESSELLATION_EVAL
:
1111 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1112 info
->prop
.tp
.domain
= GL_LINES
;
1114 info
->prop
.tp
.domain
= nir
->info
.tess
.primitive_mode
;
1115 info
->prop
.tp
.outputPatchSize
= nir
->info
.tess
.tcs_vertices_out
;
1116 info
->prop
.tp
.outputPrim
=
1117 nir
->info
.tess
.point_mode
? PIPE_PRIM_POINTS
: PIPE_PRIM_TRIANGLES
;
1118 info
->prop
.tp
.partitioning
= (nir
->info
.tess
.spacing
+ 1) % 3;
1119 info
->prop
.tp
.winding
= !nir
->info
.tess
.ccw
;
1121 case Program::TYPE_VERTEX
:
1122 info
->prop
.vp
.usesDrawParameters
=
1123 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
)) ||
1124 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
)) ||
1125 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
));
1135 Converter::visit(nir_function
*function
)
1137 // we only support emiting the main function for now
1138 assert(!strcmp(function
->name
, "main"));
1139 assert(function
->impl
);
1141 // usually the blocks will set everything up, but main is special
1142 BasicBlock
*entry
= new BasicBlock(prog
->main
);
1143 exit
= new BasicBlock(prog
->main
);
1144 blocks
[nir_start_block(function
->impl
)->index
] = entry
;
1145 prog
->main
->setEntry(entry
);
1146 prog
->main
->setExit(exit
);
1148 setPosition(entry
, true);
1150 switch (prog
->getType()) {
1151 case Program::TYPE_TESSELLATION_CONTROL
:
1153 OP_SUB
, TYPE_U32
, getSSA(),
1154 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LANEID
, 0)),
1155 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_INVOCATION_ID
, 0)));
1157 case Program::TYPE_FRAGMENT
: {
1158 Symbol
*sv
= mkSysVal(SV_POSITION
, 3);
1159 fragCoord
[3] = mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), sv
);
1160 fp
.position
= mkOp1v(OP_RCP
, TYPE_F32
, fragCoord
[3], fragCoord
[3]);
1167 nir_index_ssa_defs(function
->impl
);
1168 foreach_list_typed(nir_cf_node
, node
, node
, &function
->impl
->body
) {
1173 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::TREE
);
1174 setPosition(exit
, true);
1176 // TODO: for non main function this needs to be a OP_RETURN
1177 mkOp(OP_EXIT
, TYPE_NONE
, NULL
)->terminator
= 1;
1182 Converter::visit(nir_cf_node
*node
)
1184 switch (node
->type
) {
1185 case nir_cf_node_block
:
1186 return visit(nir_cf_node_as_block(node
));
1187 case nir_cf_node_if
:
1188 return visit(nir_cf_node_as_if(node
));
1189 case nir_cf_node_loop
:
1190 return visit(nir_cf_node_as_loop(node
));
1192 ERROR("unknown nir_cf_node type %u\n", node
->type
);
1198 Converter::visit(nir_block
*block
)
1200 if (!block
->predecessors
->entries
&& block
->instr_list
.is_empty())
1203 BasicBlock
*bb
= convert(block
);
1205 setPosition(bb
, true);
1206 nir_foreach_instr(insn
, block
) {
1214 Converter::visit(nir_if
*nif
)
1216 DataType sType
= getSType(nif
->condition
, false, false);
1217 Value
*src
= getSrc(&nif
->condition
, 0);
1219 nir_block
*lastThen
= nir_if_last_then_block(nif
);
1220 nir_block
*lastElse
= nir_if_last_else_block(nif
);
1222 assert(!lastThen
->successors
[1]);
1223 assert(!lastElse
->successors
[1]);
1225 BasicBlock
*ifBB
= convert(nir_if_first_then_block(nif
));
1226 BasicBlock
*elseBB
= convert(nir_if_first_else_block(nif
));
1228 bb
->cfg
.attach(&ifBB
->cfg
, Graph::Edge::TREE
);
1229 bb
->cfg
.attach(&elseBB
->cfg
, Graph::Edge::TREE
);
1231 // we only insert joinats, if both nodes end up at the end of the if again.
1232 // the reason for this to not happens are breaks/continues/ret/... which
1233 // have their own handling
1234 if (lastThen
->successors
[0] == lastElse
->successors
[0])
1235 bb
->joinAt
= mkFlow(OP_JOINAT
, convert(lastThen
->successors
[0]),
1238 mkFlow(OP_BRA
, elseBB
, CC_EQ
, src
)->setType(sType
);
1240 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->then_list
) {
1244 setPosition(convert(lastThen
), true);
1245 if (!bb
->getExit() ||
1246 !bb
->getExit()->asFlow() ||
1247 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1248 BasicBlock
*tailBB
= convert(lastThen
->successors
[0]);
1249 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1250 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1253 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->else_list
) {
1257 setPosition(convert(lastElse
), true);
1258 if (!bb
->getExit() ||
1259 !bb
->getExit()->asFlow() ||
1260 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1261 BasicBlock
*tailBB
= convert(lastElse
->successors
[0]);
1262 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1263 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1266 if (lastThen
->successors
[0] == lastElse
->successors
[0]) {
1267 setPosition(convert(lastThen
->successors
[0]), true);
1268 mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1275 Converter::visit(nir_loop
*loop
)
1278 func
->loopNestingBound
= std::max(func
->loopNestingBound
, curLoopDepth
);
1280 BasicBlock
*loopBB
= convert(nir_loop_first_block(loop
));
1281 BasicBlock
*tailBB
=
1282 convert(nir_cf_node_as_block(nir_cf_node_next(&loop
->cf_node
)));
1283 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::TREE
);
1285 mkFlow(OP_PREBREAK
, tailBB
, CC_ALWAYS
, NULL
);
1286 setPosition(loopBB
, false);
1287 mkFlow(OP_PRECONT
, loopBB
, CC_ALWAYS
, NULL
);
1289 foreach_list_typed(nir_cf_node
, node
, node
, &loop
->body
) {
1293 Instruction
*insn
= bb
->getExit();
1294 if (bb
->cfg
.incidentCount() != 0) {
1295 if (!insn
|| !insn
->asFlow()) {
1296 mkFlow(OP_CONT
, loopBB
, CC_ALWAYS
, NULL
);
1297 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::BACK
);
1298 } else if (insn
&& insn
->op
== OP_BRA
&& !insn
->getPredicate() &&
1299 tailBB
->cfg
.incidentCount() == 0) {
1300 // RA doesn't like having blocks around with no incident edge,
1301 // so we create a fake one to make it happy
1302 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::TREE
);
1312 Converter::visit(nir_instr
*insn
)
1314 switch (insn
->type
) {
1315 case nir_instr_type_jump
:
1316 return visit(nir_instr_as_jump(insn
));
1318 ERROR("unknown nir_instr type %u\n", insn
->type
);
1325 Converter::visit(nir_jump_instr
*insn
)
1327 switch (insn
->type
) {
1328 case nir_jump_return
:
1329 // TODO: this only works in the main function
1330 mkFlow(OP_BRA
, exit
, CC_ALWAYS
, NULL
);
1331 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::CROSS
);
1333 case nir_jump_break
:
1334 case nir_jump_continue
: {
1335 bool isBreak
= insn
->type
== nir_jump_break
;
1336 nir_block
*block
= insn
->instr
.block
;
1337 assert(!block
->successors
[1]);
1338 BasicBlock
*target
= convert(block
->successors
[0]);
1339 mkFlow(isBreak
? OP_BREAK
: OP_CONT
, target
, CC_ALWAYS
, NULL
);
1340 bb
->cfg
.attach(&target
->cfg
, isBreak
? Graph::Edge::CROSS
: Graph::Edge::BACK
);
1344 ERROR("unknown nir_jump_type %u\n", insn
->type
);
1356 if (prog
->dbgFlags
& NV50_IR_DEBUG_VERBOSE
)
1357 nir_print_shader(nir
, stderr
);
1359 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, type_size
, (nir_lower_io_options
)0);
1360 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
);
1361 NIR_PASS_V(nir
, nir_lower_load_const_to_scalar
);
1362 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
1363 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
);
1364 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
1368 NIR_PASS(progress
, nir
, nir_copy_prop
);
1369 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
1370 NIR_PASS(progress
, nir
, nir_opt_trivial_continues
);
1371 NIR_PASS(progress
, nir
, nir_opt_cse
);
1372 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
1373 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
1374 NIR_PASS(progress
, nir
, nir_copy_prop
);
1375 NIR_PASS(progress
, nir
, nir_opt_dce
);
1376 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
1379 NIR_PASS_V(nir
, nir_lower_bool_to_int32
);
1380 NIR_PASS_V(nir
, nir_lower_locals_to_regs
);
1381 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
);
1382 NIR_PASS_V(nir
, nir_convert_from_ssa
, true);
1384 // Garbage collect dead instructions
1388 ERROR("Couldn't prase NIR!\n");
1392 if (!assignSlots()) {
1393 ERROR("Couldn't assign slots!\n");
1397 if (prog
->dbgFlags
& NV50_IR_DEBUG_BASIC
)
1398 nir_print_shader(nir
, stderr
);
1400 nir_foreach_function(function
, nir
) {
1401 if (!visit(function
))
1408 } // unnamed namespace
1413 Program::makeFromNIR(struct nv50_ir_prog_info
*info
)
1415 nir_shader
*nir
= (nir_shader
*)info
->bin
.source
;
1416 Converter
converter(this, nir
, info
);
1417 bool result
= converter
.run();
1420 LoweringHelper lowering
;
1422 tlsSize
= info
->bin
.tlsSpace
;
1426 } // namespace nv50_ir