2 * Copyright 2017 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Karol Herbst <kherbst@redhat.com>
25 #include "compiler/nir/nir.h"
27 #include "util/u_debug.h"
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_from_common.h"
31 #include "codegen/nv50_ir_lowering_helper.h"
32 #include "codegen/nv50_ir_util.h"
34 #if __cplusplus >= 201103L
35 #include <unordered_map>
37 #include <tr1/unordered_map>
43 #if __cplusplus >= 201103L
45 using std::unordered_map
;
48 using std::tr1::unordered_map
;
51 using namespace nv50_ir
;
54 type_size(const struct glsl_type
*type
)
56 return glsl_count_attribute_slots(type
, false);
59 class Converter
: public ConverterCommon
62 Converter(Program
*, nir_shader
*, nv50_ir_prog_info
*);
66 typedef std::vector
<LValue
*> LValues
;
67 typedef unordered_map
<unsigned, LValues
> NirDefMap
;
68 typedef unordered_map
<unsigned, BasicBlock
*> NirBlockMap
;
70 TexTarget
convert(glsl_sampler_dim
, bool isArray
, bool isShadow
);
71 LValues
& convert(nir_alu_dest
*);
72 BasicBlock
* convert(nir_block
*);
73 LValues
& convert(nir_dest
*);
74 SVSemantic
convert(nir_intrinsic_op
);
75 LValues
& convert(nir_register
*);
76 LValues
& convert(nir_ssa_def
*);
78 Value
* getSrc(nir_alu_src
*, uint8_t component
= 0);
79 Value
* getSrc(nir_register
*, uint8_t);
80 Value
* getSrc(nir_src
*, uint8_t, bool indirect
= false);
81 Value
* getSrc(nir_ssa_def
*, uint8_t);
83 // returned value is the constant part of the given source (either the
84 // nir_src or the selected source component of an intrinsic). Even though
85 // this is mostly an optimization to be able to skip indirects in a few
86 // cases, sometimes we require immediate values or set some fileds on
87 // instructions (e.g. tex) in order for codegen to consume those.
88 // If the found value has not a constant part, the Value gets returned
89 // through the Value parameter.
90 uint32_t getIndirect(nir_src
*, uint8_t, Value
*&);
91 uint32_t getIndirect(nir_intrinsic_instr
*, uint8_t s
, uint8_t c
, Value
*&);
93 uint32_t getSlotAddress(nir_intrinsic_instr
*, uint8_t idx
, uint8_t slot
);
95 void setInterpolate(nv50_ir_varying
*,
100 Instruction
*loadFrom(DataFile
, uint8_t, DataType
, Value
*def
, uint32_t base
,
101 uint8_t c
, Value
*indirect0
= NULL
,
102 Value
*indirect1
= NULL
, bool patch
= false);
103 void storeTo(nir_intrinsic_instr
*, DataFile
, operation
, DataType
,
104 Value
*src
, uint8_t idx
, uint8_t c
, Value
*indirect0
= NULL
,
105 Value
*indirect1
= NULL
);
107 bool isFloatType(nir_alu_type
);
108 bool isSignedType(nir_alu_type
);
109 bool isResultFloat(nir_op
);
110 bool isResultSigned(nir_op
);
112 DataType
getDType(nir_alu_instr
*);
113 DataType
getDType(nir_intrinsic_instr
*);
114 DataType
getDType(nir_op
, uint8_t);
116 std::vector
<DataType
> getSTypes(nir_alu_instr
*);
117 DataType
getSType(nir_src
&, bool isFloat
, bool isSigned
);
119 operation
getOperation(nir_op
);
120 operation
getOperation(nir_texop
);
121 operation
preOperationNeeded(nir_op
);
123 int getSubOp(nir_op
);
125 CondCode
getCondCode(nir_op
);
130 bool visit(nir_alu_instr
*);
131 bool visit(nir_block
*);
132 bool visit(nir_cf_node
*);
133 bool visit(nir_function
*);
134 bool visit(nir_if
*);
135 bool visit(nir_instr
*);
136 bool visit(nir_intrinsic_instr
*);
137 bool visit(nir_jump_instr
*);
138 bool visit(nir_load_const_instr
*);
139 bool visit(nir_loop
*);
140 bool visit(nir_ssa_undef_instr
*);
141 bool visit(nir_tex_instr
*);
144 Value
* applyProjection(Value
*src
, Value
*proj
);
151 unsigned int curLoopDepth
;
156 int clipVertexOutput
;
165 Converter::Converter(Program
*prog
, nir_shader
*nir
, nv50_ir_prog_info
*info
)
166 : ConverterCommon(prog
, info
),
171 zero
= mkImm((uint32_t)0);
175 Converter::convert(nir_block
*block
)
177 NirBlockMap::iterator it
= blocks
.find(block
->index
);
178 if (it
!= blocks
.end())
181 BasicBlock
*bb
= new BasicBlock(func
);
182 blocks
[block
->index
] = bb
;
187 Converter::isFloatType(nir_alu_type type
)
189 return nir_alu_type_get_base_type(type
) == nir_type_float
;
193 Converter::isSignedType(nir_alu_type type
)
195 return nir_alu_type_get_base_type(type
) == nir_type_int
;
199 Converter::isResultFloat(nir_op op
)
201 const nir_op_info
&info
= nir_op_infos
[op
];
202 if (info
.output_type
!= nir_type_invalid
)
203 return isFloatType(info
.output_type
);
205 ERROR("isResultFloat not implemented for %s\n", nir_op_infos
[op
].name
);
211 Converter::isResultSigned(nir_op op
)
214 // there is no umul and we get wrong results if we treat all muls as signed
219 const nir_op_info
&info
= nir_op_infos
[op
];
220 if (info
.output_type
!= nir_type_invalid
)
221 return isSignedType(info
.output_type
);
222 ERROR("isResultSigned not implemented for %s\n", nir_op_infos
[op
].name
);
229 Converter::getDType(nir_alu_instr
*insn
)
231 if (insn
->dest
.dest
.is_ssa
)
232 return getDType(insn
->op
, insn
->dest
.dest
.ssa
.bit_size
);
234 return getDType(insn
->op
, insn
->dest
.dest
.reg
.reg
->bit_size
);
238 Converter::getDType(nir_intrinsic_instr
*insn
)
240 if (insn
->dest
.is_ssa
)
241 return typeOfSize(insn
->dest
.ssa
.bit_size
/ 8, false, false);
243 return typeOfSize(insn
->dest
.reg
.reg
->bit_size
/ 8, false, false);
247 Converter::getDType(nir_op op
, uint8_t bitSize
)
249 DataType ty
= typeOfSize(bitSize
/ 8, isResultFloat(op
), isResultSigned(op
));
250 if (ty
== TYPE_NONE
) {
251 ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos
[op
].name
, bitSize
);
257 std::vector
<DataType
>
258 Converter::getSTypes(nir_alu_instr
*insn
)
260 const nir_op_info
&info
= nir_op_infos
[insn
->op
];
261 std::vector
<DataType
> res(info
.num_inputs
);
263 for (uint8_t i
= 0; i
< info
.num_inputs
; ++i
) {
264 if (info
.input_types
[i
] != nir_type_invalid
) {
265 res
[i
] = getSType(insn
->src
[i
].src
, isFloatType(info
.input_types
[i
]), isSignedType(info
.input_types
[i
]));
267 ERROR("getSType not implemented for %s idx %u\n", info
.name
, i
);
278 Converter::getSType(nir_src
&src
, bool isFloat
, bool isSigned
)
282 bitSize
= src
.ssa
->bit_size
;
284 bitSize
= src
.reg
.reg
->bit_size
;
286 DataType ty
= typeOfSize(bitSize
/ 8, isFloat
, isSigned
);
287 if (ty
== TYPE_NONE
) {
295 ERROR("couldn't get Type for %s with bitSize %u\n", str
, bitSize
);
302 Converter::getOperation(nir_op op
)
305 // basic ops with float and int variants
315 case nir_op_ifind_msb
:
316 case nir_op_ufind_msb
:
338 case nir_op_fddx_coarse
:
339 case nir_op_fddx_fine
:
342 case nir_op_fddy_coarse
:
343 case nir_op_fddy_fine
:
361 case nir_op_pack_64_2x32_split
:
375 case nir_op_imul_high
:
376 case nir_op_umul_high
:
424 ERROR("couldn't get operation for op %s\n", nir_op_infos
[op
].name
);
431 Converter::getOperation(nir_texop op
)
443 case nir_texop_txf_ms
:
449 case nir_texop_query_levels
:
450 case nir_texop_texture_samples
:
454 ERROR("couldn't get operation for nir_texop %u\n", op
);
461 Converter::preOperationNeeded(nir_op op
)
473 Converter::getSubOp(nir_op op
)
476 case nir_op_imul_high
:
477 case nir_op_umul_high
:
478 return NV50_IR_SUBOP_MUL_HIGH
;
485 Converter::getCondCode(nir_op op
)
504 ERROR("couldn't get CondCode for op %s\n", nir_op_infos
[op
].name
);
511 Converter::convert(nir_alu_dest
*dest
)
513 return convert(&dest
->dest
);
517 Converter::convert(nir_dest
*dest
)
520 return convert(&dest
->ssa
);
521 if (dest
->reg
.indirect
) {
522 ERROR("no support for indirects.");
525 return convert(dest
->reg
.reg
);
529 Converter::convert(nir_register
*reg
)
531 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
532 if (it
!= regDefs
.end())
535 LValues
newDef(reg
->num_components
);
536 for (uint8_t i
= 0; i
< reg
->num_components
; i
++)
537 newDef
[i
] = getScratch(std::max(4, reg
->bit_size
/ 8));
538 return regDefs
[reg
->index
] = newDef
;
542 Converter::convert(nir_ssa_def
*def
)
544 NirDefMap::iterator it
= ssaDefs
.find(def
->index
);
545 if (it
!= ssaDefs
.end())
548 LValues
newDef(def
->num_components
);
549 for (uint8_t i
= 0; i
< def
->num_components
; i
++)
550 newDef
[i
] = getSSA(std::max(4, def
->bit_size
/ 8));
551 return ssaDefs
[def
->index
] = newDef
;
555 Converter::getSrc(nir_alu_src
*src
, uint8_t component
)
557 if (src
->abs
|| src
->negate
) {
558 ERROR("modifiers currently not supported on nir_alu_src\n");
561 return getSrc(&src
->src
, src
->swizzle
[component
]);
565 Converter::getSrc(nir_register
*reg
, uint8_t idx
)
567 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
568 if (it
== regDefs
.end())
569 return convert(reg
)[idx
];
570 return it
->second
[idx
];
574 Converter::getSrc(nir_src
*src
, uint8_t idx
, bool indirect
)
577 return getSrc(src
->ssa
, idx
);
579 if (src
->reg
.indirect
) {
581 return getSrc(src
->reg
.indirect
, idx
);
582 ERROR("no support for indirects.");
587 return getSrc(src
->reg
.reg
, idx
);
591 Converter::getSrc(nir_ssa_def
*src
, uint8_t idx
)
593 NirDefMap::iterator it
= ssaDefs
.find(src
->index
);
594 if (it
== ssaDefs
.end()) {
595 ERROR("SSA value %u not found\n", src
->index
);
599 return it
->second
[idx
];
603 Converter::getIndirect(nir_src
*src
, uint8_t idx
, Value
*&indirect
)
605 nir_const_value
*offset
= nir_src_as_const_value(*src
);
609 return offset
->u32
[0];
612 indirect
= getSrc(src
, idx
, true);
617 Converter::getIndirect(nir_intrinsic_instr
*insn
, uint8_t s
, uint8_t c
, Value
*&indirect
)
619 int32_t idx
= nir_intrinsic_base(insn
) + getIndirect(&insn
->src
[s
], c
, indirect
);
621 indirect
= mkOp2v(OP_SHL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), indirect
, loadImm(NULL
, 4));
626 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot
, unsigned *name
, unsigned *index
)
628 assert(name
&& index
);
630 if (slot
>= VERT_ATTRIB_MAX
) {
631 ERROR("invalid varying slot %u\n", slot
);
636 if (slot
>= VERT_ATTRIB_GENERIC0
&&
637 slot
< VERT_ATTRIB_GENERIC0
+ VERT_ATTRIB_GENERIC_MAX
) {
638 *name
= TGSI_SEMANTIC_GENERIC
;
639 *index
= slot
- VERT_ATTRIB_GENERIC0
;
643 if (slot
>= VERT_ATTRIB_TEX0
&&
644 slot
< VERT_ATTRIB_TEX0
+ VERT_ATTRIB_TEX_MAX
) {
645 *name
= TGSI_SEMANTIC_TEXCOORD
;
646 *index
= slot
- VERT_ATTRIB_TEX0
;
651 case VERT_ATTRIB_COLOR0
:
652 *name
= TGSI_SEMANTIC_COLOR
;
655 case VERT_ATTRIB_COLOR1
:
656 *name
= TGSI_SEMANTIC_COLOR
;
659 case VERT_ATTRIB_EDGEFLAG
:
660 *name
= TGSI_SEMANTIC_EDGEFLAG
;
663 case VERT_ATTRIB_FOG
:
664 *name
= TGSI_SEMANTIC_FOG
;
667 case VERT_ATTRIB_NORMAL
:
668 *name
= TGSI_SEMANTIC_NORMAL
;
671 case VERT_ATTRIB_POS
:
672 *name
= TGSI_SEMANTIC_POSITION
;
675 case VERT_ATTRIB_POINT_SIZE
:
676 *name
= TGSI_SEMANTIC_PSIZE
;
680 ERROR("unknown vert attrib slot %u\n", slot
);
687 varying_slot_to_tgsi_semantic(gl_varying_slot slot
, unsigned *name
, unsigned *index
)
689 assert(name
&& index
);
691 if (slot
>= VARYING_SLOT_TESS_MAX
) {
692 ERROR("invalid varying slot %u\n", slot
);
697 if (slot
>= VARYING_SLOT_PATCH0
) {
698 *name
= TGSI_SEMANTIC_PATCH
;
699 *index
= slot
- VARYING_SLOT_PATCH0
;
703 if (slot
>= VARYING_SLOT_VAR0
) {
704 *name
= TGSI_SEMANTIC_GENERIC
;
705 *index
= slot
- VARYING_SLOT_VAR0
;
709 if (slot
>= VARYING_SLOT_TEX0
&& slot
<= VARYING_SLOT_TEX7
) {
710 *name
= TGSI_SEMANTIC_TEXCOORD
;
711 *index
= slot
- VARYING_SLOT_TEX0
;
716 case VARYING_SLOT_BFC0
:
717 *name
= TGSI_SEMANTIC_BCOLOR
;
720 case VARYING_SLOT_BFC1
:
721 *name
= TGSI_SEMANTIC_BCOLOR
;
724 case VARYING_SLOT_CLIP_DIST0
:
725 *name
= TGSI_SEMANTIC_CLIPDIST
;
728 case VARYING_SLOT_CLIP_DIST1
:
729 *name
= TGSI_SEMANTIC_CLIPDIST
;
732 case VARYING_SLOT_CLIP_VERTEX
:
733 *name
= TGSI_SEMANTIC_CLIPVERTEX
;
736 case VARYING_SLOT_COL0
:
737 *name
= TGSI_SEMANTIC_COLOR
;
740 case VARYING_SLOT_COL1
:
741 *name
= TGSI_SEMANTIC_COLOR
;
744 case VARYING_SLOT_EDGE
:
745 *name
= TGSI_SEMANTIC_EDGEFLAG
;
748 case VARYING_SLOT_FACE
:
749 *name
= TGSI_SEMANTIC_FACE
;
752 case VARYING_SLOT_FOGC
:
753 *name
= TGSI_SEMANTIC_FOG
;
756 case VARYING_SLOT_LAYER
:
757 *name
= TGSI_SEMANTIC_LAYER
;
760 case VARYING_SLOT_PNTC
:
761 *name
= TGSI_SEMANTIC_PCOORD
;
764 case VARYING_SLOT_POS
:
765 *name
= TGSI_SEMANTIC_POSITION
;
768 case VARYING_SLOT_PRIMITIVE_ID
:
769 *name
= TGSI_SEMANTIC_PRIMID
;
772 case VARYING_SLOT_PSIZ
:
773 *name
= TGSI_SEMANTIC_PSIZE
;
776 case VARYING_SLOT_TESS_LEVEL_INNER
:
777 *name
= TGSI_SEMANTIC_TESSINNER
;
780 case VARYING_SLOT_TESS_LEVEL_OUTER
:
781 *name
= TGSI_SEMANTIC_TESSOUTER
;
784 case VARYING_SLOT_VIEWPORT
:
785 *name
= TGSI_SEMANTIC_VIEWPORT_INDEX
;
789 ERROR("unknown varying slot %u\n", slot
);
796 frag_result_to_tgsi_semantic(unsigned slot
, unsigned *name
, unsigned *index
)
798 if (slot
>= FRAG_RESULT_DATA0
) {
799 *name
= TGSI_SEMANTIC_COLOR
;
800 *index
= slot
- FRAG_RESULT_COLOR
- 2; // intentional
805 case FRAG_RESULT_COLOR
:
806 *name
= TGSI_SEMANTIC_COLOR
;
809 case FRAG_RESULT_DEPTH
:
810 *name
= TGSI_SEMANTIC_POSITION
;
813 case FRAG_RESULT_SAMPLE_MASK
:
814 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
818 ERROR("unknown frag result slot %u\n", slot
);
824 // copy of _mesa_sysval_to_semantic
826 system_val_to_tgsi_semantic(unsigned val
, unsigned *name
, unsigned *index
)
831 case SYSTEM_VALUE_VERTEX_ID
:
832 *name
= TGSI_SEMANTIC_VERTEXID
;
834 case SYSTEM_VALUE_INSTANCE_ID
:
835 *name
= TGSI_SEMANTIC_INSTANCEID
;
837 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
838 *name
= TGSI_SEMANTIC_VERTEXID_NOBASE
;
840 case SYSTEM_VALUE_BASE_VERTEX
:
841 *name
= TGSI_SEMANTIC_BASEVERTEX
;
843 case SYSTEM_VALUE_BASE_INSTANCE
:
844 *name
= TGSI_SEMANTIC_BASEINSTANCE
;
846 case SYSTEM_VALUE_DRAW_ID
:
847 *name
= TGSI_SEMANTIC_DRAWID
;
851 case SYSTEM_VALUE_INVOCATION_ID
:
852 *name
= TGSI_SEMANTIC_INVOCATIONID
;
856 case SYSTEM_VALUE_FRAG_COORD
:
857 *name
= TGSI_SEMANTIC_POSITION
;
859 case SYSTEM_VALUE_FRONT_FACE
:
860 *name
= TGSI_SEMANTIC_FACE
;
862 case SYSTEM_VALUE_SAMPLE_ID
:
863 *name
= TGSI_SEMANTIC_SAMPLEID
;
865 case SYSTEM_VALUE_SAMPLE_POS
:
866 *name
= TGSI_SEMANTIC_SAMPLEPOS
;
868 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
869 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
871 case SYSTEM_VALUE_HELPER_INVOCATION
:
872 *name
= TGSI_SEMANTIC_HELPER_INVOCATION
;
875 // Tessellation shader
876 case SYSTEM_VALUE_TESS_COORD
:
877 *name
= TGSI_SEMANTIC_TESSCOORD
;
879 case SYSTEM_VALUE_VERTICES_IN
:
880 *name
= TGSI_SEMANTIC_VERTICESIN
;
882 case SYSTEM_VALUE_PRIMITIVE_ID
:
883 *name
= TGSI_SEMANTIC_PRIMID
;
885 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
886 *name
= TGSI_SEMANTIC_TESSOUTER
;
888 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
889 *name
= TGSI_SEMANTIC_TESSINNER
;
893 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
894 *name
= TGSI_SEMANTIC_THREAD_ID
;
896 case SYSTEM_VALUE_WORK_GROUP_ID
:
897 *name
= TGSI_SEMANTIC_BLOCK_ID
;
899 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
900 *name
= TGSI_SEMANTIC_GRID_SIZE
;
902 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
903 *name
= TGSI_SEMANTIC_BLOCK_SIZE
;
907 case SYSTEM_VALUE_SUBGROUP_SIZE
:
908 *name
= TGSI_SEMANTIC_SUBGROUP_SIZE
;
910 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
911 *name
= TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
913 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
914 *name
= TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
916 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
917 *name
= TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
919 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
920 *name
= TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
922 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
923 *name
= TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
925 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
926 *name
= TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
930 ERROR("unknown system value %u\n", val
);
937 Converter::setInterpolate(nv50_ir_varying
*var
,
943 case INTERP_MODE_FLAT
:
946 case INTERP_MODE_NONE
:
947 if (semantic
== TGSI_SEMANTIC_COLOR
)
949 else if (semantic
== TGSI_SEMANTIC_POSITION
)
952 case INTERP_MODE_NOPERSPECTIVE
:
955 case INTERP_MODE_SMOOTH
:
958 var
->centroid
= centroid
;
962 calcSlots(const glsl_type
*type
, Program::Type stage
, const shader_info
&info
,
963 bool input
, const nir_variable
*var
)
965 if (!type
->is_array())
966 return type
->count_attribute_slots(false);
970 case Program::TYPE_GEOMETRY
:
971 slots
= type
->uniform_locations();
973 slots
/= info
.gs
.vertices_in
;
975 case Program::TYPE_TESSELLATION_CONTROL
:
976 case Program::TYPE_TESSELLATION_EVAL
:
977 // remove first dimension
978 if (var
->data
.patch
|| (!input
&& stage
== Program::TYPE_TESSELLATION_EVAL
))
979 slots
= type
->uniform_locations();
981 slots
= type
->fields
.array
->uniform_locations();
984 slots
= type
->count_attribute_slots(false);
991 bool Converter::assignSlots() {
995 info
->io
.viewportId
= -1;
998 // we have to fixup the uniform locations for arrays
999 unsigned numImages
= 0;
1000 nir_foreach_variable(var
, &nir
->uniforms
) {
1001 const glsl_type
*type
= var
->type
;
1002 if (!type
->without_array()->is_image())
1004 var
->data
.driver_location
= numImages
;
1005 numImages
+= type
->is_array() ? type
->arrays_of_arrays_size() : 1;
1008 nir_foreach_variable(var
, &nir
->inputs
) {
1009 const glsl_type
*type
= var
->type
;
1010 int slot
= var
->data
.location
;
1011 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, true, var
);
1012 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
1013 : type
->component_slots();
1014 uint32_t frac
= var
->data
.location_frac
;
1015 uint32_t vary
= var
->data
.driver_location
;
1017 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
1022 assert(vary
+ slots
<= PIPE_MAX_SHADER_INPUTS
);
1024 switch(prog
->getType()) {
1025 case Program::TYPE_FRAGMENT
:
1026 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1027 for (uint16_t i
= 0; i
< slots
; ++i
) {
1028 setInterpolate(&info
->in
[vary
+ i
], var
->data
.interpolation
,
1029 var
->data
.centroid
| var
->data
.sample
, name
);
1032 case Program::TYPE_GEOMETRY
:
1033 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1035 case Program::TYPE_TESSELLATION_CONTROL
:
1036 case Program::TYPE_TESSELLATION_EVAL
:
1037 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1038 if (var
->data
.patch
&& name
== TGSI_SEMANTIC_PATCH
)
1039 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
1041 case Program::TYPE_VERTEX
:
1042 vert_attrib_to_tgsi_semantic((gl_vert_attrib
)slot
, &name
, &index
);
1044 case TGSI_SEMANTIC_EDGEFLAG
:
1045 info
->io
.edgeFlagIn
= vary
;
1052 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1056 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1057 info
->in
[vary
].id
= vary
;
1058 info
->in
[vary
].patch
= var
->data
.patch
;
1059 info
->in
[vary
].sn
= name
;
1060 info
->in
[vary
].si
= index
+ i
;
1061 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1063 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1065 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1067 info
->in
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1069 info
->numInputs
= std::max
<uint8_t>(info
->numInputs
, vary
);
1072 info
->numOutputs
= 0;
1073 nir_foreach_variable(var
, &nir
->outputs
) {
1074 const glsl_type
*type
= var
->type
;
1075 int slot
= var
->data
.location
;
1076 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, false, var
);
1077 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
1078 : type
->component_slots();
1079 uint32_t frac
= var
->data
.location_frac
;
1080 uint32_t vary
= var
->data
.driver_location
;
1082 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
1087 assert(vary
< PIPE_MAX_SHADER_OUTPUTS
);
1089 switch(prog
->getType()) {
1090 case Program::TYPE_FRAGMENT
:
1091 frag_result_to_tgsi_semantic((gl_frag_result
)slot
, &name
, &index
);
1093 case TGSI_SEMANTIC_COLOR
:
1094 if (!var
->data
.fb_fetch_output
)
1095 info
->prop
.fp
.numColourResults
++;
1096 info
->prop
.fp
.separateFragData
= true;
1097 // sometimes we get FRAG_RESULT_DATAX with data.index 0
1098 // sometimes we get FRAG_RESULT_DATA0 with data.index X
1099 index
= index
== 0 ? var
->data
.index
: index
;
1101 case TGSI_SEMANTIC_POSITION
:
1102 info
->io
.fragDepth
= vary
;
1103 info
->prop
.fp
.writesDepth
= true;
1105 case TGSI_SEMANTIC_SAMPLEMASK
:
1106 info
->io
.sampleMask
= vary
;
1112 case Program::TYPE_GEOMETRY
:
1113 case Program::TYPE_TESSELLATION_CONTROL
:
1114 case Program::TYPE_TESSELLATION_EVAL
:
1115 case Program::TYPE_VERTEX
:
1116 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1118 if (var
->data
.patch
&& name
!= TGSI_SEMANTIC_TESSINNER
&&
1119 name
!= TGSI_SEMANTIC_TESSOUTER
)
1120 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
1123 case TGSI_SEMANTIC_CLIPDIST
:
1124 info
->io
.genUserClip
= -1;
1126 case TGSI_SEMANTIC_CLIPVERTEX
:
1127 clipVertexOutput
= vary
;
1129 case TGSI_SEMANTIC_EDGEFLAG
:
1130 info
->io
.edgeFlagOut
= vary
;
1132 case TGSI_SEMANTIC_POSITION
:
1133 if (clipVertexOutput
< 0)
1134 clipVertexOutput
= vary
;
1141 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1145 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1146 info
->out
[vary
].id
= vary
;
1147 info
->out
[vary
].patch
= var
->data
.patch
;
1148 info
->out
[vary
].sn
= name
;
1149 info
->out
[vary
].si
= index
+ i
;
1150 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1152 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1154 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1156 info
->out
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1158 if (nir
->info
.outputs_read
& 1ll << slot
)
1159 info
->out
[vary
].oread
= 1;
1161 info
->numOutputs
= std::max
<uint8_t>(info
->numOutputs
, vary
);
1164 info
->numSysVals
= 0;
1165 for (uint8_t i
= 0; i
< 64; ++i
) {
1166 if (!(nir
->info
.system_values_read
& 1ll << i
))
1169 system_val_to_tgsi_semantic(i
, &name
, &index
);
1170 info
->sv
[info
->numSysVals
].sn
= name
;
1171 info
->sv
[info
->numSysVals
].si
= index
;
1172 info
->sv
[info
->numSysVals
].input
= 0; // TODO inferSysValDirection(sn);
1175 case SYSTEM_VALUE_INSTANCE_ID
:
1176 info
->io
.instanceId
= info
->numSysVals
;
1178 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
1179 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
1180 info
->sv
[info
->numSysVals
].patch
= 1;
1182 case SYSTEM_VALUE_VERTEX_ID
:
1183 info
->io
.vertexId
= info
->numSysVals
;
1189 info
->numSysVals
+= 1;
1192 if (info
->io
.genUserClip
> 0) {
1193 info
->io
.clipDistances
= info
->io
.genUserClip
;
1195 const unsigned int nOut
= (info
->io
.genUserClip
+ 3) / 4;
1197 for (unsigned int n
= 0; n
< nOut
; ++n
) {
1198 unsigned int i
= info
->numOutputs
++;
1199 info
->out
[i
].id
= i
;
1200 info
->out
[i
].sn
= TGSI_SEMANTIC_CLIPDIST
;
1201 info
->out
[i
].si
= n
;
1202 info
->out
[i
].mask
= ((1 << info
->io
.clipDistances
) - 1) >> (n
* 4);
1206 return info
->assignSlots(info
) == 0;
1210 Converter::getSlotAddress(nir_intrinsic_instr
*insn
, uint8_t idx
, uint8_t slot
)
1213 int offset
= nir_intrinsic_component(insn
);
1216 if (nir_intrinsic_infos
[insn
->intrinsic
].has_dest
)
1217 ty
= getDType(insn
);
1219 ty
= getSType(insn
->src
[0], false, false);
1221 switch (insn
->intrinsic
) {
1222 case nir_intrinsic_load_input
:
1223 case nir_intrinsic_load_interpolated_input
:
1224 case nir_intrinsic_load_per_vertex_input
:
1227 case nir_intrinsic_load_output
:
1228 case nir_intrinsic_load_per_vertex_output
:
1229 case nir_intrinsic_store_output
:
1230 case nir_intrinsic_store_per_vertex_output
:
1234 ERROR("unknown intrinsic in getSlotAddress %s",
1235 nir_intrinsic_infos
[insn
->intrinsic
].name
);
1241 if (typeSizeof(ty
) == 8) {
1253 assert(!input
|| idx
< PIPE_MAX_SHADER_INPUTS
);
1254 assert(input
|| idx
< PIPE_MAX_SHADER_OUTPUTS
);
1256 const nv50_ir_varying
*vary
= input
? info
->in
: info
->out
;
1257 return vary
[idx
].slot
[slot
] * 4;
1261 Converter::loadFrom(DataFile file
, uint8_t i
, DataType ty
, Value
*def
,
1262 uint32_t base
, uint8_t c
, Value
*indirect0
,
1263 Value
*indirect1
, bool patch
)
1265 unsigned int tySize
= typeSizeof(ty
);
1268 (file
== FILE_MEMORY_CONST
|| file
== FILE_MEMORY_BUFFER
|| indirect0
)) {
1269 Value
*lo
= getSSA();
1270 Value
*hi
= getSSA();
1273 mkLoad(TYPE_U32
, lo
,
1274 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
),
1276 loi
->setIndirect(0, 1, indirect1
);
1277 loi
->perPatch
= patch
;
1280 mkLoad(TYPE_U32
, hi
,
1281 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
+ 4),
1283 hii
->setIndirect(0, 1, indirect1
);
1284 hii
->perPatch
= patch
;
1286 return mkOp2(OP_MERGE
, ty
, def
, lo
, hi
);
1289 mkLoad(ty
, def
, mkSymbol(file
, i
, ty
, base
+ c
* tySize
), indirect0
);
1290 ld
->setIndirect(0, 1, indirect1
);
1291 ld
->perPatch
= patch
;
1297 Converter::storeTo(nir_intrinsic_instr
*insn
, DataFile file
, operation op
,
1298 DataType ty
, Value
*src
, uint8_t idx
, uint8_t c
,
1299 Value
*indirect0
, Value
*indirect1
)
1301 uint8_t size
= typeSizeof(ty
);
1302 uint32_t address
= getSlotAddress(insn
, idx
, c
);
1304 if (size
== 8 && indirect0
) {
1306 mkSplit(split
, 4, src
);
1308 if (op
== OP_EXPORT
) {
1309 split
[0] = mkMov(getSSA(), split
[0], ty
)->getDef(0);
1310 split
[1] = mkMov(getSSA(), split
[1], ty
)->getDef(0);
1313 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
), indirect0
,
1314 split
[0])->perPatch
= info
->out
[idx
].patch
;
1315 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
+ 4), indirect0
,
1316 split
[1])->perPatch
= info
->out
[idx
].patch
;
1318 if (op
== OP_EXPORT
)
1319 src
= mkMov(getSSA(size
), src
, ty
)->getDef(0);
1320 mkStore(op
, ty
, mkSymbol(file
, 0, ty
, address
), indirect0
,
1321 src
)->perPatch
= info
->out
[idx
].patch
;
1326 Converter::parseNIR()
1328 info
->io
.clipDistances
= nir
->info
.clip_distance_array_size
;
1329 info
->io
.cullDistances
= nir
->info
.cull_distance_array_size
;
1331 switch(prog
->getType()) {
1332 case Program::TYPE_COMPUTE
:
1333 info
->prop
.cp
.numThreads
[0] = nir
->info
.cs
.local_size
[0];
1334 info
->prop
.cp
.numThreads
[1] = nir
->info
.cs
.local_size
[1];
1335 info
->prop
.cp
.numThreads
[2] = nir
->info
.cs
.local_size
[2];
1336 info
->bin
.smemSize
= nir
->info
.cs
.shared_size
;
1338 case Program::TYPE_FRAGMENT
:
1339 info
->prop
.fp
.earlyFragTests
= nir
->info
.fs
.early_fragment_tests
;
1340 info
->prop
.fp
.persampleInvocation
=
1341 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_ID
) ||
1342 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1343 info
->prop
.fp
.postDepthCoverage
= nir
->info
.fs
.post_depth_coverage
;
1344 info
->prop
.fp
.readsSampleLocations
=
1345 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1346 info
->prop
.fp
.usesDiscard
= nir
->info
.fs
.uses_discard
;
1347 info
->prop
.fp
.usesSampleMaskIn
=
1348 !!(nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
);
1350 case Program::TYPE_GEOMETRY
:
1351 info
->prop
.gp
.inputPrim
= nir
->info
.gs
.input_primitive
;
1352 info
->prop
.gp
.instanceCount
= nir
->info
.gs
.invocations
;
1353 info
->prop
.gp
.maxVertices
= nir
->info
.gs
.vertices_out
;
1354 info
->prop
.gp
.outputPrim
= nir
->info
.gs
.output_primitive
;
1356 case Program::TYPE_TESSELLATION_CONTROL
:
1357 case Program::TYPE_TESSELLATION_EVAL
:
1358 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1359 info
->prop
.tp
.domain
= GL_LINES
;
1361 info
->prop
.tp
.domain
= nir
->info
.tess
.primitive_mode
;
1362 info
->prop
.tp
.outputPatchSize
= nir
->info
.tess
.tcs_vertices_out
;
1363 info
->prop
.tp
.outputPrim
=
1364 nir
->info
.tess
.point_mode
? PIPE_PRIM_POINTS
: PIPE_PRIM_TRIANGLES
;
1365 info
->prop
.tp
.partitioning
= (nir
->info
.tess
.spacing
+ 1) % 3;
1366 info
->prop
.tp
.winding
= !nir
->info
.tess
.ccw
;
1368 case Program::TYPE_VERTEX
:
1369 info
->prop
.vp
.usesDrawParameters
=
1370 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
)) ||
1371 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
)) ||
1372 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
));
1382 Converter::visit(nir_function
*function
)
1384 // we only support emiting the main function for now
1385 assert(!strcmp(function
->name
, "main"));
1386 assert(function
->impl
);
1388 // usually the blocks will set everything up, but main is special
1389 BasicBlock
*entry
= new BasicBlock(prog
->main
);
1390 exit
= new BasicBlock(prog
->main
);
1391 blocks
[nir_start_block(function
->impl
)->index
] = entry
;
1392 prog
->main
->setEntry(entry
);
1393 prog
->main
->setExit(exit
);
1395 setPosition(entry
, true);
1397 if (info
->io
.genUserClip
> 0) {
1398 for (int c
= 0; c
< 4; ++c
)
1399 clipVtx
[c
] = getScratch();
1402 switch (prog
->getType()) {
1403 case Program::TYPE_TESSELLATION_CONTROL
:
1405 OP_SUB
, TYPE_U32
, getSSA(),
1406 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LANEID
, 0)),
1407 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_INVOCATION_ID
, 0)));
1409 case Program::TYPE_FRAGMENT
: {
1410 Symbol
*sv
= mkSysVal(SV_POSITION
, 3);
1411 fragCoord
[3] = mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), sv
);
1412 fp
.position
= mkOp1v(OP_RCP
, TYPE_F32
, fragCoord
[3], fragCoord
[3]);
1419 nir_index_ssa_defs(function
->impl
);
1420 foreach_list_typed(nir_cf_node
, node
, node
, &function
->impl
->body
) {
1425 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::TREE
);
1426 setPosition(exit
, true);
1428 if (info
->io
.genUserClip
> 0)
1429 handleUserClipPlanes();
1431 // TODO: for non main function this needs to be a OP_RETURN
1432 mkOp(OP_EXIT
, TYPE_NONE
, NULL
)->terminator
= 1;
1437 Converter::visit(nir_cf_node
*node
)
1439 switch (node
->type
) {
1440 case nir_cf_node_block
:
1441 return visit(nir_cf_node_as_block(node
));
1442 case nir_cf_node_if
:
1443 return visit(nir_cf_node_as_if(node
));
1444 case nir_cf_node_loop
:
1445 return visit(nir_cf_node_as_loop(node
));
1447 ERROR("unknown nir_cf_node type %u\n", node
->type
);
1453 Converter::visit(nir_block
*block
)
1455 if (!block
->predecessors
->entries
&& block
->instr_list
.is_empty())
1458 BasicBlock
*bb
= convert(block
);
1460 setPosition(bb
, true);
1461 nir_foreach_instr(insn
, block
) {
1469 Converter::visit(nir_if
*nif
)
1471 DataType sType
= getSType(nif
->condition
, false, false);
1472 Value
*src
= getSrc(&nif
->condition
, 0);
1474 nir_block
*lastThen
= nir_if_last_then_block(nif
);
1475 nir_block
*lastElse
= nir_if_last_else_block(nif
);
1477 assert(!lastThen
->successors
[1]);
1478 assert(!lastElse
->successors
[1]);
1480 BasicBlock
*ifBB
= convert(nir_if_first_then_block(nif
));
1481 BasicBlock
*elseBB
= convert(nir_if_first_else_block(nif
));
1483 bb
->cfg
.attach(&ifBB
->cfg
, Graph::Edge::TREE
);
1484 bb
->cfg
.attach(&elseBB
->cfg
, Graph::Edge::TREE
);
1486 // we only insert joinats, if both nodes end up at the end of the if again.
1487 // the reason for this to not happens are breaks/continues/ret/... which
1488 // have their own handling
1489 if (lastThen
->successors
[0] == lastElse
->successors
[0])
1490 bb
->joinAt
= mkFlow(OP_JOINAT
, convert(lastThen
->successors
[0]),
1493 mkFlow(OP_BRA
, elseBB
, CC_EQ
, src
)->setType(sType
);
1495 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->then_list
) {
1499 setPosition(convert(lastThen
), true);
1500 if (!bb
->getExit() ||
1501 !bb
->getExit()->asFlow() ||
1502 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1503 BasicBlock
*tailBB
= convert(lastThen
->successors
[0]);
1504 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1505 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1508 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->else_list
) {
1512 setPosition(convert(lastElse
), true);
1513 if (!bb
->getExit() ||
1514 !bb
->getExit()->asFlow() ||
1515 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1516 BasicBlock
*tailBB
= convert(lastElse
->successors
[0]);
1517 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1518 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1521 if (lastThen
->successors
[0] == lastElse
->successors
[0]) {
1522 setPosition(convert(lastThen
->successors
[0]), true);
1523 mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1530 Converter::visit(nir_loop
*loop
)
1533 func
->loopNestingBound
= std::max(func
->loopNestingBound
, curLoopDepth
);
1535 BasicBlock
*loopBB
= convert(nir_loop_first_block(loop
));
1536 BasicBlock
*tailBB
=
1537 convert(nir_cf_node_as_block(nir_cf_node_next(&loop
->cf_node
)));
1538 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::TREE
);
1540 mkFlow(OP_PREBREAK
, tailBB
, CC_ALWAYS
, NULL
);
1541 setPosition(loopBB
, false);
1542 mkFlow(OP_PRECONT
, loopBB
, CC_ALWAYS
, NULL
);
1544 foreach_list_typed(nir_cf_node
, node
, node
, &loop
->body
) {
1548 Instruction
*insn
= bb
->getExit();
1549 if (bb
->cfg
.incidentCount() != 0) {
1550 if (!insn
|| !insn
->asFlow()) {
1551 mkFlow(OP_CONT
, loopBB
, CC_ALWAYS
, NULL
);
1552 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::BACK
);
1553 } else if (insn
&& insn
->op
== OP_BRA
&& !insn
->getPredicate() &&
1554 tailBB
->cfg
.incidentCount() == 0) {
1555 // RA doesn't like having blocks around with no incident edge,
1556 // so we create a fake one to make it happy
1557 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::TREE
);
1567 Converter::visit(nir_instr
*insn
)
1569 switch (insn
->type
) {
1570 case nir_instr_type_alu
:
1571 return visit(nir_instr_as_alu(insn
));
1572 case nir_instr_type_intrinsic
:
1573 return visit(nir_instr_as_intrinsic(insn
));
1574 case nir_instr_type_jump
:
1575 return visit(nir_instr_as_jump(insn
));
1576 case nir_instr_type_load_const
:
1577 return visit(nir_instr_as_load_const(insn
));
1578 case nir_instr_type_ssa_undef
:
1579 return visit(nir_instr_as_ssa_undef(insn
));
1580 case nir_instr_type_tex
:
1581 return visit(nir_instr_as_tex(insn
));
1583 ERROR("unknown nir_instr type %u\n", insn
->type
);
1590 Converter::convert(nir_intrinsic_op intr
)
1593 case nir_intrinsic_load_base_vertex
:
1594 return SV_BASEVERTEX
;
1595 case nir_intrinsic_load_base_instance
:
1596 return SV_BASEINSTANCE
;
1597 case nir_intrinsic_load_draw_id
:
1599 case nir_intrinsic_load_front_face
:
1601 case nir_intrinsic_load_helper_invocation
:
1602 return SV_THREAD_KILL
;
1603 case nir_intrinsic_load_instance_id
:
1604 return SV_INSTANCE_ID
;
1605 case nir_intrinsic_load_invocation_id
:
1606 return SV_INVOCATION_ID
;
1607 case nir_intrinsic_load_local_group_size
:
1609 case nir_intrinsic_load_local_invocation_id
:
1611 case nir_intrinsic_load_num_work_groups
:
1613 case nir_intrinsic_load_patch_vertices_in
:
1614 return SV_VERTEX_COUNT
;
1615 case nir_intrinsic_load_primitive_id
:
1616 return SV_PRIMITIVE_ID
;
1617 case nir_intrinsic_load_sample_id
:
1618 return SV_SAMPLE_INDEX
;
1619 case nir_intrinsic_load_sample_mask_in
:
1620 return SV_SAMPLE_MASK
;
1621 case nir_intrinsic_load_sample_pos
:
1622 return SV_SAMPLE_POS
;
1623 case nir_intrinsic_load_subgroup_eq_mask
:
1624 return SV_LANEMASK_EQ
;
1625 case nir_intrinsic_load_subgroup_ge_mask
:
1626 return SV_LANEMASK_GE
;
1627 case nir_intrinsic_load_subgroup_gt_mask
:
1628 return SV_LANEMASK_GT
;
1629 case nir_intrinsic_load_subgroup_le_mask
:
1630 return SV_LANEMASK_LE
;
1631 case nir_intrinsic_load_subgroup_lt_mask
:
1632 return SV_LANEMASK_LT
;
1633 case nir_intrinsic_load_subgroup_invocation
:
1635 case nir_intrinsic_load_tess_coord
:
1636 return SV_TESS_COORD
;
1637 case nir_intrinsic_load_tess_level_inner
:
1638 return SV_TESS_INNER
;
1639 case nir_intrinsic_load_tess_level_outer
:
1640 return SV_TESS_OUTER
;
1641 case nir_intrinsic_load_vertex_id
:
1642 return SV_VERTEX_ID
;
1643 case nir_intrinsic_load_work_group_id
:
1646 ERROR("unknown SVSemantic for nir_intrinsic_op %s\n",
1647 nir_intrinsic_infos
[intr
].name
);
1654 Converter::visit(nir_intrinsic_instr
*insn
)
1656 nir_intrinsic_op op
= insn
->intrinsic
;
1659 case nir_intrinsic_load_uniform
: {
1660 LValues
&newDefs
= convert(&insn
->dest
);
1661 const DataType dType
= getDType(insn
);
1663 uint32_t coffset
= getIndirect(insn
, 0, 0, indirect
);
1664 for (uint8_t i
= 0; i
< insn
->num_components
; ++i
) {
1665 loadFrom(FILE_MEMORY_CONST
, 0, dType
, newDefs
[i
], 16 * coffset
, i
, indirect
);
1669 case nir_intrinsic_store_output
:
1670 case nir_intrinsic_store_per_vertex_output
: {
1672 DataType dType
= getSType(insn
->src
[0], false, false);
1673 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_store_output
? 1 : 2, 0, indirect
);
1675 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1676 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
1680 Value
*src
= getSrc(&insn
->src
[0], i
);
1681 switch (prog
->getType()) {
1682 case Program::TYPE_FRAGMENT
: {
1683 if (info
->out
[idx
].sn
== TGSI_SEMANTIC_POSITION
) {
1684 // TGSI uses a different interface than NIR, TGSI stores that
1685 // value in the z component, NIR in X
1687 src
= mkOp1v(OP_SAT
, TYPE_F32
, getScratch(), src
);
1691 case Program::TYPE_VERTEX
: {
1692 if (info
->io
.genUserClip
> 0 && idx
== clipVertexOutput
) {
1693 mkMov(clipVtx
[i
], src
);
1702 storeTo(insn
, FILE_SHADER_OUTPUT
, OP_EXPORT
, dType
, src
, idx
, i
+ offset
, indirect
);
1706 case nir_intrinsic_load_input
:
1707 case nir_intrinsic_load_interpolated_input
:
1708 case nir_intrinsic_load_output
: {
1709 LValues
&newDefs
= convert(&insn
->dest
);
1712 if (prog
->getType() == Program::TYPE_FRAGMENT
&&
1713 op
== nir_intrinsic_load_output
) {
1714 std::vector
<Value
*> defs
, srcs
;
1717 srcs
.push_back(getSSA());
1718 srcs
.push_back(getSSA());
1719 Value
*x
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 0));
1720 Value
*y
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 1));
1721 mkCvt(OP_CVT
, TYPE_U32
, srcs
[0], TYPE_F32
, x
)->rnd
= ROUND_Z
;
1722 mkCvt(OP_CVT
, TYPE_U32
, srcs
[1], TYPE_F32
, y
)->rnd
= ROUND_Z
;
1724 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LAYER
, 0)));
1725 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_SAMPLE_INDEX
, 0)));
1727 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1728 defs
.push_back(newDefs
[i
]);
1732 TexInstruction
*texi
= mkTex(OP_TXF
, TEX_TARGET_2D_MS_ARRAY
, 0, 0, defs
, srcs
);
1733 texi
->tex
.levelZero
= 1;
1734 texi
->tex
.mask
= mask
;
1735 texi
->tex
.useOffsets
= 0;
1736 texi
->tex
.r
= 0xffff;
1737 texi
->tex
.s
= 0xffff;
1739 info
->prop
.fp
.readsFramebuffer
= true;
1743 const DataType dType
= getDType(insn
);
1745 bool input
= op
!= nir_intrinsic_load_output
;
1749 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_load_interpolated_input
? 1 : 0, 0, indirect
);
1750 nv50_ir_varying
& vary
= input
? info
->in
[idx
] : info
->out
[idx
];
1752 // see load_barycentric_* handling
1753 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1754 mode
= translateInterpMode(&vary
, nvirOp
);
1755 if (op
== nir_intrinsic_load_interpolated_input
) {
1756 ImmediateValue immMode
;
1757 if (getSrc(&insn
->src
[0], 1)->getUniqueInsn()->src(0).getImmediate(immMode
))
1758 mode
|= immMode
.reg
.data
.u32
;
1762 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1763 uint32_t address
= getSlotAddress(insn
, idx
, i
);
1764 Symbol
*sym
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
);
1765 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1767 if (typeSizeof(dType
) == 8) {
1768 Value
*lo
= getSSA();
1769 Value
*hi
= getSSA();
1770 Instruction
*interp
;
1772 interp
= mkOp1(nvirOp
, TYPE_U32
, lo
, sym
);
1773 if (nvirOp
== OP_PINTERP
)
1774 interp
->setSrc(s
++, fp
.position
);
1775 if (mode
& NV50_IR_INTERP_OFFSET
)
1776 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1777 interp
->setInterpolate(mode
);
1778 interp
->setIndirect(0, 0, indirect
);
1780 Symbol
*sym1
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
+ 4);
1781 interp
= mkOp1(nvirOp
, TYPE_U32
, hi
, sym1
);
1782 if (nvirOp
== OP_PINTERP
)
1783 interp
->setSrc(s
++, fp
.position
);
1784 if (mode
& NV50_IR_INTERP_OFFSET
)
1785 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1786 interp
->setInterpolate(mode
);
1787 interp
->setIndirect(0, 0, indirect
);
1789 mkOp2(OP_MERGE
, dType
, newDefs
[i
], lo
, hi
);
1791 Instruction
*interp
= mkOp1(nvirOp
, dType
, newDefs
[i
], sym
);
1792 if (nvirOp
== OP_PINTERP
)
1793 interp
->setSrc(s
++, fp
.position
);
1794 if (mode
& NV50_IR_INTERP_OFFSET
)
1795 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1796 interp
->setInterpolate(mode
);
1797 interp
->setIndirect(0, 0, indirect
);
1800 mkLoad(dType
, newDefs
[i
], sym
, indirect
)->perPatch
= vary
.patch
;
1805 case nir_intrinsic_load_barycentric_at_offset
:
1806 case nir_intrinsic_load_barycentric_at_sample
:
1807 case nir_intrinsic_load_barycentric_centroid
:
1808 case nir_intrinsic_load_barycentric_pixel
:
1809 case nir_intrinsic_load_barycentric_sample
: {
1810 LValues
&newDefs
= convert(&insn
->dest
);
1813 if (op
== nir_intrinsic_load_barycentric_centroid
||
1814 op
== nir_intrinsic_load_barycentric_sample
) {
1815 mode
= NV50_IR_INTERP_CENTROID
;
1816 } else if (op
== nir_intrinsic_load_barycentric_at_offset
) {
1818 for (uint8_t c
= 0; c
< 2; c
++) {
1819 offs
[c
] = getScratch();
1820 mkOp2(OP_MIN
, TYPE_F32
, offs
[c
], getSrc(&insn
->src
[0], c
), loadImm(NULL
, 0.4375f
));
1821 mkOp2(OP_MAX
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, -0.5f
));
1822 mkOp2(OP_MUL
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, 4096.0f
));
1823 mkCvt(OP_CVT
, TYPE_S32
, offs
[c
], TYPE_F32
, offs
[c
]);
1825 mkOp3v(OP_INSBF
, TYPE_U32
, newDefs
[0], offs
[1], mkImm(0x1010), offs
[0]);
1827 mode
= NV50_IR_INTERP_OFFSET
;
1828 } else if (op
== nir_intrinsic_load_barycentric_pixel
) {
1829 mode
= NV50_IR_INTERP_DEFAULT
;
1830 } else if (op
== nir_intrinsic_load_barycentric_at_sample
) {
1831 info
->prop
.fp
.readsSampleLocations
= true;
1832 mkOp1(OP_PIXLD
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0], 0))->subOp
= NV50_IR_SUBOP_PIXLD_OFFSET
;
1833 mode
= NV50_IR_INTERP_OFFSET
;
1835 unreachable("all intrinsics already handled above");
1838 loadImm(newDefs
[1], mode
);
1841 case nir_intrinsic_discard
:
1842 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
);
1844 case nir_intrinsic_discard_if
: {
1845 Value
*pred
= getSSA(1, FILE_PREDICATE
);
1846 if (insn
->num_components
> 1) {
1847 ERROR("nir_intrinsic_discard_if only with 1 component supported!\n");
1851 mkCmp(OP_SET
, CC_NE
, TYPE_U8
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
1852 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
)->setPredicate(CC_P
, pred
);
1855 case nir_intrinsic_load_base_vertex
:
1856 case nir_intrinsic_load_base_instance
:
1857 case nir_intrinsic_load_draw_id
:
1858 case nir_intrinsic_load_front_face
:
1859 case nir_intrinsic_load_helper_invocation
:
1860 case nir_intrinsic_load_instance_id
:
1861 case nir_intrinsic_load_invocation_id
:
1862 case nir_intrinsic_load_local_group_size
:
1863 case nir_intrinsic_load_local_invocation_id
:
1864 case nir_intrinsic_load_num_work_groups
:
1865 case nir_intrinsic_load_patch_vertices_in
:
1866 case nir_intrinsic_load_primitive_id
:
1867 case nir_intrinsic_load_sample_id
:
1868 case nir_intrinsic_load_sample_mask_in
:
1869 case nir_intrinsic_load_sample_pos
:
1870 case nir_intrinsic_load_subgroup_eq_mask
:
1871 case nir_intrinsic_load_subgroup_ge_mask
:
1872 case nir_intrinsic_load_subgroup_gt_mask
:
1873 case nir_intrinsic_load_subgroup_le_mask
:
1874 case nir_intrinsic_load_subgroup_lt_mask
:
1875 case nir_intrinsic_load_subgroup_invocation
:
1876 case nir_intrinsic_load_tess_coord
:
1877 case nir_intrinsic_load_tess_level_inner
:
1878 case nir_intrinsic_load_tess_level_outer
:
1879 case nir_intrinsic_load_vertex_id
:
1880 case nir_intrinsic_load_work_group_id
: {
1881 const DataType dType
= getDType(insn
);
1882 SVSemantic sv
= convert(op
);
1883 LValues
&newDefs
= convert(&insn
->dest
);
1885 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1887 if (typeSizeof(dType
) == 8)
1892 if (sv
== SV_TID
&& info
->prop
.cp
.numThreads
[i
] == 1) {
1895 Symbol
*sym
= mkSysVal(sv
, i
);
1896 Instruction
*rdsv
= mkOp1(OP_RDSV
, TYPE_U32
, def
, sym
);
1897 if (sv
== SV_TESS_OUTER
|| sv
== SV_TESS_INNER
)
1901 if (typeSizeof(dType
) == 8)
1902 mkOp2(OP_MERGE
, dType
, newDefs
[i
], def
, loadImm(getSSA(), 0u));
1907 case nir_intrinsic_load_subgroup_size
: {
1908 LValues
&newDefs
= convert(&insn
->dest
);
1909 loadImm(newDefs
[0], 32u);
1913 ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos
[op
].name
);
1921 Converter::visit(nir_jump_instr
*insn
)
1923 switch (insn
->type
) {
1924 case nir_jump_return
:
1925 // TODO: this only works in the main function
1926 mkFlow(OP_BRA
, exit
, CC_ALWAYS
, NULL
);
1927 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::CROSS
);
1929 case nir_jump_break
:
1930 case nir_jump_continue
: {
1931 bool isBreak
= insn
->type
== nir_jump_break
;
1932 nir_block
*block
= insn
->instr
.block
;
1933 assert(!block
->successors
[1]);
1934 BasicBlock
*target
= convert(block
->successors
[0]);
1935 mkFlow(isBreak
? OP_BREAK
: OP_CONT
, target
, CC_ALWAYS
, NULL
);
1936 bb
->cfg
.attach(&target
->cfg
, isBreak
? Graph::Edge::CROSS
: Graph::Edge::BACK
);
1940 ERROR("unknown nir_jump_type %u\n", insn
->type
);
1948 Converter::visit(nir_load_const_instr
*insn
)
1950 assert(insn
->def
.bit_size
<= 64);
1952 LValues
&newDefs
= convert(&insn
->def
);
1953 for (int i
= 0; i
< insn
->def
.num_components
; i
++) {
1954 switch (insn
->def
.bit_size
) {
1956 loadImm(newDefs
[i
], insn
->value
.u64
[i
]);
1959 loadImm(newDefs
[i
], insn
->value
.u32
[i
]);
1962 loadImm(newDefs
[i
], insn
->value
.u16
[i
]);
1965 loadImm(newDefs
[i
], insn
->value
.u8
[i
]);
1972 #define DEFAULT_CHECKS \
1973 if (insn->dest.dest.ssa.num_components > 1) { \
1974 ERROR("nir_alu_instr only supported with 1 component!\n"); \
1977 if (insn->dest.write_mask != 1) { \
1978 ERROR("nir_alu_instr only with write_mask of 1 supported!\n"); \
1982 Converter::visit(nir_alu_instr
*insn
)
1984 const nir_op op
= insn
->op
;
1985 const nir_op_info
&info
= nir_op_infos
[op
];
1986 DataType dType
= getDType(insn
);
1987 const std::vector
<DataType
> sTypes
= getSTypes(insn
);
1989 Instruction
*oldPos
= this->bb
->getExit();
2001 case nir_op_fddx_coarse
:
2002 case nir_op_fddx_fine
:
2004 case nir_op_fddy_coarse
:
2005 case nir_op_fddy_fine
:
2024 case nir_op_imul_high
:
2025 case nir_op_umul_high
:
2032 case nir_op_pack_64_2x32_split
:
2050 LValues
&newDefs
= convert(&insn
->dest
);
2051 operation preOp
= preOperationNeeded(op
);
2052 if (preOp
!= OP_NOP
) {
2053 assert(info
.num_inputs
< 2);
2054 Value
*tmp
= getSSA(typeSizeof(dType
));
2055 Instruction
*i0
= mkOp(preOp
, dType
, tmp
);
2056 Instruction
*i1
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2057 if (info
.num_inputs
) {
2058 i0
->setSrc(0, getSrc(&insn
->src
[0]));
2061 i1
->subOp
= getSubOp(op
);
2063 Instruction
*i
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2064 for (unsigned s
= 0u; s
< info
.num_inputs
; ++s
) {
2065 i
->setSrc(s
, getSrc(&insn
->src
[s
]));
2067 i
->subOp
= getSubOp(op
);
2071 case nir_op_ifind_msb
:
2072 case nir_op_ufind_msb
: {
2074 LValues
&newDefs
= convert(&insn
->dest
);
2076 mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2079 case nir_op_fround_even
: {
2081 LValues
&newDefs
= convert(&insn
->dest
);
2082 mkCvt(OP_CVT
, dType
, newDefs
[0], dType
, getSrc(&insn
->src
[0]))->rnd
= ROUND_NI
;
2085 // convert instructions
2099 case nir_op_u2u64
: {
2101 LValues
&newDefs
= convert(&insn
->dest
);
2102 Instruction
*i
= mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2103 if (op
== nir_op_f2i32
|| op
== nir_op_f2i64
|| op
== nir_op_f2u32
|| op
== nir_op_f2u64
)
2105 i
->sType
= sTypes
[0];
2108 // compare instructions
2118 case nir_op_ine32
: {
2120 LValues
&newDefs
= convert(&insn
->dest
);
2121 Instruction
*i
= mkCmp(getOperation(op
),
2126 getSrc(&insn
->src
[0]),
2127 getSrc(&insn
->src
[1]));
2128 if (info
.num_inputs
== 3)
2129 i
->setSrc(2, getSrc(&insn
->src
[2]));
2130 i
->sType
= sTypes
[0];
2133 // those are weird ALU ops and need special handling, because
2134 // 1. they are always componend based
2135 // 2. they basically just merge multiple values into one data type
2141 LValues
&newDefs
= convert(&insn
->dest
);
2142 for (LValues::size_type c
= 0u; c
< newDefs
.size(); ++c
) {
2143 mkMov(newDefs
[c
], getSrc(&insn
->src
[c
]), dType
);
2148 case nir_op_pack_64_2x32
: {
2149 LValues
&newDefs
= convert(&insn
->dest
);
2150 Instruction
*merge
= mkOp(OP_MERGE
, dType
, newDefs
[0]);
2151 merge
->setSrc(0, getSrc(&insn
->src
[0], 0));
2152 merge
->setSrc(1, getSrc(&insn
->src
[0], 1));
2155 case nir_op_pack_half_2x16_split
: {
2156 LValues
&newDefs
= convert(&insn
->dest
);
2157 Value
*tmpH
= getSSA();
2158 Value
*tmpL
= getSSA();
2160 mkCvt(OP_CVT
, TYPE_F16
, tmpL
, TYPE_F32
, getSrc(&insn
->src
[0]));
2161 mkCvt(OP_CVT
, TYPE_F16
, tmpH
, TYPE_F32
, getSrc(&insn
->src
[1]));
2162 mkOp3(OP_INSBF
, TYPE_U32
, newDefs
[0], tmpH
, mkImm(0x1010), tmpL
);
2165 case nir_op_unpack_half_2x16_split_x
:
2166 case nir_op_unpack_half_2x16_split_y
: {
2167 LValues
&newDefs
= convert(&insn
->dest
);
2168 Instruction
*cvt
= mkCvt(OP_CVT
, TYPE_F32
, newDefs
[0], TYPE_F16
, getSrc(&insn
->src
[0]));
2169 if (op
== nir_op_unpack_half_2x16_split_y
)
2173 case nir_op_unpack_64_2x32
: {
2174 LValues
&newDefs
= convert(&insn
->dest
);
2175 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, newDefs
[1]);
2178 case nir_op_unpack_64_2x32_split_x
: {
2179 LValues
&newDefs
= convert(&insn
->dest
);
2180 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, getSSA());
2183 case nir_op_unpack_64_2x32_split_y
: {
2184 LValues
&newDefs
= convert(&insn
->dest
);
2185 mkOp1(OP_SPLIT
, dType
, getSSA(), getSrc(&insn
->src
[0]))->setDef(1, newDefs
[0]);
2188 // special instructions
2190 case nir_op_isign
: {
2193 if (::isFloatType(dType
))
2198 LValues
&newDefs
= convert(&insn
->dest
);
2199 LValue
*val0
= getScratch();
2200 LValue
*val1
= getScratch();
2201 mkCmp(OP_SET
, CC_GT
, iType
, val0
, dType
, getSrc(&insn
->src
[0]), zero
);
2202 mkCmp(OP_SET
, CC_LT
, iType
, val1
, dType
, getSrc(&insn
->src
[0]), zero
);
2204 if (dType
== TYPE_F64
) {
2205 mkOp2(OP_SUB
, iType
, val0
, val0
, val1
);
2206 mkCvt(OP_CVT
, TYPE_F64
, newDefs
[0], iType
, val0
);
2207 } else if (dType
== TYPE_S64
|| dType
== TYPE_U64
) {
2208 mkOp2(OP_SUB
, iType
, val0
, val1
, val0
);
2209 mkOp2(OP_SHR
, iType
, val1
, val0
, loadImm(NULL
, 31));
2210 mkOp2(OP_MERGE
, dType
, newDefs
[0], val0
, val1
);
2211 } else if (::isFloatType(dType
))
2212 mkOp2(OP_SUB
, iType
, newDefs
[0], val0
, val1
);
2214 mkOp2(OP_SUB
, iType
, newDefs
[0], val1
, val0
);
2218 case nir_op_b32csel
: {
2220 LValues
&newDefs
= convert(&insn
->dest
);
2221 mkCmp(OP_SLCT
, CC_NE
, dType
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[1]), getSrc(&insn
->src
[2]), getSrc(&insn
->src
[0]));
2224 case nir_op_ibitfield_extract
:
2225 case nir_op_ubitfield_extract
: {
2227 Value
*tmp
= getSSA();
2228 LValues
&newDefs
= convert(&insn
->dest
);
2229 mkOp3(OP_INSBF
, dType
, tmp
, getSrc(&insn
->src
[2]), loadImm(NULL
, 0x808), getSrc(&insn
->src
[1]));
2230 mkOp2(OP_EXTBF
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), tmp
);
2235 LValues
&newDefs
= convert(&insn
->dest
);
2236 mkOp3(OP_INSBF
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 0x808), getSrc(&insn
->src
[1]));
2239 case nir_op_bitfield_insert
: {
2241 LValues
&newDefs
= convert(&insn
->dest
);
2242 LValue
*temp
= getSSA();
2243 mkOp3(OP_INSBF
, TYPE_U32
, temp
, getSrc(&insn
->src
[3]), mkImm(0x808), getSrc(&insn
->src
[2]));
2244 mkOp3(OP_INSBF
, dType
, newDefs
[0], getSrc(&insn
->src
[1]), temp
, getSrc(&insn
->src
[0]));
2247 case nir_op_bit_count
: {
2249 LValues
&newDefs
= convert(&insn
->dest
);
2250 mkOp2(OP_POPCNT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), getSrc(&insn
->src
[0]));
2253 case nir_op_bitfield_reverse
: {
2255 LValues
&newDefs
= convert(&insn
->dest
);
2256 mkOp2(OP_EXTBF
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2259 case nir_op_find_lsb
: {
2261 LValues
&newDefs
= convert(&insn
->dest
);
2262 Value
*tmp
= getSSA();
2263 mkOp2(OP_EXTBF
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]), mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2264 mkOp1(OP_BFIND
, TYPE_U32
, newDefs
[0], tmp
)->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
2267 // boolean conversions
2268 case nir_op_b2f32
: {
2270 LValues
&newDefs
= convert(&insn
->dest
);
2271 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1.0f
));
2274 case nir_op_b2f64
: {
2276 LValues
&newDefs
= convert(&insn
->dest
);
2277 Value
*tmp
= getSSA(4);
2278 mkOp2(OP_AND
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]), loadImm(NULL
, 0x3ff00000));
2279 mkOp2(OP_MERGE
, TYPE_U64
, newDefs
[0], loadImm(NULL
, 0), tmp
);
2283 case nir_op_i2b32
: {
2285 LValues
&newDefs
= convert(&insn
->dest
);
2287 if (typeSizeof(sTypes
[0]) == 8) {
2288 src1
= loadImm(getSSA(8), 0.0);
2292 CondCode cc
= op
== nir_op_f2b32
? CC_NEU
: CC_NE
;
2293 mkCmp(OP_SET
, cc
, TYPE_U32
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[0]), src1
);
2296 case nir_op_b2i32
: {
2298 LValues
&newDefs
= convert(&insn
->dest
);
2299 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2302 case nir_op_b2i64
: {
2304 LValues
&newDefs
= convert(&insn
->dest
);
2305 LValue
*def
= getScratch();
2306 mkOp2(OP_AND
, TYPE_U32
, def
, getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2307 mkOp2(OP_MERGE
, TYPE_S64
, newDefs
[0], def
, loadImm(NULL
, 0));
2311 ERROR("unknown nir_op %s\n", info
.name
);
2316 oldPos
= this->bb
->getEntry();
2317 oldPos
->precise
= insn
->exact
;
2320 if (unlikely(!oldPos
))
2323 while (oldPos
->next
) {
2324 oldPos
= oldPos
->next
;
2325 oldPos
->precise
= insn
->exact
;
2327 oldPos
->saturate
= insn
->dest
.saturate
;
2331 #undef DEFAULT_CHECKS
2334 Converter::visit(nir_ssa_undef_instr
*insn
)
2336 LValues
&newDefs
= convert(&insn
->def
);
2337 for (uint8_t i
= 0u; i
< insn
->def
.num_components
; ++i
) {
2338 mkOp(OP_NOP
, TYPE_NONE
, newDefs
[i
]);
2343 #define CASE_SAMPLER(ty) \
2344 case GLSL_SAMPLER_DIM_ ## ty : \
2345 if (isArray && !isShadow) \
2346 return TEX_TARGET_ ## ty ## _ARRAY; \
2347 else if (!isArray && isShadow) \
2348 return TEX_TARGET_## ty ## _SHADOW; \
2349 else if (isArray && isShadow) \
2350 return TEX_TARGET_## ty ## _ARRAY_SHADOW; \
2352 return TEX_TARGET_ ## ty
2355 Converter::convert(glsl_sampler_dim dim
, bool isArray
, bool isShadow
)
2361 case GLSL_SAMPLER_DIM_3D
:
2362 return TEX_TARGET_3D
;
2363 case GLSL_SAMPLER_DIM_MS
:
2365 return TEX_TARGET_2D_MS_ARRAY
;
2366 return TEX_TARGET_2D_MS
;
2367 case GLSL_SAMPLER_DIM_RECT
:
2369 return TEX_TARGET_RECT_SHADOW
;
2370 return TEX_TARGET_RECT
;
2371 case GLSL_SAMPLER_DIM_BUF
:
2372 return TEX_TARGET_BUFFER
;
2373 case GLSL_SAMPLER_DIM_EXTERNAL
:
2374 return TEX_TARGET_2D
;
2376 ERROR("unknown glsl_sampler_dim %u\n", dim
);
2378 return TEX_TARGET_COUNT
;
2384 Converter::applyProjection(Value
*src
, Value
*proj
)
2388 return mkOp2v(OP_MUL
, TYPE_F32
, getScratch(), src
, proj
);
2392 Converter::visit(nir_tex_instr
*insn
)
2396 case nir_texop_query_levels
:
2398 case nir_texop_texture_samples
:
2403 case nir_texop_txf_ms
:
2405 case nir_texop_txs
: {
2406 LValues
&newDefs
= convert(&insn
->dest
);
2407 std::vector
<Value
*> srcs
;
2408 std::vector
<Value
*> defs
;
2409 std::vector
<nir_src
*> offsets
;
2413 TexInstruction::Target target
= convert(insn
->sampler_dim
, insn
->is_array
, insn
->is_shadow
);
2414 operation op
= getOperation(insn
->op
);
2417 int biasIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_bias
);
2418 int compIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_comparator
);
2419 int coordsIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_coord
);
2420 int ddxIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddx
);
2421 int ddyIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddy
);
2422 int msIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ms_index
);
2423 int lodIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_lod
);
2424 int offsetIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_offset
);
2425 int projIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_projector
);
2426 int sampOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_sampler_offset
);
2427 int texOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_texture_offset
);
2430 proj
= mkOp1v(OP_RCP
, TYPE_F32
, getScratch(), getSrc(&insn
->src
[projIdx
].src
, 0));
2432 srcs
.resize(insn
->coord_components
);
2433 for (uint8_t i
= 0u; i
< insn
->coord_components
; ++i
)
2434 srcs
[i
] = applyProjection(getSrc(&insn
->src
[coordsIdx
].src
, i
), proj
);
2436 // sometimes we get less args than target.getArgCount, but codegen expects the latter
2437 if (insn
->coord_components
) {
2438 uint32_t argCount
= target
.getArgCount();
2443 for (uint32_t i
= 0u; i
< (argCount
- insn
->coord_components
); ++i
)
2444 srcs
.push_back(getSSA());
2447 if (insn
->op
== nir_texop_texture_samples
)
2448 srcs
.push_back(zero
);
2449 else if (!insn
->num_srcs
)
2450 srcs
.push_back(loadImm(NULL
, 0));
2452 srcs
.push_back(getSrc(&insn
->src
[biasIdx
].src
, 0));
2454 srcs
.push_back(getSrc(&insn
->src
[lodIdx
].src
, 0));
2455 else if (op
== OP_TXF
)
2458 srcs
.push_back(getSrc(&insn
->src
[msIdx
].src
, 0));
2459 if (offsetIdx
!= -1)
2460 offsets
.push_back(&insn
->src
[offsetIdx
].src
);
2462 srcs
.push_back(applyProjection(getSrc(&insn
->src
[compIdx
].src
, 0), proj
));
2463 if (texOffIdx
!= -1) {
2464 srcs
.push_back(getSrc(&insn
->src
[texOffIdx
].src
, 0));
2465 texOffIdx
= srcs
.size() - 1;
2467 if (sampOffIdx
!= -1) {
2468 srcs
.push_back(getSrc(&insn
->src
[sampOffIdx
].src
, 0));
2469 sampOffIdx
= srcs
.size() - 1;
2472 r
= insn
->texture_index
;
2473 s
= insn
->sampler_index
;
2475 defs
.resize(newDefs
.size());
2476 for (uint8_t d
= 0u; d
< newDefs
.size(); ++d
) {
2477 defs
[d
] = newDefs
[d
];
2480 if (target
.isMS() || (op
== OP_TEX
&& prog
->getType() != Program::TYPE_FRAGMENT
))
2483 TexInstruction
*texi
= mkTex(op
, target
.getEnum(), r
, s
, defs
, srcs
);
2484 texi
->tex
.levelZero
= lz
;
2485 texi
->tex
.mask
= mask
;
2487 if (texOffIdx
!= -1)
2488 texi
->tex
.rIndirectSrc
= texOffIdx
;
2489 if (sampOffIdx
!= -1)
2490 texi
->tex
.sIndirectSrc
= sampOffIdx
;
2494 if (!target
.isShadow())
2495 texi
->tex
.gatherComp
= insn
->component
;
2498 texi
->tex
.query
= TXQ_DIMS
;
2500 case nir_texop_texture_samples
:
2501 texi
->tex
.mask
= 0x4;
2502 texi
->tex
.query
= TXQ_TYPE
;
2504 case nir_texop_query_levels
:
2505 texi
->tex
.mask
= 0x8;
2506 texi
->tex
.query
= TXQ_DIMS
;
2512 texi
->tex
.useOffsets
= offsets
.size();
2513 if (texi
->tex
.useOffsets
) {
2514 for (uint8_t s
= 0; s
< texi
->tex
.useOffsets
; ++s
) {
2515 for (uint32_t c
= 0u; c
< 3; ++c
) {
2516 uint8_t s2
= std::min(c
, target
.getDim() - 1);
2517 texi
->offset
[s
][c
].set(getSrc(offsets
[s
], s2
));
2518 texi
->offset
[s
][c
].setInsn(texi
);
2523 if (ddxIdx
!= -1 && ddyIdx
!= -1) {
2524 for (uint8_t c
= 0u; c
< target
.getDim() + target
.isCube(); ++c
) {
2525 texi
->dPdx
[c
].set(getSrc(&insn
->src
[ddxIdx
].src
, c
));
2526 texi
->dPdy
[c
].set(getSrc(&insn
->src
[ddyIdx
].src
, c
));
2533 ERROR("unknown nir_texop %u\n", insn
->op
);
2544 if (prog
->dbgFlags
& NV50_IR_DEBUG_VERBOSE
)
2545 nir_print_shader(nir
, stderr
);
2547 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, type_size
, (nir_lower_io_options
)0);
2548 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
);
2549 NIR_PASS_V(nir
, nir_lower_load_const_to_scalar
);
2550 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2551 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
);
2552 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
2556 NIR_PASS(progress
, nir
, nir_copy_prop
);
2557 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
2558 NIR_PASS(progress
, nir
, nir_opt_trivial_continues
);
2559 NIR_PASS(progress
, nir
, nir_opt_cse
);
2560 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
2561 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
2562 NIR_PASS(progress
, nir
, nir_copy_prop
);
2563 NIR_PASS(progress
, nir
, nir_opt_dce
);
2564 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
2567 NIR_PASS_V(nir
, nir_lower_bool_to_int32
);
2568 NIR_PASS_V(nir
, nir_lower_locals_to_regs
);
2569 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
);
2570 NIR_PASS_V(nir
, nir_convert_from_ssa
, true);
2572 // Garbage collect dead instructions
2576 ERROR("Couldn't prase NIR!\n");
2580 if (!assignSlots()) {
2581 ERROR("Couldn't assign slots!\n");
2585 if (prog
->dbgFlags
& NV50_IR_DEBUG_BASIC
)
2586 nir_print_shader(nir
, stderr
);
2588 nir_foreach_function(function
, nir
) {
2589 if (!visit(function
))
2596 } // unnamed namespace
2601 Program::makeFromNIR(struct nv50_ir_prog_info
*info
)
2603 nir_shader
*nir
= (nir_shader
*)info
->bin
.source
;
2604 Converter
converter(this, nir
, info
);
2605 bool result
= converter
.run();
2608 LoweringHelper lowering
;
2610 tlsSize
= info
->bin
.tlsSpace
;
2614 } // namespace nv50_ir