2 * Copyright 2017 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Karol Herbst <kherbst@redhat.com>
25 #include "compiler/nir/nir.h"
27 #include "util/u_debug.h"
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_from_common.h"
31 #include "codegen/nv50_ir_lowering_helper.h"
32 #include "codegen/nv50_ir_util.h"
34 #if __cplusplus >= 201103L
35 #include <unordered_map>
37 #include <tr1/unordered_map>
44 #if __cplusplus >= 201103L
46 using std::unordered_map
;
49 using std::tr1::unordered_map
;
52 using namespace nv50_ir
;
55 type_size(const struct glsl_type
*type
)
57 return glsl_count_attribute_slots(type
, false);
60 class Converter
: public ConverterCommon
63 Converter(Program
*, nir_shader
*, nv50_ir_prog_info
*);
67 typedef std::vector
<LValue
*> LValues
;
68 typedef unordered_map
<unsigned, LValues
> NirDefMap
;
69 typedef unordered_map
<unsigned, uint32_t> NirArrayLMemOffsets
;
70 typedef unordered_map
<unsigned, BasicBlock
*> NirBlockMap
;
72 TexTarget
convert(glsl_sampler_dim
, bool isArray
, bool isShadow
);
73 LValues
& convert(nir_alu_dest
*);
74 BasicBlock
* convert(nir_block
*);
75 LValues
& convert(nir_dest
*);
76 SVSemantic
convert(nir_intrinsic_op
);
77 LValues
& convert(nir_register
*);
78 LValues
& convert(nir_ssa_def
*);
80 ImgFormat
convertGLImgFormat(GLuint
);
82 Value
* getSrc(nir_alu_src
*, uint8_t component
= 0);
83 Value
* getSrc(nir_register
*, uint8_t);
84 Value
* getSrc(nir_src
*, uint8_t, bool indirect
= false);
85 Value
* getSrc(nir_ssa_def
*, uint8_t);
87 // returned value is the constant part of the given source (either the
88 // nir_src or the selected source component of an intrinsic). Even though
89 // this is mostly an optimization to be able to skip indirects in a few
90 // cases, sometimes we require immediate values or set some fileds on
91 // instructions (e.g. tex) in order for codegen to consume those.
92 // If the found value has not a constant part, the Value gets returned
93 // through the Value parameter.
94 uint32_t getIndirect(nir_src
*, uint8_t, Value
*&);
95 uint32_t getIndirect(nir_intrinsic_instr
*, uint8_t s
, uint8_t c
, Value
*&);
97 uint32_t getSlotAddress(nir_intrinsic_instr
*, uint8_t idx
, uint8_t slot
);
99 void setInterpolate(nv50_ir_varying
*,
104 Instruction
*loadFrom(DataFile
, uint8_t, DataType
, Value
*def
, uint32_t base
,
105 uint8_t c
, Value
*indirect0
= NULL
,
106 Value
*indirect1
= NULL
, bool patch
= false);
107 void storeTo(nir_intrinsic_instr
*, DataFile
, operation
, DataType
,
108 Value
*src
, uint8_t idx
, uint8_t c
, Value
*indirect0
= NULL
,
109 Value
*indirect1
= NULL
);
111 bool isFloatType(nir_alu_type
);
112 bool isSignedType(nir_alu_type
);
113 bool isResultFloat(nir_op
);
114 bool isResultSigned(nir_op
);
116 DataType
getDType(nir_alu_instr
*);
117 DataType
getDType(nir_intrinsic_instr
*);
118 DataType
getDType(nir_intrinsic_instr
*, bool isSigned
);
119 DataType
getDType(nir_op
, uint8_t);
121 std::vector
<DataType
> getSTypes(nir_alu_instr
*);
122 DataType
getSType(nir_src
&, bool isFloat
, bool isSigned
);
124 operation
getOperation(nir_intrinsic_op
);
125 operation
getOperation(nir_op
);
126 operation
getOperation(nir_texop
);
127 operation
preOperationNeeded(nir_op
);
129 int getSubOp(nir_intrinsic_op
);
130 int getSubOp(nir_op
);
132 CondCode
getCondCode(nir_op
);
137 bool visit(nir_alu_instr
*);
138 bool visit(nir_block
*);
139 bool visit(nir_cf_node
*);
140 bool visit(nir_deref_instr
*);
141 bool visit(nir_function
*);
142 bool visit(nir_if
*);
143 bool visit(nir_instr
*);
144 bool visit(nir_intrinsic_instr
*);
145 bool visit(nir_jump_instr
*);
146 bool visit(nir_load_const_instr
*);
147 bool visit(nir_loop
*);
148 bool visit(nir_ssa_undef_instr
*);
149 bool visit(nir_tex_instr
*);
152 Value
* applyProjection(Value
*src
, Value
*proj
);
153 unsigned int getNIRArgCount(TexInstruction::Target
&);
156 uint16_t handleDeref(nir_deref_instr
*, Value
* & indirect
, const nir_variable
* &);
157 CacheMode
getCacheModeFromVar(const nir_variable
*);
163 NirArrayLMemOffsets regToLmemOffset
;
165 unsigned int curLoopDepth
;
170 int clipVertexOutput
;
179 Converter::Converter(Program
*prog
, nir_shader
*nir
, nv50_ir_prog_info
*info
)
180 : ConverterCommon(prog
, info
),
185 zero
= mkImm((uint32_t)0);
189 Converter::convert(nir_block
*block
)
191 NirBlockMap::iterator it
= blocks
.find(block
->index
);
192 if (it
!= blocks
.end())
195 BasicBlock
*bb
= new BasicBlock(func
);
196 blocks
[block
->index
] = bb
;
201 Converter::isFloatType(nir_alu_type type
)
203 return nir_alu_type_get_base_type(type
) == nir_type_float
;
207 Converter::isSignedType(nir_alu_type type
)
209 return nir_alu_type_get_base_type(type
) == nir_type_int
;
213 Converter::isResultFloat(nir_op op
)
215 const nir_op_info
&info
= nir_op_infos
[op
];
216 if (info
.output_type
!= nir_type_invalid
)
217 return isFloatType(info
.output_type
);
219 ERROR("isResultFloat not implemented for %s\n", nir_op_infos
[op
].name
);
225 Converter::isResultSigned(nir_op op
)
228 // there is no umul and we get wrong results if we treat all muls as signed
233 const nir_op_info
&info
= nir_op_infos
[op
];
234 if (info
.output_type
!= nir_type_invalid
)
235 return isSignedType(info
.output_type
);
236 ERROR("isResultSigned not implemented for %s\n", nir_op_infos
[op
].name
);
243 Converter::getDType(nir_alu_instr
*insn
)
245 if (insn
->dest
.dest
.is_ssa
)
246 return getDType(insn
->op
, insn
->dest
.dest
.ssa
.bit_size
);
248 return getDType(insn
->op
, insn
->dest
.dest
.reg
.reg
->bit_size
);
252 Converter::getDType(nir_intrinsic_instr
*insn
)
255 switch (insn
->intrinsic
) {
256 case nir_intrinsic_shared_atomic_imax
:
257 case nir_intrinsic_shared_atomic_imin
:
258 case nir_intrinsic_ssbo_atomic_imax
:
259 case nir_intrinsic_ssbo_atomic_imin
:
267 return getDType(insn
, isSigned
);
271 Converter::getDType(nir_intrinsic_instr
*insn
, bool isSigned
)
273 if (insn
->dest
.is_ssa
)
274 return typeOfSize(insn
->dest
.ssa
.bit_size
/ 8, false, isSigned
);
276 return typeOfSize(insn
->dest
.reg
.reg
->bit_size
/ 8, false, isSigned
);
280 Converter::getDType(nir_op op
, uint8_t bitSize
)
282 DataType ty
= typeOfSize(bitSize
/ 8, isResultFloat(op
), isResultSigned(op
));
283 if (ty
== TYPE_NONE
) {
284 ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos
[op
].name
, bitSize
);
290 std::vector
<DataType
>
291 Converter::getSTypes(nir_alu_instr
*insn
)
293 const nir_op_info
&info
= nir_op_infos
[insn
->op
];
294 std::vector
<DataType
> res(info
.num_inputs
);
296 for (uint8_t i
= 0; i
< info
.num_inputs
; ++i
) {
297 if (info
.input_types
[i
] != nir_type_invalid
) {
298 res
[i
] = getSType(insn
->src
[i
].src
, isFloatType(info
.input_types
[i
]), isSignedType(info
.input_types
[i
]));
300 ERROR("getSType not implemented for %s idx %u\n", info
.name
, i
);
311 Converter::getSType(nir_src
&src
, bool isFloat
, bool isSigned
)
315 bitSize
= src
.ssa
->bit_size
;
317 bitSize
= src
.reg
.reg
->bit_size
;
319 DataType ty
= typeOfSize(bitSize
/ 8, isFloat
, isSigned
);
320 if (ty
== TYPE_NONE
) {
328 ERROR("couldn't get Type for %s with bitSize %u\n", str
, bitSize
);
335 Converter::getOperation(nir_op op
)
338 // basic ops with float and int variants
348 case nir_op_ifind_msb
:
349 case nir_op_ufind_msb
:
371 case nir_op_fddx_coarse
:
372 case nir_op_fddx_fine
:
375 case nir_op_fddy_coarse
:
376 case nir_op_fddy_fine
:
394 case nir_op_pack_64_2x32_split
:
408 case nir_op_imul_high
:
409 case nir_op_umul_high
:
457 ERROR("couldn't get operation for op %s\n", nir_op_infos
[op
].name
);
464 Converter::getOperation(nir_texop op
)
476 case nir_texop_txf_ms
:
482 case nir_texop_query_levels
:
483 case nir_texop_texture_samples
:
487 ERROR("couldn't get operation for nir_texop %u\n", op
);
494 Converter::getOperation(nir_intrinsic_op op
)
497 case nir_intrinsic_emit_vertex
:
499 case nir_intrinsic_end_primitive
:
501 case nir_intrinsic_image_deref_atomic_add
:
502 case nir_intrinsic_image_deref_atomic_and
:
503 case nir_intrinsic_image_deref_atomic_comp_swap
:
504 case nir_intrinsic_image_deref_atomic_exchange
:
505 case nir_intrinsic_image_deref_atomic_max
:
506 case nir_intrinsic_image_deref_atomic_min
:
507 case nir_intrinsic_image_deref_atomic_or
:
508 case nir_intrinsic_image_deref_atomic_xor
:
510 case nir_intrinsic_image_deref_load
:
512 case nir_intrinsic_image_deref_samples
:
513 case nir_intrinsic_image_deref_size
:
515 case nir_intrinsic_image_deref_store
:
518 ERROR("couldn't get operation for nir_intrinsic_op %u\n", op
);
525 Converter::preOperationNeeded(nir_op op
)
537 Converter::getSubOp(nir_op op
)
540 case nir_op_imul_high
:
541 case nir_op_umul_high
:
542 return NV50_IR_SUBOP_MUL_HIGH
;
549 Converter::getSubOp(nir_intrinsic_op op
)
552 case nir_intrinsic_image_deref_atomic_add
:
553 case nir_intrinsic_shared_atomic_add
:
554 case nir_intrinsic_ssbo_atomic_add
:
555 return NV50_IR_SUBOP_ATOM_ADD
;
556 case nir_intrinsic_image_deref_atomic_and
:
557 case nir_intrinsic_shared_atomic_and
:
558 case nir_intrinsic_ssbo_atomic_and
:
559 return NV50_IR_SUBOP_ATOM_AND
;
560 case nir_intrinsic_image_deref_atomic_comp_swap
:
561 case nir_intrinsic_shared_atomic_comp_swap
:
562 case nir_intrinsic_ssbo_atomic_comp_swap
:
563 return NV50_IR_SUBOP_ATOM_CAS
;
564 case nir_intrinsic_image_deref_atomic_exchange
:
565 case nir_intrinsic_shared_atomic_exchange
:
566 case nir_intrinsic_ssbo_atomic_exchange
:
567 return NV50_IR_SUBOP_ATOM_EXCH
;
568 case nir_intrinsic_image_deref_atomic_or
:
569 case nir_intrinsic_shared_atomic_or
:
570 case nir_intrinsic_ssbo_atomic_or
:
571 return NV50_IR_SUBOP_ATOM_OR
;
572 case nir_intrinsic_image_deref_atomic_max
:
573 case nir_intrinsic_shared_atomic_imax
:
574 case nir_intrinsic_shared_atomic_umax
:
575 case nir_intrinsic_ssbo_atomic_imax
:
576 case nir_intrinsic_ssbo_atomic_umax
:
577 return NV50_IR_SUBOP_ATOM_MAX
;
578 case nir_intrinsic_image_deref_atomic_min
:
579 case nir_intrinsic_shared_atomic_imin
:
580 case nir_intrinsic_shared_atomic_umin
:
581 case nir_intrinsic_ssbo_atomic_imin
:
582 case nir_intrinsic_ssbo_atomic_umin
:
583 return NV50_IR_SUBOP_ATOM_MIN
;
584 case nir_intrinsic_image_deref_atomic_xor
:
585 case nir_intrinsic_shared_atomic_xor
:
586 case nir_intrinsic_ssbo_atomic_xor
:
587 return NV50_IR_SUBOP_ATOM_XOR
;
589 case nir_intrinsic_group_memory_barrier
:
590 case nir_intrinsic_memory_barrier
:
591 case nir_intrinsic_memory_barrier_atomic_counter
:
592 case nir_intrinsic_memory_barrier_buffer
:
593 case nir_intrinsic_memory_barrier_image
:
594 return NV50_IR_SUBOP_MEMBAR(M
, GL
);
595 case nir_intrinsic_memory_barrier_shared
:
596 return NV50_IR_SUBOP_MEMBAR(M
, CTA
);
598 case nir_intrinsic_vote_all
:
599 return NV50_IR_SUBOP_VOTE_ALL
;
600 case nir_intrinsic_vote_any
:
601 return NV50_IR_SUBOP_VOTE_ANY
;
602 case nir_intrinsic_vote_ieq
:
603 return NV50_IR_SUBOP_VOTE_UNI
;
610 Converter::getCondCode(nir_op op
)
629 ERROR("couldn't get CondCode for op %s\n", nir_op_infos
[op
].name
);
636 Converter::convert(nir_alu_dest
*dest
)
638 return convert(&dest
->dest
);
642 Converter::convert(nir_dest
*dest
)
645 return convert(&dest
->ssa
);
646 if (dest
->reg
.indirect
) {
647 ERROR("no support for indirects.");
650 return convert(dest
->reg
.reg
);
654 Converter::convert(nir_register
*reg
)
656 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
657 if (it
!= regDefs
.end())
660 LValues
newDef(reg
->num_components
);
661 for (uint8_t i
= 0; i
< reg
->num_components
; i
++)
662 newDef
[i
] = getScratch(std::max(4, reg
->bit_size
/ 8));
663 return regDefs
[reg
->index
] = newDef
;
667 Converter::convert(nir_ssa_def
*def
)
669 NirDefMap::iterator it
= ssaDefs
.find(def
->index
);
670 if (it
!= ssaDefs
.end())
673 LValues
newDef(def
->num_components
);
674 for (uint8_t i
= 0; i
< def
->num_components
; i
++)
675 newDef
[i
] = getSSA(std::max(4, def
->bit_size
/ 8));
676 return ssaDefs
[def
->index
] = newDef
;
680 Converter::getSrc(nir_alu_src
*src
, uint8_t component
)
682 if (src
->abs
|| src
->negate
) {
683 ERROR("modifiers currently not supported on nir_alu_src\n");
686 return getSrc(&src
->src
, src
->swizzle
[component
]);
690 Converter::getSrc(nir_register
*reg
, uint8_t idx
)
692 NirDefMap::iterator it
= regDefs
.find(reg
->index
);
693 if (it
== regDefs
.end())
694 return convert(reg
)[idx
];
695 return it
->second
[idx
];
699 Converter::getSrc(nir_src
*src
, uint8_t idx
, bool indirect
)
702 return getSrc(src
->ssa
, idx
);
704 if (src
->reg
.indirect
) {
706 return getSrc(src
->reg
.indirect
, idx
);
707 ERROR("no support for indirects.");
712 return getSrc(src
->reg
.reg
, idx
);
716 Converter::getSrc(nir_ssa_def
*src
, uint8_t idx
)
718 NirDefMap::iterator it
= ssaDefs
.find(src
->index
);
719 if (it
== ssaDefs
.end()) {
720 ERROR("SSA value %u not found\n", src
->index
);
724 return it
->second
[idx
];
728 Converter::getIndirect(nir_src
*src
, uint8_t idx
, Value
*&indirect
)
730 nir_const_value
*offset
= nir_src_as_const_value(*src
);
734 return offset
->u32
[0];
737 indirect
= getSrc(src
, idx
, true);
742 Converter::getIndirect(nir_intrinsic_instr
*insn
, uint8_t s
, uint8_t c
, Value
*&indirect
)
744 int32_t idx
= nir_intrinsic_base(insn
) + getIndirect(&insn
->src
[s
], c
, indirect
);
746 indirect
= mkOp2v(OP_SHL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), indirect
, loadImm(NULL
, 4));
751 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot
, unsigned *name
, unsigned *index
)
753 assert(name
&& index
);
755 if (slot
>= VERT_ATTRIB_MAX
) {
756 ERROR("invalid varying slot %u\n", slot
);
761 if (slot
>= VERT_ATTRIB_GENERIC0
&&
762 slot
< VERT_ATTRIB_GENERIC0
+ VERT_ATTRIB_GENERIC_MAX
) {
763 *name
= TGSI_SEMANTIC_GENERIC
;
764 *index
= slot
- VERT_ATTRIB_GENERIC0
;
768 if (slot
>= VERT_ATTRIB_TEX0
&&
769 slot
< VERT_ATTRIB_TEX0
+ VERT_ATTRIB_TEX_MAX
) {
770 *name
= TGSI_SEMANTIC_TEXCOORD
;
771 *index
= slot
- VERT_ATTRIB_TEX0
;
776 case VERT_ATTRIB_COLOR0
:
777 *name
= TGSI_SEMANTIC_COLOR
;
780 case VERT_ATTRIB_COLOR1
:
781 *name
= TGSI_SEMANTIC_COLOR
;
784 case VERT_ATTRIB_EDGEFLAG
:
785 *name
= TGSI_SEMANTIC_EDGEFLAG
;
788 case VERT_ATTRIB_FOG
:
789 *name
= TGSI_SEMANTIC_FOG
;
792 case VERT_ATTRIB_NORMAL
:
793 *name
= TGSI_SEMANTIC_NORMAL
;
796 case VERT_ATTRIB_POS
:
797 *name
= TGSI_SEMANTIC_POSITION
;
800 case VERT_ATTRIB_POINT_SIZE
:
801 *name
= TGSI_SEMANTIC_PSIZE
;
805 ERROR("unknown vert attrib slot %u\n", slot
);
812 varying_slot_to_tgsi_semantic(gl_varying_slot slot
, unsigned *name
, unsigned *index
)
814 assert(name
&& index
);
816 if (slot
>= VARYING_SLOT_TESS_MAX
) {
817 ERROR("invalid varying slot %u\n", slot
);
822 if (slot
>= VARYING_SLOT_PATCH0
) {
823 *name
= TGSI_SEMANTIC_PATCH
;
824 *index
= slot
- VARYING_SLOT_PATCH0
;
828 if (slot
>= VARYING_SLOT_VAR0
) {
829 *name
= TGSI_SEMANTIC_GENERIC
;
830 *index
= slot
- VARYING_SLOT_VAR0
;
834 if (slot
>= VARYING_SLOT_TEX0
&& slot
<= VARYING_SLOT_TEX7
) {
835 *name
= TGSI_SEMANTIC_TEXCOORD
;
836 *index
= slot
- VARYING_SLOT_TEX0
;
841 case VARYING_SLOT_BFC0
:
842 *name
= TGSI_SEMANTIC_BCOLOR
;
845 case VARYING_SLOT_BFC1
:
846 *name
= TGSI_SEMANTIC_BCOLOR
;
849 case VARYING_SLOT_CLIP_DIST0
:
850 *name
= TGSI_SEMANTIC_CLIPDIST
;
853 case VARYING_SLOT_CLIP_DIST1
:
854 *name
= TGSI_SEMANTIC_CLIPDIST
;
857 case VARYING_SLOT_CLIP_VERTEX
:
858 *name
= TGSI_SEMANTIC_CLIPVERTEX
;
861 case VARYING_SLOT_COL0
:
862 *name
= TGSI_SEMANTIC_COLOR
;
865 case VARYING_SLOT_COL1
:
866 *name
= TGSI_SEMANTIC_COLOR
;
869 case VARYING_SLOT_EDGE
:
870 *name
= TGSI_SEMANTIC_EDGEFLAG
;
873 case VARYING_SLOT_FACE
:
874 *name
= TGSI_SEMANTIC_FACE
;
877 case VARYING_SLOT_FOGC
:
878 *name
= TGSI_SEMANTIC_FOG
;
881 case VARYING_SLOT_LAYER
:
882 *name
= TGSI_SEMANTIC_LAYER
;
885 case VARYING_SLOT_PNTC
:
886 *name
= TGSI_SEMANTIC_PCOORD
;
889 case VARYING_SLOT_POS
:
890 *name
= TGSI_SEMANTIC_POSITION
;
893 case VARYING_SLOT_PRIMITIVE_ID
:
894 *name
= TGSI_SEMANTIC_PRIMID
;
897 case VARYING_SLOT_PSIZ
:
898 *name
= TGSI_SEMANTIC_PSIZE
;
901 case VARYING_SLOT_TESS_LEVEL_INNER
:
902 *name
= TGSI_SEMANTIC_TESSINNER
;
905 case VARYING_SLOT_TESS_LEVEL_OUTER
:
906 *name
= TGSI_SEMANTIC_TESSOUTER
;
909 case VARYING_SLOT_VIEWPORT
:
910 *name
= TGSI_SEMANTIC_VIEWPORT_INDEX
;
914 ERROR("unknown varying slot %u\n", slot
);
921 frag_result_to_tgsi_semantic(unsigned slot
, unsigned *name
, unsigned *index
)
923 if (slot
>= FRAG_RESULT_DATA0
) {
924 *name
= TGSI_SEMANTIC_COLOR
;
925 *index
= slot
- FRAG_RESULT_COLOR
- 2; // intentional
930 case FRAG_RESULT_COLOR
:
931 *name
= TGSI_SEMANTIC_COLOR
;
934 case FRAG_RESULT_DEPTH
:
935 *name
= TGSI_SEMANTIC_POSITION
;
938 case FRAG_RESULT_SAMPLE_MASK
:
939 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
943 ERROR("unknown frag result slot %u\n", slot
);
949 // copy of _mesa_sysval_to_semantic
951 system_val_to_tgsi_semantic(unsigned val
, unsigned *name
, unsigned *index
)
956 case SYSTEM_VALUE_VERTEX_ID
:
957 *name
= TGSI_SEMANTIC_VERTEXID
;
959 case SYSTEM_VALUE_INSTANCE_ID
:
960 *name
= TGSI_SEMANTIC_INSTANCEID
;
962 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
963 *name
= TGSI_SEMANTIC_VERTEXID_NOBASE
;
965 case SYSTEM_VALUE_BASE_VERTEX
:
966 *name
= TGSI_SEMANTIC_BASEVERTEX
;
968 case SYSTEM_VALUE_BASE_INSTANCE
:
969 *name
= TGSI_SEMANTIC_BASEINSTANCE
;
971 case SYSTEM_VALUE_DRAW_ID
:
972 *name
= TGSI_SEMANTIC_DRAWID
;
976 case SYSTEM_VALUE_INVOCATION_ID
:
977 *name
= TGSI_SEMANTIC_INVOCATIONID
;
981 case SYSTEM_VALUE_FRAG_COORD
:
982 *name
= TGSI_SEMANTIC_POSITION
;
984 case SYSTEM_VALUE_FRONT_FACE
:
985 *name
= TGSI_SEMANTIC_FACE
;
987 case SYSTEM_VALUE_SAMPLE_ID
:
988 *name
= TGSI_SEMANTIC_SAMPLEID
;
990 case SYSTEM_VALUE_SAMPLE_POS
:
991 *name
= TGSI_SEMANTIC_SAMPLEPOS
;
993 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
994 *name
= TGSI_SEMANTIC_SAMPLEMASK
;
996 case SYSTEM_VALUE_HELPER_INVOCATION
:
997 *name
= TGSI_SEMANTIC_HELPER_INVOCATION
;
1000 // Tessellation shader
1001 case SYSTEM_VALUE_TESS_COORD
:
1002 *name
= TGSI_SEMANTIC_TESSCOORD
;
1004 case SYSTEM_VALUE_VERTICES_IN
:
1005 *name
= TGSI_SEMANTIC_VERTICESIN
;
1007 case SYSTEM_VALUE_PRIMITIVE_ID
:
1008 *name
= TGSI_SEMANTIC_PRIMID
;
1010 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
1011 *name
= TGSI_SEMANTIC_TESSOUTER
;
1013 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
1014 *name
= TGSI_SEMANTIC_TESSINNER
;
1018 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
1019 *name
= TGSI_SEMANTIC_THREAD_ID
;
1021 case SYSTEM_VALUE_WORK_GROUP_ID
:
1022 *name
= TGSI_SEMANTIC_BLOCK_ID
;
1024 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
1025 *name
= TGSI_SEMANTIC_GRID_SIZE
;
1027 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
1028 *name
= TGSI_SEMANTIC_BLOCK_SIZE
;
1031 // ARB_shader_ballot
1032 case SYSTEM_VALUE_SUBGROUP_SIZE
:
1033 *name
= TGSI_SEMANTIC_SUBGROUP_SIZE
;
1035 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
1036 *name
= TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
1038 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
1039 *name
= TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
1041 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
1042 *name
= TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
1044 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
1045 *name
= TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
1047 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
1048 *name
= TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
1050 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
1051 *name
= TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
1055 ERROR("unknown system value %u\n", val
);
1062 Converter::setInterpolate(nv50_ir_varying
*var
,
1068 case INTERP_MODE_FLAT
:
1071 case INTERP_MODE_NONE
:
1072 if (semantic
== TGSI_SEMANTIC_COLOR
)
1074 else if (semantic
== TGSI_SEMANTIC_POSITION
)
1077 case INTERP_MODE_NOPERSPECTIVE
:
1080 case INTERP_MODE_SMOOTH
:
1083 var
->centroid
= centroid
;
1087 calcSlots(const glsl_type
*type
, Program::Type stage
, const shader_info
&info
,
1088 bool input
, const nir_variable
*var
)
1090 if (!type
->is_array())
1091 return type
->count_attribute_slots(false);
1095 case Program::TYPE_GEOMETRY
:
1096 slots
= type
->uniform_locations();
1098 slots
/= info
.gs
.vertices_in
;
1100 case Program::TYPE_TESSELLATION_CONTROL
:
1101 case Program::TYPE_TESSELLATION_EVAL
:
1102 // remove first dimension
1103 if (var
->data
.patch
|| (!input
&& stage
== Program::TYPE_TESSELLATION_EVAL
))
1104 slots
= type
->uniform_locations();
1106 slots
= type
->fields
.array
->uniform_locations();
1109 slots
= type
->count_attribute_slots(false);
1116 bool Converter::assignSlots() {
1120 info
->io
.viewportId
= -1;
1121 info
->numInputs
= 0;
1123 // we have to fixup the uniform locations for arrays
1124 unsigned numImages
= 0;
1125 nir_foreach_variable(var
, &nir
->uniforms
) {
1126 const glsl_type
*type
= var
->type
;
1127 if (!type
->without_array()->is_image())
1129 var
->data
.driver_location
= numImages
;
1130 numImages
+= type
->is_array() ? type
->arrays_of_arrays_size() : 1;
1133 nir_foreach_variable(var
, &nir
->inputs
) {
1134 const glsl_type
*type
= var
->type
;
1135 int slot
= var
->data
.location
;
1136 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, true, var
);
1137 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
1138 : type
->component_slots();
1139 uint32_t frac
= var
->data
.location_frac
;
1140 uint32_t vary
= var
->data
.driver_location
;
1142 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
1147 assert(vary
+ slots
<= PIPE_MAX_SHADER_INPUTS
);
1149 switch(prog
->getType()) {
1150 case Program::TYPE_FRAGMENT
:
1151 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1152 for (uint16_t i
= 0; i
< slots
; ++i
) {
1153 setInterpolate(&info
->in
[vary
+ i
], var
->data
.interpolation
,
1154 var
->data
.centroid
| var
->data
.sample
, name
);
1157 case Program::TYPE_GEOMETRY
:
1158 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1160 case Program::TYPE_TESSELLATION_CONTROL
:
1161 case Program::TYPE_TESSELLATION_EVAL
:
1162 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1163 if (var
->data
.patch
&& name
== TGSI_SEMANTIC_PATCH
)
1164 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
1166 case Program::TYPE_VERTEX
:
1167 vert_attrib_to_tgsi_semantic((gl_vert_attrib
)slot
, &name
, &index
);
1169 case TGSI_SEMANTIC_EDGEFLAG
:
1170 info
->io
.edgeFlagIn
= vary
;
1177 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1181 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1182 info
->in
[vary
].id
= vary
;
1183 info
->in
[vary
].patch
= var
->data
.patch
;
1184 info
->in
[vary
].sn
= name
;
1185 info
->in
[vary
].si
= index
+ i
;
1186 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1188 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1190 info
->in
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1192 info
->in
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1194 info
->numInputs
= std::max
<uint8_t>(info
->numInputs
, vary
);
1197 info
->numOutputs
= 0;
1198 nir_foreach_variable(var
, &nir
->outputs
) {
1199 const glsl_type
*type
= var
->type
;
1200 int slot
= var
->data
.location
;
1201 uint16_t slots
= calcSlots(type
, prog
->getType(), nir
->info
, false, var
);
1202 uint32_t comp
= type
->is_array() ? type
->without_array()->component_slots()
1203 : type
->component_slots();
1204 uint32_t frac
= var
->data
.location_frac
;
1205 uint32_t vary
= var
->data
.driver_location
;
1207 if (glsl_base_type_is_64bit(type
->without_array()->base_type
)) {
1212 assert(vary
< PIPE_MAX_SHADER_OUTPUTS
);
1214 switch(prog
->getType()) {
1215 case Program::TYPE_FRAGMENT
:
1216 frag_result_to_tgsi_semantic((gl_frag_result
)slot
, &name
, &index
);
1218 case TGSI_SEMANTIC_COLOR
:
1219 if (!var
->data
.fb_fetch_output
)
1220 info
->prop
.fp
.numColourResults
++;
1221 info
->prop
.fp
.separateFragData
= true;
1222 // sometimes we get FRAG_RESULT_DATAX with data.index 0
1223 // sometimes we get FRAG_RESULT_DATA0 with data.index X
1224 index
= index
== 0 ? var
->data
.index
: index
;
1226 case TGSI_SEMANTIC_POSITION
:
1227 info
->io
.fragDepth
= vary
;
1228 info
->prop
.fp
.writesDepth
= true;
1230 case TGSI_SEMANTIC_SAMPLEMASK
:
1231 info
->io
.sampleMask
= vary
;
1237 case Program::TYPE_GEOMETRY
:
1238 case Program::TYPE_TESSELLATION_CONTROL
:
1239 case Program::TYPE_TESSELLATION_EVAL
:
1240 case Program::TYPE_VERTEX
:
1241 varying_slot_to_tgsi_semantic((gl_varying_slot
)slot
, &name
, &index
);
1243 if (var
->data
.patch
&& name
!= TGSI_SEMANTIC_TESSINNER
&&
1244 name
!= TGSI_SEMANTIC_TESSOUTER
)
1245 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, index
+ slots
);
1248 case TGSI_SEMANTIC_CLIPDIST
:
1249 info
->io
.genUserClip
= -1;
1251 case TGSI_SEMANTIC_CLIPVERTEX
:
1252 clipVertexOutput
= vary
;
1254 case TGSI_SEMANTIC_EDGEFLAG
:
1255 info
->io
.edgeFlagOut
= vary
;
1257 case TGSI_SEMANTIC_POSITION
:
1258 if (clipVertexOutput
< 0)
1259 clipVertexOutput
= vary
;
1266 ERROR("unknown shader type %u in assignSlots\n", prog
->getType());
1270 for (uint16_t i
= 0u; i
< slots
; ++i
, ++vary
) {
1271 info
->out
[vary
].id
= vary
;
1272 info
->out
[vary
].patch
= var
->data
.patch
;
1273 info
->out
[vary
].sn
= name
;
1274 info
->out
[vary
].si
= index
+ i
;
1275 if (glsl_base_type_is_64bit(type
->without_array()->base_type
))
1277 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) >> 0x4);
1279 info
->out
[vary
].mask
|= (((1 << (comp
* 2)) - 1) << (frac
* 2) & 0xf);
1281 info
->out
[vary
].mask
|= ((1 << comp
) - 1) << frac
;
1283 if (nir
->info
.outputs_read
& 1ll << slot
)
1284 info
->out
[vary
].oread
= 1;
1286 info
->numOutputs
= std::max
<uint8_t>(info
->numOutputs
, vary
);
1289 info
->numSysVals
= 0;
1290 for (uint8_t i
= 0; i
< 64; ++i
) {
1291 if (!(nir
->info
.system_values_read
& 1ll << i
))
1294 system_val_to_tgsi_semantic(i
, &name
, &index
);
1295 info
->sv
[info
->numSysVals
].sn
= name
;
1296 info
->sv
[info
->numSysVals
].si
= index
;
1297 info
->sv
[info
->numSysVals
].input
= 0; // TODO inferSysValDirection(sn);
1300 case SYSTEM_VALUE_INSTANCE_ID
:
1301 info
->io
.instanceId
= info
->numSysVals
;
1303 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
1304 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
1305 info
->sv
[info
->numSysVals
].patch
= 1;
1307 case SYSTEM_VALUE_VERTEX_ID
:
1308 info
->io
.vertexId
= info
->numSysVals
;
1314 info
->numSysVals
+= 1;
1317 if (info
->io
.genUserClip
> 0) {
1318 info
->io
.clipDistances
= info
->io
.genUserClip
;
1320 const unsigned int nOut
= (info
->io
.genUserClip
+ 3) / 4;
1322 for (unsigned int n
= 0; n
< nOut
; ++n
) {
1323 unsigned int i
= info
->numOutputs
++;
1324 info
->out
[i
].id
= i
;
1325 info
->out
[i
].sn
= TGSI_SEMANTIC_CLIPDIST
;
1326 info
->out
[i
].si
= n
;
1327 info
->out
[i
].mask
= ((1 << info
->io
.clipDistances
) - 1) >> (n
* 4);
1331 return info
->assignSlots(info
) == 0;
1335 Converter::getSlotAddress(nir_intrinsic_instr
*insn
, uint8_t idx
, uint8_t slot
)
1338 int offset
= nir_intrinsic_component(insn
);
1341 if (nir_intrinsic_infos
[insn
->intrinsic
].has_dest
)
1342 ty
= getDType(insn
);
1344 ty
= getSType(insn
->src
[0], false, false);
1346 switch (insn
->intrinsic
) {
1347 case nir_intrinsic_load_input
:
1348 case nir_intrinsic_load_interpolated_input
:
1349 case nir_intrinsic_load_per_vertex_input
:
1352 case nir_intrinsic_load_output
:
1353 case nir_intrinsic_load_per_vertex_output
:
1354 case nir_intrinsic_store_output
:
1355 case nir_intrinsic_store_per_vertex_output
:
1359 ERROR("unknown intrinsic in getSlotAddress %s",
1360 nir_intrinsic_infos
[insn
->intrinsic
].name
);
1366 if (typeSizeof(ty
) == 8) {
1378 assert(!input
|| idx
< PIPE_MAX_SHADER_INPUTS
);
1379 assert(input
|| idx
< PIPE_MAX_SHADER_OUTPUTS
);
1381 const nv50_ir_varying
*vary
= input
? info
->in
: info
->out
;
1382 return vary
[idx
].slot
[slot
] * 4;
1386 Converter::loadFrom(DataFile file
, uint8_t i
, DataType ty
, Value
*def
,
1387 uint32_t base
, uint8_t c
, Value
*indirect0
,
1388 Value
*indirect1
, bool patch
)
1390 unsigned int tySize
= typeSizeof(ty
);
1393 (file
== FILE_MEMORY_CONST
|| file
== FILE_MEMORY_BUFFER
|| indirect0
)) {
1394 Value
*lo
= getSSA();
1395 Value
*hi
= getSSA();
1398 mkLoad(TYPE_U32
, lo
,
1399 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
),
1401 loi
->setIndirect(0, 1, indirect1
);
1402 loi
->perPatch
= patch
;
1405 mkLoad(TYPE_U32
, hi
,
1406 mkSymbol(file
, i
, TYPE_U32
, base
+ c
* tySize
+ 4),
1408 hii
->setIndirect(0, 1, indirect1
);
1409 hii
->perPatch
= patch
;
1411 return mkOp2(OP_MERGE
, ty
, def
, lo
, hi
);
1414 mkLoad(ty
, def
, mkSymbol(file
, i
, ty
, base
+ c
* tySize
), indirect0
);
1415 ld
->setIndirect(0, 1, indirect1
);
1416 ld
->perPatch
= patch
;
1422 Converter::storeTo(nir_intrinsic_instr
*insn
, DataFile file
, operation op
,
1423 DataType ty
, Value
*src
, uint8_t idx
, uint8_t c
,
1424 Value
*indirect0
, Value
*indirect1
)
1426 uint8_t size
= typeSizeof(ty
);
1427 uint32_t address
= getSlotAddress(insn
, idx
, c
);
1429 if (size
== 8 && indirect0
) {
1431 mkSplit(split
, 4, src
);
1433 if (op
== OP_EXPORT
) {
1434 split
[0] = mkMov(getSSA(), split
[0], ty
)->getDef(0);
1435 split
[1] = mkMov(getSSA(), split
[1], ty
)->getDef(0);
1438 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
), indirect0
,
1439 split
[0])->perPatch
= info
->out
[idx
].patch
;
1440 mkStore(op
, TYPE_U32
, mkSymbol(file
, 0, TYPE_U32
, address
+ 4), indirect0
,
1441 split
[1])->perPatch
= info
->out
[idx
].patch
;
1443 if (op
== OP_EXPORT
)
1444 src
= mkMov(getSSA(size
), src
, ty
)->getDef(0);
1445 mkStore(op
, ty
, mkSymbol(file
, 0, ty
, address
), indirect0
,
1446 src
)->perPatch
= info
->out
[idx
].patch
;
1451 Converter::parseNIR()
1453 info
->bin
.tlsSpace
= 0;
1454 info
->io
.clipDistances
= nir
->info
.clip_distance_array_size
;
1455 info
->io
.cullDistances
= nir
->info
.cull_distance_array_size
;
1457 switch(prog
->getType()) {
1458 case Program::TYPE_COMPUTE
:
1459 info
->prop
.cp
.numThreads
[0] = nir
->info
.cs
.local_size
[0];
1460 info
->prop
.cp
.numThreads
[1] = nir
->info
.cs
.local_size
[1];
1461 info
->prop
.cp
.numThreads
[2] = nir
->info
.cs
.local_size
[2];
1462 info
->bin
.smemSize
= nir
->info
.cs
.shared_size
;
1464 case Program::TYPE_FRAGMENT
:
1465 info
->prop
.fp
.earlyFragTests
= nir
->info
.fs
.early_fragment_tests
;
1466 info
->prop
.fp
.persampleInvocation
=
1467 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_ID
) ||
1468 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1469 info
->prop
.fp
.postDepthCoverage
= nir
->info
.fs
.post_depth_coverage
;
1470 info
->prop
.fp
.readsSampleLocations
=
1471 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
1472 info
->prop
.fp
.usesDiscard
= nir
->info
.fs
.uses_discard
;
1473 info
->prop
.fp
.usesSampleMaskIn
=
1474 !!(nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
);
1476 case Program::TYPE_GEOMETRY
:
1477 info
->prop
.gp
.inputPrim
= nir
->info
.gs
.input_primitive
;
1478 info
->prop
.gp
.instanceCount
= nir
->info
.gs
.invocations
;
1479 info
->prop
.gp
.maxVertices
= nir
->info
.gs
.vertices_out
;
1480 info
->prop
.gp
.outputPrim
= nir
->info
.gs
.output_primitive
;
1482 case Program::TYPE_TESSELLATION_CONTROL
:
1483 case Program::TYPE_TESSELLATION_EVAL
:
1484 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1485 info
->prop
.tp
.domain
= GL_LINES
;
1487 info
->prop
.tp
.domain
= nir
->info
.tess
.primitive_mode
;
1488 info
->prop
.tp
.outputPatchSize
= nir
->info
.tess
.tcs_vertices_out
;
1489 info
->prop
.tp
.outputPrim
=
1490 nir
->info
.tess
.point_mode
? PIPE_PRIM_POINTS
: PIPE_PRIM_TRIANGLES
;
1491 info
->prop
.tp
.partitioning
= (nir
->info
.tess
.spacing
+ 1) % 3;
1492 info
->prop
.tp
.winding
= !nir
->info
.tess
.ccw
;
1494 case Program::TYPE_VERTEX
:
1495 info
->prop
.vp
.usesDrawParameters
=
1496 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
)) ||
1497 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
)) ||
1498 (nir
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
));
1508 Converter::visit(nir_function
*function
)
1510 // we only support emiting the main function for now
1511 assert(!strcmp(function
->name
, "main"));
1512 assert(function
->impl
);
1514 // usually the blocks will set everything up, but main is special
1515 BasicBlock
*entry
= new BasicBlock(prog
->main
);
1516 exit
= new BasicBlock(prog
->main
);
1517 blocks
[nir_start_block(function
->impl
)->index
] = entry
;
1518 prog
->main
->setEntry(entry
);
1519 prog
->main
->setExit(exit
);
1521 setPosition(entry
, true);
1523 if (info
->io
.genUserClip
> 0) {
1524 for (int c
= 0; c
< 4; ++c
)
1525 clipVtx
[c
] = getScratch();
1528 switch (prog
->getType()) {
1529 case Program::TYPE_TESSELLATION_CONTROL
:
1531 OP_SUB
, TYPE_U32
, getSSA(),
1532 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LANEID
, 0)),
1533 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_INVOCATION_ID
, 0)));
1535 case Program::TYPE_FRAGMENT
: {
1536 Symbol
*sv
= mkSysVal(SV_POSITION
, 3);
1537 fragCoord
[3] = mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), sv
);
1538 fp
.position
= mkOp1v(OP_RCP
, TYPE_F32
, fragCoord
[3], fragCoord
[3]);
1545 nir_foreach_register(reg
, &function
->impl
->registers
) {
1546 if (reg
->num_array_elems
) {
1547 // TODO: packed variables would be nice, but MemoryOpt fails
1548 // replace 4 with reg->num_components
1549 uint32_t size
= 4 * reg
->num_array_elems
* (reg
->bit_size
/ 8);
1550 regToLmemOffset
[reg
->index
] = info
->bin
.tlsSpace
;
1551 info
->bin
.tlsSpace
+= size
;
1555 nir_index_ssa_defs(function
->impl
);
1556 foreach_list_typed(nir_cf_node
, node
, node
, &function
->impl
->body
) {
1561 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::TREE
);
1562 setPosition(exit
, true);
1564 if (info
->io
.genUserClip
> 0)
1565 handleUserClipPlanes();
1567 // TODO: for non main function this needs to be a OP_RETURN
1568 mkOp(OP_EXIT
, TYPE_NONE
, NULL
)->terminator
= 1;
1573 Converter::visit(nir_cf_node
*node
)
1575 switch (node
->type
) {
1576 case nir_cf_node_block
:
1577 return visit(nir_cf_node_as_block(node
));
1578 case nir_cf_node_if
:
1579 return visit(nir_cf_node_as_if(node
));
1580 case nir_cf_node_loop
:
1581 return visit(nir_cf_node_as_loop(node
));
1583 ERROR("unknown nir_cf_node type %u\n", node
->type
);
1589 Converter::visit(nir_block
*block
)
1591 if (!block
->predecessors
->entries
&& block
->instr_list
.is_empty())
1594 BasicBlock
*bb
= convert(block
);
1596 setPosition(bb
, true);
1597 nir_foreach_instr(insn
, block
) {
1605 Converter::visit(nir_if
*nif
)
1607 DataType sType
= getSType(nif
->condition
, false, false);
1608 Value
*src
= getSrc(&nif
->condition
, 0);
1610 nir_block
*lastThen
= nir_if_last_then_block(nif
);
1611 nir_block
*lastElse
= nir_if_last_else_block(nif
);
1613 assert(!lastThen
->successors
[1]);
1614 assert(!lastElse
->successors
[1]);
1616 BasicBlock
*ifBB
= convert(nir_if_first_then_block(nif
));
1617 BasicBlock
*elseBB
= convert(nir_if_first_else_block(nif
));
1619 bb
->cfg
.attach(&ifBB
->cfg
, Graph::Edge::TREE
);
1620 bb
->cfg
.attach(&elseBB
->cfg
, Graph::Edge::TREE
);
1622 // we only insert joinats, if both nodes end up at the end of the if again.
1623 // the reason for this to not happens are breaks/continues/ret/... which
1624 // have their own handling
1625 if (lastThen
->successors
[0] == lastElse
->successors
[0])
1626 bb
->joinAt
= mkFlow(OP_JOINAT
, convert(lastThen
->successors
[0]),
1629 mkFlow(OP_BRA
, elseBB
, CC_EQ
, src
)->setType(sType
);
1631 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->then_list
) {
1635 setPosition(convert(lastThen
), true);
1636 if (!bb
->getExit() ||
1637 !bb
->getExit()->asFlow() ||
1638 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1639 BasicBlock
*tailBB
= convert(lastThen
->successors
[0]);
1640 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1641 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1644 foreach_list_typed(nir_cf_node
, node
, node
, &nif
->else_list
) {
1648 setPosition(convert(lastElse
), true);
1649 if (!bb
->getExit() ||
1650 !bb
->getExit()->asFlow() ||
1651 bb
->getExit()->asFlow()->op
== OP_JOIN
) {
1652 BasicBlock
*tailBB
= convert(lastElse
->successors
[0]);
1653 mkFlow(OP_BRA
, tailBB
, CC_ALWAYS
, NULL
);
1654 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::FORWARD
);
1657 if (lastThen
->successors
[0] == lastElse
->successors
[0]) {
1658 setPosition(convert(lastThen
->successors
[0]), true);
1659 mkFlow(OP_JOIN
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
1666 Converter::visit(nir_loop
*loop
)
1669 func
->loopNestingBound
= std::max(func
->loopNestingBound
, curLoopDepth
);
1671 BasicBlock
*loopBB
= convert(nir_loop_first_block(loop
));
1672 BasicBlock
*tailBB
=
1673 convert(nir_cf_node_as_block(nir_cf_node_next(&loop
->cf_node
)));
1674 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::TREE
);
1676 mkFlow(OP_PREBREAK
, tailBB
, CC_ALWAYS
, NULL
);
1677 setPosition(loopBB
, false);
1678 mkFlow(OP_PRECONT
, loopBB
, CC_ALWAYS
, NULL
);
1680 foreach_list_typed(nir_cf_node
, node
, node
, &loop
->body
) {
1684 Instruction
*insn
= bb
->getExit();
1685 if (bb
->cfg
.incidentCount() != 0) {
1686 if (!insn
|| !insn
->asFlow()) {
1687 mkFlow(OP_CONT
, loopBB
, CC_ALWAYS
, NULL
);
1688 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::BACK
);
1689 } else if (insn
&& insn
->op
== OP_BRA
&& !insn
->getPredicate() &&
1690 tailBB
->cfg
.incidentCount() == 0) {
1691 // RA doesn't like having blocks around with no incident edge,
1692 // so we create a fake one to make it happy
1693 bb
->cfg
.attach(&tailBB
->cfg
, Graph::Edge::TREE
);
1703 Converter::visit(nir_instr
*insn
)
1705 switch (insn
->type
) {
1706 case nir_instr_type_alu
:
1707 return visit(nir_instr_as_alu(insn
));
1708 case nir_instr_type_deref
:
1709 return visit(nir_instr_as_deref(insn
));
1710 case nir_instr_type_intrinsic
:
1711 return visit(nir_instr_as_intrinsic(insn
));
1712 case nir_instr_type_jump
:
1713 return visit(nir_instr_as_jump(insn
));
1714 case nir_instr_type_load_const
:
1715 return visit(nir_instr_as_load_const(insn
));
1716 case nir_instr_type_ssa_undef
:
1717 return visit(nir_instr_as_ssa_undef(insn
));
1718 case nir_instr_type_tex
:
1719 return visit(nir_instr_as_tex(insn
));
1721 ERROR("unknown nir_instr type %u\n", insn
->type
);
1728 Converter::convert(nir_intrinsic_op intr
)
1731 case nir_intrinsic_load_base_vertex
:
1732 return SV_BASEVERTEX
;
1733 case nir_intrinsic_load_base_instance
:
1734 return SV_BASEINSTANCE
;
1735 case nir_intrinsic_load_draw_id
:
1737 case nir_intrinsic_load_front_face
:
1739 case nir_intrinsic_load_helper_invocation
:
1740 return SV_THREAD_KILL
;
1741 case nir_intrinsic_load_instance_id
:
1742 return SV_INSTANCE_ID
;
1743 case nir_intrinsic_load_invocation_id
:
1744 return SV_INVOCATION_ID
;
1745 case nir_intrinsic_load_local_group_size
:
1747 case nir_intrinsic_load_local_invocation_id
:
1749 case nir_intrinsic_load_num_work_groups
:
1751 case nir_intrinsic_load_patch_vertices_in
:
1752 return SV_VERTEX_COUNT
;
1753 case nir_intrinsic_load_primitive_id
:
1754 return SV_PRIMITIVE_ID
;
1755 case nir_intrinsic_load_sample_id
:
1756 return SV_SAMPLE_INDEX
;
1757 case nir_intrinsic_load_sample_mask_in
:
1758 return SV_SAMPLE_MASK
;
1759 case nir_intrinsic_load_sample_pos
:
1760 return SV_SAMPLE_POS
;
1761 case nir_intrinsic_load_subgroup_eq_mask
:
1762 return SV_LANEMASK_EQ
;
1763 case nir_intrinsic_load_subgroup_ge_mask
:
1764 return SV_LANEMASK_GE
;
1765 case nir_intrinsic_load_subgroup_gt_mask
:
1766 return SV_LANEMASK_GT
;
1767 case nir_intrinsic_load_subgroup_le_mask
:
1768 return SV_LANEMASK_LE
;
1769 case nir_intrinsic_load_subgroup_lt_mask
:
1770 return SV_LANEMASK_LT
;
1771 case nir_intrinsic_load_subgroup_invocation
:
1773 case nir_intrinsic_load_tess_coord
:
1774 return SV_TESS_COORD
;
1775 case nir_intrinsic_load_tess_level_inner
:
1776 return SV_TESS_INNER
;
1777 case nir_intrinsic_load_tess_level_outer
:
1778 return SV_TESS_OUTER
;
1779 case nir_intrinsic_load_vertex_id
:
1780 return SV_VERTEX_ID
;
1781 case nir_intrinsic_load_work_group_id
:
1784 ERROR("unknown SVSemantic for nir_intrinsic_op %s\n",
1785 nir_intrinsic_infos
[intr
].name
);
1792 Converter::convertGLImgFormat(GLuint format
)
1794 #define FMT_CASE(a, b) \
1795 case GL_ ## a: return nv50_ir::FMT_ ## b
1798 FMT_CASE(NONE
, NONE
);
1800 FMT_CASE(RGBA32F
, RGBA32F
);
1801 FMT_CASE(RGBA16F
, RGBA16F
);
1802 FMT_CASE(RG32F
, RG32F
);
1803 FMT_CASE(RG16F
, RG16F
);
1804 FMT_CASE(R11F_G11F_B10F
, R11G11B10F
);
1805 FMT_CASE(R32F
, R32F
);
1806 FMT_CASE(R16F
, R16F
);
1808 FMT_CASE(RGBA32UI
, RGBA32UI
);
1809 FMT_CASE(RGBA16UI
, RGBA16UI
);
1810 FMT_CASE(RGB10_A2UI
, RGB10A2UI
);
1811 FMT_CASE(RGBA8UI
, RGBA8UI
);
1812 FMT_CASE(RG32UI
, RG32UI
);
1813 FMT_CASE(RG16UI
, RG16UI
);
1814 FMT_CASE(RG8UI
, RG8UI
);
1815 FMT_CASE(R32UI
, R32UI
);
1816 FMT_CASE(R16UI
, R16UI
);
1817 FMT_CASE(R8UI
, R8UI
);
1819 FMT_CASE(RGBA32I
, RGBA32I
);
1820 FMT_CASE(RGBA16I
, RGBA16I
);
1821 FMT_CASE(RGBA8I
, RGBA8I
);
1822 FMT_CASE(RG32I
, RG32I
);
1823 FMT_CASE(RG16I
, RG16I
);
1824 FMT_CASE(RG8I
, RG8I
);
1825 FMT_CASE(R32I
, R32I
);
1826 FMT_CASE(R16I
, R16I
);
1829 FMT_CASE(RGBA16
, RGBA16
);
1830 FMT_CASE(RGB10_A2
, RGB10A2
);
1831 FMT_CASE(RGBA8
, RGBA8
);
1832 FMT_CASE(RG16
, RG16
);
1837 FMT_CASE(RGBA16_SNORM
, RGBA16_SNORM
);
1838 FMT_CASE(RGBA8_SNORM
, RGBA8_SNORM
);
1839 FMT_CASE(RG16_SNORM
, RG16_SNORM
);
1840 FMT_CASE(RG8_SNORM
, RG8_SNORM
);
1841 FMT_CASE(R16_SNORM
, R16_SNORM
);
1842 FMT_CASE(R8_SNORM
, R8_SNORM
);
1844 FMT_CASE(BGRA_INTEGER
, BGRA8
);
1846 ERROR("unknown format %x\n", format
);
1848 return nv50_ir::FMT_NONE
;
1854 Converter::visit(nir_intrinsic_instr
*insn
)
1856 nir_intrinsic_op op
= insn
->intrinsic
;
1857 const nir_intrinsic_info
&opInfo
= nir_intrinsic_infos
[op
];
1860 case nir_intrinsic_load_uniform
: {
1861 LValues
&newDefs
= convert(&insn
->dest
);
1862 const DataType dType
= getDType(insn
);
1864 uint32_t coffset
= getIndirect(insn
, 0, 0, indirect
);
1865 for (uint8_t i
= 0; i
< insn
->num_components
; ++i
) {
1866 loadFrom(FILE_MEMORY_CONST
, 0, dType
, newDefs
[i
], 16 * coffset
, i
, indirect
);
1870 case nir_intrinsic_store_output
:
1871 case nir_intrinsic_store_per_vertex_output
: {
1873 DataType dType
= getSType(insn
->src
[0], false, false);
1874 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_store_output
? 1 : 2, 0, indirect
);
1876 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1877 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
1881 Value
*src
= getSrc(&insn
->src
[0], i
);
1882 switch (prog
->getType()) {
1883 case Program::TYPE_FRAGMENT
: {
1884 if (info
->out
[idx
].sn
== TGSI_SEMANTIC_POSITION
) {
1885 // TGSI uses a different interface than NIR, TGSI stores that
1886 // value in the z component, NIR in X
1888 src
= mkOp1v(OP_SAT
, TYPE_F32
, getScratch(), src
);
1892 case Program::TYPE_VERTEX
: {
1893 if (info
->io
.genUserClip
> 0 && idx
== clipVertexOutput
) {
1894 mkMov(clipVtx
[i
], src
);
1903 storeTo(insn
, FILE_SHADER_OUTPUT
, OP_EXPORT
, dType
, src
, idx
, i
+ offset
, indirect
);
1907 case nir_intrinsic_load_input
:
1908 case nir_intrinsic_load_interpolated_input
:
1909 case nir_intrinsic_load_output
: {
1910 LValues
&newDefs
= convert(&insn
->dest
);
1913 if (prog
->getType() == Program::TYPE_FRAGMENT
&&
1914 op
== nir_intrinsic_load_output
) {
1915 std::vector
<Value
*> defs
, srcs
;
1918 srcs
.push_back(getSSA());
1919 srcs
.push_back(getSSA());
1920 Value
*x
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 0));
1921 Value
*y
= mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 1));
1922 mkCvt(OP_CVT
, TYPE_U32
, srcs
[0], TYPE_F32
, x
)->rnd
= ROUND_Z
;
1923 mkCvt(OP_CVT
, TYPE_U32
, srcs
[1], TYPE_F32
, y
)->rnd
= ROUND_Z
;
1925 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LAYER
, 0)));
1926 srcs
.push_back(mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_SAMPLE_INDEX
, 0)));
1928 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1929 defs
.push_back(newDefs
[i
]);
1933 TexInstruction
*texi
= mkTex(OP_TXF
, TEX_TARGET_2D_MS_ARRAY
, 0, 0, defs
, srcs
);
1934 texi
->tex
.levelZero
= 1;
1935 texi
->tex
.mask
= mask
;
1936 texi
->tex
.useOffsets
= 0;
1937 texi
->tex
.r
= 0xffff;
1938 texi
->tex
.s
= 0xffff;
1940 info
->prop
.fp
.readsFramebuffer
= true;
1944 const DataType dType
= getDType(insn
);
1946 bool input
= op
!= nir_intrinsic_load_output
;
1950 uint32_t idx
= getIndirect(insn
, op
== nir_intrinsic_load_interpolated_input
? 1 : 0, 0, indirect
);
1951 nv50_ir_varying
& vary
= input
? info
->in
[idx
] : info
->out
[idx
];
1953 // see load_barycentric_* handling
1954 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1955 mode
= translateInterpMode(&vary
, nvirOp
);
1956 if (op
== nir_intrinsic_load_interpolated_input
) {
1957 ImmediateValue immMode
;
1958 if (getSrc(&insn
->src
[0], 1)->getUniqueInsn()->src(0).getImmediate(immMode
))
1959 mode
|= immMode
.reg
.data
.u32
;
1963 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
1964 uint32_t address
= getSlotAddress(insn
, idx
, i
);
1965 Symbol
*sym
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
);
1966 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
1968 if (typeSizeof(dType
) == 8) {
1969 Value
*lo
= getSSA();
1970 Value
*hi
= getSSA();
1971 Instruction
*interp
;
1973 interp
= mkOp1(nvirOp
, TYPE_U32
, lo
, sym
);
1974 if (nvirOp
== OP_PINTERP
)
1975 interp
->setSrc(s
++, fp
.position
);
1976 if (mode
& NV50_IR_INTERP_OFFSET
)
1977 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1978 interp
->setInterpolate(mode
);
1979 interp
->setIndirect(0, 0, indirect
);
1981 Symbol
*sym1
= mkSymbol(input
? FILE_SHADER_INPUT
: FILE_SHADER_OUTPUT
, 0, dType
, address
+ 4);
1982 interp
= mkOp1(nvirOp
, TYPE_U32
, hi
, sym1
);
1983 if (nvirOp
== OP_PINTERP
)
1984 interp
->setSrc(s
++, fp
.position
);
1985 if (mode
& NV50_IR_INTERP_OFFSET
)
1986 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1987 interp
->setInterpolate(mode
);
1988 interp
->setIndirect(0, 0, indirect
);
1990 mkOp2(OP_MERGE
, dType
, newDefs
[i
], lo
, hi
);
1992 Instruction
*interp
= mkOp1(nvirOp
, dType
, newDefs
[i
], sym
);
1993 if (nvirOp
== OP_PINTERP
)
1994 interp
->setSrc(s
++, fp
.position
);
1995 if (mode
& NV50_IR_INTERP_OFFSET
)
1996 interp
->setSrc(s
++, getSrc(&insn
->src
[0], 0));
1997 interp
->setInterpolate(mode
);
1998 interp
->setIndirect(0, 0, indirect
);
2001 mkLoad(dType
, newDefs
[i
], sym
, indirect
)->perPatch
= vary
.patch
;
2006 case nir_intrinsic_load_barycentric_at_offset
:
2007 case nir_intrinsic_load_barycentric_at_sample
:
2008 case nir_intrinsic_load_barycentric_centroid
:
2009 case nir_intrinsic_load_barycentric_pixel
:
2010 case nir_intrinsic_load_barycentric_sample
: {
2011 LValues
&newDefs
= convert(&insn
->dest
);
2014 if (op
== nir_intrinsic_load_barycentric_centroid
||
2015 op
== nir_intrinsic_load_barycentric_sample
) {
2016 mode
= NV50_IR_INTERP_CENTROID
;
2017 } else if (op
== nir_intrinsic_load_barycentric_at_offset
) {
2019 for (uint8_t c
= 0; c
< 2; c
++) {
2020 offs
[c
] = getScratch();
2021 mkOp2(OP_MIN
, TYPE_F32
, offs
[c
], getSrc(&insn
->src
[0], c
), loadImm(NULL
, 0.4375f
));
2022 mkOp2(OP_MAX
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, -0.5f
));
2023 mkOp2(OP_MUL
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, 4096.0f
));
2024 mkCvt(OP_CVT
, TYPE_S32
, offs
[c
], TYPE_F32
, offs
[c
]);
2026 mkOp3v(OP_INSBF
, TYPE_U32
, newDefs
[0], offs
[1], mkImm(0x1010), offs
[0]);
2028 mode
= NV50_IR_INTERP_OFFSET
;
2029 } else if (op
== nir_intrinsic_load_barycentric_pixel
) {
2030 mode
= NV50_IR_INTERP_DEFAULT
;
2031 } else if (op
== nir_intrinsic_load_barycentric_at_sample
) {
2032 info
->prop
.fp
.readsSampleLocations
= true;
2033 mkOp1(OP_PIXLD
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0], 0))->subOp
= NV50_IR_SUBOP_PIXLD_OFFSET
;
2034 mode
= NV50_IR_INTERP_OFFSET
;
2036 unreachable("all intrinsics already handled above");
2039 loadImm(newDefs
[1], mode
);
2042 case nir_intrinsic_discard
:
2043 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
);
2045 case nir_intrinsic_discard_if
: {
2046 Value
*pred
= getSSA(1, FILE_PREDICATE
);
2047 if (insn
->num_components
> 1) {
2048 ERROR("nir_intrinsic_discard_if only with 1 component supported!\n");
2052 mkCmp(OP_SET
, CC_NE
, TYPE_U8
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
2053 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
)->setPredicate(CC_P
, pred
);
2056 case nir_intrinsic_load_base_vertex
:
2057 case nir_intrinsic_load_base_instance
:
2058 case nir_intrinsic_load_draw_id
:
2059 case nir_intrinsic_load_front_face
:
2060 case nir_intrinsic_load_helper_invocation
:
2061 case nir_intrinsic_load_instance_id
:
2062 case nir_intrinsic_load_invocation_id
:
2063 case nir_intrinsic_load_local_group_size
:
2064 case nir_intrinsic_load_local_invocation_id
:
2065 case nir_intrinsic_load_num_work_groups
:
2066 case nir_intrinsic_load_patch_vertices_in
:
2067 case nir_intrinsic_load_primitive_id
:
2068 case nir_intrinsic_load_sample_id
:
2069 case nir_intrinsic_load_sample_mask_in
:
2070 case nir_intrinsic_load_sample_pos
:
2071 case nir_intrinsic_load_subgroup_eq_mask
:
2072 case nir_intrinsic_load_subgroup_ge_mask
:
2073 case nir_intrinsic_load_subgroup_gt_mask
:
2074 case nir_intrinsic_load_subgroup_le_mask
:
2075 case nir_intrinsic_load_subgroup_lt_mask
:
2076 case nir_intrinsic_load_subgroup_invocation
:
2077 case nir_intrinsic_load_tess_coord
:
2078 case nir_intrinsic_load_tess_level_inner
:
2079 case nir_intrinsic_load_tess_level_outer
:
2080 case nir_intrinsic_load_vertex_id
:
2081 case nir_intrinsic_load_work_group_id
: {
2082 const DataType dType
= getDType(insn
);
2083 SVSemantic sv
= convert(op
);
2084 LValues
&newDefs
= convert(&insn
->dest
);
2086 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2088 if (typeSizeof(dType
) == 8)
2093 if (sv
== SV_TID
&& info
->prop
.cp
.numThreads
[i
] == 1) {
2096 Symbol
*sym
= mkSysVal(sv
, i
);
2097 Instruction
*rdsv
= mkOp1(OP_RDSV
, TYPE_U32
, def
, sym
);
2098 if (sv
== SV_TESS_OUTER
|| sv
== SV_TESS_INNER
)
2102 if (typeSizeof(dType
) == 8)
2103 mkOp2(OP_MERGE
, dType
, newDefs
[i
], def
, loadImm(getSSA(), 0u));
2108 case nir_intrinsic_load_subgroup_size
: {
2109 LValues
&newDefs
= convert(&insn
->dest
);
2110 loadImm(newDefs
[0], 32u);
2113 case nir_intrinsic_vote_all
:
2114 case nir_intrinsic_vote_any
:
2115 case nir_intrinsic_vote_ieq
: {
2116 LValues
&newDefs
= convert(&insn
->dest
);
2117 Value
*pred
= getScratch(1, FILE_PREDICATE
);
2118 mkCmp(OP_SET
, CC_NE
, TYPE_U32
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
2119 mkOp1(OP_VOTE
, TYPE_U32
, pred
, pred
)->subOp
= getSubOp(op
);
2120 mkCvt(OP_CVT
, TYPE_U32
, newDefs
[0], TYPE_U8
, pred
);
2123 case nir_intrinsic_ballot
: {
2124 LValues
&newDefs
= convert(&insn
->dest
);
2125 Value
*pred
= getSSA(1, FILE_PREDICATE
);
2126 mkCmp(OP_SET
, CC_NE
, TYPE_U32
, pred
, TYPE_U32
, getSrc(&insn
->src
[0], 0), zero
);
2127 mkOp1(OP_VOTE
, TYPE_U32
, newDefs
[0], pred
)->subOp
= NV50_IR_SUBOP_VOTE_ANY
;
2130 case nir_intrinsic_read_first_invocation
:
2131 case nir_intrinsic_read_invocation
: {
2132 LValues
&newDefs
= convert(&insn
->dest
);
2133 const DataType dType
= getDType(insn
);
2134 Value
*tmp
= getScratch();
2136 if (op
== nir_intrinsic_read_first_invocation
) {
2137 mkOp1(OP_VOTE
, TYPE_U32
, tmp
, mkImm(1))->subOp
= NV50_IR_SUBOP_VOTE_ANY
;
2138 mkOp2(OP_EXTBF
, TYPE_U32
, tmp
, tmp
, mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2139 mkOp1(OP_BFIND
, TYPE_U32
, tmp
, tmp
)->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
2141 tmp
= getSrc(&insn
->src
[1], 0);
2143 for (uint8_t i
= 0; i
< insn
->num_components
; ++i
) {
2144 mkOp3(OP_SHFL
, dType
, newDefs
[i
], getSrc(&insn
->src
[0], i
), tmp
, mkImm(0x1f))
2145 ->subOp
= NV50_IR_SUBOP_SHFL_IDX
;
2149 case nir_intrinsic_load_per_vertex_input
: {
2150 const DataType dType
= getDType(insn
);
2151 LValues
&newDefs
= convert(&insn
->dest
);
2152 Value
*indirectVertex
;
2153 Value
*indirectOffset
;
2154 uint32_t baseVertex
= getIndirect(&insn
->src
[0], 0, indirectVertex
);
2155 uint32_t idx
= getIndirect(insn
, 1, 0, indirectOffset
);
2157 Value
*vtxBase
= mkOp2v(OP_PFETCH
, TYPE_U32
, getSSA(4, FILE_ADDRESS
),
2158 mkImm(baseVertex
), indirectVertex
);
2159 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2160 uint32_t address
= getSlotAddress(insn
, idx
, i
);
2161 loadFrom(FILE_SHADER_INPUT
, 0, dType
, newDefs
[i
], address
, 0,
2162 indirectOffset
, vtxBase
, info
->in
[idx
].patch
);
2166 case nir_intrinsic_load_per_vertex_output
: {
2167 const DataType dType
= getDType(insn
);
2168 LValues
&newDefs
= convert(&insn
->dest
);
2169 Value
*indirectVertex
;
2170 Value
*indirectOffset
;
2171 uint32_t baseVertex
= getIndirect(&insn
->src
[0], 0, indirectVertex
);
2172 uint32_t idx
= getIndirect(insn
, 1, 0, indirectOffset
);
2173 Value
*vtxBase
= NULL
;
2176 vtxBase
= indirectVertex
;
2178 vtxBase
= loadImm(NULL
, baseVertex
);
2180 vtxBase
= mkOp2v(OP_ADD
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), outBase
, vtxBase
);
2182 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2183 uint32_t address
= getSlotAddress(insn
, idx
, i
);
2184 loadFrom(FILE_SHADER_OUTPUT
, 0, dType
, newDefs
[i
], address
, 0,
2185 indirectOffset
, vtxBase
, info
->in
[idx
].patch
);
2189 case nir_intrinsic_emit_vertex
:
2190 case nir_intrinsic_end_primitive
: {
2191 uint32_t idx
= nir_intrinsic_stream_id(insn
);
2192 mkOp1(getOperation(op
), TYPE_U32
, NULL
, mkImm(idx
))->fixed
= 1;
2195 case nir_intrinsic_load_ubo
: {
2196 const DataType dType
= getDType(insn
);
2197 LValues
&newDefs
= convert(&insn
->dest
);
2198 Value
*indirectIndex
;
2199 Value
*indirectOffset
;
2200 uint32_t index
= getIndirect(&insn
->src
[0], 0, indirectIndex
) + 1;
2201 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2203 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2204 loadFrom(FILE_MEMORY_CONST
, index
, dType
, newDefs
[i
], offset
, i
,
2205 indirectOffset
, indirectIndex
);
2209 case nir_intrinsic_get_buffer_size
: {
2210 LValues
&newDefs
= convert(&insn
->dest
);
2211 const DataType dType
= getDType(insn
);
2212 Value
*indirectBuffer
;
2213 uint32_t buffer
= getIndirect(&insn
->src
[0], 0, indirectBuffer
);
2215 Symbol
*sym
= mkSymbol(FILE_MEMORY_BUFFER
, buffer
, dType
, 0);
2216 mkOp1(OP_BUFQ
, dType
, newDefs
[0], sym
)->setIndirect(0, 0, indirectBuffer
);
2219 case nir_intrinsic_store_ssbo
: {
2220 DataType sType
= getSType(insn
->src
[0], false, false);
2221 Value
*indirectBuffer
;
2222 Value
*indirectOffset
;
2223 uint32_t buffer
= getIndirect(&insn
->src
[1], 0, indirectBuffer
);
2224 uint32_t offset
= getIndirect(&insn
->src
[2], 0, indirectOffset
);
2226 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2227 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
2229 Symbol
*sym
= mkSymbol(FILE_MEMORY_BUFFER
, buffer
, sType
,
2230 offset
+ i
* typeSizeof(sType
));
2231 mkStore(OP_STORE
, sType
, sym
, indirectOffset
, getSrc(&insn
->src
[0], i
))
2232 ->setIndirect(0, 1, indirectBuffer
);
2234 info
->io
.globalAccess
|= 0x2;
2237 case nir_intrinsic_load_ssbo
: {
2238 const DataType dType
= getDType(insn
);
2239 LValues
&newDefs
= convert(&insn
->dest
);
2240 Value
*indirectBuffer
;
2241 Value
*indirectOffset
;
2242 uint32_t buffer
= getIndirect(&insn
->src
[0], 0, indirectBuffer
);
2243 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2245 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
)
2246 loadFrom(FILE_MEMORY_BUFFER
, buffer
, dType
, newDefs
[i
], offset
, i
,
2247 indirectOffset
, indirectBuffer
);
2249 info
->io
.globalAccess
|= 0x1;
2252 case nir_intrinsic_shared_atomic_add
:
2253 case nir_intrinsic_shared_atomic_and
:
2254 case nir_intrinsic_shared_atomic_comp_swap
:
2255 case nir_intrinsic_shared_atomic_exchange
:
2256 case nir_intrinsic_shared_atomic_or
:
2257 case nir_intrinsic_shared_atomic_imax
:
2258 case nir_intrinsic_shared_atomic_imin
:
2259 case nir_intrinsic_shared_atomic_umax
:
2260 case nir_intrinsic_shared_atomic_umin
:
2261 case nir_intrinsic_shared_atomic_xor
: {
2262 const DataType dType
= getDType(insn
);
2263 LValues
&newDefs
= convert(&insn
->dest
);
2264 Value
*indirectOffset
;
2265 uint32_t offset
= getIndirect(&insn
->src
[0], 0, indirectOffset
);
2266 Symbol
*sym
= mkSymbol(FILE_MEMORY_SHARED
, 0, dType
, offset
);
2267 Instruction
*atom
= mkOp2(OP_ATOM
, dType
, newDefs
[0], sym
, getSrc(&insn
->src
[1], 0));
2268 if (op
== nir_intrinsic_shared_atomic_comp_swap
)
2269 atom
->setSrc(2, getSrc(&insn
->src
[2], 0));
2270 atom
->setIndirect(0, 0, indirectOffset
);
2271 atom
->subOp
= getSubOp(op
);
2274 case nir_intrinsic_ssbo_atomic_add
:
2275 case nir_intrinsic_ssbo_atomic_and
:
2276 case nir_intrinsic_ssbo_atomic_comp_swap
:
2277 case nir_intrinsic_ssbo_atomic_exchange
:
2278 case nir_intrinsic_ssbo_atomic_or
:
2279 case nir_intrinsic_ssbo_atomic_imax
:
2280 case nir_intrinsic_ssbo_atomic_imin
:
2281 case nir_intrinsic_ssbo_atomic_umax
:
2282 case nir_intrinsic_ssbo_atomic_umin
:
2283 case nir_intrinsic_ssbo_atomic_xor
: {
2284 const DataType dType
= getDType(insn
);
2285 LValues
&newDefs
= convert(&insn
->dest
);
2286 Value
*indirectBuffer
;
2287 Value
*indirectOffset
;
2288 uint32_t buffer
= getIndirect(&insn
->src
[0], 0, indirectBuffer
);
2289 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2291 Symbol
*sym
= mkSymbol(FILE_MEMORY_BUFFER
, buffer
, dType
, offset
);
2292 Instruction
*atom
= mkOp2(OP_ATOM
, dType
, newDefs
[0], sym
,
2293 getSrc(&insn
->src
[2], 0));
2294 if (op
== nir_intrinsic_ssbo_atomic_comp_swap
)
2295 atom
->setSrc(2, getSrc(&insn
->src
[3], 0));
2296 atom
->setIndirect(0, 0, indirectOffset
);
2297 atom
->setIndirect(0, 1, indirectBuffer
);
2298 atom
->subOp
= getSubOp(op
);
2300 info
->io
.globalAccess
|= 0x2;
2303 case nir_intrinsic_image_deref_atomic_add
:
2304 case nir_intrinsic_image_deref_atomic_and
:
2305 case nir_intrinsic_image_deref_atomic_comp_swap
:
2306 case nir_intrinsic_image_deref_atomic_exchange
:
2307 case nir_intrinsic_image_deref_atomic_max
:
2308 case nir_intrinsic_image_deref_atomic_min
:
2309 case nir_intrinsic_image_deref_atomic_or
:
2310 case nir_intrinsic_image_deref_atomic_xor
:
2311 case nir_intrinsic_image_deref_load
:
2312 case nir_intrinsic_image_deref_samples
:
2313 case nir_intrinsic_image_deref_size
:
2314 case nir_intrinsic_image_deref_store
: {
2315 const nir_variable
*tex
;
2316 std::vector
<Value
*> srcs
, defs
;
2321 nir_deref_instr
*deref
= nir_src_as_deref(insn
->src
[0]);
2322 const glsl_type
*type
= deref
->type
;
2323 TexInstruction::Target target
=
2324 convert((glsl_sampler_dim
)type
->sampler_dimensionality
,
2325 type
->sampler_array
, type
->sampler_shadow
);
2326 unsigned int argCount
= getNIRArgCount(target
);
2327 uint16_t location
= handleDeref(deref
, indirect
, tex
);
2329 if (opInfo
.has_dest
) {
2330 LValues
&newDefs
= convert(&insn
->dest
);
2331 for (uint8_t i
= 0u; i
< newDefs
.size(); ++i
) {
2332 defs
.push_back(newDefs
[i
]);
2338 case nir_intrinsic_image_deref_atomic_add
:
2339 case nir_intrinsic_image_deref_atomic_and
:
2340 case nir_intrinsic_image_deref_atomic_comp_swap
:
2341 case nir_intrinsic_image_deref_atomic_exchange
:
2342 case nir_intrinsic_image_deref_atomic_max
:
2343 case nir_intrinsic_image_deref_atomic_min
:
2344 case nir_intrinsic_image_deref_atomic_or
:
2345 case nir_intrinsic_image_deref_atomic_xor
:
2346 ty
= getDType(insn
);
2348 info
->io
.globalAccess
|= 0x2;
2350 case nir_intrinsic_image_deref_load
:
2352 info
->io
.globalAccess
|= 0x1;
2354 case nir_intrinsic_image_deref_store
:
2357 info
->io
.globalAccess
|= 0x2;
2359 case nir_intrinsic_image_deref_samples
:
2363 case nir_intrinsic_image_deref_size
:
2367 unreachable("unhandled image opcode");
2372 if (opInfo
.num_srcs
>= 2)
2373 for (unsigned int i
= 0u; i
< argCount
; ++i
)
2374 srcs
.push_back(getSrc(&insn
->src
[1], i
));
2376 // the sampler is just another src added after coords
2377 if (opInfo
.num_srcs
>= 3 && target
.isMS())
2378 srcs
.push_back(getSrc(&insn
->src
[2], 0));
2380 if (opInfo
.num_srcs
>= 4) {
2381 unsigned components
= opInfo
.src_components
[3] ? opInfo
.src_components
[3] : insn
->num_components
;
2382 for (uint8_t i
= 0u; i
< components
; ++i
)
2383 srcs
.push_back(getSrc(&insn
->src
[3], i
));
2386 if (opInfo
.num_srcs
>= 5)
2387 // 1 for aotmic swap
2388 for (uint8_t i
= 0u; i
< opInfo
.src_components
[4]; ++i
)
2389 srcs
.push_back(getSrc(&insn
->src
[4], i
));
2391 TexInstruction
*texi
= mkTex(getOperation(op
), target
.getEnum(), location
, 0, defs
, srcs
);
2392 texi
->tex
.bindless
= false;
2393 texi
->tex
.format
= &nv50_ir::TexInstruction::formatTable
[convertGLImgFormat(tex
->data
.image
.format
)];
2394 texi
->tex
.mask
= mask
;
2395 texi
->cache
= getCacheModeFromVar(tex
);
2397 texi
->subOp
= getSubOp(op
);
2400 texi
->setIndirectR(indirect
);
2404 case nir_intrinsic_store_shared
: {
2405 DataType sType
= getSType(insn
->src
[0], false, false);
2406 Value
*indirectOffset
;
2407 uint32_t offset
= getIndirect(&insn
->src
[1], 0, indirectOffset
);
2409 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
) {
2410 if (!((1u << i
) & nir_intrinsic_write_mask(insn
)))
2412 Symbol
*sym
= mkSymbol(FILE_MEMORY_SHARED
, 0, sType
, offset
+ i
* typeSizeof(sType
));
2413 mkStore(OP_STORE
, sType
, sym
, indirectOffset
, getSrc(&insn
->src
[0], i
));
2417 case nir_intrinsic_load_shared
: {
2418 const DataType dType
= getDType(insn
);
2419 LValues
&newDefs
= convert(&insn
->dest
);
2420 Value
*indirectOffset
;
2421 uint32_t offset
= getIndirect(&insn
->src
[0], 0, indirectOffset
);
2423 for (uint8_t i
= 0u; i
< insn
->num_components
; ++i
)
2424 loadFrom(FILE_MEMORY_SHARED
, 0, dType
, newDefs
[i
], offset
, i
, indirectOffset
);
2428 case nir_intrinsic_barrier
: {
2429 // TODO: add flag to shader_info
2430 info
->numBarriers
= 1;
2431 Instruction
*bar
= mkOp2(OP_BAR
, TYPE_U32
, NULL
, mkImm(0), mkImm(0));
2433 bar
->subOp
= NV50_IR_SUBOP_BAR_SYNC
;
2436 case nir_intrinsic_group_memory_barrier
:
2437 case nir_intrinsic_memory_barrier
:
2438 case nir_intrinsic_memory_barrier_atomic_counter
:
2439 case nir_intrinsic_memory_barrier_buffer
:
2440 case nir_intrinsic_memory_barrier_image
:
2441 case nir_intrinsic_memory_barrier_shared
: {
2442 Instruction
*bar
= mkOp(OP_MEMBAR
, TYPE_NONE
, NULL
);
2444 bar
->subOp
= getSubOp(op
);
2448 ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos
[op
].name
);
2456 Converter::visit(nir_jump_instr
*insn
)
2458 switch (insn
->type
) {
2459 case nir_jump_return
:
2460 // TODO: this only works in the main function
2461 mkFlow(OP_BRA
, exit
, CC_ALWAYS
, NULL
);
2462 bb
->cfg
.attach(&exit
->cfg
, Graph::Edge::CROSS
);
2464 case nir_jump_break
:
2465 case nir_jump_continue
: {
2466 bool isBreak
= insn
->type
== nir_jump_break
;
2467 nir_block
*block
= insn
->instr
.block
;
2468 assert(!block
->successors
[1]);
2469 BasicBlock
*target
= convert(block
->successors
[0]);
2470 mkFlow(isBreak
? OP_BREAK
: OP_CONT
, target
, CC_ALWAYS
, NULL
);
2471 bb
->cfg
.attach(&target
->cfg
, isBreak
? Graph::Edge::CROSS
: Graph::Edge::BACK
);
2475 ERROR("unknown nir_jump_type %u\n", insn
->type
);
2483 Converter::visit(nir_load_const_instr
*insn
)
2485 assert(insn
->def
.bit_size
<= 64);
2487 LValues
&newDefs
= convert(&insn
->def
);
2488 for (int i
= 0; i
< insn
->def
.num_components
; i
++) {
2489 switch (insn
->def
.bit_size
) {
2491 loadImm(newDefs
[i
], insn
->value
.u64
[i
]);
2494 loadImm(newDefs
[i
], insn
->value
.u32
[i
]);
2497 loadImm(newDefs
[i
], insn
->value
.u16
[i
]);
2500 loadImm(newDefs
[i
], insn
->value
.u8
[i
]);
2507 #define DEFAULT_CHECKS \
2508 if (insn->dest.dest.ssa.num_components > 1) { \
2509 ERROR("nir_alu_instr only supported with 1 component!\n"); \
2512 if (insn->dest.write_mask != 1) { \
2513 ERROR("nir_alu_instr only with write_mask of 1 supported!\n"); \
2517 Converter::visit(nir_alu_instr
*insn
)
2519 const nir_op op
= insn
->op
;
2520 const nir_op_info
&info
= nir_op_infos
[op
];
2521 DataType dType
= getDType(insn
);
2522 const std::vector
<DataType
> sTypes
= getSTypes(insn
);
2524 Instruction
*oldPos
= this->bb
->getExit();
2536 case nir_op_fddx_coarse
:
2537 case nir_op_fddx_fine
:
2539 case nir_op_fddy_coarse
:
2540 case nir_op_fddy_fine
:
2559 case nir_op_imul_high
:
2560 case nir_op_umul_high
:
2567 case nir_op_pack_64_2x32_split
:
2585 LValues
&newDefs
= convert(&insn
->dest
);
2586 operation preOp
= preOperationNeeded(op
);
2587 if (preOp
!= OP_NOP
) {
2588 assert(info
.num_inputs
< 2);
2589 Value
*tmp
= getSSA(typeSizeof(dType
));
2590 Instruction
*i0
= mkOp(preOp
, dType
, tmp
);
2591 Instruction
*i1
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2592 if (info
.num_inputs
) {
2593 i0
->setSrc(0, getSrc(&insn
->src
[0]));
2596 i1
->subOp
= getSubOp(op
);
2598 Instruction
*i
= mkOp(getOperation(op
), dType
, newDefs
[0]);
2599 for (unsigned s
= 0u; s
< info
.num_inputs
; ++s
) {
2600 i
->setSrc(s
, getSrc(&insn
->src
[s
]));
2602 i
->subOp
= getSubOp(op
);
2606 case nir_op_ifind_msb
:
2607 case nir_op_ufind_msb
: {
2609 LValues
&newDefs
= convert(&insn
->dest
);
2611 mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2614 case nir_op_fround_even
: {
2616 LValues
&newDefs
= convert(&insn
->dest
);
2617 mkCvt(OP_CVT
, dType
, newDefs
[0], dType
, getSrc(&insn
->src
[0]))->rnd
= ROUND_NI
;
2620 // convert instructions
2634 case nir_op_u2u64
: {
2636 LValues
&newDefs
= convert(&insn
->dest
);
2637 Instruction
*i
= mkOp1(getOperation(op
), dType
, newDefs
[0], getSrc(&insn
->src
[0]));
2638 if (op
== nir_op_f2i32
|| op
== nir_op_f2i64
|| op
== nir_op_f2u32
|| op
== nir_op_f2u64
)
2640 i
->sType
= sTypes
[0];
2643 // compare instructions
2653 case nir_op_ine32
: {
2655 LValues
&newDefs
= convert(&insn
->dest
);
2656 Instruction
*i
= mkCmp(getOperation(op
),
2661 getSrc(&insn
->src
[0]),
2662 getSrc(&insn
->src
[1]));
2663 if (info
.num_inputs
== 3)
2664 i
->setSrc(2, getSrc(&insn
->src
[2]));
2665 i
->sType
= sTypes
[0];
2668 // those are weird ALU ops and need special handling, because
2669 // 1. they are always componend based
2670 // 2. they basically just merge multiple values into one data type
2673 if (!insn
->dest
.dest
.is_ssa
&& insn
->dest
.dest
.reg
.reg
->num_array_elems
) {
2674 nir_reg_dest
& reg
= insn
->dest
.dest
.reg
;
2675 uint32_t goffset
= regToLmemOffset
[reg
.reg
->index
];
2676 uint8_t comps
= reg
.reg
->num_components
;
2677 uint8_t size
= reg
.reg
->bit_size
/ 8;
2678 uint8_t csize
= 4 * size
; // TODO after fixing MemoryOpts: comps * size;
2679 uint32_t aoffset
= csize
* reg
.base_offset
;
2680 Value
*indirect
= NULL
;
2683 indirect
= mkOp2v(OP_MUL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
),
2684 getSrc(reg
.indirect
, 0), mkImm(csize
));
2686 for (uint8_t i
= 0u; i
< comps
; ++i
) {
2687 if (!((1u << i
) & insn
->dest
.write_mask
))
2690 Symbol
*sym
= mkSymbol(FILE_MEMORY_LOCAL
, 0, dType
, goffset
+ aoffset
+ i
* size
);
2691 mkStore(OP_STORE
, dType
, sym
, indirect
, getSrc(&insn
->src
[0], i
));
2694 } else if (!insn
->src
[0].src
.is_ssa
&& insn
->src
[0].src
.reg
.reg
->num_array_elems
) {
2695 LValues
&newDefs
= convert(&insn
->dest
);
2696 nir_reg_src
& reg
= insn
->src
[0].src
.reg
;
2697 uint32_t goffset
= regToLmemOffset
[reg
.reg
->index
];
2698 // uint8_t comps = reg.reg->num_components;
2699 uint8_t size
= reg
.reg
->bit_size
/ 8;
2700 uint8_t csize
= 4 * size
; // TODO after fixing MemoryOpts: comps * size;
2701 uint32_t aoffset
= csize
* reg
.base_offset
;
2702 Value
*indirect
= NULL
;
2705 indirect
= mkOp2v(OP_MUL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), getSrc(reg
.indirect
, 0), mkImm(csize
));
2707 for (uint8_t i
= 0u; i
< newDefs
.size(); ++i
)
2708 loadFrom(FILE_MEMORY_LOCAL
, 0, dType
, newDefs
[i
], goffset
+ aoffset
, i
, indirect
);
2712 LValues
&newDefs
= convert(&insn
->dest
);
2713 for (LValues::size_type c
= 0u; c
< newDefs
.size(); ++c
) {
2714 mkMov(newDefs
[c
], getSrc(&insn
->src
[0], c
), dType
);
2721 LValues
&newDefs
= convert(&insn
->dest
);
2722 for (LValues::size_type c
= 0u; c
< newDefs
.size(); ++c
) {
2723 mkMov(newDefs
[c
], getSrc(&insn
->src
[c
]), dType
);
2728 case nir_op_pack_64_2x32
: {
2729 LValues
&newDefs
= convert(&insn
->dest
);
2730 Instruction
*merge
= mkOp(OP_MERGE
, dType
, newDefs
[0]);
2731 merge
->setSrc(0, getSrc(&insn
->src
[0], 0));
2732 merge
->setSrc(1, getSrc(&insn
->src
[0], 1));
2735 case nir_op_pack_half_2x16_split
: {
2736 LValues
&newDefs
= convert(&insn
->dest
);
2737 Value
*tmpH
= getSSA();
2738 Value
*tmpL
= getSSA();
2740 mkCvt(OP_CVT
, TYPE_F16
, tmpL
, TYPE_F32
, getSrc(&insn
->src
[0]));
2741 mkCvt(OP_CVT
, TYPE_F16
, tmpH
, TYPE_F32
, getSrc(&insn
->src
[1]));
2742 mkOp3(OP_INSBF
, TYPE_U32
, newDefs
[0], tmpH
, mkImm(0x1010), tmpL
);
2745 case nir_op_unpack_half_2x16_split_x
:
2746 case nir_op_unpack_half_2x16_split_y
: {
2747 LValues
&newDefs
= convert(&insn
->dest
);
2748 Instruction
*cvt
= mkCvt(OP_CVT
, TYPE_F32
, newDefs
[0], TYPE_F16
, getSrc(&insn
->src
[0]));
2749 if (op
== nir_op_unpack_half_2x16_split_y
)
2753 case nir_op_unpack_64_2x32
: {
2754 LValues
&newDefs
= convert(&insn
->dest
);
2755 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, newDefs
[1]);
2758 case nir_op_unpack_64_2x32_split_x
: {
2759 LValues
&newDefs
= convert(&insn
->dest
);
2760 mkOp1(OP_SPLIT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]))->setDef(1, getSSA());
2763 case nir_op_unpack_64_2x32_split_y
: {
2764 LValues
&newDefs
= convert(&insn
->dest
);
2765 mkOp1(OP_SPLIT
, dType
, getSSA(), getSrc(&insn
->src
[0]))->setDef(1, newDefs
[0]);
2768 // special instructions
2770 case nir_op_isign
: {
2773 if (::isFloatType(dType
))
2778 LValues
&newDefs
= convert(&insn
->dest
);
2779 LValue
*val0
= getScratch();
2780 LValue
*val1
= getScratch();
2781 mkCmp(OP_SET
, CC_GT
, iType
, val0
, dType
, getSrc(&insn
->src
[0]), zero
);
2782 mkCmp(OP_SET
, CC_LT
, iType
, val1
, dType
, getSrc(&insn
->src
[0]), zero
);
2784 if (dType
== TYPE_F64
) {
2785 mkOp2(OP_SUB
, iType
, val0
, val0
, val1
);
2786 mkCvt(OP_CVT
, TYPE_F64
, newDefs
[0], iType
, val0
);
2787 } else if (dType
== TYPE_S64
|| dType
== TYPE_U64
) {
2788 mkOp2(OP_SUB
, iType
, val0
, val1
, val0
);
2789 mkOp2(OP_SHR
, iType
, val1
, val0
, loadImm(NULL
, 31));
2790 mkOp2(OP_MERGE
, dType
, newDefs
[0], val0
, val1
);
2791 } else if (::isFloatType(dType
))
2792 mkOp2(OP_SUB
, iType
, newDefs
[0], val0
, val1
);
2794 mkOp2(OP_SUB
, iType
, newDefs
[0], val1
, val0
);
2798 case nir_op_b32csel
: {
2800 LValues
&newDefs
= convert(&insn
->dest
);
2801 mkCmp(OP_SLCT
, CC_NE
, dType
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[1]), getSrc(&insn
->src
[2]), getSrc(&insn
->src
[0]));
2804 case nir_op_ibitfield_extract
:
2805 case nir_op_ubitfield_extract
: {
2807 Value
*tmp
= getSSA();
2808 LValues
&newDefs
= convert(&insn
->dest
);
2809 mkOp3(OP_INSBF
, dType
, tmp
, getSrc(&insn
->src
[2]), loadImm(NULL
, 0x808), getSrc(&insn
->src
[1]));
2810 mkOp2(OP_EXTBF
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), tmp
);
2815 LValues
&newDefs
= convert(&insn
->dest
);
2816 mkOp3(OP_INSBF
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 0x808), getSrc(&insn
->src
[1]));
2819 case nir_op_bitfield_insert
: {
2821 LValues
&newDefs
= convert(&insn
->dest
);
2822 LValue
*temp
= getSSA();
2823 mkOp3(OP_INSBF
, TYPE_U32
, temp
, getSrc(&insn
->src
[3]), mkImm(0x808), getSrc(&insn
->src
[2]));
2824 mkOp3(OP_INSBF
, dType
, newDefs
[0], getSrc(&insn
->src
[1]), temp
, getSrc(&insn
->src
[0]));
2827 case nir_op_bit_count
: {
2829 LValues
&newDefs
= convert(&insn
->dest
);
2830 mkOp2(OP_POPCNT
, dType
, newDefs
[0], getSrc(&insn
->src
[0]), getSrc(&insn
->src
[0]));
2833 case nir_op_bitfield_reverse
: {
2835 LValues
&newDefs
= convert(&insn
->dest
);
2836 mkOp2(OP_EXTBF
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2839 case nir_op_find_lsb
: {
2841 LValues
&newDefs
= convert(&insn
->dest
);
2842 Value
*tmp
= getSSA();
2843 mkOp2(OP_EXTBF
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]), mkImm(0x2000))->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
2844 mkOp1(OP_BFIND
, TYPE_U32
, newDefs
[0], tmp
)->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
2847 // boolean conversions
2848 case nir_op_b2f32
: {
2850 LValues
&newDefs
= convert(&insn
->dest
);
2851 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1.0f
));
2854 case nir_op_b2f64
: {
2856 LValues
&newDefs
= convert(&insn
->dest
);
2857 Value
*tmp
= getSSA(4);
2858 mkOp2(OP_AND
, TYPE_U32
, tmp
, getSrc(&insn
->src
[0]), loadImm(NULL
, 0x3ff00000));
2859 mkOp2(OP_MERGE
, TYPE_U64
, newDefs
[0], loadImm(NULL
, 0), tmp
);
2863 case nir_op_i2b32
: {
2865 LValues
&newDefs
= convert(&insn
->dest
);
2867 if (typeSizeof(sTypes
[0]) == 8) {
2868 src1
= loadImm(getSSA(8), 0.0);
2872 CondCode cc
= op
== nir_op_f2b32
? CC_NEU
: CC_NE
;
2873 mkCmp(OP_SET
, cc
, TYPE_U32
, newDefs
[0], sTypes
[0], getSrc(&insn
->src
[0]), src1
);
2876 case nir_op_b2i32
: {
2878 LValues
&newDefs
= convert(&insn
->dest
);
2879 mkOp2(OP_AND
, TYPE_U32
, newDefs
[0], getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2882 case nir_op_b2i64
: {
2884 LValues
&newDefs
= convert(&insn
->dest
);
2885 LValue
*def
= getScratch();
2886 mkOp2(OP_AND
, TYPE_U32
, def
, getSrc(&insn
->src
[0]), loadImm(NULL
, 1));
2887 mkOp2(OP_MERGE
, TYPE_S64
, newDefs
[0], def
, loadImm(NULL
, 0));
2891 ERROR("unknown nir_op %s\n", info
.name
);
2896 oldPos
= this->bb
->getEntry();
2897 oldPos
->precise
= insn
->exact
;
2900 if (unlikely(!oldPos
))
2903 while (oldPos
->next
) {
2904 oldPos
= oldPos
->next
;
2905 oldPos
->precise
= insn
->exact
;
2907 oldPos
->saturate
= insn
->dest
.saturate
;
2911 #undef DEFAULT_CHECKS
2914 Converter::visit(nir_ssa_undef_instr
*insn
)
2916 LValues
&newDefs
= convert(&insn
->def
);
2917 for (uint8_t i
= 0u; i
< insn
->def
.num_components
; ++i
) {
2918 mkOp(OP_NOP
, TYPE_NONE
, newDefs
[i
]);
2923 #define CASE_SAMPLER(ty) \
2924 case GLSL_SAMPLER_DIM_ ## ty : \
2925 if (isArray && !isShadow) \
2926 return TEX_TARGET_ ## ty ## _ARRAY; \
2927 else if (!isArray && isShadow) \
2928 return TEX_TARGET_## ty ## _SHADOW; \
2929 else if (isArray && isShadow) \
2930 return TEX_TARGET_## ty ## _ARRAY_SHADOW; \
2932 return TEX_TARGET_ ## ty
2935 Converter::convert(glsl_sampler_dim dim
, bool isArray
, bool isShadow
)
2941 case GLSL_SAMPLER_DIM_3D
:
2942 return TEX_TARGET_3D
;
2943 case GLSL_SAMPLER_DIM_MS
:
2945 return TEX_TARGET_2D_MS_ARRAY
;
2946 return TEX_TARGET_2D_MS
;
2947 case GLSL_SAMPLER_DIM_RECT
:
2949 return TEX_TARGET_RECT_SHADOW
;
2950 return TEX_TARGET_RECT
;
2951 case GLSL_SAMPLER_DIM_BUF
:
2952 return TEX_TARGET_BUFFER
;
2953 case GLSL_SAMPLER_DIM_EXTERNAL
:
2954 return TEX_TARGET_2D
;
2956 ERROR("unknown glsl_sampler_dim %u\n", dim
);
2958 return TEX_TARGET_COUNT
;
2964 Converter::applyProjection(Value
*src
, Value
*proj
)
2968 return mkOp2v(OP_MUL
, TYPE_F32
, getScratch(), src
, proj
);
2972 Converter::getNIRArgCount(TexInstruction::Target
& target
)
2974 unsigned int result
= target
.getArgCount();
2975 if (target
.isCube() && target
.isArray())
2983 Converter::handleDeref(nir_deref_instr
*deref
, Value
* &indirect
, const nir_variable
* &tex
)
2985 typedef std::pair
<uint32_t,Value
*> DerefPair
;
2986 std::list
<DerefPair
> derefs
;
2988 uint16_t result
= 0;
2989 while (deref
->deref_type
!= nir_deref_type_var
) {
2990 switch (deref
->deref_type
) {
2991 case nir_deref_type_array
: {
2993 uint8_t size
= type_size(deref
->type
);
2994 result
+= size
* getIndirect(&deref
->arr
.index
, 0, indirect
);
2997 derefs
.push_front(std::make_pair(size
, indirect
));
3002 case nir_deref_type_struct
: {
3003 result
+= nir_deref_instr_parent(deref
)->type
->struct_location_offset(deref
->strct
.index
);
3006 case nir_deref_type_var
:
3008 unreachable("nir_deref_type_var reached in handleDeref!");
3011 deref
= nir_deref_instr_parent(deref
);
3015 for (std::list
<DerefPair
>::const_iterator it
= derefs
.begin(); it
!= derefs
.end(); ++it
) {
3016 Value
*offset
= mkOp2v(OP_MUL
, TYPE_U32
, getSSA(), loadImm(getSSA(), it
->first
), it
->second
);
3018 indirect
= mkOp2v(OP_ADD
, TYPE_U32
, getSSA(), indirect
, offset
);
3023 tex
= nir_deref_instr_get_variable(deref
);
3026 return result
+ tex
->data
.driver_location
;
3030 Converter::getCacheModeFromVar(const nir_variable
*var
)
3032 if (var
->data
.image
.access
== ACCESS_VOLATILE
)
3034 if (var
->data
.image
.access
== ACCESS_COHERENT
)
3040 Converter::visit(nir_tex_instr
*insn
)
3044 case nir_texop_query_levels
:
3046 case nir_texop_texture_samples
:
3051 case nir_texop_txf_ms
:
3053 case nir_texop_txs
: {
3054 LValues
&newDefs
= convert(&insn
->dest
);
3055 std::vector
<Value
*> srcs
;
3056 std::vector
<Value
*> defs
;
3057 std::vector
<nir_src
*> offsets
;
3061 TexInstruction::Target target
= convert(insn
->sampler_dim
, insn
->is_array
, insn
->is_shadow
);
3062 operation op
= getOperation(insn
->op
);
3065 int biasIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_bias
);
3066 int compIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_comparator
);
3067 int coordsIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_coord
);
3068 int ddxIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddx
);
3069 int ddyIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ddy
);
3070 int msIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_ms_index
);
3071 int lodIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_lod
);
3072 int offsetIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_offset
);
3073 int projIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_projector
);
3074 int sampOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_sampler_offset
);
3075 int texOffIdx
= nir_tex_instr_src_index(insn
, nir_tex_src_texture_offset
);
3078 proj
= mkOp1v(OP_RCP
, TYPE_F32
, getScratch(), getSrc(&insn
->src
[projIdx
].src
, 0));
3080 srcs
.resize(insn
->coord_components
);
3081 for (uint8_t i
= 0u; i
< insn
->coord_components
; ++i
)
3082 srcs
[i
] = applyProjection(getSrc(&insn
->src
[coordsIdx
].src
, i
), proj
);
3084 // sometimes we get less args than target.getArgCount, but codegen expects the latter
3085 if (insn
->coord_components
) {
3086 uint32_t argCount
= target
.getArgCount();
3091 for (uint32_t i
= 0u; i
< (argCount
- insn
->coord_components
); ++i
)
3092 srcs
.push_back(getSSA());
3095 if (insn
->op
== nir_texop_texture_samples
)
3096 srcs
.push_back(zero
);
3097 else if (!insn
->num_srcs
)
3098 srcs
.push_back(loadImm(NULL
, 0));
3100 srcs
.push_back(getSrc(&insn
->src
[biasIdx
].src
, 0));
3102 srcs
.push_back(getSrc(&insn
->src
[lodIdx
].src
, 0));
3103 else if (op
== OP_TXF
)
3106 srcs
.push_back(getSrc(&insn
->src
[msIdx
].src
, 0));
3107 if (offsetIdx
!= -1)
3108 offsets
.push_back(&insn
->src
[offsetIdx
].src
);
3110 srcs
.push_back(applyProjection(getSrc(&insn
->src
[compIdx
].src
, 0), proj
));
3111 if (texOffIdx
!= -1) {
3112 srcs
.push_back(getSrc(&insn
->src
[texOffIdx
].src
, 0));
3113 texOffIdx
= srcs
.size() - 1;
3115 if (sampOffIdx
!= -1) {
3116 srcs
.push_back(getSrc(&insn
->src
[sampOffIdx
].src
, 0));
3117 sampOffIdx
= srcs
.size() - 1;
3120 r
= insn
->texture_index
;
3121 s
= insn
->sampler_index
;
3123 defs
.resize(newDefs
.size());
3124 for (uint8_t d
= 0u; d
< newDefs
.size(); ++d
) {
3125 defs
[d
] = newDefs
[d
];
3128 if (target
.isMS() || (op
== OP_TEX
&& prog
->getType() != Program::TYPE_FRAGMENT
))
3131 TexInstruction
*texi
= mkTex(op
, target
.getEnum(), r
, s
, defs
, srcs
);
3132 texi
->tex
.levelZero
= lz
;
3133 texi
->tex
.mask
= mask
;
3135 if (texOffIdx
!= -1)
3136 texi
->tex
.rIndirectSrc
= texOffIdx
;
3137 if (sampOffIdx
!= -1)
3138 texi
->tex
.sIndirectSrc
= sampOffIdx
;
3142 if (!target
.isShadow())
3143 texi
->tex
.gatherComp
= insn
->component
;
3146 texi
->tex
.query
= TXQ_DIMS
;
3148 case nir_texop_texture_samples
:
3149 texi
->tex
.mask
= 0x4;
3150 texi
->tex
.query
= TXQ_TYPE
;
3152 case nir_texop_query_levels
:
3153 texi
->tex
.mask
= 0x8;
3154 texi
->tex
.query
= TXQ_DIMS
;
3160 texi
->tex
.useOffsets
= offsets
.size();
3161 if (texi
->tex
.useOffsets
) {
3162 for (uint8_t s
= 0; s
< texi
->tex
.useOffsets
; ++s
) {
3163 for (uint32_t c
= 0u; c
< 3; ++c
) {
3164 uint8_t s2
= std::min(c
, target
.getDim() - 1);
3165 texi
->offset
[s
][c
].set(getSrc(offsets
[s
], s2
));
3166 texi
->offset
[s
][c
].setInsn(texi
);
3171 if (ddxIdx
!= -1 && ddyIdx
!= -1) {
3172 for (uint8_t c
= 0u; c
< target
.getDim() + target
.isCube(); ++c
) {
3173 texi
->dPdx
[c
].set(getSrc(&insn
->src
[ddxIdx
].src
, c
));
3174 texi
->dPdy
[c
].set(getSrc(&insn
->src
[ddyIdx
].src
, c
));
3181 ERROR("unknown nir_texop %u\n", insn
->op
);
3188 Converter::visit(nir_deref_instr
*deref
)
3190 // we just ignore those, because images intrinsics are the only place where
3191 // we should end up with deref sources and those have to backtrack anyway
3192 // to get the nir_variable. This code just exists to handle some special
3194 switch (deref
->deref_type
) {
3195 case nir_deref_type_array
:
3196 case nir_deref_type_struct
:
3197 case nir_deref_type_var
:
3200 ERROR("unknown nir_deref_instr %u\n", deref
->deref_type
);
3211 if (prog
->dbgFlags
& NV50_IR_DEBUG_VERBOSE
)
3212 nir_print_shader(nir
, stderr
);
3214 struct nir_lower_subgroups_options subgroup_options
= {
3215 .subgroup_size
= 32,
3216 .ballot_bit_size
= 32,
3219 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, type_size
, (nir_lower_io_options
)0);
3220 NIR_PASS_V(nir
, nir_lower_subgroups
, &subgroup_options
);
3221 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
);
3222 NIR_PASS_V(nir
, nir_lower_load_const_to_scalar
);
3223 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3224 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
);
3225 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
3229 NIR_PASS(progress
, nir
, nir_copy_prop
);
3230 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
3231 NIR_PASS(progress
, nir
, nir_opt_trivial_continues
);
3232 NIR_PASS(progress
, nir
, nir_opt_cse
);
3233 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
3234 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
3235 NIR_PASS(progress
, nir
, nir_copy_prop
);
3236 NIR_PASS(progress
, nir
, nir_opt_dce
);
3237 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
3240 NIR_PASS_V(nir
, nir_lower_bool_to_int32
);
3241 NIR_PASS_V(nir
, nir_lower_locals_to_regs
);
3242 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
);
3243 NIR_PASS_V(nir
, nir_convert_from_ssa
, true);
3245 // Garbage collect dead instructions
3249 ERROR("Couldn't prase NIR!\n");
3253 if (!assignSlots()) {
3254 ERROR("Couldn't assign slots!\n");
3258 if (prog
->dbgFlags
& NV50_IR_DEBUG_BASIC
)
3259 nir_print_shader(nir
, stderr
);
3261 nir_foreach_function(function
, nir
) {
3262 if (!visit(function
))
3269 } // unnamed namespace
3274 Program::makeFromNIR(struct nv50_ir_prog_info
*info
)
3276 nir_shader
*nir
= (nir_shader
*)info
->bin
.source
;
3277 Converter
converter(this, nir
, info
);
3278 bool result
= converter
.run();
3281 LoweringHelper lowering
;
3283 tlsSize
= info
->bin
.tlsSpace
;
3287 } // namespace nv50_ir