src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

   1 /*
   2  * Copyright 2017 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Karol Herbst <kherbst@redhat.com>
  23  */
  24
  25 #include "compiler/nir/nir.h"
  26
  27 #include "util/u_debug.h"
  28
  29 #include "codegen/nv50_ir.h"
  30 #include "codegen/nv50_ir_from_common.h"
  31 #include "codegen/nv50_ir_lowering_helper.h"
  32 #include "codegen/nv50_ir_util.h"
  33 #include "tgsi/tgsi_from_mesa.h"
  34
  35 #if __cplusplus >= 201103L
  36 #include <unordered_map>
  37 #else
  38 #include <tr1/unordered_map>
  39 #endif
  40 #include <cstring>
  41 #include <list>
  42 #include <vector>
  43
  44 namespace {
  45
  46 #if __cplusplus >= 201103L
  47 using std::hash;
  48 using std::unordered_map;
  49 #else
  50 using std::tr1::hash;
  51 using std::tr1::unordered_map;
  52 #endif
  53
  54 using namespace nv50_ir;
  55
  56 int
  57 type_size(const struct glsl_type *type, bool bindless)
  58 {
  59    return glsl_count_attribute_slots(type, false);
  60 }
  61
  62 class Converter : public ConverterCommon
  63 {
  64 public:
  65    Converter(Program *, nir_shader *, nv50_ir_prog_info *);
  66
  67    bool run();
  68 private:
  69    typedef std::vector<LValue*> LValues;
  70    typedef unordered_map<unsigned, LValues> NirDefMap;
  71    typedef unordered_map<unsigned, nir_load_const_instr*> ImmediateMap;
  72    typedef unordered_map<unsigned, uint32_t> NirArrayLMemOffsets;
  73    typedef unordered_map<unsigned, BasicBlock*> NirBlockMap;
  74
  75    CacheMode convert(enum gl_access_qualifier);
  76    TexTarget convert(glsl_sampler_dim, bool isArray, bool isShadow);
  77    LValues& convert(nir_alu_dest *);
  78    BasicBlock* convert(nir_block *);
  79    LValues& convert(nir_dest *);
  80    SVSemantic convert(nir_intrinsic_op);
  81    Value* convert(nir_load_const_instr*, uint8_t);
  82    LValues& convert(nir_register *);
  83    LValues& convert(nir_ssa_def *);
  84
  85    Value* getSrc(nir_alu_src *, uint8_t component = 0);
  86    Value* getSrc(nir_register *, uint8_t);
  87    Value* getSrc(nir_src *, uint8_t, bool indirect = false);
  88    Value* getSrc(nir_ssa_def *, uint8_t);
  89
  90    // returned value is the constant part of the given source (either the
  91    // nir_src or the selected source component of an intrinsic). Even though
  92    // this is mostly an optimization to be able to skip indirects in a few
  93    // cases, sometimes we require immediate values or set some fileds on
  94    // instructions (e.g. tex) in order for codegen to consume those.
  95    // If the found value has not a constant part, the Value gets returned
  96    // through the Value parameter.
  97    uint32_t getIndirect(nir_src *, uint8_t, Value *&);
  98    // isScalar indicates that the addressing is scalar, vec4 addressing is
  99    // assumed otherwise
 100    uint32_t getIndirect(nir_intrinsic_instr *, uint8_t s, uint8_t c, Value *&,
 101                         bool isScalar = false);
 102
 103    uint32_t getSlotAddress(nir_intrinsic_instr *, uint8_t idx, uint8_t slot);
 104
 105    void setInterpolate(nv50_ir_varying *,
 106                        uint8_t,
 107                        bool centroid,
 108                        unsigned semantics);
 109
 110    Instruction *loadFrom(DataFile, uint8_t, DataType, Value *def, uint32_t base,
 111                          uint8_t c, Value *indirect0 = NULL,
 112                          Value *indirect1 = NULL, bool patch = false);
 113    void storeTo(nir_intrinsic_instr *, DataFile, operation, DataType,
 114                 Value *src, uint8_t idx, uint8_t c, Value *indirect0 = NULL,
 115                 Value *indirect1 = NULL);
 116
 117    bool isFloatType(nir_alu_type);
 118    bool isSignedType(nir_alu_type);
 119    bool isResultFloat(nir_op);
 120    bool isResultSigned(nir_op);
 121
 122    DataType getDType(nir_alu_instr *);
 123    DataType getDType(nir_intrinsic_instr *);
 124    DataType getDType(nir_intrinsic_instr *, bool isSigned);
 125    DataType getDType(nir_op, uint8_t);
 126
 127    std::vector<DataType> getSTypes(nir_alu_instr *);
 128    DataType getSType(nir_src &, bool isFloat, bool isSigned);
 129
 130    operation getOperation(nir_intrinsic_op);
 131    operation getOperation(nir_op);
 132    operation getOperation(nir_texop);
 133    operation preOperationNeeded(nir_op);
 134
 135    int getSubOp(nir_intrinsic_op);
 136    int getSubOp(nir_op);
 137
 138    CondCode getCondCode(nir_op);
 139
 140    bool assignSlots();
 141    bool parseNIR();
 142
 143    bool visit(nir_alu_instr *);
 144    bool visit(nir_block *);
 145    bool visit(nir_cf_node *);
 146    bool visit(nir_deref_instr *);
 147    bool visit(nir_function *);
 148    bool visit(nir_if *);
 149    bool visit(nir_instr *);
 150    bool visit(nir_intrinsic_instr *);
 151    bool visit(nir_jump_instr *);
 152    bool visit(nir_load_const_instr*);
 153    bool visit(nir_loop *);
 154    bool visit(nir_ssa_undef_instr *);
 155    bool visit(nir_tex_instr *);
 156
 157    // tex stuff
 158    Value* applyProjection(Value *src, Value *proj);
 159    unsigned int getNIRArgCount(TexInstruction::Target&);
 160
 161    // image stuff
 162    uint16_t handleDeref(nir_deref_instr *, Value * & indirect, const nir_variable * &);
 163    CacheMode getCacheModeFromVar(const nir_variable *);
 164
 165    nir_shader *nir;
 166
 167    NirDefMap ssaDefs;
 168    NirDefMap regDefs;
 169    ImmediateMap immediates;
 170    NirArrayLMemOffsets regToLmemOffset;
 171    NirBlockMap blocks;
 172    unsigned int curLoopDepth;
 173
 174    BasicBlock *exit;
 175    Value *zero;
 176    Instruction *immInsertPos;
 177
 178    int clipVertexOutput;
 179
 180    union {
 181       struct {
 182          Value *position;
 183       } fp;
 184    };
 185 };
 186
 187 Converter::Converter(Program *prog, nir_shader *nir, nv50_ir_prog_info *info)
 188    : ConverterCommon(prog, info),
 189      nir(nir),
 190      curLoopDepth(0),
 191      clipVertexOutput(-1)
 192 {
 193    zero = mkImm((uint32_t)0);
 194 }
 195
 196 BasicBlock *
 197 Converter::convert(nir_block *block)
 198 {
 199    NirBlockMap::iterator it = blocks.find(block->index);
 200    if (it != blocks.end())
 201       return it->second;
 202
 203    BasicBlock *bb = new BasicBlock(func);
 204    blocks[block->index] = bb;
 205    return bb;
 206 }
 207
 208 bool
 209 Converter::isFloatType(nir_alu_type type)
 210 {
 211    return nir_alu_type_get_base_type(type) == nir_type_float;
 212 }
 213
 214 bool
 215 Converter::isSignedType(nir_alu_type type)
 216 {
 217    return nir_alu_type_get_base_type(type) == nir_type_int;
 218 }
 219
 220 bool
 221 Converter::isResultFloat(nir_op op)
 222 {
 223    const nir_op_info &info = nir_op_infos[op];
 224    if (info.output_type != nir_type_invalid)
 225       return isFloatType(info.output_type);
 226
 227    ERROR("isResultFloat not implemented for %s\n", nir_op_infos[op].name);
 228    assert(false);
 229    return true;
 230 }
 231
 232 bool
 233 Converter::isResultSigned(nir_op op)
 234 {
 235    switch (op) {
 236    // there is no umul and we get wrong results if we treat all muls as signed
 237    case nir_op_imul:
 238    case nir_op_inot:
 239       return false;
 240    default:
 241       const nir_op_info &info = nir_op_infos[op];
 242       if (info.output_type != nir_type_invalid)
 243          return isSignedType(info.output_type);
 244       ERROR("isResultSigned not implemented for %s\n", nir_op_infos[op].name);
 245       assert(false);
 246       return true;
 247    }
 248 }
 249
 250 DataType
 251 Converter::getDType(nir_alu_instr *insn)
 252 {
 253    if (insn->dest.dest.is_ssa)
 254       return getDType(insn->op, insn->dest.dest.ssa.bit_size);
 255    else
 256       return getDType(insn->op, insn->dest.dest.reg.reg->bit_size);
 257 }
 258
 259 DataType
 260 Converter::getDType(nir_intrinsic_instr *insn)
 261 {
 262    bool isSigned;
 263    switch (insn->intrinsic) {
 264    case nir_intrinsic_shared_atomic_imax:
 265    case nir_intrinsic_shared_atomic_imin:
 266    case nir_intrinsic_ssbo_atomic_imax:
 267    case nir_intrinsic_ssbo_atomic_imin:
 268       isSigned = true;
 269       break;
 270    default:
 271       isSigned = false;
 272       break;
 273    }
 274
 275    return getDType(insn, isSigned);
 276 }
 277
 278 DataType
 279 Converter::getDType(nir_intrinsic_instr *insn, bool isSigned)
 280 {
 281    if (insn->dest.is_ssa)
 282       return typeOfSize(insn->dest.ssa.bit_size / 8, false, isSigned);
 283    else
 284       return typeOfSize(insn->dest.reg.reg->bit_size / 8, false, isSigned);
 285 }
 286
 287 DataType
 288 Converter::getDType(nir_op op, uint8_t bitSize)
 289 {
 290    DataType ty = typeOfSize(bitSize / 8, isResultFloat(op), isResultSigned(op));
 291    if (ty == TYPE_NONE) {
 292       ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos[op].name, bitSize);
 293       assert(false);
 294    }
 295    return ty;
 296 }
 297
 298 std::vector<DataType>
 299 Converter::getSTypes(nir_alu_instr *insn)
 300 {
 301    const nir_op_info &info = nir_op_infos[insn->op];
 302    std::vector<DataType> res(info.num_inputs);
 303
 304    for (uint8_t i = 0; i < info.num_inputs; ++i) {
 305       if (info.input_types[i] != nir_type_invalid) {
 306          res[i] = getSType(insn->src[i].src, isFloatType(info.input_types[i]), isSignedType(info.input_types[i]));
 307       } else {
 308          ERROR("getSType not implemented for %s idx %u\n", info.name, i);
 309          assert(false);
 310          res[i] = TYPE_NONE;
 311          break;
 312       }
 313    }
 314
 315    return res;
 316 }
 317
 318 DataType
 319 Converter::getSType(nir_src &src, bool isFloat, bool isSigned)
 320 {
 321    uint8_t bitSize;
 322    if (src.is_ssa)
 323       bitSize = src.ssa->bit_size;
 324    else
 325       bitSize = src.reg.reg->bit_size;
 326
 327    DataType ty = typeOfSize(bitSize / 8, isFloat, isSigned);
 328    if (ty == TYPE_NONE) {
 329       const char *str;
 330       if (isFloat)
 331          str = "float";
 332       else if (isSigned)
 333          str = "int";
 334       else
 335          str = "uint";
 336       ERROR("couldn't get Type for %s with bitSize %u\n", str, bitSize);
 337       assert(false);
 338    }
 339    return ty;
 340 }
 341
 342 operation
 343 Converter::getOperation(nir_op op)
 344 {
 345    switch (op) {
 346    // basic ops with float and int variants
 347    case nir_op_fabs:
 348    case nir_op_iabs:
 349       return OP_ABS;
 350    case nir_op_fadd:
 351    case nir_op_iadd:
 352       return OP_ADD;
 353    case nir_op_iand:
 354       return OP_AND;
 355    case nir_op_ifind_msb:
 356    case nir_op_ufind_msb:
 357       return OP_BFIND;
 358    case nir_op_fceil:
 359       return OP_CEIL;
 360    case nir_op_fcos:
 361       return OP_COS;
 362    case nir_op_f2f32:
 363    case nir_op_f2f64:
 364    case nir_op_f2i32:
 365    case nir_op_f2i64:
 366    case nir_op_f2u32:
 367    case nir_op_f2u64:
 368    case nir_op_i2f32:
 369    case nir_op_i2f64:
 370    case nir_op_i2i32:
 371    case nir_op_i2i64:
 372    case nir_op_u2f32:
 373    case nir_op_u2f64:
 374    case nir_op_u2u32:
 375    case nir_op_u2u64:
 376       return OP_CVT;
 377    case nir_op_fddx:
 378    case nir_op_fddx_coarse:
 379    case nir_op_fddx_fine:
 380       return OP_DFDX;
 381    case nir_op_fddy:
 382    case nir_op_fddy_coarse:
 383    case nir_op_fddy_fine:
 384       return OP_DFDY;
 385    case nir_op_fdiv:
 386    case nir_op_idiv:
 387    case nir_op_udiv:
 388       return OP_DIV;
 389    case nir_op_fexp2:
 390       return OP_EX2;
 391    case nir_op_ffloor:
 392       return OP_FLOOR;
 393    case nir_op_ffma:
 394       return OP_FMA;
 395    case nir_op_flog2:
 396       return OP_LG2;
 397    case nir_op_fmax:
 398    case nir_op_imax:
 399    case nir_op_umax:
 400       return OP_MAX;
 401    case nir_op_pack_64_2x32_split:
 402       return OP_MERGE;
 403    case nir_op_fmin:
 404    case nir_op_imin:
 405    case nir_op_umin:
 406       return OP_MIN;
 407    case nir_op_fmod:
 408    case nir_op_imod:
 409    case nir_op_umod:
 410    case nir_op_frem:
 411    case nir_op_irem:
 412       return OP_MOD;
 413    case nir_op_fmul:
 414    case nir_op_imul:
 415    case nir_op_imul_high:
 416    case nir_op_umul_high:
 417       return OP_MUL;
 418    case nir_op_fneg:
 419    case nir_op_ineg:
 420       return OP_NEG;
 421    case nir_op_inot:
 422       return OP_NOT;
 423    case nir_op_ior:
 424       return OP_OR;
 425    case nir_op_fpow:
 426       return OP_POW;
 427    case nir_op_frcp:
 428       return OP_RCP;
 429    case nir_op_frsq:
 430       return OP_RSQ;
 431    case nir_op_fsat:
 432       return OP_SAT;
 433    case nir_op_feq32:
 434    case nir_op_ieq32:
 435    case nir_op_fge32:
 436    case nir_op_ige32:
 437    case nir_op_uge32:
 438    case nir_op_flt32:
 439    case nir_op_ilt32:
 440    case nir_op_ult32:
 441    case nir_op_fne32:
 442    case nir_op_ine32:
 443       return OP_SET;
 444    case nir_op_ishl:
 445       return OP_SHL;
 446    case nir_op_ishr:
 447    case nir_op_ushr:
 448       return OP_SHR;
 449    case nir_op_fsin:
 450       return OP_SIN;
 451    case nir_op_fsqrt:
 452       return OP_SQRT;
 453    case nir_op_ftrunc:
 454       return OP_TRUNC;
 455    case nir_op_ixor:
 456       return OP_XOR;
 457    default:
 458       ERROR("couldn't get operation for op %s\n", nir_op_infos[op].name);
 459       assert(false);
 460       return OP_NOP;
 461    }
 462 }
 463
 464 operation
 465 Converter::getOperation(nir_texop op)
 466 {
 467    switch (op) {
 468    case nir_texop_tex:
 469       return OP_TEX;
 470    case nir_texop_lod:
 471       return OP_TXLQ;
 472    case nir_texop_txb:
 473       return OP_TXB;
 474    case nir_texop_txd:
 475       return OP_TXD;
 476    case nir_texop_txf:
 477    case nir_texop_txf_ms:
 478       return OP_TXF;
 479    case nir_texop_tg4:
 480       return OP_TXG;
 481    case nir_texop_txl:
 482       return OP_TXL;
 483    case nir_texop_query_levels:
 484    case nir_texop_texture_samples:
 485    case nir_texop_txs:
 486       return OP_TXQ;
 487    default:
 488       ERROR("couldn't get operation for nir_texop %u\n", op);
 489       assert(false);
 490       return OP_NOP;
 491    }
 492 }
 493
 494 operation
 495 Converter::getOperation(nir_intrinsic_op op)
 496 {
 497    switch (op) {
 498    case nir_intrinsic_emit_vertex:
 499       return OP_EMIT;
 500    case nir_intrinsic_end_primitive:
 501       return OP_RESTART;
 502    case nir_intrinsic_bindless_image_atomic_add:
 503    case nir_intrinsic_image_atomic_add:
 504    case nir_intrinsic_image_deref_atomic_add:
 505    case nir_intrinsic_bindless_image_atomic_and:
 506    case nir_intrinsic_image_atomic_and:
 507    case nir_intrinsic_image_deref_atomic_and:
 508    case nir_intrinsic_bindless_image_atomic_comp_swap:
 509    case nir_intrinsic_image_atomic_comp_swap:
 510    case nir_intrinsic_image_deref_atomic_comp_swap:
 511    case nir_intrinsic_bindless_image_atomic_exchange:
 512    case nir_intrinsic_image_atomic_exchange:
 513    case nir_intrinsic_image_deref_atomic_exchange:
 514    case nir_intrinsic_bindless_image_atomic_imax:
 515    case nir_intrinsic_image_atomic_imax:
 516    case nir_intrinsic_image_deref_atomic_imax:
 517    case nir_intrinsic_bindless_image_atomic_umax:
 518    case nir_intrinsic_image_atomic_umax:
 519    case nir_intrinsic_image_deref_atomic_umax:
 520    case nir_intrinsic_bindless_image_atomic_imin:
 521    case nir_intrinsic_image_atomic_imin:
 522    case nir_intrinsic_image_deref_atomic_imin:
 523    case nir_intrinsic_bindless_image_atomic_umin:
 524    case nir_intrinsic_image_atomic_umin:
 525    case nir_intrinsic_image_deref_atomic_umin:
 526    case nir_intrinsic_bindless_image_atomic_or:
 527    case nir_intrinsic_image_atomic_or:
 528    case nir_intrinsic_image_deref_atomic_or:
 529    case nir_intrinsic_bindless_image_atomic_xor:
 530    case nir_intrinsic_image_atomic_xor:
 531    case nir_intrinsic_image_deref_atomic_xor:
 532       return OP_SUREDP;
 533    case nir_intrinsic_bindless_image_load:
 534    case nir_intrinsic_image_load:
 535    case nir_intrinsic_image_deref_load:
 536       return OP_SULDP;
 537    case nir_intrinsic_bindless_image_samples:
 538    case nir_intrinsic_image_samples:
 539    case nir_intrinsic_image_deref_samples:
 540    case nir_intrinsic_bindless_image_size:
 541    case nir_intrinsic_image_size:
 542    case nir_intrinsic_image_deref_size:
 543       return OP_SUQ;
 544    case nir_intrinsic_bindless_image_store:
 545    case nir_intrinsic_image_store:
 546    case nir_intrinsic_image_deref_store:
 547       return OP_SUSTP;
 548    default:
 549       ERROR("couldn't get operation for nir_intrinsic_op %u\n", op);
 550       assert(false);
 551       return OP_NOP;
 552    }
 553 }
 554
 555 operation
 556 Converter::preOperationNeeded(nir_op op)
 557 {
 558    switch (op) {
 559    case nir_op_fcos:
 560    case nir_op_fsin:
 561       return OP_PRESIN;
 562    default:
 563       return OP_NOP;
 564    }
 565 }
 566
 567 int
 568 Converter::getSubOp(nir_op op)
 569 {
 570    switch (op) {
 571    case nir_op_imul_high:
 572    case nir_op_umul_high:
 573       return NV50_IR_SUBOP_MUL_HIGH;
 574    default:
 575       return 0;
 576    }
 577 }
 578
 579 int
 580 Converter::getSubOp(nir_intrinsic_op op)
 581 {
 582    switch (op) {
 583    case nir_intrinsic_bindless_image_atomic_add:
 584    case nir_intrinsic_global_atomic_add:
 585    case nir_intrinsic_image_atomic_add:
 586    case nir_intrinsic_image_deref_atomic_add:
 587    case nir_intrinsic_shared_atomic_add:
 588    case nir_intrinsic_ssbo_atomic_add:
 589       return  NV50_IR_SUBOP_ATOM_ADD;
 590    case nir_intrinsic_bindless_image_atomic_and:
 591    case nir_intrinsic_global_atomic_and:
 592    case nir_intrinsic_image_atomic_and:
 593    case nir_intrinsic_image_deref_atomic_and:
 594    case nir_intrinsic_shared_atomic_and:
 595    case nir_intrinsic_ssbo_atomic_and:
 596       return  NV50_IR_SUBOP_ATOM_AND;
 597    case nir_intrinsic_bindless_image_atomic_comp_swap:
 598    case nir_intrinsic_global_atomic_comp_swap:
 599    case nir_intrinsic_image_atomic_comp_swap:
 600    case nir_intrinsic_image_deref_atomic_comp_swap:
 601    case nir_intrinsic_shared_atomic_comp_swap:
 602    case nir_intrinsic_ssbo_atomic_comp_swap:
 603       return  NV50_IR_SUBOP_ATOM_CAS;
 604    case nir_intrinsic_bindless_image_atomic_exchange:
 605    case nir_intrinsic_global_atomic_exchange:
 606    case nir_intrinsic_image_atomic_exchange:
 607    case nir_intrinsic_image_deref_atomic_exchange:
 608    case nir_intrinsic_shared_atomic_exchange:
 609    case nir_intrinsic_ssbo_atomic_exchange:
 610       return  NV50_IR_SUBOP_ATOM_EXCH;
 611    case nir_intrinsic_bindless_image_atomic_or:
 612    case nir_intrinsic_global_atomic_or:
 613    case nir_intrinsic_image_atomic_or:
 614    case nir_intrinsic_image_deref_atomic_or:
 615    case nir_intrinsic_shared_atomic_or:
 616    case nir_intrinsic_ssbo_atomic_or:
 617       return  NV50_IR_SUBOP_ATOM_OR;
 618    case nir_intrinsic_bindless_image_atomic_imax:
 619    case nir_intrinsic_bindless_image_atomic_umax:
 620    case nir_intrinsic_global_atomic_imax:
 621    case nir_intrinsic_global_atomic_umax:
 622    case nir_intrinsic_image_atomic_imax:
 623    case nir_intrinsic_image_atomic_umax:
 624    case nir_intrinsic_image_deref_atomic_imax:
 625    case nir_intrinsic_image_deref_atomic_umax:
 626    case nir_intrinsic_shared_atomic_imax:
 627    case nir_intrinsic_shared_atomic_umax:
 628    case nir_intrinsic_ssbo_atomic_imax:
 629    case nir_intrinsic_ssbo_atomic_umax:
 630       return  NV50_IR_SUBOP_ATOM_MAX;
 631    case nir_intrinsic_bindless_image_atomic_imin:
 632    case nir_intrinsic_bindless_image_atomic_umin:
 633    case nir_intrinsic_global_atomic_imin:
 634    case nir_intrinsic_global_atomic_umin:
 635    case nir_intrinsic_image_atomic_imin:
 636    case nir_intrinsic_image_atomic_umin:
 637    case nir_intrinsic_image_deref_atomic_imin:
 638    case nir_intrinsic_image_deref_atomic_umin:
 639    case nir_intrinsic_shared_atomic_imin:
 640    case nir_intrinsic_shared_atomic_umin:
 641    case nir_intrinsic_ssbo_atomic_imin:
 642    case nir_intrinsic_ssbo_atomic_umin:
 643       return  NV50_IR_SUBOP_ATOM_MIN;
 644    case nir_intrinsic_bindless_image_atomic_xor:
 645    case nir_intrinsic_global_atomic_xor:
 646    case nir_intrinsic_image_atomic_xor:
 647    case nir_intrinsic_image_deref_atomic_xor:
 648    case nir_intrinsic_shared_atomic_xor:
 649    case nir_intrinsic_ssbo_atomic_xor:
 650       return  NV50_IR_SUBOP_ATOM_XOR;
 651
 652    case nir_intrinsic_group_memory_barrier:
 653    case nir_intrinsic_memory_barrier:
 654    case nir_intrinsic_memory_barrier_buffer:
 655    case nir_intrinsic_memory_barrier_image:
 656       return NV50_IR_SUBOP_MEMBAR(M, GL);
 657    case nir_intrinsic_memory_barrier_shared:
 658       return NV50_IR_SUBOP_MEMBAR(M, CTA);
 659
 660    case nir_intrinsic_vote_all:
 661       return NV50_IR_SUBOP_VOTE_ALL;
 662    case nir_intrinsic_vote_any:
 663       return NV50_IR_SUBOP_VOTE_ANY;
 664    case nir_intrinsic_vote_ieq:
 665       return NV50_IR_SUBOP_VOTE_UNI;
 666    default:
 667       return 0;
 668    }
 669 }
 670
 671 CondCode
 672 Converter::getCondCode(nir_op op)
 673 {
 674    switch (op) {
 675    case nir_op_feq32:
 676    case nir_op_ieq32:
 677       return CC_EQ;
 678    case nir_op_fge32:
 679    case nir_op_ige32:
 680    case nir_op_uge32:
 681       return CC_GE;
 682    case nir_op_flt32:
 683    case nir_op_ilt32:
 684    case nir_op_ult32:
 685       return CC_LT;
 686    case nir_op_fne32:
 687       return CC_NEU;
 688    case nir_op_ine32:
 689       return CC_NE;
 690    default:
 691       ERROR("couldn't get CondCode for op %s\n", nir_op_infos[op].name);
 692       assert(false);
 693       return CC_FL;
 694    }
 695 }
 696
 697 Converter::LValues&
 698 Converter::convert(nir_alu_dest *dest)
 699 {
 700    return convert(&dest->dest);
 701 }
 702
 703 Converter::LValues&
 704 Converter::convert(nir_dest *dest)
 705 {
 706    if (dest->is_ssa)
 707       return convert(&dest->ssa);
 708    if (dest->reg.indirect) {
 709       ERROR("no support for indirects.");
 710       assert(false);
 711    }
 712    return convert(dest->reg.reg);
 713 }
 714
 715 Converter::LValues&
 716 Converter::convert(nir_register *reg)
 717 {
 718    NirDefMap::iterator it = regDefs.find(reg->index);
 719    if (it != regDefs.end())
 720       return it->second;
 721
 722    LValues newDef(reg->num_components);
 723    for (uint8_t i = 0; i < reg->num_components; i++)
 724       newDef[i] = getScratch(std::max(4, reg->bit_size / 8));
 725    return regDefs[reg->index] = newDef;
 726 }
 727
 728 Converter::LValues&
 729 Converter::convert(nir_ssa_def *def)
 730 {
 731    NirDefMap::iterator it = ssaDefs.find(def->index);
 732    if (it != ssaDefs.end())
 733       return it->second;
 734
 735    LValues newDef(def->num_components);
 736    for (uint8_t i = 0; i < def->num_components; i++)
 737       newDef[i] = getSSA(std::max(4, def->bit_size / 8));
 738    return ssaDefs[def->index] = newDef;
 739 }
 740
 741 Value*
 742 Converter::getSrc(nir_alu_src *src, uint8_t component)
 743 {
 744    if (src->abs || src->negate) {
 745       ERROR("modifiers currently not supported on nir_alu_src\n");
 746       assert(false);
 747    }
 748    return getSrc(&src->src, src->swizzle[component]);
 749 }
 750
 751 Value*
 752 Converter::getSrc(nir_register *reg, uint8_t idx)
 753 {
 754    NirDefMap::iterator it = regDefs.find(reg->index);
 755    if (it == regDefs.end())
 756       return convert(reg)[idx];
 757    return it->second[idx];
 758 }
 759
 760 Value*
 761 Converter::getSrc(nir_src *src, uint8_t idx, bool indirect)
 762 {
 763    if (src->is_ssa)
 764       return getSrc(src->ssa, idx);
 765
 766    if (src->reg.indirect) {
 767       if (indirect)
 768          return getSrc(src->reg.indirect, idx);
 769       ERROR("no support for indirects.");
 770       assert(false);
 771       return NULL;
 772    }
 773
 774    return getSrc(src->reg.reg, idx);
 775 }
 776
 777 Value*
 778 Converter::getSrc(nir_ssa_def *src, uint8_t idx)
 779 {
 780    ImmediateMap::iterator iit = immediates.find(src->index);
 781    if (iit != immediates.end())
 782       return convert((*iit).second, idx);
 783
 784    NirDefMap::iterator it = ssaDefs.find(src->index);
 785    if (it == ssaDefs.end()) {
 786       ERROR("SSA value %u not found\n", src->index);
 787       assert(false);
 788       return NULL;
 789    }
 790    return it->second[idx];
 791 }
 792
 793 uint32_t
 794 Converter::getIndirect(nir_src *src, uint8_t idx, Value *&indirect)
 795 {
 796    nir_const_value *offset = nir_src_as_const_value(*src);
 797
 798    if (offset) {
 799       indirect = NULL;
 800       return offset[0].u32;
 801    }
 802
 803    indirect = getSrc(src, idx, true);
 804    return 0;
 805 }
 806
 807 uint32_t
 808 Converter::getIndirect(nir_intrinsic_instr *insn, uint8_t s, uint8_t c, Value *&indirect, bool isScalar)
 809 {
 810    int32_t idx = nir_intrinsic_base(insn) + getIndirect(&insn->src[s], c, indirect);
 811    if (indirect && !isScalar)
 812       indirect = mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), indirect, loadImm(NULL, 4));
 813    return idx;
 814 }
 815
 816 static void
 817 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot, unsigned *name, unsigned *index)
 818 {
 819    assert(name && index);
 820
 821    if (slot >= VERT_ATTRIB_MAX) {
 822       ERROR("invalid varying slot %u\n", slot);
 823       assert(false);
 824       return;
 825    }
 826
 827    if (slot >= VERT_ATTRIB_GENERIC0 &&
 828        slot < VERT_ATTRIB_GENERIC0 + VERT_ATTRIB_GENERIC_MAX) {
 829       *name = TGSI_SEMANTIC_GENERIC;
 830       *index = slot - VERT_ATTRIB_GENERIC0;
 831       return;
 832    }
 833
 834    if (slot >= VERT_ATTRIB_TEX0 &&
 835        slot < VERT_ATTRIB_TEX0 + VERT_ATTRIB_TEX_MAX) {
 836       *name = TGSI_SEMANTIC_TEXCOORD;
 837       *index = slot - VERT_ATTRIB_TEX0;
 838       return;
 839    }
 840
 841    switch (slot) {
 842    case VERT_ATTRIB_COLOR0:
 843       *name = TGSI_SEMANTIC_COLOR;
 844       *index = 0;
 845       break;
 846    case VERT_ATTRIB_COLOR1:
 847       *name = TGSI_SEMANTIC_COLOR;
 848       *index = 1;
 849       break;
 850    case VERT_ATTRIB_EDGEFLAG:
 851       *name = TGSI_SEMANTIC_EDGEFLAG;
 852       *index = 0;
 853       break;
 854    case VERT_ATTRIB_FOG:
 855       *name = TGSI_SEMANTIC_FOG;
 856       *index = 0;
 857       break;
 858    case VERT_ATTRIB_NORMAL:
 859       *name = TGSI_SEMANTIC_NORMAL;
 860       *index = 0;
 861       break;
 862    case VERT_ATTRIB_POS:
 863       *name = TGSI_SEMANTIC_POSITION;
 864       *index = 0;
 865       break;
 866    case VERT_ATTRIB_POINT_SIZE:
 867       *name = TGSI_SEMANTIC_PSIZE;
 868       *index = 0;
 869       break;
 870    default:
 871       ERROR("unknown vert attrib slot %u\n", slot);
 872       assert(false);
 873       break;
 874    }
 875 }
 876
 877 void
 878 Converter::setInterpolate(nv50_ir_varying *var,
 879                           uint8_t mode,
 880                           bool centroid,
 881                           unsigned semantic)
 882 {
 883    switch (mode) {
 884    case INTERP_MODE_FLAT:
 885       var->flat = 1;
 886       break;
 887    case INTERP_MODE_NONE:
 888       if (semantic == TGSI_SEMANTIC_COLOR)
 889          var->sc = 1;
 890       else if (semantic == TGSI_SEMANTIC_POSITION)
 891          var->linear = 1;
 892       break;
 893    case INTERP_MODE_NOPERSPECTIVE:
 894       var->linear = 1;
 895       break;
 896    case INTERP_MODE_SMOOTH:
 897       break;
 898    }
 899    var->centroid = centroid;
 900 }
 901
 902 static uint16_t
 903 calcSlots(const glsl_type *type, Program::Type stage, const shader_info &info,
 904           bool input, const nir_variable *var)
 905 {
 906    if (!type->is_array())
 907       return type->count_attribute_slots(false);
 908
 909    uint16_t slots;
 910    switch (stage) {
 911    case Program::TYPE_GEOMETRY:
 912       slots = type->uniform_locations();
 913       if (input)
 914          slots /= info.gs.vertices_in;
 915       break;
 916    case Program::TYPE_TESSELLATION_CONTROL:
 917    case Program::TYPE_TESSELLATION_EVAL:
 918       // remove first dimension
 919       if (var->data.patch || (!input && stage == Program::TYPE_TESSELLATION_EVAL))
 920          slots = type->uniform_locations();
 921       else
 922          slots = type->fields.array->uniform_locations();
 923       break;
 924    default:
 925       slots = type->count_attribute_slots(false);
 926       break;
 927    }
 928
 929    return slots;
 930 }
 931
 932 bool Converter::assignSlots() {
 933    unsigned name;
 934    unsigned index;
 935
 936    info->io.viewportId = -1;
 937    info->numInputs = 0;
 938    info->numOutputs = 0;
 939
 940    // we have to fixup the uniform locations for arrays
 941    unsigned numImages = 0;
 942    nir_foreach_variable(var, &nir->uniforms) {
 943       const glsl_type *type = var->type;
 944       if (!type->without_array()->is_image())
 945          continue;
 946       var->data.driver_location = numImages;
 947       numImages += type->is_array() ? type->arrays_of_arrays_size() : 1;
 948    }
 949
 950    info->numSysVals = 0;
 951    for (uint8_t i = 0; i < SYSTEM_VALUE_MAX; ++i) {
 952       if (!(nir->info.system_values_read & 1ull << i))
 953          continue;
 954
 955       info->sv[info->numSysVals].sn = tgsi_get_sysval_semantic(i);
 956       info->sv[info->numSysVals].si = 0;
 957       info->sv[info->numSysVals].input = 0; // TODO inferSysValDirection(sn);
 958
 959       switch (i) {
 960       case SYSTEM_VALUE_INSTANCE_ID:
 961          info->io.instanceId = info->numSysVals;
 962          break;
 963       case SYSTEM_VALUE_TESS_LEVEL_INNER:
 964       case SYSTEM_VALUE_TESS_LEVEL_OUTER:
 965          info->sv[info->numSysVals].patch = 1;
 966          break;
 967       case SYSTEM_VALUE_VERTEX_ID:
 968          info->io.vertexId = info->numSysVals;
 969          break;
 970       default:
 971          break;
 972       }
 973
 974       info->numSysVals += 1;
 975    }
 976
 977    if (prog->getType() == Program::TYPE_COMPUTE)
 978       return true;
 979
 980    nir_foreach_variable(var, &nir->inputs) {
 981       const glsl_type *type = var->type;
 982       int slot = var->data.location;
 983       uint16_t slots = calcSlots(type, prog->getType(), nir->info, true, var);
 984       uint32_t comp = type->is_array() ? type->without_array()->component_slots()
 985                                        : type->component_slots();
 986       uint32_t frac = var->data.location_frac;
 987       uint32_t vary = var->data.driver_location;
 988
 989       if (glsl_base_type_is_64bit(type->without_array()->base_type)) {
 990          if (comp > 2)
 991             slots *= 2;
 992       }
 993
 994       assert(vary + slots <= PIPE_MAX_SHADER_INPUTS);
 995
 996       switch(prog->getType()) {
 997       case Program::TYPE_FRAGMENT:
 998          tgsi_get_gl_varying_semantic((gl_varying_slot)slot, true,
 999                                       &name, &index);
1000          for (uint16_t i = 0; i < slots; ++i) {
1001             setInterpolate(&info->in[vary + i], var->data.interpolation,
1002                            var->data.centroid | var->data.sample, name);
1003          }
1004          break;
1005       case Program::TYPE_GEOMETRY:
1006          tgsi_get_gl_varying_semantic((gl_varying_slot)slot, true,
1007                                       &name, &index);
1008          break;
1009       case Program::TYPE_TESSELLATION_CONTROL:
1010       case Program::TYPE_TESSELLATION_EVAL:
1011          tgsi_get_gl_varying_semantic((gl_varying_slot)slot, true,
1012                                       &name, &index);
1013          if (var->data.patch && name == TGSI_SEMANTIC_PATCH)
1014             info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
1015          break;
1016       case Program::TYPE_VERTEX:
1017          vert_attrib_to_tgsi_semantic((gl_vert_attrib)slot, &name, &index);
1018          switch (name) {
1019          case TGSI_SEMANTIC_EDGEFLAG:
1020             info->io.edgeFlagIn = vary;
1021             break;
1022          default:
1023             break;
1024          }
1025          break;
1026       default:
1027          ERROR("unknown shader type %u in assignSlots\n", prog->getType());
1028          return false;
1029       }
1030
1031       for (uint16_t i = 0u; i < slots; ++i, ++vary) {
1032          info->in[vary].id = vary;
1033          info->in[vary].patch = var->data.patch;
1034          info->in[vary].sn = name;
1035          info->in[vary].si = index + i;
1036          if (glsl_base_type_is_64bit(type->without_array()->base_type))
1037             if (i & 0x1)
1038                info->in[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) >> 0x4);
1039             else
1040                info->in[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) & 0xf);
1041          else
1042             info->in[vary].mask |= ((1 << comp) - 1) << frac;
1043       }
1044       info->numInputs = std::max<uint8_t>(info->numInputs, vary);
1045    }
1046
1047    nir_foreach_variable(var, &nir->outputs) {
1048       const glsl_type *type = var->type;
1049       int slot = var->data.location;
1050       uint16_t slots = calcSlots(type, prog->getType(), nir->info, false, var);
1051       uint32_t comp = type->is_array() ? type->without_array()->component_slots()
1052                                        : type->component_slots();
1053       uint32_t frac = var->data.location_frac;
1054       uint32_t vary = var->data.driver_location;
1055
1056       if (glsl_base_type_is_64bit(type->without_array()->base_type)) {
1057          if (comp > 2)
1058             slots *= 2;
1059       }
1060
1061       assert(vary < PIPE_MAX_SHADER_OUTPUTS);
1062
1063       switch(prog->getType()) {
1064       case Program::TYPE_FRAGMENT:
1065          tgsi_get_gl_frag_result_semantic((gl_frag_result)slot, &name, &index);
1066          switch (name) {
1067          case TGSI_SEMANTIC_COLOR:
1068             if (!var->data.fb_fetch_output)
1069                info->prop.fp.numColourResults++;
1070
1071             if (var->data.location == FRAG_RESULT_COLOR &&
1072                 nir->info.outputs_written & BITFIELD64_BIT(var->data.location))
1073                info->prop.fp.separateFragData = true;
1074
1075             // sometimes we get FRAG_RESULT_DATAX with data.index 0
1076             // sometimes we get FRAG_RESULT_DATA0 with data.index X
1077             index = index == 0 ? var->data.index : index;
1078             break;
1079          case TGSI_SEMANTIC_POSITION:
1080             info->io.fragDepth = vary;
1081             info->prop.fp.writesDepth = true;
1082             break;
1083          case TGSI_SEMANTIC_SAMPLEMASK:
1084             info->io.sampleMask = vary;
1085             break;
1086          default:
1087             break;
1088          }
1089          break;
1090       case Program::TYPE_GEOMETRY:
1091       case Program::TYPE_TESSELLATION_CONTROL:
1092       case Program::TYPE_TESSELLATION_EVAL:
1093       case Program::TYPE_VERTEX:
1094          tgsi_get_gl_varying_semantic((gl_varying_slot)slot, true,
1095                                       &name, &index);
1096
1097          if (var->data.patch && name != TGSI_SEMANTIC_TESSINNER &&
1098              name != TGSI_SEMANTIC_TESSOUTER)
1099             info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
1100
1101          switch (name) {
1102          case TGSI_SEMANTIC_CLIPDIST:
1103             info->io.genUserClip = -1;
1104             break;
1105          case TGSI_SEMANTIC_CLIPVERTEX:
1106             clipVertexOutput = vary;
1107             break;
1108          case TGSI_SEMANTIC_EDGEFLAG:
1109             info->io.edgeFlagOut = vary;
1110             break;
1111          case TGSI_SEMANTIC_POSITION:
1112             if (clipVertexOutput < 0)
1113                clipVertexOutput = vary;
1114             break;
1115          default:
1116             break;
1117          }
1118          break;
1119       default:
1120          ERROR("unknown shader type %u in assignSlots\n", prog->getType());
1121          return false;
1122       }
1123
1124       for (uint16_t i = 0u; i < slots; ++i, ++vary) {
1125          info->out[vary].id = vary;
1126          info->out[vary].patch = var->data.patch;
1127          info->out[vary].sn = name;
1128          info->out[vary].si = index + i;
1129          if (glsl_base_type_is_64bit(type->without_array()->base_type))
1130             if (i & 0x1)
1131                info->out[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) >> 0x4);
1132             else
1133                info->out[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) & 0xf);
1134          else
1135             info->out[vary].mask |= ((1 << comp) - 1) << frac;
1136
1137          if (nir->info.outputs_read & 1ull << slot)
1138             info->out[vary].oread = 1;
1139       }
1140       info->numOutputs = std::max<uint8_t>(info->numOutputs, vary);
1141    }
1142
1143    if (info->io.genUserClip > 0) {
1144       info->io.clipDistances = info->io.genUserClip;
1145
1146       const unsigned int nOut = (info->io.genUserClip + 3) / 4;
1147
1148       for (unsigned int n = 0; n < nOut; ++n) {
1149          unsigned int i = info->numOutputs++;
1150          info->out[i].id = i;
1151          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
1152          info->out[i].si = n;
1153          info->out[i].mask = ((1 << info->io.clipDistances) - 1) >> (n * 4);
1154       }
1155    }
1156
1157    return info->assignSlots(info) == 0;
1158 }
1159
1160 uint32_t
1161 Converter::getSlotAddress(nir_intrinsic_instr *insn, uint8_t idx, uint8_t slot)
1162 {
1163    DataType ty;
1164    int offset = nir_intrinsic_component(insn);
1165    bool input;
1166
1167    if (nir_intrinsic_infos[insn->intrinsic].has_dest)
1168       ty = getDType(insn);
1169    else
1170       ty = getSType(insn->src[0], false, false);
1171
1172    switch (insn->intrinsic) {
1173    case nir_intrinsic_load_input:
1174    case nir_intrinsic_load_interpolated_input:
1175    case nir_intrinsic_load_per_vertex_input:
1176       input = true;
1177       break;
1178    case nir_intrinsic_load_output:
1179    case nir_intrinsic_load_per_vertex_output:
1180    case nir_intrinsic_store_output:
1181    case nir_intrinsic_store_per_vertex_output:
1182       input = false;
1183       break;
1184    default:
1185       ERROR("unknown intrinsic in getSlotAddress %s",
1186             nir_intrinsic_infos[insn->intrinsic].name);
1187       input = false;
1188       assert(false);
1189       break;
1190    }
1191
1192    if (typeSizeof(ty) == 8) {
1193       slot *= 2;
1194       slot += offset;
1195       if (slot >= 4) {
1196          idx += 1;
1197          slot -= 4;
1198       }
1199    } else {
1200       slot += offset;
1201    }
1202
1203    assert(slot < 4);
1204    assert(!input || idx < PIPE_MAX_SHADER_INPUTS);
1205    assert(input || idx < PIPE_MAX_SHADER_OUTPUTS);
1206
1207    const nv50_ir_varying *vary = input ? info->in : info->out;
1208    return vary[idx].slot[slot] * 4;
1209 }
1210
1211 Instruction *
1212 Converter::loadFrom(DataFile file, uint8_t i, DataType ty, Value *def,
1213                     uint32_t base, uint8_t c, Value *indirect0,
1214                     Value *indirect1, bool patch)
1215 {
1216    unsigned int tySize = typeSizeof(ty);
1217
1218    if (tySize == 8 &&
1219        (file == FILE_MEMORY_CONST || file == FILE_MEMORY_BUFFER || indirect0)) {
1220       Value *lo = getSSA();
1221       Value *hi = getSSA();
1222
1223       Instruction *loi =
1224          mkLoad(TYPE_U32, lo,
1225                 mkSymbol(file, i, TYPE_U32, base + c * tySize),
1226                 indirect0);
1227       loi->setIndirect(0, 1, indirect1);
1228       loi->perPatch = patch;
1229
1230       Instruction *hii =
1231          mkLoad(TYPE_U32, hi,
1232                 mkSymbol(file, i, TYPE_U32, base + c * tySize + 4),
1233                 indirect0);
1234       hii->setIndirect(0, 1, indirect1);
1235       hii->perPatch = patch;
1236
1237       return mkOp2(OP_MERGE, ty, def, lo, hi);
1238    } else {
1239       Instruction *ld =
1240          mkLoad(ty, def, mkSymbol(file, i, ty, base + c * tySize), indirect0);
1241       ld->setIndirect(0, 1, indirect1);
1242       ld->perPatch = patch;
1243       return ld;
1244    }
1245 }
1246
1247 void
1248 Converter::storeTo(nir_intrinsic_instr *insn, DataFile file, operation op,
1249                    DataType ty, Value *src, uint8_t idx, uint8_t c,
1250                    Value *indirect0, Value *indirect1)
1251 {
1252    uint8_t size = typeSizeof(ty);
1253    uint32_t address = getSlotAddress(insn, idx, c);
1254
1255    if (size == 8 && indirect0) {
1256       Value *split[2];
1257       mkSplit(split, 4, src);
1258
1259       if (op == OP_EXPORT) {
1260          split[0] = mkMov(getSSA(), split[0], ty)->getDef(0);
1261          split[1] = mkMov(getSSA(), split[1], ty)->getDef(0);
1262       }
1263
1264       mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address), indirect0,
1265               split[0])->perPatch = info->out[idx].patch;
1266       mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address + 4), indirect0,
1267               split[1])->perPatch = info->out[idx].patch;
1268    } else {
1269       if (op == OP_EXPORT)
1270          src = mkMov(getSSA(size), src, ty)->getDef(0);
1271       mkStore(op, ty, mkSymbol(file, 0, ty, address), indirect0,
1272               src)->perPatch = info->out[idx].patch;
1273    }
1274 }
1275
1276 bool
1277 Converter::parseNIR()
1278 {
1279    info->bin.tlsSpace = 0;
1280    info->io.clipDistances = nir->info.clip_distance_array_size;
1281    info->io.cullDistances = nir->info.cull_distance_array_size;
1282
1283    switch(prog->getType()) {
1284    case Program::TYPE_COMPUTE:
1285       info->prop.cp.numThreads[0] = nir->info.cs.local_size[0];
1286       info->prop.cp.numThreads[1] = nir->info.cs.local_size[1];
1287       info->prop.cp.numThreads[2] = nir->info.cs.local_size[2];
1288       info->bin.smemSize = nir->info.cs.shared_size;
1289       break;
1290    case Program::TYPE_FRAGMENT:
1291       info->prop.fp.earlyFragTests = nir->info.fs.early_fragment_tests;
1292       info->prop.fp.persampleInvocation =
1293          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_ID) ||
1294          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1295       info->prop.fp.postDepthCoverage = nir->info.fs.post_depth_coverage;
1296       info->prop.fp.readsSampleLocations =
1297          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1298       info->prop.fp.usesDiscard = nir->info.fs.uses_discard;
1299       info->prop.fp.usesSampleMaskIn =
1300          !!(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN);
1301       break;
1302    case Program::TYPE_GEOMETRY:
1303       info->prop.gp.inputPrim = nir->info.gs.input_primitive;
1304       info->prop.gp.instanceCount = nir->info.gs.invocations;
1305       info->prop.gp.maxVertices = nir->info.gs.vertices_out;
1306       info->prop.gp.outputPrim = nir->info.gs.output_primitive;
1307       break;
1308    case Program::TYPE_TESSELLATION_CONTROL:
1309    case Program::TYPE_TESSELLATION_EVAL:
1310       if (nir->info.tess.primitive_mode == GL_ISOLINES)
1311          info->prop.tp.domain = GL_LINES;
1312       else
1313          info->prop.tp.domain = nir->info.tess.primitive_mode;
1314       info->prop.tp.outputPatchSize = nir->info.tess.tcs_vertices_out;
1315       info->prop.tp.outputPrim =
1316          nir->info.tess.point_mode ? PIPE_PRIM_POINTS : PIPE_PRIM_TRIANGLES;
1317       info->prop.tp.partitioning = (nir->info.tess.spacing + 1) % 3;
1318       info->prop.tp.winding = !nir->info.tess.ccw;
1319       break;
1320    case Program::TYPE_VERTEX:
1321       info->prop.vp.usesDrawParameters =
1322          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) ||
1323          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE)) ||
1324          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID));
1325       break;
1326    default:
1327       break;
1328    }
1329
1330    return true;
1331 }
1332
1333 bool
1334 Converter::visit(nir_function *function)
1335 {
1336    assert(function->impl);
1337
1338    // usually the blocks will set everything up, but main is special
1339    BasicBlock *entry = new BasicBlock(prog->main);
1340    exit = new BasicBlock(prog->main);
1341    blocks[nir_start_block(function->impl)->index] = entry;
1342    prog->main->setEntry(entry);
1343    prog->main->setExit(exit);
1344
1345    setPosition(entry, true);
1346
1347    if (info->io.genUserClip > 0) {
1348       for (int c = 0; c < 4; ++c)
1349          clipVtx[c] = getScratch();
1350    }
1351
1352    switch (prog->getType()) {
1353    case Program::TYPE_TESSELLATION_CONTROL:
1354       outBase = mkOp2v(
1355          OP_SUB, TYPE_U32, getSSA(),
1356          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
1357          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
1358       break;
1359    case Program::TYPE_FRAGMENT: {
1360       Symbol *sv = mkSysVal(SV_POSITION, 3);
1361       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
1362       fp.position = mkOp1v(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
1363       break;
1364    }
1365    default:
1366       break;
1367    }
1368
1369    nir_foreach_register(reg, &function->impl->registers) {
1370       if (reg->num_array_elems) {
1371          // TODO: packed variables would be nice, but MemoryOpt fails
1372          // replace 4 with reg->num_components
1373          uint32_t size = 4 * reg->num_array_elems * (reg->bit_size / 8);
1374          regToLmemOffset[reg->index] = info->bin.tlsSpace;
1375          info->bin.tlsSpace += size;
1376       }
1377    }
1378
1379    nir_index_ssa_defs(function->impl);
1380    foreach_list_typed(nir_cf_node, node, node, &function->impl->body) {
1381       if (!visit(node))
1382          return false;
1383    }
1384
1385    bb->cfg.attach(&exit->cfg, Graph::Edge::TREE);
1386    setPosition(exit, true);
1387
1388    if ((prog->getType() == Program::TYPE_VERTEX ||
1389         prog->getType() == Program::TYPE_TESSELLATION_EVAL)
1390        && info->io.genUserClip > 0)
1391       handleUserClipPlanes();
1392
1393    // TODO: for non main function this needs to be a OP_RETURN
1394    mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
1395    return true;
1396 }
1397
1398 bool
1399 Converter::visit(nir_cf_node *node)
1400 {
1401    switch (node->type) {
1402    case nir_cf_node_block:
1403       return visit(nir_cf_node_as_block(node));
1404    case nir_cf_node_if:
1405       return visit(nir_cf_node_as_if(node));
1406    case nir_cf_node_loop:
1407       return visit(nir_cf_node_as_loop(node));
1408    default:
1409       ERROR("unknown nir_cf_node type %u\n", node->type);
1410       return false;
1411    }
1412 }
1413
1414 bool
1415 Converter::visit(nir_block *block)
1416 {
1417    if (!block->predecessors->entries && block->instr_list.is_empty())
1418       return true;
1419
1420    BasicBlock *bb = convert(block);
1421
1422    setPosition(bb, true);
1423    nir_foreach_instr(insn, block) {
1424       if (!visit(insn))
1425          return false;
1426    }
1427    return true;
1428 }
1429
1430 bool
1431 Converter::visit(nir_if *nif)
1432 {
1433    DataType sType = getSType(nif->condition, false, false);
1434    Value *src = getSrc(&nif->condition, 0);
1435
1436    nir_block *lastThen = nir_if_last_then_block(nif);
1437    nir_block *lastElse = nir_if_last_else_block(nif);
1438
1439    assert(!lastThen->successors[1]);
1440    assert(!lastElse->successors[1]);
1441
1442    BasicBlock *ifBB = convert(nir_if_first_then_block(nif));
1443    BasicBlock *elseBB = convert(nir_if_first_else_block(nif));
1444
1445    bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
1446    bb->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
1447
1448    // we only insert joinats, if both nodes end up at the end of the if again.
1449    // the reason for this to not happens are breaks/continues/ret/... which
1450    // have their own handling
1451    if (lastThen->successors[0] == lastElse->successors[0])
1452       bb->joinAt = mkFlow(OP_JOINAT, convert(lastThen->successors[0]),
1453                           CC_ALWAYS, NULL);
1454
1455    mkFlow(OP_BRA, elseBB, CC_EQ, src)->setType(sType);
1456
1457    foreach_list_typed(nir_cf_node, node, node, &nif->then_list) {
1458       if (!visit(node))
1459          return false;
1460    }
1461    setPosition(convert(lastThen), true);
1462    if (!bb->getExit() ||
1463        !bb->getExit()->asFlow() ||
1464         bb->getExit()->asFlow()->op == OP_JOIN) {
1465       BasicBlock *tailBB = convert(lastThen->successors[0]);
1466       mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1467       bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1468    }
1469
1470    foreach_list_typed(nir_cf_node, node, node, &nif->else_list) {
1471       if (!visit(node))
1472          return false;
1473    }
1474    setPosition(convert(lastElse), true);
1475    if (!bb->getExit() ||
1476        !bb->getExit()->asFlow() ||
1477         bb->getExit()->asFlow()->op == OP_JOIN) {
1478       BasicBlock *tailBB = convert(lastElse->successors[0]);
1479       mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1480       bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1481    }
1482
1483    if (lastThen->successors[0] == lastElse->successors[0]) {
1484       setPosition(convert(lastThen->successors[0]), true);
1485       mkFlow(OP_JOIN, NULL, CC_ALWAYS, NULL)->fixed = 1;
1486    }
1487
1488    return true;
1489 }
1490
1491 bool
1492 Converter::visit(nir_loop *loop)
1493 {
1494    curLoopDepth += 1;
1495    func->loopNestingBound = std::max(func->loopNestingBound, curLoopDepth);
1496
1497    BasicBlock *loopBB = convert(nir_loop_first_block(loop));
1498    BasicBlock *tailBB =
1499       convert(nir_cf_node_as_block(nir_cf_node_next(&loop->cf_node)));
1500    bb->cfg.attach(&loopBB->cfg, Graph::Edge::TREE);
1501
1502    mkFlow(OP_PREBREAK, tailBB, CC_ALWAYS, NULL);
1503    setPosition(loopBB, false);
1504    mkFlow(OP_PRECONT, loopBB, CC_ALWAYS, NULL);
1505
1506    foreach_list_typed(nir_cf_node, node, node, &loop->body) {
1507       if (!visit(node))
1508          return false;
1509    }
1510    Instruction *insn = bb->getExit();
1511    if (bb->cfg.incidentCount() != 0) {
1512       if (!insn || !insn->asFlow()) {
1513          mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
1514          bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
1515       } else if (insn && insn->op == OP_BRA && !insn->getPredicate() &&
1516                  tailBB->cfg.incidentCount() == 0) {
1517          // RA doesn't like having blocks around with no incident edge,
1518          // so we create a fake one to make it happy
1519          bb->cfg.attach(&tailBB->cfg, Graph::Edge::TREE);
1520       }
1521    }
1522
1523    curLoopDepth -= 1;
1524
1525    return true;
1526 }
1527
1528 bool
1529 Converter::visit(nir_instr *insn)
1530 {
1531    // we need an insertion point for on the fly generated immediate loads
1532    immInsertPos = bb->getExit();
1533    switch (insn->type) {
1534    case nir_instr_type_alu:
1535       return visit(nir_instr_as_alu(insn));
1536    case nir_instr_type_deref:
1537       return visit(nir_instr_as_deref(insn));
1538    case nir_instr_type_intrinsic:
1539       return visit(nir_instr_as_intrinsic(insn));
1540    case nir_instr_type_jump:
1541       return visit(nir_instr_as_jump(insn));
1542    case nir_instr_type_load_const:
1543       return visit(nir_instr_as_load_const(insn));
1544    case nir_instr_type_ssa_undef:
1545       return visit(nir_instr_as_ssa_undef(insn));
1546    case nir_instr_type_tex:
1547       return visit(nir_instr_as_tex(insn));
1548    default:
1549       ERROR("unknown nir_instr type %u\n", insn->type);
1550       return false;
1551    }
1552    return true;
1553 }
1554
1555 SVSemantic
1556 Converter::convert(nir_intrinsic_op intr)
1557 {
1558    switch (intr) {
1559    case nir_intrinsic_load_base_vertex:
1560       return SV_BASEVERTEX;
1561    case nir_intrinsic_load_base_instance:
1562       return SV_BASEINSTANCE;
1563    case nir_intrinsic_load_draw_id:
1564       return SV_DRAWID;
1565    case nir_intrinsic_load_front_face:
1566       return SV_FACE;
1567    case nir_intrinsic_load_helper_invocation:
1568       return SV_THREAD_KILL;
1569    case nir_intrinsic_load_instance_id:
1570       return SV_INSTANCE_ID;
1571    case nir_intrinsic_load_invocation_id:
1572       return SV_INVOCATION_ID;
1573    case nir_intrinsic_load_local_group_size:
1574       return SV_NTID;
1575    case nir_intrinsic_load_local_invocation_id:
1576       return SV_TID;
1577    case nir_intrinsic_load_num_work_groups:
1578       return SV_NCTAID;
1579    case nir_intrinsic_load_patch_vertices_in:
1580       return SV_VERTEX_COUNT;
1581    case nir_intrinsic_load_primitive_id:
1582       return SV_PRIMITIVE_ID;
1583    case nir_intrinsic_load_sample_id:
1584       return SV_SAMPLE_INDEX;
1585    case nir_intrinsic_load_sample_mask_in:
1586       return SV_SAMPLE_MASK;
1587    case nir_intrinsic_load_sample_pos:
1588       return SV_SAMPLE_POS;
1589    case nir_intrinsic_load_subgroup_eq_mask:
1590       return SV_LANEMASK_EQ;
1591    case nir_intrinsic_load_subgroup_ge_mask:
1592       return SV_LANEMASK_GE;
1593    case nir_intrinsic_load_subgroup_gt_mask:
1594       return SV_LANEMASK_GT;
1595    case nir_intrinsic_load_subgroup_le_mask:
1596       return SV_LANEMASK_LE;
1597    case nir_intrinsic_load_subgroup_lt_mask:
1598       return SV_LANEMASK_LT;
1599    case nir_intrinsic_load_subgroup_invocation:
1600       return SV_LANEID;
1601    case nir_intrinsic_load_tess_coord:
1602       return SV_TESS_COORD;
1603    case nir_intrinsic_load_tess_level_inner:
1604       return SV_TESS_INNER;
1605    case nir_intrinsic_load_tess_level_outer:
1606       return SV_TESS_OUTER;
1607    case nir_intrinsic_load_vertex_id:
1608       return SV_VERTEX_ID;
1609    case nir_intrinsic_load_work_group_id:
1610       return SV_CTAID;
1611    default:
1612       ERROR("unknown SVSemantic for nir_intrinsic_op %s\n",
1613             nir_intrinsic_infos[intr].name);
1614       assert(false);
1615       return SV_LAST;
1616    }
1617 }
1618
1619 bool
1620 Converter::visit(nir_intrinsic_instr *insn)
1621 {
1622    nir_intrinsic_op op = insn->intrinsic;
1623    const nir_intrinsic_info &opInfo = nir_intrinsic_infos[op];
1624    unsigned dest_components = nir_intrinsic_dest_components(insn);
1625
1626    switch (op) {
1627    case nir_intrinsic_load_uniform: {
1628       LValues &newDefs = convert(&insn->dest);
1629       const DataType dType = getDType(insn);
1630       Value *indirect;
1631       uint32_t coffset = getIndirect(insn, 0, 0, indirect);
1632       for (uint8_t i = 0; i < dest_components; ++i) {
1633          loadFrom(FILE_MEMORY_CONST, 0, dType, newDefs[i], 16 * coffset, i, indirect);
1634       }
1635       break;
1636    }
1637    case nir_intrinsic_store_output:
1638    case nir_intrinsic_store_per_vertex_output: {
1639       Value *indirect;
1640       DataType dType = getSType(insn->src[0], false, false);
1641       uint32_t idx = getIndirect(insn, op == nir_intrinsic_store_output ? 1 : 2, 0, indirect);
1642
1643       for (uint8_t i = 0u; i < nir_intrinsic_src_components(insn, 0); ++i) {
1644          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
1645             continue;
1646
1647          uint8_t offset = 0;
1648          Value *src = getSrc(&insn->src[0], i);
1649          switch (prog->getType()) {
1650          case Program::TYPE_FRAGMENT: {
1651             if (info->out[idx].sn == TGSI_SEMANTIC_POSITION) {
1652                // TGSI uses a different interface than NIR, TGSI stores that
1653                // value in the z component, NIR in X
1654                offset += 2;
1655                src = mkOp1v(OP_SAT, TYPE_F32, getScratch(), src);
1656             }
1657             break;
1658          }
1659          case Program::TYPE_GEOMETRY:
1660          case Program::TYPE_VERTEX: {
1661             if (info->io.genUserClip > 0 && idx == (uint32_t)clipVertexOutput) {
1662                mkMov(clipVtx[i], src);
1663                src = clipVtx[i];
1664             }
1665             break;
1666          }
1667          default:
1668             break;
1669          }
1670
1671          storeTo(insn, FILE_SHADER_OUTPUT, OP_EXPORT, dType, src, idx, i + offset, indirect);
1672       }
1673       break;
1674    }
1675    case nir_intrinsic_load_input:
1676    case nir_intrinsic_load_interpolated_input:
1677    case nir_intrinsic_load_output: {
1678       LValues &newDefs = convert(&insn->dest);
1679
1680       // FBFetch
1681       if (prog->getType() == Program::TYPE_FRAGMENT &&
1682           op == nir_intrinsic_load_output) {
1683          std::vector<Value*> defs, srcs;
1684          uint8_t mask = 0;
1685
1686          srcs.push_back(getSSA());
1687          srcs.push_back(getSSA());
1688          Value *x = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 0));
1689          Value *y = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 1));
1690          mkCvt(OP_CVT, TYPE_U32, srcs[0], TYPE_F32, x)->rnd = ROUND_Z;
1691          mkCvt(OP_CVT, TYPE_U32, srcs[1], TYPE_F32, y)->rnd = ROUND_Z;
1692
1693          srcs.push_back(mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LAYER, 0)));
1694          srcs.push_back(mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_SAMPLE_INDEX, 0)));
1695
1696          for (uint8_t i = 0u; i < dest_components; ++i) {
1697             defs.push_back(newDefs[i]);
1698             mask |= 1 << i;
1699          }
1700
1701          TexInstruction *texi = mkTex(OP_TXF, TEX_TARGET_2D_MS_ARRAY, 0, 0, defs, srcs);
1702          texi->tex.levelZero = 1;
1703          texi->tex.mask = mask;
1704          texi->tex.useOffsets = 0;
1705          texi->tex.r = 0xffff;
1706          texi->tex.s = 0xffff;
1707
1708          info->prop.fp.readsFramebuffer = true;
1709          break;
1710       }
1711
1712       const DataType dType = getDType(insn);
1713       Value *indirect;
1714       bool input = op != nir_intrinsic_load_output;
1715       operation nvirOp;
1716       uint32_t mode = 0;
1717
1718       uint32_t idx = getIndirect(insn, op == nir_intrinsic_load_interpolated_input ? 1 : 0, 0, indirect);
1719       nv50_ir_varying& vary = input ? info->in[idx] : info->out[idx];
1720
1721       // see load_barycentric_* handling
1722       if (prog->getType() == Program::TYPE_FRAGMENT) {
1723          mode = translateInterpMode(&vary, nvirOp);
1724          if (op == nir_intrinsic_load_interpolated_input) {
1725             ImmediateValue immMode;
1726             if (getSrc(&insn->src[0], 1)->getUniqueInsn()->src(0).getImmediate(immMode))
1727                mode |= immMode.reg.data.u32;
1728          }
1729       }
1730
1731       for (uint8_t i = 0u; i < dest_components; ++i) {
1732          uint32_t address = getSlotAddress(insn, idx, i);
1733          Symbol *sym = mkSymbol(input ? FILE_SHADER_INPUT : FILE_SHADER_OUTPUT, 0, dType, address);
1734          if (prog->getType() == Program::TYPE_FRAGMENT) {
1735             int s = 1;
1736             if (typeSizeof(dType) == 8) {
1737                Value *lo = getSSA();
1738                Value *hi = getSSA();
1739                Instruction *interp;
1740
1741                interp = mkOp1(nvirOp, TYPE_U32, lo, sym);
1742                if (nvirOp == OP_PINTERP)
1743                   interp->setSrc(s++, fp.position);
1744                if (mode & NV50_IR_INTERP_OFFSET)
1745                   interp->setSrc(s++, getSrc(&insn->src[0], 0));
1746                interp->setInterpolate(mode);
1747                interp->setIndirect(0, 0, indirect);
1748
1749                Symbol *sym1 = mkSymbol(input ? FILE_SHADER_INPUT : FILE_SHADER_OUTPUT, 0, dType, address + 4);
1750                interp = mkOp1(nvirOp, TYPE_U32, hi, sym1);
1751                if (nvirOp == OP_PINTERP)
1752                   interp->setSrc(s++, fp.position);
1753                if (mode & NV50_IR_INTERP_OFFSET)
1754                   interp->setSrc(s++, getSrc(&insn->src[0], 0));
1755                interp->setInterpolate(mode);
1756                interp->setIndirect(0, 0, indirect);
1757
1758                mkOp2(OP_MERGE, dType, newDefs[i], lo, hi);
1759             } else {
1760                Instruction *interp = mkOp1(nvirOp, dType, newDefs[i], sym);
1761                if (nvirOp == OP_PINTERP)
1762                   interp->setSrc(s++, fp.position);
1763                if (mode & NV50_IR_INTERP_OFFSET)
1764                   interp->setSrc(s++, getSrc(&insn->src[0], 0));
1765                interp->setInterpolate(mode);
1766                interp->setIndirect(0, 0, indirect);
1767             }
1768          } else {
1769             mkLoad(dType, newDefs[i], sym, indirect)->perPatch = vary.patch;
1770          }
1771       }
1772       break;
1773    }
1774    case nir_intrinsic_load_kernel_input: {
1775       assert(prog->getType() == Program::TYPE_COMPUTE);
1776       assert(insn->num_components == 1);
1777
1778       LValues &newDefs = convert(&insn->dest);
1779       const DataType dType = getDType(insn);
1780       Value *indirect;
1781       uint32_t idx = getIndirect(insn, 0, 0, indirect, true);
1782
1783       mkLoad(dType, newDefs[0], mkSymbol(FILE_SHADER_INPUT, 0, dType, idx), indirect);
1784       break;
1785    }
1786    case nir_intrinsic_load_barycentric_at_offset:
1787    case nir_intrinsic_load_barycentric_at_sample:
1788    case nir_intrinsic_load_barycentric_centroid:
1789    case nir_intrinsic_load_barycentric_pixel:
1790    case nir_intrinsic_load_barycentric_sample: {
1791       LValues &newDefs = convert(&insn->dest);
1792       uint32_t mode;
1793
1794       if (op == nir_intrinsic_load_barycentric_centroid ||
1795           op == nir_intrinsic_load_barycentric_sample) {
1796          mode = NV50_IR_INTERP_CENTROID;
1797       } else if (op == nir_intrinsic_load_barycentric_at_offset) {
1798          Value *offs[2];
1799          for (uint8_t c = 0; c < 2; c++) {
1800             offs[c] = getScratch();
1801             mkOp2(OP_MIN, TYPE_F32, offs[c], getSrc(&insn->src[0], c), loadImm(NULL, 0.4375f));
1802             mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
1803             mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
1804             mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
1805          }
1806          mkOp3v(OP_INSBF, TYPE_U32, newDefs[0], offs[1], mkImm(0x1010), offs[0]);
1807
1808          mode = NV50_IR_INTERP_OFFSET;
1809       } else if (op == nir_intrinsic_load_barycentric_pixel) {
1810          mode = NV50_IR_INTERP_DEFAULT;
1811       } else if (op == nir_intrinsic_load_barycentric_at_sample) {
1812          info->prop.fp.readsSampleLocations = true;
1813          mkOp1(OP_PIXLD, TYPE_U32, newDefs[0], getSrc(&insn->src[0], 0))->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
1814          mode = NV50_IR_INTERP_OFFSET;
1815       } else {
1816          unreachable("all intrinsics already handled above");
1817       }
1818
1819       loadImm(newDefs[1], mode);
1820       break;
1821    }
1822    case nir_intrinsic_discard:
1823       mkOp(OP_DISCARD, TYPE_NONE, NULL);
1824       break;
1825    case nir_intrinsic_discard_if: {
1826       Value *pred = getSSA(1, FILE_PREDICATE);
1827       if (insn->num_components > 1) {
1828          ERROR("nir_intrinsic_discard_if only with 1 component supported!\n");
1829          assert(false);
1830          return false;
1831       }
1832       mkCmp(OP_SET, CC_NE, TYPE_U8, pred, TYPE_U32, getSrc(&insn->src[0], 0), zero);
1833       mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, pred);
1834       break;
1835    }
1836    case nir_intrinsic_load_base_vertex:
1837    case nir_intrinsic_load_base_instance:
1838    case nir_intrinsic_load_draw_id:
1839    case nir_intrinsic_load_front_face:
1840    case nir_intrinsic_load_helper_invocation:
1841    case nir_intrinsic_load_instance_id:
1842    case nir_intrinsic_load_invocation_id:
1843    case nir_intrinsic_load_local_group_size:
1844    case nir_intrinsic_load_local_invocation_id:
1845    case nir_intrinsic_load_num_work_groups:
1846    case nir_intrinsic_load_patch_vertices_in:
1847    case nir_intrinsic_load_primitive_id:
1848    case nir_intrinsic_load_sample_id:
1849    case nir_intrinsic_load_sample_mask_in:
1850    case nir_intrinsic_load_sample_pos:
1851    case nir_intrinsic_load_subgroup_eq_mask:
1852    case nir_intrinsic_load_subgroup_ge_mask:
1853    case nir_intrinsic_load_subgroup_gt_mask:
1854    case nir_intrinsic_load_subgroup_le_mask:
1855    case nir_intrinsic_load_subgroup_lt_mask:
1856    case nir_intrinsic_load_subgroup_invocation:
1857    case nir_intrinsic_load_tess_coord:
1858    case nir_intrinsic_load_tess_level_inner:
1859    case nir_intrinsic_load_tess_level_outer:
1860    case nir_intrinsic_load_vertex_id:
1861    case nir_intrinsic_load_work_group_id: {
1862       const DataType dType = getDType(insn);
1863       SVSemantic sv = convert(op);
1864       LValues &newDefs = convert(&insn->dest);
1865
1866       for (uint8_t i = 0u; i < nir_intrinsic_dest_components(insn); ++i) {
1867          Value *def;
1868          if (typeSizeof(dType) == 8)
1869             def = getSSA();
1870          else
1871             def = newDefs[i];
1872
1873          if (sv == SV_TID && info->prop.cp.numThreads[i] == 1) {
1874             loadImm(def, 0u);
1875          } else {
1876             Symbol *sym = mkSysVal(sv, i);
1877             Instruction *rdsv = mkOp1(OP_RDSV, TYPE_U32, def, sym);
1878             if (sv == SV_TESS_OUTER || sv == SV_TESS_INNER)
1879                rdsv->perPatch = 1;
1880          }
1881
1882          if (typeSizeof(dType) == 8)
1883             mkOp2(OP_MERGE, dType, newDefs[i], def, loadImm(getSSA(), 0u));
1884       }
1885       break;
1886    }
1887    // constants
1888    case nir_intrinsic_load_subgroup_size: {
1889       LValues &newDefs = convert(&insn->dest);
1890       loadImm(newDefs[0], 32u);
1891       break;
1892    }
1893    case nir_intrinsic_vote_all:
1894    case nir_intrinsic_vote_any:
1895    case nir_intrinsic_vote_ieq: {
1896       LValues &newDefs = convert(&insn->dest);
1897       Value *pred = getScratch(1, FILE_PREDICATE);
1898       mkCmp(OP_SET, CC_NE, TYPE_U32, pred, TYPE_U32, getSrc(&insn->src[0], 0), zero);
1899       mkOp1(OP_VOTE, TYPE_U32, pred, pred)->subOp = getSubOp(op);
1900       mkCvt(OP_CVT, TYPE_U32, newDefs[0], TYPE_U8, pred);
1901       break;
1902    }
1903    case nir_intrinsic_ballot: {
1904       LValues &newDefs = convert(&insn->dest);
1905       Value *pred = getSSA(1, FILE_PREDICATE);
1906       mkCmp(OP_SET, CC_NE, TYPE_U32, pred, TYPE_U32, getSrc(&insn->src[0], 0), zero);
1907       mkOp1(OP_VOTE, TYPE_U32, newDefs[0], pred)->subOp = NV50_IR_SUBOP_VOTE_ANY;
1908       break;
1909    }
1910    case nir_intrinsic_read_first_invocation:
1911    case nir_intrinsic_read_invocation: {
1912       LValues &newDefs = convert(&insn->dest);
1913       const DataType dType = getDType(insn);
1914       Value *tmp = getScratch();
1915
1916       if (op == nir_intrinsic_read_first_invocation) {
1917          mkOp1(OP_VOTE, TYPE_U32, tmp, mkImm(1))->subOp = NV50_IR_SUBOP_VOTE_ANY;
1918          mkOp1(OP_BREV, TYPE_U32, tmp, tmp);
1919          mkOp1(OP_BFIND, TYPE_U32, tmp, tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT;
1920       } else
1921          tmp = getSrc(&insn->src[1], 0);
1922
1923       for (uint8_t i = 0; i < dest_components; ++i) {
1924          mkOp3(OP_SHFL, dType, newDefs[i], getSrc(&insn->src[0], i), tmp, mkImm(0x1f))
1925             ->subOp = NV50_IR_SUBOP_SHFL_IDX;
1926       }
1927       break;
1928    }
1929    case nir_intrinsic_load_per_vertex_input: {
1930       const DataType dType = getDType(insn);
1931       LValues &newDefs = convert(&insn->dest);
1932       Value *indirectVertex;
1933       Value *indirectOffset;
1934       uint32_t baseVertex = getIndirect(&insn->src[0], 0, indirectVertex);
1935       uint32_t idx = getIndirect(insn, 1, 0, indirectOffset);
1936
1937       Value *vtxBase = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1938                               mkImm(baseVertex), indirectVertex);
1939       for (uint8_t i = 0u; i < dest_components; ++i) {
1940          uint32_t address = getSlotAddress(insn, idx, i);
1941          loadFrom(FILE_SHADER_INPUT, 0, dType, newDefs[i], address, 0,
1942                   indirectOffset, vtxBase, info->in[idx].patch);
1943       }
1944       break;
1945    }
1946    case nir_intrinsic_load_per_vertex_output: {
1947       const DataType dType = getDType(insn);
1948       LValues &newDefs = convert(&insn->dest);
1949       Value *indirectVertex;
1950       Value *indirectOffset;
1951       uint32_t baseVertex = getIndirect(&insn->src[0], 0, indirectVertex);
1952       uint32_t idx = getIndirect(insn, 1, 0, indirectOffset);
1953       Value *vtxBase = NULL;
1954
1955       if (indirectVertex)
1956          vtxBase = indirectVertex;
1957       else
1958          vtxBase = loadImm(NULL, baseVertex);
1959
1960       vtxBase = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, FILE_ADDRESS), outBase, vtxBase);
1961
1962       for (uint8_t i = 0u; i < dest_components; ++i) {
1963          uint32_t address = getSlotAddress(insn, idx, i);
1964          loadFrom(FILE_SHADER_OUTPUT, 0, dType, newDefs[i], address, 0,
1965                   indirectOffset, vtxBase, info->in[idx].patch);
1966       }
1967       break;
1968    }
1969    case nir_intrinsic_emit_vertex:
1970       if (info->io.genUserClip > 0)
1971          handleUserClipPlanes();
1972       // fallthrough
1973    case nir_intrinsic_end_primitive: {
1974       uint32_t idx = nir_intrinsic_stream_id(insn);
1975       mkOp1(getOperation(op), TYPE_U32, NULL, mkImm(idx))->fixed = 1;
1976       break;
1977    }
1978    case nir_intrinsic_load_ubo: {
1979       const DataType dType = getDType(insn);
1980       LValues &newDefs = convert(&insn->dest);
1981       Value *indirectIndex;
1982       Value *indirectOffset;
1983       uint32_t index = getIndirect(&insn->src[0], 0, indirectIndex) + 1;
1984       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
1985
1986       for (uint8_t i = 0u; i < dest_components; ++i) {
1987          loadFrom(FILE_MEMORY_CONST, index, dType, newDefs[i], offset, i,
1988                   indirectOffset, indirectIndex);
1989       }
1990       break;
1991    }
1992    case nir_intrinsic_get_buffer_size: {
1993       LValues &newDefs = convert(&insn->dest);
1994       const DataType dType = getDType(insn);
1995       Value *indirectBuffer;
1996       uint32_t buffer = getIndirect(&insn->src[0], 0, indirectBuffer);
1997
1998       Symbol *sym = mkSymbol(FILE_MEMORY_BUFFER, buffer, dType, 0);
1999       mkOp1(OP_BUFQ, dType, newDefs[0], sym)->setIndirect(0, 0, indirectBuffer);
2000       break;
2001    }
2002    case nir_intrinsic_store_ssbo: {
2003       DataType sType = getSType(insn->src[0], false, false);
2004       Value *indirectBuffer;
2005       Value *indirectOffset;
2006       uint32_t buffer = getIndirect(&insn->src[1], 0, indirectBuffer);
2007       uint32_t offset = getIndirect(&insn->src[2], 0, indirectOffset);
2008
2009       for (uint8_t i = 0u; i < nir_intrinsic_src_components(insn, 0); ++i) {
2010          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
2011             continue;
2012          Symbol *sym = mkSymbol(FILE_MEMORY_BUFFER, buffer, sType,
2013                                 offset + i * typeSizeof(sType));
2014          mkStore(OP_STORE, sType, sym, indirectOffset, getSrc(&insn->src[0], i))
2015             ->setIndirect(0, 1, indirectBuffer);
2016       }
2017       info->io.globalAccess |= 0x2;
2018       break;
2019    }
2020    case nir_intrinsic_load_ssbo: {
2021       const DataType dType = getDType(insn);
2022       LValues &newDefs = convert(&insn->dest);
2023       Value *indirectBuffer;
2024       Value *indirectOffset;
2025       uint32_t buffer = getIndirect(&insn->src[0], 0, indirectBuffer);
2026       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2027
2028       for (uint8_t i = 0u; i < dest_components; ++i)
2029          loadFrom(FILE_MEMORY_BUFFER, buffer, dType, newDefs[i], offset, i,
2030                   indirectOffset, indirectBuffer);
2031
2032       info->io.globalAccess |= 0x1;
2033       break;
2034    }
2035    case nir_intrinsic_shared_atomic_add:
2036    case nir_intrinsic_shared_atomic_and:
2037    case nir_intrinsic_shared_atomic_comp_swap:
2038    case nir_intrinsic_shared_atomic_exchange:
2039    case nir_intrinsic_shared_atomic_or:
2040    case nir_intrinsic_shared_atomic_imax:
2041    case nir_intrinsic_shared_atomic_imin:
2042    case nir_intrinsic_shared_atomic_umax:
2043    case nir_intrinsic_shared_atomic_umin:
2044    case nir_intrinsic_shared_atomic_xor: {
2045       const DataType dType = getDType(insn);
2046       LValues &newDefs = convert(&insn->dest);
2047       Value *indirectOffset;
2048       uint32_t offset = getIndirect(&insn->src[0], 0, indirectOffset);
2049       Symbol *sym = mkSymbol(FILE_MEMORY_SHARED, 0, dType, offset);
2050       Instruction *atom = mkOp2(OP_ATOM, dType, newDefs[0], sym, getSrc(&insn->src[1], 0));
2051       if (op == nir_intrinsic_shared_atomic_comp_swap)
2052          atom->setSrc(2, getSrc(&insn->src[2], 0));
2053       atom->setIndirect(0, 0, indirectOffset);
2054       atom->subOp = getSubOp(op);
2055       break;
2056    }
2057    case nir_intrinsic_ssbo_atomic_add:
2058    case nir_intrinsic_ssbo_atomic_and:
2059    case nir_intrinsic_ssbo_atomic_comp_swap:
2060    case nir_intrinsic_ssbo_atomic_exchange:
2061    case nir_intrinsic_ssbo_atomic_or:
2062    case nir_intrinsic_ssbo_atomic_imax:
2063    case nir_intrinsic_ssbo_atomic_imin:
2064    case nir_intrinsic_ssbo_atomic_umax:
2065    case nir_intrinsic_ssbo_atomic_umin:
2066    case nir_intrinsic_ssbo_atomic_xor: {
2067       const DataType dType = getDType(insn);
2068       LValues &newDefs = convert(&insn->dest);
2069       Value *indirectBuffer;
2070       Value *indirectOffset;
2071       uint32_t buffer = getIndirect(&insn->src[0], 0, indirectBuffer);
2072       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2073
2074       Symbol *sym = mkSymbol(FILE_MEMORY_BUFFER, buffer, dType, offset);
2075       Instruction *atom = mkOp2(OP_ATOM, dType, newDefs[0], sym,
2076                                 getSrc(&insn->src[2], 0));
2077       if (op == nir_intrinsic_ssbo_atomic_comp_swap)
2078          atom->setSrc(2, getSrc(&insn->src[3], 0));
2079       atom->setIndirect(0, 0, indirectOffset);
2080       atom->setIndirect(0, 1, indirectBuffer);
2081       atom->subOp = getSubOp(op);
2082
2083       info->io.globalAccess |= 0x2;
2084       break;
2085    }
2086    case nir_intrinsic_global_atomic_add:
2087    case nir_intrinsic_global_atomic_and:
2088    case nir_intrinsic_global_atomic_comp_swap:
2089    case nir_intrinsic_global_atomic_exchange:
2090    case nir_intrinsic_global_atomic_or:
2091    case nir_intrinsic_global_atomic_imax:
2092    case nir_intrinsic_global_atomic_imin:
2093    case nir_intrinsic_global_atomic_umax:
2094    case nir_intrinsic_global_atomic_umin:
2095    case nir_intrinsic_global_atomic_xor: {
2096       const DataType dType = getDType(insn);
2097       LValues &newDefs = convert(&insn->dest);
2098       Value *address;
2099       uint32_t offset = getIndirect(&insn->src[0], 0, address);
2100
2101       Symbol *sym = mkSymbol(FILE_MEMORY_GLOBAL, 0, dType, offset);
2102       Instruction *atom =
2103          mkOp2(OP_ATOM, dType, newDefs[0], sym, getSrc(&insn->src[1], 0));
2104       atom->setIndirect(0, 0, address);
2105       atom->subOp = getSubOp(op);
2106
2107       info->io.globalAccess |= 0x2;
2108       break;
2109    }
2110    case nir_intrinsic_bindless_image_atomic_add:
2111    case nir_intrinsic_bindless_image_atomic_and:
2112    case nir_intrinsic_bindless_image_atomic_comp_swap:
2113    case nir_intrinsic_bindless_image_atomic_exchange:
2114    case nir_intrinsic_bindless_image_atomic_imax:
2115    case nir_intrinsic_bindless_image_atomic_umax:
2116    case nir_intrinsic_bindless_image_atomic_imin:
2117    case nir_intrinsic_bindless_image_atomic_umin:
2118    case nir_intrinsic_bindless_image_atomic_or:
2119    case nir_intrinsic_bindless_image_atomic_xor:
2120    case nir_intrinsic_bindless_image_load:
2121    case nir_intrinsic_bindless_image_samples:
2122    case nir_intrinsic_bindless_image_size:
2123    case nir_intrinsic_bindless_image_store: {
2124       std::vector<Value*> srcs, defs;
2125       Value *indirect = getSrc(&insn->src[0], 0);
2126       DataType ty;
2127
2128       uint32_t mask = 0;
2129       TexInstruction::Target target =
2130          convert(nir_intrinsic_image_dim(insn), !!nir_intrinsic_image_array(insn), false);
2131       unsigned int argCount = getNIRArgCount(target);
2132       uint16_t location = 0;
2133
2134       if (opInfo.has_dest) {
2135          LValues &newDefs = convert(&insn->dest);
2136          for (uint8_t i = 0u; i < newDefs.size(); ++i) {
2137             defs.push_back(newDefs[i]);
2138             mask |= 1 << i;
2139          }
2140       }
2141
2142       switch (op) {
2143       case nir_intrinsic_bindless_image_atomic_add:
2144       case nir_intrinsic_bindless_image_atomic_and:
2145       case nir_intrinsic_bindless_image_atomic_comp_swap:
2146       case nir_intrinsic_bindless_image_atomic_exchange:
2147       case nir_intrinsic_bindless_image_atomic_imax:
2148       case nir_intrinsic_bindless_image_atomic_umax:
2149       case nir_intrinsic_bindless_image_atomic_imin:
2150       case nir_intrinsic_bindless_image_atomic_umin:
2151       case nir_intrinsic_bindless_image_atomic_or:
2152       case nir_intrinsic_bindless_image_atomic_xor:
2153          ty = getDType(insn);
2154          mask = 0x1;
2155          info->io.globalAccess |= 0x2;
2156          break;
2157       case nir_intrinsic_bindless_image_load:
2158          ty = TYPE_U32;
2159          info->io.globalAccess |= 0x1;
2160          break;
2161       case nir_intrinsic_bindless_image_store:
2162          ty = TYPE_U32;
2163          mask = 0xf;
2164          info->io.globalAccess |= 0x2;
2165          break;
2166       case nir_intrinsic_bindless_image_samples:
2167          mask = 0x8;
2168          ty = TYPE_U32;
2169          break;
2170       case nir_intrinsic_bindless_image_size:
2171          ty = TYPE_U32;
2172          break;
2173       default:
2174          unreachable("unhandled image opcode");
2175          break;
2176       }
2177
2178       // coords
2179       if (opInfo.num_srcs >= 2)
2180          for (unsigned int i = 0u; i < argCount; ++i)
2181             srcs.push_back(getSrc(&insn->src[1], i));
2182
2183       // the sampler is just another src added after coords
2184       if (opInfo.num_srcs >= 3 && target.isMS())
2185          srcs.push_back(getSrc(&insn->src[2], 0));
2186
2187       if (opInfo.num_srcs >= 4) {
2188          unsigned components = opInfo.src_components[3] ? opInfo.src_components[3] : insn->num_components;
2189          for (uint8_t i = 0u; i < components; ++i)
2190             srcs.push_back(getSrc(&insn->src[3], i));
2191       }
2192
2193       if (opInfo.num_srcs >= 5)
2194          // 1 for aotmic swap
2195          for (uint8_t i = 0u; i < opInfo.src_components[4]; ++i)
2196             srcs.push_back(getSrc(&insn->src[4], i));
2197
2198       TexInstruction *texi = mkTex(getOperation(op), target.getEnum(), location, 0, defs, srcs);
2199       texi->tex.bindless = false;
2200       texi->tex.format = nv50_ir::TexInstruction::translateImgFormat(nir_intrinsic_format(insn));
2201       texi->tex.mask = mask;
2202       texi->tex.bindless = true;
2203       texi->cache = convert(nir_intrinsic_access(insn));
2204       texi->setType(ty);
2205       texi->subOp = getSubOp(op);
2206
2207       if (indirect)
2208          texi->setIndirectR(indirect);
2209
2210       break;
2211    }
2212    case nir_intrinsic_image_deref_atomic_add:
2213    case nir_intrinsic_image_deref_atomic_and:
2214    case nir_intrinsic_image_deref_atomic_comp_swap:
2215    case nir_intrinsic_image_deref_atomic_exchange:
2216    case nir_intrinsic_image_deref_atomic_imax:
2217    case nir_intrinsic_image_deref_atomic_umax:
2218    case nir_intrinsic_image_deref_atomic_imin:
2219    case nir_intrinsic_image_deref_atomic_umin:
2220    case nir_intrinsic_image_deref_atomic_or:
2221    case nir_intrinsic_image_deref_atomic_xor:
2222    case nir_intrinsic_image_deref_load:
2223    case nir_intrinsic_image_deref_samples:
2224    case nir_intrinsic_image_deref_size:
2225    case nir_intrinsic_image_deref_store: {
2226       const nir_variable *tex;
2227       std::vector<Value*> srcs, defs;
2228       Value *indirect;
2229       DataType ty;
2230
2231       uint32_t mask = 0;
2232       nir_deref_instr *deref = nir_src_as_deref(insn->src[0]);
2233       const glsl_type *type = deref->type;
2234       TexInstruction::Target target =
2235          convert((glsl_sampler_dim)type->sampler_dimensionality,
2236                  type->sampler_array, type->sampler_shadow);
2237       unsigned int argCount = getNIRArgCount(target);
2238       uint16_t location = handleDeref(deref, indirect, tex);
2239
2240       if (opInfo.has_dest) {
2241          LValues &newDefs = convert(&insn->dest);
2242          for (uint8_t i = 0u; i < newDefs.size(); ++i) {
2243             defs.push_back(newDefs[i]);
2244             mask |= 1 << i;
2245          }
2246       }
2247
2248       switch (op) {
2249       case nir_intrinsic_image_deref_atomic_add:
2250       case nir_intrinsic_image_deref_atomic_and:
2251       case nir_intrinsic_image_deref_atomic_comp_swap:
2252       case nir_intrinsic_image_deref_atomic_exchange:
2253       case nir_intrinsic_image_deref_atomic_imax:
2254       case nir_intrinsic_image_deref_atomic_umax:
2255       case nir_intrinsic_image_deref_atomic_imin:
2256       case nir_intrinsic_image_deref_atomic_umin:
2257       case nir_intrinsic_image_deref_atomic_or:
2258       case nir_intrinsic_image_deref_atomic_xor:
2259          ty = getDType(insn);
2260          mask = 0x1;
2261          info->io.globalAccess |= 0x2;
2262          break;
2263       case nir_intrinsic_image_deref_load:
2264          ty = TYPE_U32;
2265          info->io.globalAccess |= 0x1;
2266          break;
2267       case nir_intrinsic_image_deref_store:
2268          ty = TYPE_U32;
2269          mask = 0xf;
2270          info->io.globalAccess |= 0x2;
2271          break;
2272       case nir_intrinsic_image_deref_samples:
2273          mask = 0x8;
2274          ty = TYPE_U32;
2275          break;
2276       case nir_intrinsic_image_deref_size:
2277          ty = TYPE_U32;
2278          break;
2279       default:
2280          unreachable("unhandled image opcode");
2281          break;
2282       }
2283
2284       // coords
2285       if (opInfo.num_srcs >= 2)
2286          for (unsigned int i = 0u; i < argCount; ++i)
2287             srcs.push_back(getSrc(&insn->src[1], i));
2288
2289       // the sampler is just another src added after coords
2290       if (opInfo.num_srcs >= 3 && target.isMS())
2291          srcs.push_back(getSrc(&insn->src[2], 0));
2292
2293       if (opInfo.num_srcs >= 4) {
2294          unsigned components = opInfo.src_components[3] ? opInfo.src_components[3] : insn->num_components;
2295          for (uint8_t i = 0u; i < components; ++i)
2296             srcs.push_back(getSrc(&insn->src[3], i));
2297       }
2298
2299       if (opInfo.num_srcs >= 5)
2300          // 1 for aotmic swap
2301          for (uint8_t i = 0u; i < opInfo.src_components[4]; ++i)
2302             srcs.push_back(getSrc(&insn->src[4], i));
2303
2304       TexInstruction *texi = mkTex(getOperation(op), target.getEnum(), location, 0, defs, srcs);
2305       texi->tex.bindless = false;
2306       texi->tex.format = nv50_ir::TexInstruction::translateImgFormat(tex->data.image.format);
2307       texi->tex.mask = mask;
2308       texi->cache = getCacheModeFromVar(tex);
2309       texi->setType(ty);
2310       texi->subOp = getSubOp(op);
2311
2312       if (indirect)
2313          texi->setIndirectR(indirect);
2314
2315       break;
2316    }
2317    case nir_intrinsic_store_shared: {
2318       DataType sType = getSType(insn->src[0], false, false);
2319       Value *indirectOffset;
2320       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2321
2322       for (uint8_t i = 0u; i < nir_intrinsic_src_components(insn, 0); ++i) {
2323          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
2324             continue;
2325          Symbol *sym = mkSymbol(FILE_MEMORY_SHARED, 0, sType, offset + i * typeSizeof(sType));
2326          mkStore(OP_STORE, sType, sym, indirectOffset, getSrc(&insn->src[0], i));
2327       }
2328       break;
2329    }
2330    case nir_intrinsic_load_shared: {
2331       const DataType dType = getDType(insn);
2332       LValues &newDefs = convert(&insn->dest);
2333       Value *indirectOffset;
2334       uint32_t offset = getIndirect(&insn->src[0], 0, indirectOffset);
2335
2336       for (uint8_t i = 0u; i < dest_components; ++i)
2337          loadFrom(FILE_MEMORY_SHARED, 0, dType, newDefs[i], offset, i, indirectOffset);
2338
2339       break;
2340    }
2341    case nir_intrinsic_control_barrier: {
2342       // TODO: add flag to shader_info
2343       info->numBarriers = 1;
2344       Instruction *bar = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2345       bar->fixed = 1;
2346       bar->subOp = NV50_IR_SUBOP_BAR_SYNC;
2347       break;
2348    }
2349    case nir_intrinsic_group_memory_barrier:
2350    case nir_intrinsic_memory_barrier:
2351    case nir_intrinsic_memory_barrier_buffer:
2352    case nir_intrinsic_memory_barrier_image:
2353    case nir_intrinsic_memory_barrier_shared: {
2354       Instruction *bar = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2355       bar->fixed = 1;
2356       bar->subOp = getSubOp(op);
2357       break;
2358    }
2359    case nir_intrinsic_memory_barrier_tcs_patch:
2360       break;
2361    case nir_intrinsic_shader_clock: {
2362       const DataType dType = getDType(insn);
2363       LValues &newDefs = convert(&insn->dest);
2364
2365       loadImm(newDefs[0], 0u);
2366       mkOp1(OP_RDSV, dType, newDefs[1], mkSysVal(SV_CLOCK, 0))->fixed = 1;
2367       break;
2368    }
2369    case nir_intrinsic_load_global: {
2370       const DataType dType = getDType(insn);
2371       LValues &newDefs = convert(&insn->dest);
2372       Value *indirectOffset;
2373       uint32_t offset = getIndirect(&insn->src[0], 0, indirectOffset);
2374
2375       for (auto i = 0u; i < dest_components; ++i)
2376          loadFrom(FILE_MEMORY_GLOBAL, 0, dType, newDefs[i], offset, i, indirectOffset);
2377
2378       info->io.globalAccess |= 0x1;
2379       break;
2380    }
2381    case nir_intrinsic_store_global: {
2382       DataType sType = getSType(insn->src[0], false, false);
2383
2384       for (auto i = 0u; i < nir_intrinsic_src_components(insn, 0); ++i) {
2385          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
2386             continue;
2387          if (typeSizeof(sType) == 8) {
2388             Value *split[2];
2389             mkSplit(split, 4, getSrc(&insn->src[0], i));
2390
2391             Symbol *sym = mkSymbol(FILE_MEMORY_GLOBAL, 0, TYPE_U32, i * typeSizeof(sType));
2392             mkStore(OP_STORE, TYPE_U32, sym, getSrc(&insn->src[1], 0), split[0]);
2393
2394             sym = mkSymbol(FILE_MEMORY_GLOBAL, 0, TYPE_U32, i * typeSizeof(sType) + 4);
2395             mkStore(OP_STORE, TYPE_U32, sym, getSrc(&insn->src[1], 0), split[1]);
2396          } else {
2397             Symbol *sym = mkSymbol(FILE_MEMORY_GLOBAL, 0, sType, i * typeSizeof(sType));
2398             mkStore(OP_STORE, sType, sym, getSrc(&insn->src[1], 0), getSrc(&insn->src[0], i));
2399          }
2400       }
2401
2402       info->io.globalAccess |= 0x2;
2403       break;
2404    }
2405    default:
2406       ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos[op].name);
2407       return false;
2408    }
2409
2410    return true;
2411 }
2412
2413 bool
2414 Converter::visit(nir_jump_instr *insn)
2415 {
2416    switch (insn->type) {
2417    case nir_jump_return:
2418       // TODO: this only works in the main function
2419       mkFlow(OP_BRA, exit, CC_ALWAYS, NULL);
2420       bb->cfg.attach(&exit->cfg, Graph::Edge::CROSS);
2421       break;
2422    case nir_jump_break:
2423    case nir_jump_continue: {
2424       bool isBreak = insn->type == nir_jump_break;
2425       nir_block *block = insn->instr.block;
2426       assert(!block->successors[1]);
2427       BasicBlock *target = convert(block->successors[0]);
2428       mkFlow(isBreak ? OP_BREAK : OP_CONT, target, CC_ALWAYS, NULL);
2429       bb->cfg.attach(&target->cfg, isBreak ? Graph::Edge::CROSS : Graph::Edge::BACK);
2430       break;
2431    }
2432    default:
2433       ERROR("unknown nir_jump_type %u\n", insn->type);
2434       return false;
2435    }
2436
2437    return true;
2438 }
2439
2440 Value*
2441 Converter::convert(nir_load_const_instr *insn, uint8_t idx)
2442 {
2443    Value *val;
2444
2445    if (immInsertPos)
2446       setPosition(immInsertPos, true);
2447    else
2448       setPosition(bb, false);
2449
2450    switch (insn->def.bit_size) {
2451    case 64:
2452       val = loadImm(getSSA(8), insn->value[idx].u64);
2453       break;
2454    case 32:
2455       val = loadImm(getSSA(4), insn->value[idx].u32);
2456       break;
2457    case 16:
2458       val = loadImm(getSSA(2), insn->value[idx].u16);
2459       break;
2460    case 8:
2461       val = loadImm(getSSA(1), insn->value[idx].u8);
2462       break;
2463    default:
2464       unreachable("unhandled bit size!\n");
2465    }
2466    setPosition(bb, true);
2467    return val;
2468 }
2469
2470 bool
2471 Converter::visit(nir_load_const_instr *insn)
2472 {
2473    assert(insn->def.bit_size <= 64);
2474    immediates[insn->def.index] = insn;
2475    return true;
2476 }
2477
2478 #define DEFAULT_CHECKS \
2479       if (insn->dest.dest.ssa.num_components > 1) { \
2480          ERROR("nir_alu_instr only supported with 1 component!\n"); \
2481          return false; \
2482       } \
2483       if (insn->dest.write_mask != 1) { \
2484          ERROR("nir_alu_instr only with write_mask of 1 supported!\n"); \
2485          return false; \
2486       }
2487 bool
2488 Converter::visit(nir_alu_instr *insn)
2489 {
2490    const nir_op op = insn->op;
2491    const nir_op_info &info = nir_op_infos[op];
2492    DataType dType = getDType(insn);
2493    const std::vector<DataType> sTypes = getSTypes(insn);
2494
2495    Instruction *oldPos = this->bb->getExit();
2496
2497    switch (op) {
2498    case nir_op_fabs:
2499    case nir_op_iabs:
2500    case nir_op_fadd:
2501    case nir_op_iadd:
2502    case nir_op_iand:
2503    case nir_op_fceil:
2504    case nir_op_fcos:
2505    case nir_op_fddx:
2506    case nir_op_fddx_coarse:
2507    case nir_op_fddx_fine:
2508    case nir_op_fddy:
2509    case nir_op_fddy_coarse:
2510    case nir_op_fddy_fine:
2511    case nir_op_fdiv:
2512    case nir_op_idiv:
2513    case nir_op_udiv:
2514    case nir_op_fexp2:
2515    case nir_op_ffloor:
2516    case nir_op_ffma:
2517    case nir_op_flog2:
2518    case nir_op_fmax:
2519    case nir_op_imax:
2520    case nir_op_umax:
2521    case nir_op_fmin:
2522    case nir_op_imin:
2523    case nir_op_umin:
2524    case nir_op_fmod:
2525    case nir_op_imod:
2526    case nir_op_umod:
2527    case nir_op_fmul:
2528    case nir_op_imul:
2529    case nir_op_imul_high:
2530    case nir_op_umul_high:
2531    case nir_op_fneg:
2532    case nir_op_ineg:
2533    case nir_op_inot:
2534    case nir_op_ior:
2535    case nir_op_pack_64_2x32_split:
2536    case nir_op_fpow:
2537    case nir_op_frcp:
2538    case nir_op_frem:
2539    case nir_op_irem:
2540    case nir_op_frsq:
2541    case nir_op_fsat:
2542    case nir_op_ishr:
2543    case nir_op_ushr:
2544    case nir_op_fsin:
2545    case nir_op_fsqrt:
2546    case nir_op_ftrunc:
2547    case nir_op_ishl:
2548    case nir_op_ixor: {
2549       DEFAULT_CHECKS;
2550       LValues &newDefs = convert(&insn->dest);
2551       operation preOp = preOperationNeeded(op);
2552       if (preOp != OP_NOP) {
2553          assert(info.num_inputs < 2);
2554          Value *tmp = getSSA(typeSizeof(dType));
2555          Instruction *i0 = mkOp(preOp, dType, tmp);
2556          Instruction *i1 = mkOp(getOperation(op), dType, newDefs[0]);
2557          if (info.num_inputs) {
2558             i0->setSrc(0, getSrc(&insn->src[0]));
2559             i1->setSrc(0, tmp);
2560          }
2561          i1->subOp = getSubOp(op);
2562       } else {
2563          Instruction *i = mkOp(getOperation(op), dType, newDefs[0]);
2564          for (unsigned s = 0u; s < info.num_inputs; ++s) {
2565             i->setSrc(s, getSrc(&insn->src[s]));
2566          }
2567          i->subOp = getSubOp(op);
2568       }
2569       break;
2570    }
2571    case nir_op_ifind_msb:
2572    case nir_op_ufind_msb: {
2573       DEFAULT_CHECKS;
2574       LValues &newDefs = convert(&insn->dest);
2575       dType = sTypes[0];
2576       mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0]));
2577       break;
2578    }
2579    case nir_op_fround_even: {
2580       DEFAULT_CHECKS;
2581       LValues &newDefs = convert(&insn->dest);
2582       mkCvt(OP_CVT, dType, newDefs[0], dType, getSrc(&insn->src[0]))->rnd = ROUND_NI;
2583       break;
2584    }
2585    // convert instructions
2586    case nir_op_f2f32:
2587    case nir_op_f2i32:
2588    case nir_op_f2u32:
2589    case nir_op_i2f32:
2590    case nir_op_i2i32:
2591    case nir_op_u2f32:
2592    case nir_op_u2u32:
2593    case nir_op_f2f64:
2594    case nir_op_f2i64:
2595    case nir_op_f2u64:
2596    case nir_op_i2f64:
2597    case nir_op_i2i64:
2598    case nir_op_u2f64:
2599    case nir_op_u2u64: {
2600       DEFAULT_CHECKS;
2601       LValues &newDefs = convert(&insn->dest);
2602       Instruction *i = mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0]));
2603       if (op == nir_op_f2i32 || op == nir_op_f2i64 || op == nir_op_f2u32 || op == nir_op_f2u64)
2604          i->rnd = ROUND_Z;
2605       i->sType = sTypes[0];
2606       break;
2607    }
2608    // compare instructions
2609    case nir_op_feq32:
2610    case nir_op_ieq32:
2611    case nir_op_fge32:
2612    case nir_op_ige32:
2613    case nir_op_uge32:
2614    case nir_op_flt32:
2615    case nir_op_ilt32:
2616    case nir_op_ult32:
2617    case nir_op_fne32:
2618    case nir_op_ine32: {
2619       DEFAULT_CHECKS;
2620       LValues &newDefs = convert(&insn->dest);
2621       Instruction *i = mkCmp(getOperation(op),
2622                              getCondCode(op),
2623                              dType,
2624                              newDefs[0],
2625                              dType,
2626                              getSrc(&insn->src[0]),
2627                              getSrc(&insn->src[1]));
2628       if (info.num_inputs == 3)
2629          i->setSrc(2, getSrc(&insn->src[2]));
2630       i->sType = sTypes[0];
2631       break;
2632    }
2633    // those are weird ALU ops and need special handling, because
2634    //   1. they are always componend based
2635    //   2. they basically just merge multiple values into one data type
2636    case nir_op_mov:
2637       if (!insn->dest.dest.is_ssa && insn->dest.dest.reg.reg->num_array_elems) {
2638          nir_reg_dest& reg = insn->dest.dest.reg;
2639          uint32_t goffset = regToLmemOffset[reg.reg->index];
2640          uint8_t comps = reg.reg->num_components;
2641          uint8_t size = reg.reg->bit_size / 8;
2642          uint8_t csize = 4 * size; // TODO after fixing MemoryOpts: comps * size;
2643          uint32_t aoffset = csize * reg.base_offset;
2644          Value *indirect = NULL;
2645
2646          if (reg.indirect)
2647             indirect = mkOp2v(OP_MUL, TYPE_U32, getSSA(4, FILE_ADDRESS),
2648                               getSrc(reg.indirect, 0), mkImm(csize));
2649
2650          for (uint8_t i = 0u; i < comps; ++i) {
2651             if (!((1u << i) & insn->dest.write_mask))
2652                continue;
2653
2654             Symbol *sym = mkSymbol(FILE_MEMORY_LOCAL, 0, dType, goffset + aoffset + i * size);
2655             mkStore(OP_STORE, dType, sym, indirect, getSrc(&insn->src[0], i));
2656          }
2657          break;
2658       } else if (!insn->src[0].src.is_ssa && insn->src[0].src.reg.reg->num_array_elems) {
2659          LValues &newDefs = convert(&insn->dest);
2660          nir_reg_src& reg = insn->src[0].src.reg;
2661          uint32_t goffset = regToLmemOffset[reg.reg->index];
2662          // uint8_t comps = reg.reg->num_components;
2663          uint8_t size = reg.reg->bit_size / 8;
2664          uint8_t csize = 4 * size; // TODO after fixing MemoryOpts: comps * size;
2665          uint32_t aoffset = csize * reg.base_offset;
2666          Value *indirect = NULL;
2667
2668          if (reg.indirect)
2669             indirect = mkOp2v(OP_MUL, TYPE_U32, getSSA(4, FILE_ADDRESS), getSrc(reg.indirect, 0), mkImm(csize));
2670
2671          for (uint8_t i = 0u; i < newDefs.size(); ++i)
2672             loadFrom(FILE_MEMORY_LOCAL, 0, dType, newDefs[i], goffset + aoffset, i, indirect);
2673
2674          break;
2675       } else {
2676          LValues &newDefs = convert(&insn->dest);
2677          for (LValues::size_type c = 0u; c < newDefs.size(); ++c) {
2678             mkMov(newDefs[c], getSrc(&insn->src[0], c), dType);
2679          }
2680       }
2681       break;
2682    case nir_op_vec2:
2683    case nir_op_vec3:
2684    case nir_op_vec4:
2685    case nir_op_vec8:
2686    case nir_op_vec16: {
2687       LValues &newDefs = convert(&insn->dest);
2688       for (LValues::size_type c = 0u; c < newDefs.size(); ++c) {
2689          mkMov(newDefs[c], getSrc(&insn->src[c]), dType);
2690       }
2691       break;
2692    }
2693    // (un)pack
2694    case nir_op_pack_64_2x32: {
2695       LValues &newDefs = convert(&insn->dest);
2696       Instruction *merge = mkOp(OP_MERGE, dType, newDefs[0]);
2697       merge->setSrc(0, getSrc(&insn->src[0], 0));
2698       merge->setSrc(1, getSrc(&insn->src[0], 1));
2699       break;
2700    }
2701    case nir_op_pack_half_2x16_split: {
2702       LValues &newDefs = convert(&insn->dest);
2703       Value *tmpH = getSSA();
2704       Value *tmpL = getSSA();
2705
2706       mkCvt(OP_CVT, TYPE_F16, tmpL, TYPE_F32, getSrc(&insn->src[0]));
2707       mkCvt(OP_CVT, TYPE_F16, tmpH, TYPE_F32, getSrc(&insn->src[1]));
2708       mkOp3(OP_INSBF, TYPE_U32, newDefs[0], tmpH, mkImm(0x1010), tmpL);
2709       break;
2710    }
2711    case nir_op_unpack_half_2x16_split_x:
2712    case nir_op_unpack_half_2x16_split_y: {
2713       LValues &newDefs = convert(&insn->dest);
2714       Instruction *cvt = mkCvt(OP_CVT, TYPE_F32, newDefs[0], TYPE_F16, getSrc(&insn->src[0]));
2715       if (op == nir_op_unpack_half_2x16_split_y)
2716          cvt->subOp = 1;
2717       break;
2718    }
2719    case nir_op_unpack_64_2x32: {
2720       LValues &newDefs = convert(&insn->dest);
2721       mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, newDefs[1]);
2722       break;
2723    }
2724    case nir_op_unpack_64_2x32_split_x: {
2725       LValues &newDefs = convert(&insn->dest);
2726       mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, getSSA());
2727       break;
2728    }
2729    case nir_op_unpack_64_2x32_split_y: {
2730       LValues &newDefs = convert(&insn->dest);
2731       mkOp1(OP_SPLIT, dType, getSSA(), getSrc(&insn->src[0]))->setDef(1, newDefs[0]);
2732       break;
2733    }
2734    // special instructions
2735    case nir_op_fsign:
2736    case nir_op_isign: {
2737       DEFAULT_CHECKS;
2738       DataType iType;
2739       if (::isFloatType(dType))
2740          iType = TYPE_F32;
2741       else
2742          iType = TYPE_S32;
2743
2744       LValues &newDefs = convert(&insn->dest);
2745       LValue *val0 = getScratch();
2746       LValue *val1 = getScratch();
2747       mkCmp(OP_SET, CC_GT, iType, val0, dType, getSrc(&insn->src[0]), zero);
2748       mkCmp(OP_SET, CC_LT, iType, val1, dType, getSrc(&insn->src[0]), zero);
2749
2750       if (dType == TYPE_F64) {
2751          mkOp2(OP_SUB, iType, val0, val0, val1);
2752          mkCvt(OP_CVT, TYPE_F64, newDefs[0], iType, val0);
2753       } else if (dType == TYPE_S64 || dType == TYPE_U64) {
2754          mkOp2(OP_SUB, iType, val0, val1, val0);
2755          mkOp2(OP_SHR, iType, val1, val0, loadImm(NULL, 31));
2756          mkOp2(OP_MERGE, dType, newDefs[0], val0, val1);
2757       } else if (::isFloatType(dType))
2758          mkOp2(OP_SUB, iType, newDefs[0], val0, val1);
2759       else
2760          mkOp2(OP_SUB, iType, newDefs[0], val1, val0);
2761       break;
2762    }
2763    case nir_op_fcsel:
2764    case nir_op_b32csel: {
2765       DEFAULT_CHECKS;
2766       LValues &newDefs = convert(&insn->dest);
2767       mkCmp(OP_SLCT, CC_NE, dType, newDefs[0], sTypes[0], getSrc(&insn->src[1]), getSrc(&insn->src[2]), getSrc(&insn->src[0]));
2768       break;
2769    }
2770    case nir_op_ibitfield_extract:
2771    case nir_op_ubitfield_extract: {
2772       DEFAULT_CHECKS;
2773       Value *tmp = getSSA();
2774       LValues &newDefs = convert(&insn->dest);
2775       mkOp3(OP_INSBF, dType, tmp, getSrc(&insn->src[2]), loadImm(NULL, 0x808), getSrc(&insn->src[1]));
2776       mkOp2(OP_EXTBF, dType, newDefs[0], getSrc(&insn->src[0]), tmp);
2777       break;
2778    }
2779    case nir_op_bfm: {
2780       DEFAULT_CHECKS;
2781       LValues &newDefs = convert(&insn->dest);
2782       mkOp2(OP_BMSK, dType, newDefs[0], getSrc(&insn->src[1]), getSrc(&insn->src[0]))->subOp = NV50_IR_SUBOP_BMSK_W;
2783       break;
2784    }
2785    case nir_op_bitfield_insert: {
2786       DEFAULT_CHECKS;
2787       LValues &newDefs = convert(&insn->dest);
2788       LValue *temp = getSSA();
2789       mkOp3(OP_INSBF, TYPE_U32, temp, getSrc(&insn->src[3]), mkImm(0x808), getSrc(&insn->src[2]));
2790       mkOp3(OP_INSBF, dType, newDefs[0], getSrc(&insn->src[1]), temp, getSrc(&insn->src[0]));
2791       break;
2792    }
2793    case nir_op_bit_count: {
2794       DEFAULT_CHECKS;
2795       LValues &newDefs = convert(&insn->dest);
2796       mkOp2(OP_POPCNT, dType, newDefs[0], getSrc(&insn->src[0]), getSrc(&insn->src[0]));
2797       break;
2798    }
2799    case nir_op_bitfield_reverse: {
2800       DEFAULT_CHECKS;
2801       LValues &newDefs = convert(&insn->dest);
2802       mkOp1(OP_BREV, TYPE_U32, newDefs[0], getSrc(&insn->src[0]));
2803       break;
2804    }
2805    case nir_op_find_lsb: {
2806       DEFAULT_CHECKS;
2807       LValues &newDefs = convert(&insn->dest);
2808       Value *tmp = getSSA();
2809       mkOp1(OP_BREV, TYPE_U32, tmp, getSrc(&insn->src[0]));
2810       mkOp1(OP_BFIND, TYPE_U32, newDefs[0], tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT;
2811       break;
2812    }
2813    // boolean conversions
2814    case nir_op_b2f32: {
2815       DEFAULT_CHECKS;
2816       LValues &newDefs = convert(&insn->dest);
2817       mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1.0f));
2818       break;
2819    }
2820    case nir_op_b2f64: {
2821       DEFAULT_CHECKS;
2822       LValues &newDefs = convert(&insn->dest);
2823       Value *tmp = getSSA(4);
2824       mkOp2(OP_AND, TYPE_U32, tmp, getSrc(&insn->src[0]), loadImm(NULL, 0x3ff00000));
2825       mkOp2(OP_MERGE, TYPE_U64, newDefs[0], loadImm(NULL, 0), tmp);
2826       break;
2827    }
2828    case nir_op_f2b32:
2829    case nir_op_i2b32: {
2830       DEFAULT_CHECKS;
2831       LValues &newDefs = convert(&insn->dest);
2832       Value *src1;
2833       if (typeSizeof(sTypes[0]) == 8) {
2834          src1 = loadImm(getSSA(8), 0.0);
2835       } else {
2836          src1 = zero;
2837       }
2838       CondCode cc = op == nir_op_f2b32 ? CC_NEU : CC_NE;
2839       mkCmp(OP_SET, cc, TYPE_U32, newDefs[0], sTypes[0], getSrc(&insn->src[0]), src1);
2840       break;
2841    }
2842    case nir_op_b2i32: {
2843       DEFAULT_CHECKS;
2844       LValues &newDefs = convert(&insn->dest);
2845       mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1));
2846       break;
2847    }
2848    case nir_op_b2i64: {
2849       DEFAULT_CHECKS;
2850       LValues &newDefs = convert(&insn->dest);
2851       LValue *def = getScratch();
2852       mkOp2(OP_AND, TYPE_U32, def, getSrc(&insn->src[0]), loadImm(NULL, 1));
2853       mkOp2(OP_MERGE, TYPE_S64, newDefs[0], def, loadImm(NULL, 0));
2854       break;
2855    }
2856    default:
2857       ERROR("unknown nir_op %s\n", info.name);
2858       return false;
2859    }
2860
2861    if (!oldPos) {
2862       oldPos = this->bb->getEntry();
2863       oldPos->precise = insn->exact;
2864    }
2865
2866    if (unlikely(!oldPos))
2867       return true;
2868
2869    while (oldPos->next) {
2870       oldPos = oldPos->next;
2871       oldPos->precise = insn->exact;
2872    }
2873    oldPos->saturate = insn->dest.saturate;
2874
2875    return true;
2876 }
2877 #undef DEFAULT_CHECKS
2878
2879 bool
2880 Converter::visit(nir_ssa_undef_instr *insn)
2881 {
2882    LValues &newDefs = convert(&insn->def);
2883    for (uint8_t i = 0u; i < insn->def.num_components; ++i) {
2884       mkOp(OP_NOP, TYPE_NONE, newDefs[i]);
2885    }
2886    return true;
2887 }
2888
2889 #define CASE_SAMPLER(ty) \
2890    case GLSL_SAMPLER_DIM_ ## ty : \
2891       if (isArray && !isShadow) \
2892          return TEX_TARGET_ ## ty ## _ARRAY; \
2893       else if (!isArray && isShadow) \
2894          return TEX_TARGET_## ty ## _SHADOW; \
2895       else if (isArray && isShadow) \
2896          return TEX_TARGET_## ty ## _ARRAY_SHADOW; \
2897       else \
2898          return TEX_TARGET_ ## ty
2899
2900 TexTarget
2901 Converter::convert(glsl_sampler_dim dim, bool isArray, bool isShadow)
2902 {
2903    switch (dim) {
2904    CASE_SAMPLER(1D);
2905    CASE_SAMPLER(2D);
2906    CASE_SAMPLER(CUBE);
2907    case GLSL_SAMPLER_DIM_3D:
2908       return TEX_TARGET_3D;
2909    case GLSL_SAMPLER_DIM_MS:
2910       if (isArray)
2911          return TEX_TARGET_2D_MS_ARRAY;
2912       return TEX_TARGET_2D_MS;
2913    case GLSL_SAMPLER_DIM_RECT:
2914       if (isShadow)
2915          return TEX_TARGET_RECT_SHADOW;
2916       return TEX_TARGET_RECT;
2917    case GLSL_SAMPLER_DIM_BUF:
2918       return TEX_TARGET_BUFFER;
2919    case GLSL_SAMPLER_DIM_EXTERNAL:
2920       return TEX_TARGET_2D;
2921    default:
2922       ERROR("unknown glsl_sampler_dim %u\n", dim);
2923       assert(false);
2924       return TEX_TARGET_COUNT;
2925    }
2926 }
2927 #undef CASE_SAMPLER
2928
2929 Value*
2930 Converter::applyProjection(Value *src, Value *proj)
2931 {
2932    if (!proj)
2933       return src;
2934    return mkOp2v(OP_MUL, TYPE_F32, getScratch(), src, proj);
2935 }
2936
2937 unsigned int
2938 Converter::getNIRArgCount(TexInstruction::Target& target)
2939 {
2940    unsigned int result = target.getArgCount();
2941    if (target.isCube() && target.isArray())
2942       result--;
2943    if (target.isMS())
2944       result--;
2945    return result;
2946 }
2947
2948 uint16_t
2949 Converter::handleDeref(nir_deref_instr *deref, Value * &indirect, const nir_variable * &tex)
2950 {
2951    typedef std::pair<uint32_t,Value*> DerefPair;
2952    std::list<DerefPair> derefs;
2953
2954    uint16_t result = 0;
2955    while (deref->deref_type != nir_deref_type_var) {
2956       switch (deref->deref_type) {
2957       case nir_deref_type_array: {
2958          Value *indirect;
2959          uint8_t size = type_size(deref->type, true);
2960          result += size * getIndirect(&deref->arr.index, 0, indirect);
2961
2962          if (indirect) {
2963             derefs.push_front(std::make_pair(size, indirect));
2964          }
2965
2966          break;
2967       }
2968       case nir_deref_type_struct: {
2969          result += nir_deref_instr_parent(deref)->type->struct_location_offset(deref->strct.index);
2970          break;
2971       }
2972       case nir_deref_type_var:
2973       default:
2974          unreachable("nir_deref_type_var reached in handleDeref!");
2975          break;
2976       }
2977       deref = nir_deref_instr_parent(deref);
2978    }
2979
2980    indirect = NULL;
2981    for (std::list<DerefPair>::const_iterator it = derefs.begin(); it != derefs.end(); ++it) {
2982       Value *offset = mkOp2v(OP_MUL, TYPE_U32, getSSA(), loadImm(getSSA(), it->first), it->second);
2983       if (indirect)
2984          indirect = mkOp2v(OP_ADD, TYPE_U32, getSSA(), indirect, offset);
2985       else
2986          indirect = offset;
2987    }
2988
2989    tex = nir_deref_instr_get_variable(deref);
2990    assert(tex);
2991
2992    return result + tex->data.driver_location;
2993 }
2994
2995 CacheMode
2996 Converter::convert(enum gl_access_qualifier access)
2997 {
2998    switch (access) {
2999    case ACCESS_VOLATILE:
3000       return CACHE_CV;
3001    case ACCESS_COHERENT:
3002       return CACHE_CG;
3003    default:
3004       return CACHE_CA;
3005    }
3006 }
3007
3008 CacheMode
3009 Converter::getCacheModeFromVar(const nir_variable *var)
3010 {
3011    return convert(var->data.access);
3012 }
3013
3014 bool
3015 Converter::visit(nir_tex_instr *insn)
3016 {
3017    switch (insn->op) {
3018    case nir_texop_lod:
3019    case nir_texop_query_levels:
3020    case nir_texop_tex:
3021    case nir_texop_texture_samples:
3022    case nir_texop_tg4:
3023    case nir_texop_txb:
3024    case nir_texop_txd:
3025    case nir_texop_txf:
3026    case nir_texop_txf_ms:
3027    case nir_texop_txl:
3028    case nir_texop_txs: {
3029       LValues &newDefs = convert(&insn->dest);
3030       std::vector<Value*> srcs;
3031       std::vector<Value*> defs;
3032       std::vector<nir_src*> offsets;
3033       uint8_t mask = 0;
3034       bool lz = false;
3035       Value *proj = NULL;
3036       TexInstruction::Target target = convert(insn->sampler_dim, insn->is_array, insn->is_shadow);
3037       operation op = getOperation(insn->op);
3038
3039       int r, s;
3040       int biasIdx = nir_tex_instr_src_index(insn, nir_tex_src_bias);
3041       int compIdx = nir_tex_instr_src_index(insn, nir_tex_src_comparator);
3042       int coordsIdx = nir_tex_instr_src_index(insn, nir_tex_src_coord);
3043       int ddxIdx = nir_tex_instr_src_index(insn, nir_tex_src_ddx);
3044       int ddyIdx = nir_tex_instr_src_index(insn, nir_tex_src_ddy);
3045       int msIdx = nir_tex_instr_src_index(insn, nir_tex_src_ms_index);
3046       int lodIdx = nir_tex_instr_src_index(insn, nir_tex_src_lod);
3047       int offsetIdx = nir_tex_instr_src_index(insn, nir_tex_src_offset);
3048       int projIdx = nir_tex_instr_src_index(insn, nir_tex_src_projector);
3049       int sampOffIdx = nir_tex_instr_src_index(insn, nir_tex_src_sampler_offset);
3050       int texOffIdx = nir_tex_instr_src_index(insn, nir_tex_src_texture_offset);
3051       int sampHandleIdx = nir_tex_instr_src_index(insn, nir_tex_src_sampler_handle);
3052       int texHandleIdx = nir_tex_instr_src_index(insn, nir_tex_src_texture_handle);
3053
3054       bool bindless = sampHandleIdx != -1 || texHandleIdx != -1;
3055       assert((sampHandleIdx != -1) == (texHandleIdx != -1));
3056
3057       if (projIdx != -1)
3058          proj = mkOp1v(OP_RCP, TYPE_F32, getScratch(), getSrc(&insn->src[projIdx].src, 0));
3059
3060       srcs.resize(insn->coord_components);
3061       for (uint8_t i = 0u; i < insn->coord_components; ++i)
3062          srcs[i] = applyProjection(getSrc(&insn->src[coordsIdx].src, i), proj);
3063
3064       // sometimes we get less args than target.getArgCount, but codegen expects the latter
3065       if (insn->coord_components) {
3066          uint32_t argCount = target.getArgCount();
3067
3068          if (target.isMS())
3069             argCount -= 1;
3070
3071          for (uint32_t i = 0u; i < (argCount - insn->coord_components); ++i)
3072             srcs.push_back(getSSA());
3073       }
3074
3075       if (insn->op == nir_texop_texture_samples)
3076          srcs.push_back(zero);
3077       else if (!insn->num_srcs)
3078          srcs.push_back(loadImm(NULL, 0));
3079       if (biasIdx != -1)
3080          srcs.push_back(getSrc(&insn->src[biasIdx].src, 0));
3081       if (lodIdx != -1)
3082          srcs.push_back(getSrc(&insn->src[lodIdx].src, 0));
3083       else if (op == OP_TXF)
3084          lz = true;
3085       if (msIdx != -1)
3086          srcs.push_back(getSrc(&insn->src[msIdx].src, 0));
3087       if (offsetIdx != -1)
3088          offsets.push_back(&insn->src[offsetIdx].src);
3089       if (compIdx != -1)
3090          srcs.push_back(applyProjection(getSrc(&insn->src[compIdx].src, 0), proj));
3091       if (texOffIdx != -1) {
3092          srcs.push_back(getSrc(&insn->src[texOffIdx].src, 0));
3093          texOffIdx = srcs.size() - 1;
3094       }
3095       if (sampOffIdx != -1) {
3096          srcs.push_back(getSrc(&insn->src[sampOffIdx].src, 0));
3097          sampOffIdx = srcs.size() - 1;
3098       }
3099       if (bindless) {
3100          // currently we use the lower bits
3101          Value *split[2];
3102          Value *handle = getSrc(&insn->src[sampHandleIdx].src, 0);
3103
3104          mkSplit(split, 4, handle);
3105
3106          srcs.push_back(split[0]);
3107          texOffIdx = srcs.size() - 1;
3108       }
3109
3110       r = bindless ? 0xff : insn->texture_index;
3111       s = bindless ? 0x1f : insn->sampler_index;
3112
3113       defs.resize(newDefs.size());
3114       for (uint8_t d = 0u; d < newDefs.size(); ++d) {
3115          defs[d] = newDefs[d];
3116          mask |= 1 << d;
3117       }
3118       if (target.isMS() || (op == OP_TEX && prog->getType() != Program::TYPE_FRAGMENT))
3119          lz = true;
3120
3121       TexInstruction *texi = mkTex(op, target.getEnum(), r, s, defs, srcs);
3122       texi->tex.levelZero = lz;
3123       texi->tex.mask = mask;
3124       texi->tex.bindless = bindless;
3125
3126       if (texOffIdx != -1)
3127          texi->tex.rIndirectSrc = texOffIdx;
3128       if (sampOffIdx != -1)
3129          texi->tex.sIndirectSrc = sampOffIdx;
3130
3131       switch (insn->op) {
3132       case nir_texop_tg4:
3133          if (!target.isShadow())
3134             texi->tex.gatherComp = insn->component;
3135          break;
3136       case nir_texop_txs:
3137          texi->tex.query = TXQ_DIMS;
3138          break;
3139       case nir_texop_texture_samples:
3140          texi->tex.mask = 0x4;
3141          texi->tex.query = TXQ_TYPE;
3142          break;
3143       case nir_texop_query_levels:
3144          texi->tex.mask = 0x8;
3145          texi->tex.query = TXQ_DIMS;
3146          break;
3147       default:
3148          break;
3149       }
3150
3151       texi->tex.useOffsets = offsets.size();
3152       if (texi->tex.useOffsets) {
3153          for (uint8_t s = 0; s < texi->tex.useOffsets; ++s) {
3154             for (uint32_t c = 0u; c < 3; ++c) {
3155                uint8_t s2 = std::min(c, target.getDim() - 1);
3156                texi->offset[s][c].set(getSrc(offsets[s], s2));
3157                texi->offset[s][c].setInsn(texi);
3158             }
3159          }
3160       }
3161
3162       if (op == OP_TXG && offsetIdx == -1) {
3163          if (nir_tex_instr_has_explicit_tg4_offsets(insn)) {
3164             texi->tex.useOffsets = 4;
3165             setPosition(texi, false);
3166             for (uint8_t i = 0; i < 4; ++i) {
3167                for (uint8_t j = 0; j < 2; ++j) {
3168                   texi->offset[i][j].set(loadImm(NULL, insn->tg4_offsets[i][j]));
3169                   texi->offset[i][j].setInsn(texi);
3170                }
3171             }
3172             setPosition(texi, true);
3173          }
3174       }
3175
3176       if (ddxIdx != -1 && ddyIdx != -1) {
3177          for (uint8_t c = 0u; c < target.getDim() + target.isCube(); ++c) {
3178             texi->dPdx[c].set(getSrc(&insn->src[ddxIdx].src, c));
3179             texi->dPdy[c].set(getSrc(&insn->src[ddyIdx].src, c));
3180          }
3181       }
3182
3183       break;
3184    }
3185    default:
3186       ERROR("unknown nir_texop %u\n", insn->op);
3187       return false;
3188    }
3189    return true;
3190 }
3191
3192 bool
3193 Converter::visit(nir_deref_instr *deref)
3194 {
3195    // we just ignore those, because images intrinsics are the only place where
3196    // we should end up with deref sources and those have to backtrack anyway
3197    // to get the nir_variable. This code just exists to handle some special
3198    // cases.
3199    switch (deref->deref_type) {
3200    case nir_deref_type_array:
3201    case nir_deref_type_struct:
3202    case nir_deref_type_var:
3203       break;
3204    default:
3205       ERROR("unknown nir_deref_instr %u\n", deref->deref_type);
3206       return false;
3207    }
3208    return true;
3209 }
3210
3211 bool
3212 Converter::run()
3213 {
3214    bool progress;
3215
3216    if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE)
3217       nir_print_shader(nir, stderr);
3218
3219    struct nir_lower_subgroups_options subgroup_options = {
3220       .subgroup_size = 32,
3221       .ballot_bit_size = 32,
3222    };
3223
3224    NIR_PASS_V(nir, nir_lower_io, nir_var_all, type_size, (nir_lower_io_options)0);
3225    NIR_PASS_V(nir, nir_lower_subgroups, &subgroup_options);
3226    NIR_PASS_V(nir, nir_lower_regs_to_ssa);
3227    NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
3228    NIR_PASS_V(nir, nir_lower_vars_to_ssa);
3229    NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
3230    NIR_PASS_V(nir, nir_lower_phis_to_scalar);
3231
3232    do {
3233       progress = false;
3234       NIR_PASS(progress, nir, nir_copy_prop);
3235       NIR_PASS(progress, nir, nir_opt_remove_phis);
3236       NIR_PASS(progress, nir, nir_opt_trivial_continues);
3237       NIR_PASS(progress, nir, nir_opt_cse);
3238       NIR_PASS(progress, nir, nir_opt_algebraic);
3239       NIR_PASS(progress, nir, nir_opt_constant_folding);
3240       NIR_PASS(progress, nir, nir_copy_prop);
3241       NIR_PASS(progress, nir, nir_opt_dce);
3242       NIR_PASS(progress, nir, nir_opt_dead_cf);
3243    } while (progress);
3244
3245    NIR_PASS_V(nir, nir_lower_bool_to_int32);
3246    NIR_PASS_V(nir, nir_lower_locals_to_regs);
3247    NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
3248    NIR_PASS_V(nir, nir_convert_from_ssa, true);
3249
3250    // Garbage collect dead instructions
3251    nir_sweep(nir);
3252
3253    if (!parseNIR()) {
3254       ERROR("Couldn't prase NIR!\n");
3255       return false;
3256    }
3257
3258    if (!assignSlots()) {
3259       ERROR("Couldn't assign slots!\n");
3260       return false;
3261    }
3262
3263    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
3264       nir_print_shader(nir, stderr);
3265
3266    nir_foreach_function(function, nir) {
3267       if (!visit(function))
3268          return false;
3269    }
3270
3271    return true;
3272 }
3273
3274 } // unnamed namespace
3275
3276 namespace nv50_ir {
3277
3278 bool
3279 Program::makeFromNIR(struct nv50_ir_prog_info *info)
3280 {
3281    nir_shader *nir = (nir_shader*)info->bin.source;
3282    Converter converter(this, nir, info);
3283    bool result = converter.run();
3284    if (!result)
3285       return result;
3286    LoweringHelper lowering;
3287    lowering.run(this);
3288    tlsSize = info->bin.tlsSpace;
3289    return result;
3290 }
3291
3292 } // namespace nv50_ir
3293
3294 static nir_shader_compiler_options
3295 nvir_nir_shader_compiler_options(int chipset)
3296 {
3297    return {
3298       .lower_fdiv = false,
3299       .lower_ffma = false,
3300       .fuse_ffma = false, /* nir doesn't track mad vs fma */
3301       .lower_flrp32 = true,
3302       .lower_flrp64 = true,
3303       .lower_fpow = false,
3304       .lower_fsat = false,
3305       .lower_fsqrt = false, // TODO: only before gm200
3306       .lower_fmod = true,
3307       .lower_bitfield_extract = false,
3308       .lower_bitfield_extract_to_shifts = false,
3309       .lower_bitfield_insert = false,
3310       .lower_bitfield_insert_to_shifts = false,
3311       .lower_bitfield_reverse = false,
3312       .lower_bit_count = false,
3313       .lower_ifind_msb = false,
3314       .lower_find_lsb = false,
3315       .lower_uadd_carry = true, // TODO
3316       .lower_usub_borrow = true, // TODO
3317       .lower_mul_high = false,
3318       .lower_negate = false,
3319       .lower_sub = true,
3320       .lower_scmp = true, // TODO: not implemented yet
3321       .lower_idiv = true,
3322       .lower_isign = false, // TODO
3323       .fdot_replicates = false, // TODO
3324       .lower_ffloor = false, // TODO
3325       .lower_ffract = true,
3326       .lower_fceil = false, // TODO
3327       .lower_ldexp = true,
3328       .lower_pack_half_2x16 = true,
3329       .lower_pack_unorm_2x16 = true,
3330       .lower_pack_snorm_2x16 = true,
3331       .lower_pack_unorm_4x8 = true,
3332       .lower_pack_snorm_4x8 = true,
3333       .lower_unpack_half_2x16 = true,
3334       .lower_unpack_unorm_2x16 = true,
3335       .lower_unpack_snorm_2x16 = true,
3336       .lower_unpack_unorm_4x8 = true,
3337       .lower_unpack_snorm_4x8 = true,
3338       .lower_extract_byte = true,
3339       .lower_extract_word = true,
3340       .lower_all_io_to_temps = false,
3341       .vertex_id_zero_based = false,
3342       .lower_base_vertex = false,
3343       .lower_helper_invocation = false,
3344       .lower_cs_local_index_from_id = true,
3345       .lower_cs_local_id_from_index = false,
3346       .lower_device_index_to_zero = false, // TODO
3347       .lower_wpos_pntc = false, // TODO
3348       .lower_hadd = true, // TODO
3349       .lower_add_sat = true, // TODO
3350       .lower_to_scalar = true,
3351       .use_interpolated_input_intrinsics = true,
3352       .lower_mul_2x32_64 = true, // TODO
3353       .max_unroll_iterations = 32,
3354       .lower_int64_options = (nir_lower_int64_options) ( // TODO
3355             nir_lower_divmod64 |
3356             nir_lower_ufind_msb64
3357       ),
3358       .lower_doubles_options = (nir_lower_doubles_options) ( // TODO
3359             nir_lower_dmod
3360       ),
3361    };
3362 }
3363
3364 static const nir_shader_compiler_options gf100_nir_shader_compiler_options =
3365 nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET);
3366
3367 const nir_shader_compiler_options *
3368 nv50_ir_nir_shader_compiler_options(int chipset)
3369 {
3370    return &gf100_nir_shader_compiler_options;
3371 }