src/gallium/drivers/nouveau/codegen/nv50_ir_target.h

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __NV50_IR_TARGET_H__
  24 #define __NV50_IR_TARGET_H__
  25
  26 #include "codegen/nv50_ir.h"
  27
  28 namespace nv50_ir {
  29
  30 struct RelocInfo;
  31
  32 struct RelocEntry
  33 {
  34    enum Type
  35    {
  36       TYPE_CODE,
  37       TYPE_BUILTIN,
  38       TYPE_DATA
  39    };
  40
  41    uint32_t data;
  42    uint32_t mask;
  43    uint32_t offset;
  44    int8_t bitPos;
  45    Type type;
  46
  47    inline void apply(uint32_t *binary, const RelocInfo *info) const;
  48 };
  49
  50 struct RelocInfo
  51 {
  52    uint32_t codePos;
  53    uint32_t libPos;
  54    uint32_t dataPos;
  55
  56    uint32_t count;
  57
  58    RelocEntry entry[0];
  59 };
  60
  61 struct FixupData {
  62    FixupData(bool force, bool flat, uint8_t alphatest) :
  63       force_persample_interp(force), flatshade(flat), alphatest(alphatest) {}
  64    bool force_persample_interp;
  65    bool flatshade;
  66    uint8_t alphatest;
  67 };
  68
  69 struct FixupEntry;
  70 typedef void (*FixupApply)(const FixupEntry*, uint32_t*, const FixupData&);
  71
  72 struct FixupEntry
  73 {
  74    FixupEntry(FixupApply apply, int ipa, int reg, int loc) :
  75       apply(apply), ipa(ipa), reg(reg), loc(loc) {}
  76
  77    FixupApply apply;
  78    union {
  79       struct {
  80          uint32_t ipa:4; // SC mode used to identify colors
  81          uint32_t reg:8; // The reg used for perspective division
  82          uint32_t loc:20; // Let's hope we don't have more than 1M-sized shaders
  83       };
  84       uint32_t val;
  85    };
  86 };
  87
  88 struct FixupInfo
  89 {
  90    uint32_t count;
  91    FixupEntry entry[0];
  92 };
  93
  94 class CodeEmitter
  95 {
  96 public:
  97    CodeEmitter(const Target *);
  98    virtual ~CodeEmitter() { }
  99
 100    // returns whether the instruction was encodable and written
 101    virtual bool emitInstruction(Instruction *) = 0;
 102
 103    virtual uint32_t getMinEncodingSize(const Instruction *) const = 0;
 104
 105    void setCodeLocation(void *, uint32_t size);
 106    inline void *getCodeLocation() const { return code; }
 107    inline uint32_t getCodeSize() const { return codeSize; }
 108
 109    bool addReloc(RelocEntry::Type, int w, uint32_t data, uint32_t m,
 110                  int s);
 111
 112    inline void *getRelocInfo() const { return relocInfo; }
 113
 114    bool addInterp(int ipa, int reg, FixupApply apply);
 115    inline void *getFixupInfo() const { return fixupInfo; }
 116
 117    virtual void prepareEmission(Program *);
 118    virtual void prepareEmission(Function *);
 119    virtual void prepareEmission(BasicBlock *);
 120
 121    void printBinary() const;
 122
 123 protected:
 124    const Target *targ;
 125
 126    uint32_t *code;
 127    uint32_t codeSize;
 128    uint32_t codeSizeLimit;
 129
 130    RelocInfo *relocInfo;
 131    FixupInfo *fixupInfo;
 132 };
 133
 134
 135 enum OpClass
 136 {
 137    OPCLASS_MOVE          = 0,
 138    OPCLASS_LOAD          = 1,
 139    OPCLASS_STORE         = 2,
 140    OPCLASS_ARITH         = 3,
 141    OPCLASS_SHIFT         = 4,
 142    OPCLASS_SFU           = 5,
 143    OPCLASS_LOGIC         = 6,
 144    OPCLASS_COMPARE       = 7,
 145    OPCLASS_CONVERT       = 8,
 146    OPCLASS_ATOMIC        = 9,
 147    OPCLASS_TEXTURE       = 10,
 148    OPCLASS_SURFACE       = 11,
 149    OPCLASS_FLOW          = 12,
 150    OPCLASS_PSEUDO        = 14,
 151    OPCLASS_VECTOR        = 15,
 152    OPCLASS_BITFIELD      = 16,
 153    OPCLASS_CONTROL       = 17,
 154    OPCLASS_OTHER         = 18
 155 };
 156
 157 class Target
 158 {
 159 public:
 160    Target(bool m, bool j, bool s) : hasJoin(m), joinAnterior(j), hasSWSched(s) { }
 161    virtual ~Target() { }
 162
 163    static Target *create(uint32_t chipset);
 164    static void destroy(Target *);
 165
 166    // 0x50 and 0x84 to 0xaf for nv50
 167    // 0xc0 to 0xdf for nvc0
 168    inline uint32_t getChipset() const { return chipset; }
 169
 170    virtual CodeEmitter *getCodeEmitter(Program::Type) = 0;
 171
 172    // Drivers should upload this so we can use it from all programs.
 173    // The address chosen is supplied to the relocation routine.
 174    virtual void getBuiltinCode(const uint32_t **code, uint32_t *size) const = 0;
 175
 176    virtual void parseDriverInfo(const struct nv50_ir_prog_info *info,
 177                                 const struct nv50_ir_prog_info_out *info_out) {
 178       if (info_out->type == PIPE_SHADER_COMPUTE) {
 179          threads = info->prop.cp.numThreads[0] *
 180             info->prop.cp.numThreads[1] *
 181             info->prop.cp.numThreads[2];
 182          if (threads == 0)
 183             threads = info->target >= NVISA_GK104_CHIPSET ? 1024 : 512;
 184       } else {
 185          threads = 32; // doesn't matter, just not too big.
 186       }
 187    }
 188
 189    virtual bool runLegalizePass(Program *, CGStage stage) const = 0;
 190
 191 public:
 192    struct OpInfo
 193    {
 194       OpInfo *variants;
 195       operation op;
 196       uint16_t srcTypes;
 197       uint16_t dstTypes;
 198       uint32_t immdBits;
 199       uint8_t srcNr;
 200       uint8_t srcMods[3];
 201       uint8_t dstMods;
 202       uint16_t srcFiles[3];
 203       uint16_t dstFiles;
 204       unsigned int minEncSize  : 5;
 205       unsigned int vector      : 1;
 206       unsigned int predicate   : 1;
 207       unsigned int commutative : 1;
 208       unsigned int pseudo      : 1;
 209       unsigned int flow        : 1;
 210       unsigned int hasDest     : 1;
 211       unsigned int terminator  : 1;
 212    };
 213
 214    inline const OpInfo& getOpInfo(const Instruction *) const;
 215    inline const OpInfo& getOpInfo(const operation) const;
 216
 217    inline DataFile nativeFile(DataFile f) const;
 218
 219    virtual bool insnCanLoad(const Instruction *insn, int s,
 220                             const Instruction *ld) const = 0;
 221    virtual bool insnCanLoadOffset(const Instruction *insn, int s,
 222                                   int offset) const = 0;
 223    virtual bool isOpSupported(operation, DataType) const = 0;
 224    virtual bool isAccessSupported(DataFile, DataType) const = 0;
 225    virtual bool isModSupported(const Instruction *,
 226                                int s, Modifier) const = 0;
 227    virtual bool isSatSupported(const Instruction *) const = 0;
 228    virtual bool isPostMultiplySupported(operation op, float f,
 229                                         int& e) const { return false; }
 230    virtual bool mayPredicate(const Instruction *,
 231                              const Value *) const = 0;
 232
 233    // whether @insn can be issued together with @next (order matters)
 234    virtual bool canDualIssue(const Instruction *insn,
 235                              const Instruction *next) const { return false; }
 236    virtual int getLatency(const Instruction *) const { return 1; }
 237    virtual int getThroughput(const Instruction *) const { return 1; }
 238
 239    virtual unsigned int getFileSize(DataFile) const = 0;
 240    virtual unsigned int getFileUnit(DataFile) const = 0;
 241
 242    virtual uint32_t getSVAddress(DataFile, const Symbol *) const = 0;
 243
 244 public:
 245    const bool hasJoin;      // true if instructions have a join modifier
 246    const bool joinAnterior; // true if join is executed before the op
 247    const bool hasSWSched;   // true if code should provide scheduling data
 248
 249    static const uint8_t operationSrcNr[];
 250    static const OpClass operationClass[];
 251
 252    static inline uint8_t getOpSrcNr(operation op)
 253    {
 254       return operationSrcNr[op];
 255    }
 256    static inline OpClass getOpClass(operation op)
 257    {
 258       return operationClass[op];
 259    }
 260
 261 protected:
 262    uint32_t chipset;
 263    uint32_t threads;
 264
 265    DataFile nativeFileMap[DATA_FILE_COUNT];
 266
 267    OpInfo opInfo[OP_LAST + 1];
 268 };
 269
 270 const Target::OpInfo& Target::getOpInfo(const Instruction *insn) const
 271 {
 272    return opInfo[MIN2(insn->op, OP_LAST)];
 273 }
 274
 275 const Target::OpInfo& Target::getOpInfo(const operation op) const
 276 {
 277    return opInfo[op];
 278 }
 279
 280 inline DataFile Target::nativeFile(DataFile f) const
 281 {
 282    return nativeFileMap[f];
 283 }
 284
 285 } // namespace nv50_ir
 286
 287 #endif // __NV50_IR_TARGET_H__