src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "codegen/nv50_ir_target_nvc0.h"
  24
  25 namespace nv50_ir {
  26
  27 Target *getTargetNVC0(unsigned int chipset)
  28 {
  29    return new TargetNVC0(chipset);
  30 }
  31
  32 TargetNVC0::TargetNVC0(unsigned int card) :
  33    Target(card < 0x110, false, card >= 0xe4)
  34 {
  35    chipset = card;
  36    initOpInfo();
  37 }
  38
  39 // BULTINS / LIBRARY FUNCTIONS:
  40
  41 // lazyness -> will just hardcode everything for the time being
  42
  43 #include "lib/gf100.asm.h"
  44 #include "lib/gk104.asm.h"
  45 #include "lib/gk110.asm.h"
  46
  47 void
  48 TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
  49 {
  50    switch (chipset & ~0xf) {
  51    case 0xe0:
  52       if (chipset < NVISA_GK20A_CHIPSET) {
  53          *code = (const uint32_t *)&gk104_builtin_code[0];
  54          *size = sizeof(gk104_builtin_code);
  55          break;
  56       }
  57       /* fall-through for GK20A */
  58    case 0xf0:
  59    case 0x100:
  60       *code = (const uint32_t *)&gk110_builtin_code[0];
  61       *size = sizeof(gk110_builtin_code);
  62       break;
  63    default:
  64       *code = (const uint32_t *)&gf100_builtin_code[0];
  65       *size = sizeof(gf100_builtin_code);
  66       break;
  67    }
  68 }
  69
  70 uint32_t
  71 TargetNVC0::getBuiltinOffset(int builtin) const
  72 {
  73    assert(builtin < NVC0_BUILTIN_COUNT);
  74
  75    switch (chipset & ~0xf) {
  76    case 0xe0:
  77       if (chipset < NVISA_GK20A_CHIPSET)
  78          return gk104_builtin_offsets[builtin];
  79       /* fall-through for GK20A */
  80    case 0xf0:
  81    case 0x100:
  82       return gk110_builtin_offsets[builtin];
  83    default:
  84       return gf100_builtin_offsets[builtin];
  85    }
  86 }
  87
  88 struct opProperties
  89 {
  90    operation op;
  91    unsigned int mNeg   : 4;
  92    unsigned int mAbs   : 4;
  93    unsigned int mNot   : 4;
  94    unsigned int mSat   : 4;
  95    unsigned int fConst : 3;
  96    unsigned int fImmd  : 4; // last bit indicates if full immediate is suppoted
  97 };
  98
  99 static const struct opProperties _initProps[] =
 100 {
 101    //           neg  abs  not  sat  c[]  imm
 102    { OP_ADD,    0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 },
 103    { OP_SUB,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 },
 104    { OP_MUL,    0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
 105    { OP_MAX,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 106    { OP_MIN,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 107    { OP_MAD,    0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // special c[] constraint
 108    { OP_SHLADD, 0x5, 0x0, 0x0, 0x0, 0x4, 0x6 },
 109    { OP_MADSP,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 110    { OP_ABS,    0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
 111    { OP_NEG,    0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
 112    { OP_CVT,    0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 113    { OP_CEIL,   0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 114    { OP_FLOOR,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 115    { OP_TRUNC,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 116    { OP_AND,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 117    { OP_OR,     0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 118    { OP_XOR,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 119    { OP_SHL,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 120    { OP_SHR,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 121    { OP_SET,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 122    { OP_SLCT,   0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint
 123    { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
 124    { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
 125    { OP_COS,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 126    { OP_SIN,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 127    { OP_EX2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 128    { OP_LG2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 129    { OP_RCP,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 130    { OP_RSQ,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 131    { OP_DFDX,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
 132    { OP_DFDY,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
 133    { OP_CALL,   0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
 134    { OP_POPCNT, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 },
 135    { OP_INSBF,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 136    { OP_EXTBF,  0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 137    { OP_BFIND,  0x0, 0x0, 0x1, 0x0, 0x1, 0x1 },
 138    { OP_PERMT,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 139    { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 140    { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 141    { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 142    // saturate only:
 143    { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
 144    { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
 145    // nve4 ops:
 146    { OP_SULDB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 147    { OP_SUSTB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 148    { OP_SUSTP,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 149    { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 150    { OP_SUBFM,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 151    { OP_SUEAU,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
 152 };
 153
 154 void TargetNVC0::initOpInfo()
 155 {
 156    unsigned int i, j;
 157
 158    static const uint32_t commutative[(OP_LAST + 31) / 32] =
 159    {
 160       // ADD, MUL, MAD, FMA, AND, OR, XOR, MAX, MIN, SET_AND, SET_OR, SET_XOR,
 161       // SET, SELP, SLCT
 162       0x0ce0ca00, 0x0000007e, 0x00000000, 0x00000000
 163    };
 164
 165    static const uint32_t shortForm[(OP_LAST + 31) / 32] =
 166    {
 167       // ADD, MUL, MAD, FMA, AND, OR, XOR, MAX, MIN
 168       0x0ce0ca00, 0x00000000, 0x00000000, 0x00000000
 169    };
 170
 171    static const operation noDest[] =
 172    {
 173       OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
 174       OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
 175       OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
 176       OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
 177       OP_SUREDB, OP_BAR
 178    };
 179
 180    static const operation noPred[] =
 181    {
 182       OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
 183       OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT
 184    };
 185
 186    for (i = 0; i < DATA_FILE_COUNT; ++i)
 187       nativeFileMap[i] = (DataFile)i;
 188    nativeFileMap[FILE_ADDRESS] = FILE_GPR;
 189
 190    for (i = 0; i < OP_LAST; ++i) {
 191       opInfo[i].variants = NULL;
 192       opInfo[i].op = (operation)i;
 193       opInfo[i].srcTypes = 1 << (int)TYPE_F32;
 194       opInfo[i].dstTypes = 1 << (int)TYPE_F32;
 195       opInfo[i].immdBits = 0;
 196       opInfo[i].srcNr = operationSrcNr[i];
 197
 198       for (j = 0; j < opInfo[i].srcNr; ++j) {
 199          opInfo[i].srcMods[j] = 0;
 200          opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
 201       }
 202       opInfo[i].dstMods = 0;
 203       opInfo[i].dstFiles = 1 << (int)FILE_GPR;
 204
 205       opInfo[i].hasDest = 1;
 206       opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
 207       opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1;
 208       opInfo[i].pseudo = (i < OP_MOV);
 209       opInfo[i].predicate = !opInfo[i].pseudo;
 210       opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
 211       opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8;
 212    }
 213    for (i = 0; i < sizeof(noDest) / sizeof(noDest[0]); ++i)
 214       opInfo[noDest[i]].hasDest = 0;
 215    for (i = 0; i < sizeof(noPred) / sizeof(noPred[0]); ++i)
 216       opInfo[noPred[i]].predicate = 0;
 217
 218    for (i = 0; i < sizeof(_initProps) / sizeof(_initProps[0]); ++i) {
 219       const struct opProperties *prop = &_initProps[i];
 220
 221       for (int s = 0; s < 3; ++s) {
 222          if (prop->mNeg & (1 << s))
 223             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
 224          if (prop->mAbs & (1 << s))
 225             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
 226          if (prop->mNot & (1 << s))
 227             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
 228          if (prop->fConst & (1 << s))
 229             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
 230          if (prop->fImmd & (1 << s))
 231             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
 232          if (prop->fImmd & 8)
 233             opInfo[prop->op].immdBits = 0xffffffff;
 234       }
 235       if (prop->mSat & 8)
 236          opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
 237    }
 238 }
 239
 240 unsigned int
 241 TargetNVC0::getFileSize(DataFile file) const
 242 {
 243    const unsigned int gprs = (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63;
 244    const unsigned int smregs = (chipset >= NVISA_GK104_CHIPSET) ? 65536 : 32768;
 245    switch (file) {
 246    case FILE_NULL:          return 0;
 247    case FILE_GPR:           return MIN2(gprs, smregs / threads);
 248    case FILE_PREDICATE:     return 7;
 249    case FILE_FLAGS:         return 1;
 250    case FILE_ADDRESS:       return 0;
 251    case FILE_IMMEDIATE:     return 0;
 252    case FILE_MEMORY_CONST:  return 65536;
 253    case FILE_SHADER_INPUT:  return 0x400;
 254    case FILE_SHADER_OUTPUT: return 0x400;
 255    case FILE_MEMORY_BUFFER: return 0xffffffff;
 256    case FILE_MEMORY_GLOBAL: return 0xffffffff;
 257    case FILE_MEMORY_SHARED: return 16 << 10;
 258    case FILE_MEMORY_LOCAL:  return 48 << 10;
 259    case FILE_SYSTEM_VALUE:  return 32;
 260    default:
 261       assert(!"invalid file");
 262       return 0;
 263    }
 264 }
 265
 266 unsigned int
 267 TargetNVC0::getFileUnit(DataFile file) const
 268 {
 269    if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE)
 270       return 2;
 271    return 0;
 272 }
 273
 274 uint32_t
 275 TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const
 276 {
 277    const int idx = sym->reg.data.sv.index;
 278    const SVSemantic sv = sym->reg.data.sv.sv;
 279
 280    const bool isInput = shaderFile == FILE_SHADER_INPUT;
 281    const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
 282
 283    switch (sv) {
 284    case SV_POSITION:       return 0x070 + idx * 4;
 285    case SV_INSTANCE_ID:    return 0x2f8;
 286    case SV_VERTEX_ID:      return 0x2fc;
 287    case SV_PRIMITIVE_ID:   return isInput ? 0x060 : 0x040;
 288    case SV_LAYER:          return 0x064;
 289    case SV_VIEWPORT_INDEX: return 0x068;
 290    case SV_POINT_SIZE:     return 0x06c;
 291    case SV_CLIP_DISTANCE:  return 0x2c0 + idx * 4;
 292    case SV_POINT_COORD:    return 0x2e0 + idx * 4;
 293    case SV_FACE:           return 0x3fc;
 294    case SV_TESS_OUTER:     return 0x000 + idx * 4;
 295    case SV_TESS_INNER:     return 0x010 + idx * 4;
 296    case SV_TESS_COORD:     return 0x2f0 + idx * 4;
 297    case SV_NTID:           return kepler ? (0x00 + idx * 4) : ~0;
 298    case SV_NCTAID:         return kepler ? (0x0c + idx * 4) : ~0;
 299    case SV_GRIDID:         return kepler ? 0x18 : ~0;
 300    case SV_WORK_DIM:       return 0x1c;
 301    case SV_SAMPLE_INDEX:   return 0;
 302    case SV_SAMPLE_POS:     return 0;
 303    case SV_SAMPLE_MASK:    return 0;
 304    case SV_BASEVERTEX:     return 0;
 305    case SV_BASEINSTANCE:   return 0;
 306    case SV_DRAWID:         return 0;
 307    default:
 308       return 0xffffffff;
 309    }
 310 }
 311
 312 bool
 313 TargetNVC0::insnCanLoad(const Instruction *i, int s,
 314                         const Instruction *ld) const
 315 {
 316    DataFile sf = ld->src(0).getFile();
 317
 318    // immediate 0 can be represented by GPR $r63/$r255
 319    if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
 320       return (!i->isPseudo() &&
 321               !i->asTex() &&
 322               i->op != OP_EXPORT && i->op != OP_STORE);
 323
 324    if (s >= opInfo[i->op].srcNr)
 325       return false;
 326    if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
 327       return false;
 328
 329    // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0
 330    if (ld->src(0).isIndirect(0))
 331       return false;
 332    // these are implemented using shf.r and shf.l which can't load consts
 333    if ((i->op == OP_SHL || i->op == OP_SHR) && typeSizeof(i->sType) == 8 &&
 334        sf == FILE_MEMORY_CONST)
 335       return false;
 336
 337    for (int k = 0; i->srcExists(k); ++k) {
 338       if (i->src(k).getFile() == FILE_IMMEDIATE) {
 339          if (k == 2 && i->op == OP_SUCLAMP) // special case
 340             continue;
 341          if (k == 1 && i->op == OP_SHLADD) // special case
 342             continue;
 343          if (i->getSrc(k)->reg.data.u64 != 0)
 344             return false;
 345       } else
 346       if (i->src(k).getFile() != FILE_GPR &&
 347           i->src(k).getFile() != FILE_PREDICATE &&
 348           i->src(k).getFile() != FILE_FLAGS) {
 349          return false;
 350       }
 351    }
 352
 353    // not all instructions support full 32 bit immediates
 354    if (sf == FILE_IMMEDIATE) {
 355       Storage &reg = ld->getSrc(0)->asImm()->reg;
 356
 357       if (opInfo[i->op].immdBits != 0xffffffff || typeSizeof(i->sType) > 4) {
 358          switch (i->sType) {
 359          case TYPE_F64:
 360             if (reg.data.u64 & 0x00000fffffffffffULL)
 361                return false;
 362             break;
 363          case TYPE_F32:
 364             if (reg.data.u32 & 0xfff)
 365                return false;
 366             break;
 367          case TYPE_S32:
 368          case TYPE_U32:
 369             // with u32, 0xfffff counts as 0xffffffff as well
 370             if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
 371                return false;
 372             break;
 373          case TYPE_U8:
 374          case TYPE_S8:
 375          case TYPE_U16:
 376          case TYPE_S16:
 377          case TYPE_F16:
 378             break;
 379          default:
 380             return false;
 381          }
 382       } else
 383       if (i->op == OP_MAD || i->op == OP_FMA) {
 384          // requires src == dst, cannot decide before RA
 385          // (except if we implement more constraints)
 386          if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff)
 387             return false;
 388       } else
 389       if (i->op == OP_ADD && i->sType == TYPE_F32) {
 390          // add f32 LIMM cannot saturate
 391          if (i->saturate && (reg.data.u32 & 0xfff))
 392             return false;
 393       }
 394    }
 395
 396    return true;
 397 }
 398
 399 bool
 400 TargetNVC0::insnCanLoadOffset(const Instruction *insn, int s, int offset) const
 401 {
 402    const ValueRef& ref = insn->src(s);
 403    if (ref.getFile() == FILE_MEMORY_CONST &&
 404        (insn->op != OP_LOAD || insn->subOp != NV50_IR_SUBOP_LDC_IS))
 405       return offset >= -0x8000 && offset < 0x8000;
 406    return true;
 407 }
 408
 409 bool
 410 TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
 411 {
 412    if (ty == TYPE_NONE)
 413       return false;
 414    if (file == FILE_MEMORY_CONST) {
 415       if (getChipset() >= NVISA_GM107_CHIPSET)
 416          return typeSizeof(ty) <= 4;
 417       else
 418       if (getChipset() >= NVISA_GK104_CHIPSET) // wrong encoding ?
 419          return typeSizeof(ty) <= 8;
 420    }
 421    if (ty == TYPE_B96)
 422       return false;
 423    return true;
 424 }
 425
 426 bool
 427 TargetNVC0::isOpSupported(operation op, DataType ty) const
 428 {
 429    if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
 430       return false;
 431    if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
 432       return false;
 433    return true;
 434 }
 435
 436 bool
 437 TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
 438 {
 439    if (!isFloatType(insn->dType)) {
 440       switch (insn->op) {
 441       case OP_ABS:
 442       case OP_NEG:
 443       case OP_CVT:
 444       case OP_CEIL:
 445       case OP_FLOOR:
 446       case OP_TRUNC:
 447       case OP_AND:
 448       case OP_OR:
 449       case OP_XOR:
 450       case OP_POPCNT:
 451       case OP_BFIND:
 452          break;
 453       case OP_SET:
 454          if (insn->sType != TYPE_F32)
 455             return false;
 456          break;
 457       case OP_ADD:
 458          if (mod.abs())
 459             return false;
 460          if (insn->src(s ? 0 : 1).mod.neg())
 461             return false;
 462          break;
 463       case OP_SUB:
 464          if (s == 0)
 465             return insn->src(1).mod.neg() ? false : true;
 466          break;
 467       case OP_SHLADD:
 468          if (s == 1)
 469             return false;
 470          if (insn->src(s ? 0 : 2).mod.neg())
 471             return false;
 472          break;
 473       default:
 474          return false;
 475       }
 476    }
 477    if (s >= opInfo[insn->op].srcNr || s >= 3)
 478       return false;
 479    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
 480 }
 481
 482 bool
 483 TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const
 484 {
 485    if (insn->getPredicate())
 486       return false;
 487    return opInfo[insn->op].predicate;
 488 }
 489
 490 bool
 491 TargetNVC0::isSatSupported(const Instruction *insn) const
 492 {
 493    if (insn->op == OP_CVT)
 494       return true;
 495    if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT))
 496       return false;
 497
 498    if (insn->dType == TYPE_U32)
 499       return (insn->op == OP_ADD) || (insn->op == OP_MAD);
 500
 501    // add f32 LIMM cannot saturate
 502    if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
 503       if (insn->getSrc(1)->asImm() &&
 504           insn->getSrc(1)->reg.data.u32 & 0xfff)
 505          return false;
 506    }
 507
 508    return insn->dType == TYPE_F32;
 509 }
 510
 511 bool
 512 TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const
 513 {
 514    if (op != OP_MUL)
 515       return false;
 516    f = fabsf(f);
 517    e = static_cast<int>(log2f(f));
 518    if (e < -3 || e > 3)
 519       return false;
 520    return f == exp2f(static_cast<float>(e));
 521 }
 522
 523 // TODO: better values
 524 // this could be more precise, e.g. depending on the issue-to-read/write delay
 525 // of the depending instruction, but it's good enough
 526 int TargetNVC0::getLatency(const Instruction *i) const
 527 {
 528    if (chipset >= 0xe4) {
 529       if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
 530          return 20;
 531       switch (i->op) {
 532       case OP_LINTERP:
 533       case OP_PINTERP:
 534          return 15;
 535       case OP_LOAD:
 536          if (i->src(0).getFile() == FILE_MEMORY_CONST)
 537             return 9;
 538          // fall through
 539       case OP_VFETCH:
 540          return 24;
 541       default:
 542          if (Target::getOpClass(i->op) == OPCLASS_TEXTURE)
 543             return 17;
 544          if (i->op == OP_MUL && i->dType != TYPE_F32)
 545             return 15;
 546          return 9;
 547       }
 548    } else {
 549       if (i->op == OP_LOAD) {
 550          if (i->cache == CACHE_CV)
 551             return 700;
 552          return 48;
 553       }
 554       return 24;
 555    }
 556    return 32;
 557 }
 558
 559 // These are "inverse" throughput values, i.e. the number of cycles required
 560 // to issue a specific instruction for a full warp (32 threads).
 561 //
 562 // Assuming we have more than 1 warp in flight, a higher issue latency results
 563 // in a lower result latency since the MP will have spent more time with other
 564 // warps.
 565 // This also helps to determine the number of cycles between instructions in
 566 // a single warp.
 567 //
 568 int TargetNVC0::getThroughput(const Instruction *i) const
 569 {
 570    // TODO: better values
 571    if (i->dType == TYPE_F32) {
 572       switch (i->op) {
 573       case OP_ADD:
 574       case OP_MUL:
 575       case OP_MAD:
 576       case OP_FMA:
 577          return 1;
 578       case OP_CVT:
 579       case OP_CEIL:
 580       case OP_FLOOR:
 581       case OP_TRUNC:
 582       case OP_SET:
 583       case OP_SLCT:
 584       case OP_MIN:
 585       case OP_MAX:
 586          return 2;
 587       case OP_RCP:
 588       case OP_RSQ:
 589       case OP_LG2:
 590       case OP_SIN:
 591       case OP_COS:
 592       case OP_PRESIN:
 593       case OP_PREEX2:
 594       default:
 595          return 8;
 596       }
 597    } else
 598    if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
 599       switch (i->op) {
 600       case OP_ADD:
 601       case OP_AND:
 602       case OP_OR:
 603       case OP_XOR:
 604       case OP_NOT:
 605          return 1;
 606       case OP_MUL:
 607       case OP_MAD:
 608       case OP_CVT:
 609       case OP_SET:
 610       case OP_SLCT:
 611       case OP_SHL:
 612       case OP_SHR:
 613       case OP_NEG:
 614       case OP_ABS:
 615       case OP_MIN:
 616       case OP_MAX:
 617       default:
 618          return 2;
 619       }
 620    } else
 621    if (i->dType == TYPE_F64) {
 622       return 2;
 623    } else {
 624       return 1;
 625    }
 626 }
 627
 628 bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const
 629 {
 630    const OpClass clA = operationClass[a->op];
 631    const OpClass clB = operationClass[b->op];
 632
 633    if (getChipset() >= 0xe4) {
 634       // not texturing
 635       // not if the 2nd instruction isn't necessarily executed
 636       if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW)
 637          return false;
 638
 639       // Check that a and b don't write to the same sources, nor that b reads
 640       // anything that a writes.
 641       if (!a->canCommuteDefDef(b) || !a->canCommuteDefSrc(b))
 642          return false;
 643
 644       // anything with MOV
 645       if (a->op == OP_MOV || b->op == OP_MOV)
 646          return true;
 647       if (clA == clB) {
 648          switch (clA) {
 649          // there might be more
 650          case OPCLASS_COMPARE:
 651             if ((a->op == OP_MIN || a->op == OP_MAX) &&
 652                 (b->op == OP_MIN || b->op == OP_MAX))
 653                break;
 654             return false;
 655          case OPCLASS_ARITH:
 656             break;
 657          default:
 658             return false;
 659          }
 660          // only F32 arith or integer additions
 661          return (a->dType == TYPE_F32 || a->op == OP_ADD ||
 662                  b->dType == TYPE_F32 || b->op == OP_ADD);
 663       }
 664       // nothing with TEXBAR
 665       if (a->op == OP_TEXBAR || b->op == OP_TEXBAR)
 666          return false;
 667       // no loads and stores accessing the same space
 668       if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) ||
 669           (clB == OPCLASS_LOAD && clA == OPCLASS_STORE))
 670          if (a->src(0).getFile() == b->src(0).getFile())
 671             return false;
 672       // no > 32-bit ops
 673       if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 ||
 674           typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4)
 675          return false;
 676       return true;
 677    } else {
 678       return false; // info not needed (yet)
 679    }
 680 }
 681
 682 } // namespace nv50_ir