src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "codegen/nv50_ir_target_nvc0.h"
  24
  25 namespace nv50_ir {
  26
  27 Target *getTargetNVC0(unsigned int chipset)
  28 {
  29    return new TargetNVC0(chipset);
  30 }
  31
  32 TargetNVC0::TargetNVC0(unsigned int card) : Target(false, card >= 0xe4)
  33 {
  34    chipset = card;
  35    initOpInfo();
  36 }
  37
  38 // BULTINS / LIBRARY FUNCTIONS:
  39
  40 // lazyness -> will just hardcode everything for the time being
  41
  42 #include "target_lib_nvc0.asm.h"
  43 #include "target_lib_nve4.asm.h"
  44 #include "target_lib_nvf0.asm.h"
  45
  46 void
  47 TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
  48 {
  49    switch (chipset & ~0xf) {
  50    case 0xe0:
  51       *code = (const uint32_t *)&nve4_builtin_code[0];
  52       *size = sizeof(nve4_builtin_code);
  53       break;
  54    case 0xf0:
  55    case 0x100:
  56       *code = (const uint32_t *)&nvf0_builtin_code[0];
  57       *size = sizeof(nvf0_builtin_code);
  58       break;
  59    default:
  60       *code = (const uint32_t *)&nvc0_builtin_code[0];
  61       *size = sizeof(nvc0_builtin_code);
  62       break;
  63    }
  64 }
  65
  66 uint32_t
  67 TargetNVC0::getBuiltinOffset(int builtin) const
  68 {
  69    assert(builtin < NVC0_BUILTIN_COUNT);
  70
  71    switch (chipset & ~0xf) {
  72    case 0xe0:
  73       return nve4_builtin_offsets[builtin];
  74    case 0xf0:
  75    case 0x100:
  76       return nvf0_builtin_offsets[builtin];
  77    default:
  78       return nvc0_builtin_offsets[builtin];
  79    }
  80 }
  81
  82 struct opProperties
  83 {
  84    operation op;
  85    unsigned int mNeg   : 4;
  86    unsigned int mAbs   : 4;
  87    unsigned int mNot   : 4;
  88    unsigned int mSat   : 4;
  89    unsigned int fConst : 3;
  90    unsigned int fImmd  : 4; // last bit indicates if full immediate is suppoted
  91 };
  92
  93 static const struct opProperties _initProps[] =
  94 {
  95    //           neg  abs  not  sat  c[]  imm
  96    { OP_ADD,    0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 },
  97    { OP_SUB,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 },
  98    { OP_MUL,    0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
  99    { OP_MAX,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 100    { OP_MIN,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 101    { OP_MAD,    0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // special c[] constraint
 102    { OP_MADSP,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 103    { OP_ABS,    0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
 104    { OP_NEG,    0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
 105    { OP_CVT,    0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 106    { OP_CEIL,   0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 107    { OP_FLOOR,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 108    { OP_TRUNC,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 109    { OP_AND,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 110    { OP_OR,     0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 111    { OP_XOR,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 112    { OP_SHL,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 113    { OP_SHR,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 114    { OP_SET,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 115    { OP_SLCT,   0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint
 116    { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
 117    { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
 118    { OP_COS,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 119    { OP_SIN,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 120    { OP_EX2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 121    { OP_LG2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 122    { OP_RCP,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 123    { OP_RSQ,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 124    { OP_DFDX,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
 125    { OP_DFDY,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
 126    { OP_CALL,   0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
 127    { OP_INSBF,  0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
 128    { OP_PERMT,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 129    { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 130    { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 131    { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 132    // saturate only:
 133    { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
 134    { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
 135    // nve4 ops:
 136    { OP_SULDB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 137    { OP_SUSTB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 138    { OP_SUSTP,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 139    { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 140    { OP_SUBFM,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 141    { OP_SUEAU,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
 142 };
 143
 144 void TargetNVC0::initOpInfo()
 145 {
 146    unsigned int i, j;
 147
 148    static const uint32_t commutative[(OP_LAST + 31) / 32] =
 149    {
 150       // ADD, MAD, MUL, AND, OR, XOR, MAX, MIN
 151       0x0670ca00, 0x0000003f, 0x00000000, 0x00000000
 152    };
 153
 154    static const uint32_t shortForm[(OP_LAST + 31) / 32] =
 155    {
 156       // ADD, MAD, MUL, AND, OR, XOR, PRESIN, PREEX2, SFN, CVT, PINTERP, MOV
 157       0x0670ca00, 0x00000000, 0x00000000, 0x00000000
 158    };
 159
 160    static const operation noDest[] =
 161    {
 162       OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
 163       OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
 164       OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
 165       OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
 166       OP_SUREDB, OP_BAR
 167    };
 168
 169    static const operation noPred[] =
 170    {
 171       OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
 172       OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT
 173    };
 174
 175    for (i = 0; i < DATA_FILE_COUNT; ++i)
 176       nativeFileMap[i] = (DataFile)i;
 177    nativeFileMap[FILE_ADDRESS] = FILE_GPR;
 178
 179    for (i = 0; i < OP_LAST; ++i) {
 180       opInfo[i].variants = NULL;
 181       opInfo[i].op = (operation)i;
 182       opInfo[i].srcTypes = 1 << (int)TYPE_F32;
 183       opInfo[i].dstTypes = 1 << (int)TYPE_F32;
 184       opInfo[i].immdBits = 0;
 185       opInfo[i].srcNr = operationSrcNr[i];
 186
 187       for (j = 0; j < opInfo[i].srcNr; ++j) {
 188          opInfo[i].srcMods[j] = 0;
 189          opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
 190       }
 191       opInfo[i].dstMods = 0;
 192       opInfo[i].dstFiles = 1 << (int)FILE_GPR;
 193
 194       opInfo[i].hasDest = 1;
 195       opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
 196       opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1;
 197       opInfo[i].pseudo = (i < OP_MOV);
 198       opInfo[i].predicate = !opInfo[i].pseudo;
 199       opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
 200       opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8;
 201    }
 202    for (i = 0; i < sizeof(noDest) / sizeof(noDest[0]); ++i)
 203       opInfo[noDest[i]].hasDest = 0;
 204    for (i = 0; i < sizeof(noPred) / sizeof(noPred[0]); ++i)
 205       opInfo[noPred[i]].predicate = 0;
 206
 207    for (i = 0; i < sizeof(_initProps) / sizeof(_initProps[0]); ++i) {
 208       const struct opProperties *prop = &_initProps[i];
 209
 210       for (int s = 0; s < 3; ++s) {
 211          if (prop->mNeg & (1 << s))
 212             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
 213          if (prop->mAbs & (1 << s))
 214             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
 215          if (prop->mNot & (1 << s))
 216             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
 217          if (prop->fConst & (1 << s))
 218             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
 219          if (prop->fImmd & (1 << s))
 220             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
 221          if (prop->fImmd & 8)
 222             opInfo[prop->op].immdBits = 0xffffffff;
 223       }
 224       if (prop->mSat & 8)
 225          opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
 226    }
 227 }
 228
 229 unsigned int
 230 TargetNVC0::getFileSize(DataFile file) const
 231 {
 232    switch (file) {
 233    case FILE_NULL:          return 0;
 234    case FILE_GPR:           return (chipset >= NVISA_GK110_CHIPSET) ? 255 : 63;
 235    case FILE_PREDICATE:     return 7;
 236    case FILE_FLAGS:         return 1;
 237    case FILE_ADDRESS:       return 0;
 238    case FILE_IMMEDIATE:     return 0;
 239    case FILE_MEMORY_CONST:  return 65536;
 240    case FILE_SHADER_INPUT:  return 0x400;
 241    case FILE_SHADER_OUTPUT: return 0x400;
 242    case FILE_MEMORY_GLOBAL: return 0xffffffff;
 243    case FILE_MEMORY_SHARED: return 16 << 10;
 244    case FILE_MEMORY_LOCAL:  return 48 << 10;
 245    case FILE_SYSTEM_VALUE:  return 32;
 246    default:
 247       assert(!"invalid file");
 248       return 0;
 249    }
 250 }
 251
 252 unsigned int
 253 TargetNVC0::getFileUnit(DataFile file) const
 254 {
 255    if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE)
 256       return 2;
 257    return 0;
 258 }
 259
 260 uint32_t
 261 TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const
 262 {
 263    const int idx = sym->reg.data.sv.index;
 264    const SVSemantic sv = sym->reg.data.sv.sv;
 265
 266    const bool isInput = shaderFile == FILE_SHADER_INPUT;
 267    const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
 268
 269    switch (sv) {
 270    case SV_POSITION:       return 0x070 + idx * 4;
 271    case SV_INSTANCE_ID:    return 0x2f8;
 272    case SV_VERTEX_ID:      return 0x2fc;
 273    case SV_PRIMITIVE_ID:   return isInput ? 0x060 : 0x040;
 274    case SV_LAYER:          return 0x064;
 275    case SV_VIEWPORT_INDEX: return 0x068;
 276    case SV_POINT_SIZE:     return 0x06c;
 277    case SV_CLIP_DISTANCE:  return 0x2c0 + idx * 4;
 278    case SV_POINT_COORD:    return 0x2e0 + idx * 4;
 279    case SV_FACE:           return 0x3fc;
 280    case SV_TESS_FACTOR:    return 0x000 + idx * 4;
 281    case SV_TESS_COORD:     return 0x2f0 + idx * 4;
 282    case SV_NTID:           return kepler ? (0x00 + idx * 4) : ~0;
 283    case SV_NCTAID:         return kepler ? (0x0c + idx * 4) : ~0;
 284    case SV_GRIDID:         return kepler ? 0x18 : ~0;
 285    default:
 286       return 0xffffffff;
 287    }
 288 }
 289
 290 bool
 291 TargetNVC0::insnCanLoad(const Instruction *i, int s,
 292                         const Instruction *ld) const
 293 {
 294    DataFile sf = ld->src(0).getFile();
 295
 296    // immediate 0 can be represented by GPR $r63/$r255
 297    if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
 298       return (!i->isPseudo() &&
 299               !i->asTex() &&
 300               i->op != OP_EXPORT && i->op != OP_STORE);
 301
 302    if (s >= opInfo[i->op].srcNr)
 303       return false;
 304    if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
 305       return false;
 306
 307    // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0
 308    if (ld->src(0).isIndirect(0))
 309       return false;
 310
 311    for (int k = 0; i->srcExists(k); ++k) {
 312       if (i->src(k).getFile() == FILE_IMMEDIATE) {
 313          if (k == 2 && i->op == OP_SUCLAMP) // special case
 314             continue;
 315          if (i->getSrc(k)->reg.data.u64 != 0)
 316             return false;
 317       } else
 318       if (i->src(k).getFile() != FILE_GPR &&
 319           i->src(k).getFile() != FILE_PREDICATE) {
 320          return false;
 321       }
 322    }
 323
 324    // not all instructions support full 32 bit immediates
 325    if (sf == FILE_IMMEDIATE) {
 326       Storage &reg = ld->getSrc(0)->asImm()->reg;
 327
 328       if (opInfo[i->op].immdBits != 0xffffffff) {
 329          if (i->sType == TYPE_F32) {
 330             if (reg.data.u32 & 0xfff)
 331                return false;
 332          } else
 333          if (i->sType == TYPE_S32 || i->sType == TYPE_U32) {
 334             // with u32, 0xfffff counts as 0xffffffff as well
 335             if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
 336                return false;
 337          }
 338       } else
 339       if (i->op == OP_MAD || i->op == OP_FMA) {
 340          // requires src == dst, cannot decide before RA
 341          // (except if we implement more constraints)
 342          if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff)
 343             return false;
 344       } else
 345       if (i->op == OP_ADD && i->sType == TYPE_F32) {
 346          // add f32 LIMM cannot saturate
 347          if (i->saturate && (reg.data.u32 & 0xfff))
 348             return false;
 349       }
 350    }
 351
 352    return true;
 353 }
 354
 355 bool
 356 TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
 357 {
 358    if (ty == TYPE_NONE)
 359       return false;
 360    if (file == FILE_MEMORY_CONST && getChipset() >= 0xe0) // wrong encoding ?
 361       return typeSizeof(ty) <= 8;
 362    if (ty == TYPE_B96)
 363       return false;
 364    if (getChipset() >= 0xf0) {
 365       // XXX: find wide vfetch/export
 366       if (ty == TYPE_B128)
 367          return false;
 368       if (ty == TYPE_U64)
 369          return false;
 370    }
 371    return true;
 372 }
 373
 374 bool
 375 TargetNVC0::isOpSupported(operation op, DataType ty) const
 376 {
 377    if ((op == OP_MAD || op == OP_FMA) && (ty != TYPE_F32))
 378       return false;
 379    if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
 380       return false;
 381    if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
 382       return false;
 383    return true;
 384 }
 385
 386 bool
 387 TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
 388 {
 389    if (!isFloatType(insn->dType)) {
 390       switch (insn->op) {
 391       case OP_ABS:
 392       case OP_NEG:
 393       case OP_CVT:
 394       case OP_CEIL:
 395       case OP_FLOOR:
 396       case OP_TRUNC:
 397       case OP_AND:
 398       case OP_OR:
 399       case OP_XOR:
 400          break;
 401       case OP_SET:
 402          if (insn->sType != TYPE_F32)
 403             return false;
 404          break;
 405       case OP_ADD:
 406          if (mod.abs())
 407             return false;
 408          if (insn->src(s ? 0 : 1).mod.neg())
 409             return false;
 410          break;
 411       case OP_SUB:
 412          if (s == 0)
 413             return insn->src(1).mod.neg() ? false : true;
 414          break;
 415       default:
 416          return false;
 417       }
 418    }
 419    if (s > 3)
 420       return false;
 421    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
 422 }
 423
 424 bool
 425 TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const
 426 {
 427    if (insn->getPredicate())
 428       return false;
 429    return opInfo[insn->op].predicate;
 430 }
 431
 432 bool
 433 TargetNVC0::isSatSupported(const Instruction *insn) const
 434 {
 435    if (insn->op == OP_CVT)
 436       return true;
 437    if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT))
 438       return false;
 439
 440    if (insn->dType == TYPE_U32)
 441       return (insn->op == OP_ADD) || (insn->op == OP_MAD);
 442
 443    // add f32 LIMM cannot saturate
 444    if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
 445       if (insn->getSrc(1)->asImm() &&
 446           insn->getSrc(1)->reg.data.u32 & 0xfff)
 447          return false;
 448    }
 449
 450    return insn->dType == TYPE_F32;
 451 }
 452
 453 bool
 454 TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const
 455 {
 456    if (op != OP_MUL)
 457       return false;
 458    f = fabsf(f);
 459    e = static_cast<int>(log2f(f));
 460    if (e < -3 || e > 3)
 461       return false;
 462    return f == exp2f(static_cast<float>(e));
 463 }
 464
 465 // TODO: better values
 466 // this could be more precise, e.g. depending on the issue-to-read/write delay
 467 // of the depending instruction, but it's good enough
 468 int TargetNVC0::getLatency(const Instruction *i) const
 469 {
 470    if (chipset >= 0xe4) {
 471       if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
 472          return 20;
 473       switch (i->op) {
 474       case OP_LINTERP:
 475       case OP_PINTERP:
 476          return 15;
 477       case OP_LOAD:
 478          if (i->src(0).getFile() == FILE_MEMORY_CONST)
 479             return 9;
 480          // fall through
 481       case OP_VFETCH:
 482          return 24;
 483       default:
 484          if (Target::getOpClass(i->op) == OPCLASS_TEXTURE)
 485             return 17;
 486          if (i->op == OP_MUL && i->dType != TYPE_F32)
 487             return 15;
 488          return 9;
 489       }
 490    } else {
 491       if (i->op == OP_LOAD) {
 492          if (i->cache == CACHE_CV)
 493             return 700;
 494          return 48;
 495       }
 496       return 24;
 497    }
 498    return 32;
 499 }
 500
 501 // These are "inverse" throughput values, i.e. the number of cycles required
 502 // to issue a specific instruction for a full warp (32 threads).
 503 //
 504 // Assuming we have more than 1 warp in flight, a higher issue latency results
 505 // in a lower result latency since the MP will have spent more time with other
 506 // warps.
 507 // This also helps to determine the number of cycles between instructions in
 508 // a single warp.
 509 //
 510 int TargetNVC0::getThroughput(const Instruction *i) const
 511 {
 512    // TODO: better values
 513    if (i->dType == TYPE_F32) {
 514       switch (i->op) {
 515       case OP_ADD:
 516       case OP_MUL:
 517       case OP_MAD:
 518       case OP_FMA:
 519          return 1;
 520       case OP_CVT:
 521       case OP_CEIL:
 522       case OP_FLOOR:
 523       case OP_TRUNC:
 524       case OP_SET:
 525       case OP_SLCT:
 526       case OP_MIN:
 527       case OP_MAX:
 528          return 2;
 529       case OP_RCP:
 530       case OP_RSQ:
 531       case OP_LG2:
 532       case OP_SIN:
 533       case OP_COS:
 534       case OP_PRESIN:
 535       case OP_PREEX2:
 536       default:
 537          return 8;
 538       }
 539    } else
 540    if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
 541       switch (i->op) {
 542       case OP_ADD:
 543       case OP_AND:
 544       case OP_OR:
 545       case OP_XOR:
 546       case OP_NOT:
 547          return 1;
 548       case OP_MUL:
 549       case OP_MAD:
 550       case OP_CVT:
 551       case OP_SET:
 552       case OP_SLCT:
 553       case OP_SHL:
 554       case OP_SHR:
 555       case OP_NEG:
 556       case OP_ABS:
 557       case OP_MIN:
 558       case OP_MAX:
 559       default:
 560          return 2;
 561       }
 562    } else
 563    if (i->dType == TYPE_F64) {
 564       return 2;
 565    } else {
 566       return 1;
 567    }
 568 }
 569
 570 bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const
 571 {
 572    const OpClass clA = operationClass[a->op];
 573    const OpClass clB = operationClass[b->op];
 574
 575    if (getChipset() >= 0xe4) {
 576       // not texturing
 577       // not if the 2nd instruction isn't necessarily executed
 578       if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW)
 579          return false;
 580       // anything with MOV
 581       if (a->op == OP_MOV || b->op == OP_MOV)
 582          return true;
 583       if (clA == clB) {
 584          // only F32 arith or integer additions
 585          if (clA != OPCLASS_ARITH)
 586             return false;
 587          return (a->dType == TYPE_F32 || a->op == OP_ADD ||
 588                  b->dType == TYPE_F32 || b->op == OP_ADD);
 589       }
 590       // nothing with TEXBAR
 591       if (a->op == OP_TEXBAR || b->op == OP_TEXBAR)
 592          return false;
 593       // no loads and stores accessing the the same space
 594       if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) ||
 595           (clB == OPCLASS_LOAD && clA == OPCLASS_STORE))
 596          if (a->src(0).getFile() == b->src(0).getFile())
 597             return false;
 598       // no > 32-bit ops
 599       if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 ||
 600           typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4)
 601          return false;
 602       return true;
 603    } else {
 604       return false; // info not needed (yet)
 605    }
 606 }
 607
 608 } // namespace nv50_ir