src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "codegen/nv50_ir_target_nvc0.h"
  24
  25 namespace nv50_ir {
  26
  27 Target *getTargetNVC0(unsigned int chipset)
  28 {
  29    return new TargetNVC0(chipset);
  30 }
  31
  32 TargetNVC0::TargetNVC0(unsigned int card) :
  33    Target(card < 0x110, false, card >= 0xe4)
  34 {
  35    chipset = card;
  36    initOpInfo();
  37 }
  38
  39 // BULTINS / LIBRARY FUNCTIONS:
  40
  41 // lazyness -> will just hardcode everything for the time being
  42
  43 #include "lib/gf100.asm.h"
  44 #include "lib/gk104.asm.h"
  45 #include "lib/gk110.asm.h"
  46
  47 void
  48 TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
  49 {
  50    switch (chipset & ~0xf) {
  51    case 0xe0:
  52       if (chipset < NVISA_GK20A_CHIPSET) {
  53          *code = (const uint32_t *)&gk104_builtin_code[0];
  54          *size = sizeof(gk104_builtin_code);
  55          break;
  56       }
  57       /* fall-through for GK20A */
  58    case 0xf0:
  59    case 0x100:
  60       *code = (const uint32_t *)&gk110_builtin_code[0];
  61       *size = sizeof(gk110_builtin_code);
  62       break;
  63    default:
  64       *code = (const uint32_t *)&gf100_builtin_code[0];
  65       *size = sizeof(gf100_builtin_code);
  66       break;
  67    }
  68 }
  69
  70 uint32_t
  71 TargetNVC0::getBuiltinOffset(int builtin) const
  72 {
  73    assert(builtin < NVC0_BUILTIN_COUNT);
  74
  75    switch (chipset & ~0xf) {
  76    case 0xe0:
  77       if (chipset < NVISA_GK20A_CHIPSET)
  78          return gk104_builtin_offsets[builtin];
  79       /* fall-through for GK20A */
  80    case 0xf0:
  81    case 0x100:
  82       return gk110_builtin_offsets[builtin];
  83    default:
  84       return gf100_builtin_offsets[builtin];
  85    }
  86 }
  87
  88 struct opProperties
  89 {
  90    operation op;
  91    unsigned int mNeg   : 4;
  92    unsigned int mAbs   : 4;
  93    unsigned int mNot   : 4;
  94    unsigned int mSat   : 4;
  95    unsigned int fConst : 3;
  96    unsigned int fImmd  : 4; // last bit indicates if full immediate is suppoted
  97 };
  98
  99 static const struct opProperties _initProps[] =
 100 {
 101    //           neg  abs  not  sat  c[]  imm
 102    { OP_ADD,    0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 },
 103    { OP_SUB,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 },
 104    { OP_MUL,    0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
 105    { OP_MAX,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 106    { OP_MIN,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 107    { OP_MAD,    0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // special c[] constraint
 108    { OP_MADSP,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 109    { OP_ABS,    0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
 110    { OP_NEG,    0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
 111    { OP_CVT,    0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 112    { OP_CEIL,   0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 113    { OP_FLOOR,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 114    { OP_TRUNC,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 115    { OP_AND,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 116    { OP_OR,     0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 117    { OP_XOR,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 118    { OP_SHL,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 119    { OP_SHR,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 120    { OP_SET,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 121    { OP_SLCT,   0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint
 122    { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
 123    { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
 124    { OP_COS,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 125    { OP_SIN,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 126    { OP_EX2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 127    { OP_LG2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 128    { OP_RCP,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 129    { OP_RSQ,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 130    { OP_DFDX,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
 131    { OP_DFDY,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
 132    { OP_CALL,   0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
 133    { OP_POPCNT, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 },
 134    { OP_INSBF,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 135    { OP_EXTBF,  0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 136    { OP_BFIND,  0x0, 0x0, 0x1, 0x0, 0x1, 0x1 },
 137    { OP_PERMT,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 138    { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 139    { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 140    { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 141    // saturate only:
 142    { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
 143    { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
 144    // nve4 ops:
 145    { OP_SULDB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 146    { OP_SUSTB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 147    { OP_SUSTP,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 148    { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 149    { OP_SUBFM,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 150    { OP_SUEAU,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
 151 };
 152
 153 void TargetNVC0::initOpInfo()
 154 {
 155    unsigned int i, j;
 156
 157    static const uint32_t commutative[(OP_LAST + 31) / 32] =
 158    {
 159       // ADD, MAD, MUL, AND, OR, XOR, MAX, MIN
 160       0x0670ca00, 0x0000003f, 0x00000000, 0x00000000
 161    };
 162
 163    static const uint32_t shortForm[(OP_LAST + 31) / 32] =
 164    {
 165       // ADD, MAD, MUL, AND, OR, XOR, PRESIN, PREEX2, SFN, CVT, PINTERP, MOV
 166       0x0670ca00, 0x00000000, 0x00000000, 0x00000000
 167    };
 168
 169    static const operation noDest[] =
 170    {
 171       OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
 172       OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
 173       OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
 174       OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
 175       OP_SUREDB, OP_BAR
 176    };
 177
 178    static const operation noPred[] =
 179    {
 180       OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
 181       OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT
 182    };
 183
 184    for (i = 0; i < DATA_FILE_COUNT; ++i)
 185       nativeFileMap[i] = (DataFile)i;
 186    nativeFileMap[FILE_ADDRESS] = FILE_GPR;
 187
 188    for (i = 0; i < OP_LAST; ++i) {
 189       opInfo[i].variants = NULL;
 190       opInfo[i].op = (operation)i;
 191       opInfo[i].srcTypes = 1 << (int)TYPE_F32;
 192       opInfo[i].dstTypes = 1 << (int)TYPE_F32;
 193       opInfo[i].immdBits = 0;
 194       opInfo[i].srcNr = operationSrcNr[i];
 195
 196       for (j = 0; j < opInfo[i].srcNr; ++j) {
 197          opInfo[i].srcMods[j] = 0;
 198          opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
 199       }
 200       opInfo[i].dstMods = 0;
 201       opInfo[i].dstFiles = 1 << (int)FILE_GPR;
 202
 203       opInfo[i].hasDest = 1;
 204       opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
 205       opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1;
 206       opInfo[i].pseudo = (i < OP_MOV);
 207       opInfo[i].predicate = !opInfo[i].pseudo;
 208       opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
 209       opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8;
 210    }
 211    for (i = 0; i < sizeof(noDest) / sizeof(noDest[0]); ++i)
 212       opInfo[noDest[i]].hasDest = 0;
 213    for (i = 0; i < sizeof(noPred) / sizeof(noPred[0]); ++i)
 214       opInfo[noPred[i]].predicate = 0;
 215
 216    for (i = 0; i < sizeof(_initProps) / sizeof(_initProps[0]); ++i) {
 217       const struct opProperties *prop = &_initProps[i];
 218
 219       for (int s = 0; s < 3; ++s) {
 220          if (prop->mNeg & (1 << s))
 221             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
 222          if (prop->mAbs & (1 << s))
 223             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
 224          if (prop->mNot & (1 << s))
 225             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
 226          if (prop->fConst & (1 << s))
 227             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
 228          if (prop->fImmd & (1 << s))
 229             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
 230          if (prop->fImmd & 8)
 231             opInfo[prop->op].immdBits = 0xffffffff;
 232       }
 233       if (prop->mSat & 8)
 234          opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
 235    }
 236 }
 237
 238 unsigned int
 239 TargetNVC0::getFileSize(DataFile file) const
 240 {
 241    const unsigned int gprs = (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63;
 242    const unsigned int smregs = (chipset >= NVISA_GK104_CHIPSET) ? 65536 : 32768;
 243    switch (file) {
 244    case FILE_NULL:          return 0;
 245    case FILE_GPR:           return MIN2(gprs, smregs / threads);
 246    case FILE_PREDICATE:     return 7;
 247    case FILE_FLAGS:         return 1;
 248    case FILE_ADDRESS:       return 0;
 249    case FILE_IMMEDIATE:     return 0;
 250    case FILE_MEMORY_CONST:  return 65536;
 251    case FILE_SHADER_INPUT:  return 0x400;
 252    case FILE_SHADER_OUTPUT: return 0x400;
 253    case FILE_MEMORY_BUFFER: return 0xffffffff;
 254    case FILE_MEMORY_GLOBAL: return 0xffffffff;
 255    case FILE_MEMORY_SHARED: return 16 << 10;
 256    case FILE_MEMORY_LOCAL:  return 48 << 10;
 257    case FILE_SYSTEM_VALUE:  return 32;
 258    default:
 259       assert(!"invalid file");
 260       return 0;
 261    }
 262 }
 263
 264 unsigned int
 265 TargetNVC0::getFileUnit(DataFile file) const
 266 {
 267    if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE)
 268       return 2;
 269    return 0;
 270 }
 271
 272 uint32_t
 273 TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const
 274 {
 275    const int idx = sym->reg.data.sv.index;
 276    const SVSemantic sv = sym->reg.data.sv.sv;
 277
 278    const bool isInput = shaderFile == FILE_SHADER_INPUT;
 279    const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
 280
 281    switch (sv) {
 282    case SV_POSITION:       return 0x070 + idx * 4;
 283    case SV_INSTANCE_ID:    return 0x2f8;
 284    case SV_VERTEX_ID:      return 0x2fc;
 285    case SV_PRIMITIVE_ID:   return isInput ? 0x060 : 0x040;
 286    case SV_LAYER:          return 0x064;
 287    case SV_VIEWPORT_INDEX: return 0x068;
 288    case SV_POINT_SIZE:     return 0x06c;
 289    case SV_CLIP_DISTANCE:  return 0x2c0 + idx * 4;
 290    case SV_POINT_COORD:    return 0x2e0 + idx * 4;
 291    case SV_FACE:           return 0x3fc;
 292    case SV_TESS_OUTER:     return 0x000 + idx * 4;
 293    case SV_TESS_INNER:     return 0x010 + idx * 4;
 294    case SV_TESS_COORD:     return 0x2f0 + idx * 4;
 295    case SV_NTID:           return kepler ? (0x00 + idx * 4) : ~0;
 296    case SV_NCTAID:         return kepler ? (0x0c + idx * 4) : ~0;
 297    case SV_GRIDID:         return kepler ? 0x18 : ~0;
 298    case SV_WORK_DIM:       return 0x1c;
 299    case SV_SAMPLE_INDEX:   return 0;
 300    case SV_SAMPLE_POS:     return 0;
 301    case SV_SAMPLE_MASK:    return 0;
 302    case SV_BASEVERTEX:     return 0;
 303    case SV_BASEINSTANCE:   return 0;
 304    case SV_DRAWID:         return 0;
 305    default:
 306       return 0xffffffff;
 307    }
 308 }
 309
 310 bool
 311 TargetNVC0::insnCanLoad(const Instruction *i, int s,
 312                         const Instruction *ld) const
 313 {
 314    DataFile sf = ld->src(0).getFile();
 315
 316    // immediate 0 can be represented by GPR $r63/$r255
 317    if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
 318       return (!i->isPseudo() &&
 319               !i->asTex() &&
 320               i->op != OP_EXPORT && i->op != OP_STORE);
 321
 322    if (s >= opInfo[i->op].srcNr)
 323       return false;
 324    if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
 325       return false;
 326
 327    // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0
 328    if (ld->src(0).isIndirect(0))
 329       return false;
 330
 331    for (int k = 0; i->srcExists(k); ++k) {
 332       if (i->src(k).getFile() == FILE_IMMEDIATE) {
 333          if (k == 2 && i->op == OP_SUCLAMP) // special case
 334             continue;
 335          if (i->getSrc(k)->reg.data.u64 != 0)
 336             return false;
 337       } else
 338       if (i->src(k).getFile() != FILE_GPR &&
 339           i->src(k).getFile() != FILE_PREDICATE) {
 340          return false;
 341       }
 342    }
 343
 344    // not all instructions support full 32 bit immediates
 345    if (sf == FILE_IMMEDIATE) {
 346       Storage &reg = ld->getSrc(0)->asImm()->reg;
 347
 348       if (opInfo[i->op].immdBits != 0xffffffff || typeSizeof(i->sType) > 4) {
 349          switch (i->sType) {
 350          case TYPE_F64:
 351             if (reg.data.u64 & 0x00000fffffffffffULL)
 352                return false;
 353             break;
 354          case TYPE_F32:
 355             if (reg.data.u32 & 0xfff)
 356                return false;
 357             break;
 358          case TYPE_S32:
 359          case TYPE_U32:
 360             // with u32, 0xfffff counts as 0xffffffff as well
 361             if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
 362                return false;
 363             break;
 364          case TYPE_U8:
 365          case TYPE_S8:
 366          case TYPE_U16:
 367          case TYPE_S16:
 368          case TYPE_F16:
 369             break;
 370          default:
 371             return false;
 372          }
 373       } else
 374       if (i->op == OP_MAD || i->op == OP_FMA) {
 375          // requires src == dst, cannot decide before RA
 376          // (except if we implement more constraints)
 377          if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff)
 378             return false;
 379       } else
 380       if (i->op == OP_ADD && i->sType == TYPE_F32) {
 381          // add f32 LIMM cannot saturate
 382          if (i->saturate && (reg.data.u32 & 0xfff))
 383             return false;
 384       }
 385    }
 386
 387    return true;
 388 }
 389
 390 bool
 391 TargetNVC0::insnCanLoadOffset(const Instruction *insn, int s, int offset) const
 392 {
 393    const ValueRef& ref = insn->src(s);
 394    if (ref.getFile() == FILE_MEMORY_CONST &&
 395        (insn->op != OP_LOAD || insn->subOp != NV50_IR_SUBOP_LDC_IS))
 396       return offset >= -0x8000 && offset < 0x8000;
 397    return true;
 398 }
 399
 400 bool
 401 TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
 402 {
 403    if (ty == TYPE_NONE)
 404       return false;
 405    if (file == FILE_MEMORY_CONST && getChipset() >= 0xe0) // wrong encoding ?
 406       return typeSizeof(ty) <= 8;
 407    if (ty == TYPE_B96)
 408       return false;
 409    return true;
 410 }
 411
 412 bool
 413 TargetNVC0::isOpSupported(operation op, DataType ty) const
 414 {
 415    if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
 416       return false;
 417    if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
 418       return false;
 419    return true;
 420 }
 421
 422 bool
 423 TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
 424 {
 425    if (!isFloatType(insn->dType)) {
 426       switch (insn->op) {
 427       case OP_ABS:
 428       case OP_NEG:
 429       case OP_CVT:
 430       case OP_CEIL:
 431       case OP_FLOOR:
 432       case OP_TRUNC:
 433       case OP_AND:
 434       case OP_OR:
 435       case OP_XOR:
 436       case OP_POPCNT:
 437       case OP_BFIND:
 438          break;
 439       case OP_SET:
 440          if (insn->sType != TYPE_F32)
 441             return false;
 442          break;
 443       case OP_ADD:
 444          if (mod.abs())
 445             return false;
 446          if (insn->src(s ? 0 : 1).mod.neg())
 447             return false;
 448          break;
 449       case OP_SUB:
 450          if (s == 0)
 451             return insn->src(1).mod.neg() ? false : true;
 452          break;
 453       default:
 454          return false;
 455       }
 456    }
 457    if (s >= opInfo[insn->op].srcNr || s >= 3)
 458       return false;
 459    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
 460 }
 461
 462 bool
 463 TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const
 464 {
 465    if (insn->getPredicate())
 466       return false;
 467    return opInfo[insn->op].predicate;
 468 }
 469
 470 bool
 471 TargetNVC0::isSatSupported(const Instruction *insn) const
 472 {
 473    if (insn->op == OP_CVT)
 474       return true;
 475    if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT))
 476       return false;
 477
 478    if (insn->dType == TYPE_U32)
 479       return (insn->op == OP_ADD) || (insn->op == OP_MAD);
 480
 481    // add f32 LIMM cannot saturate
 482    if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
 483       if (insn->getSrc(1)->asImm() &&
 484           insn->getSrc(1)->reg.data.u32 & 0xfff)
 485          return false;
 486    }
 487
 488    return insn->dType == TYPE_F32;
 489 }
 490
 491 bool
 492 TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const
 493 {
 494    if (op != OP_MUL)
 495       return false;
 496    f = fabsf(f);
 497    e = static_cast<int>(log2f(f));
 498    if (e < -3 || e > 3)
 499       return false;
 500    return f == exp2f(static_cast<float>(e));
 501 }
 502
 503 // TODO: better values
 504 // this could be more precise, e.g. depending on the issue-to-read/write delay
 505 // of the depending instruction, but it's good enough
 506 int TargetNVC0::getLatency(const Instruction *i) const
 507 {
 508    if (chipset >= 0xe4) {
 509       if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
 510          return 20;
 511       switch (i->op) {
 512       case OP_LINTERP:
 513       case OP_PINTERP:
 514          return 15;
 515       case OP_LOAD:
 516          if (i->src(0).getFile() == FILE_MEMORY_CONST)
 517             return 9;
 518          // fall through
 519       case OP_VFETCH:
 520          return 24;
 521       default:
 522          if (Target::getOpClass(i->op) == OPCLASS_TEXTURE)
 523             return 17;
 524          if (i->op == OP_MUL && i->dType != TYPE_F32)
 525             return 15;
 526          return 9;
 527       }
 528    } else {
 529       if (i->op == OP_LOAD) {
 530          if (i->cache == CACHE_CV)
 531             return 700;
 532          return 48;
 533       }
 534       return 24;
 535    }
 536    return 32;
 537 }
 538
 539 // These are "inverse" throughput values, i.e. the number of cycles required
 540 // to issue a specific instruction for a full warp (32 threads).
 541 //
 542 // Assuming we have more than 1 warp in flight, a higher issue latency results
 543 // in a lower result latency since the MP will have spent more time with other
 544 // warps.
 545 // This also helps to determine the number of cycles between instructions in
 546 // a single warp.
 547 //
 548 int TargetNVC0::getThroughput(const Instruction *i) const
 549 {
 550    // TODO: better values
 551    if (i->dType == TYPE_F32) {
 552       switch (i->op) {
 553       case OP_ADD:
 554       case OP_MUL:
 555       case OP_MAD:
 556       case OP_FMA:
 557          return 1;
 558       case OP_CVT:
 559       case OP_CEIL:
 560       case OP_FLOOR:
 561       case OP_TRUNC:
 562       case OP_SET:
 563       case OP_SLCT:
 564       case OP_MIN:
 565       case OP_MAX:
 566          return 2;
 567       case OP_RCP:
 568       case OP_RSQ:
 569       case OP_LG2:
 570       case OP_SIN:
 571       case OP_COS:
 572       case OP_PRESIN:
 573       case OP_PREEX2:
 574       default:
 575          return 8;
 576       }
 577    } else
 578    if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
 579       switch (i->op) {
 580       case OP_ADD:
 581       case OP_AND:
 582       case OP_OR:
 583       case OP_XOR:
 584       case OP_NOT:
 585          return 1;
 586       case OP_MUL:
 587       case OP_MAD:
 588       case OP_CVT:
 589       case OP_SET:
 590       case OP_SLCT:
 591       case OP_SHL:
 592       case OP_SHR:
 593       case OP_NEG:
 594       case OP_ABS:
 595       case OP_MIN:
 596       case OP_MAX:
 597       default:
 598          return 2;
 599       }
 600    } else
 601    if (i->dType == TYPE_F64) {
 602       return 2;
 603    } else {
 604       return 1;
 605    }
 606 }
 607
 608 bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const
 609 {
 610    const OpClass clA = operationClass[a->op];
 611    const OpClass clB = operationClass[b->op];
 612
 613    if (getChipset() >= 0xe4) {
 614       // not texturing
 615       // not if the 2nd instruction isn't necessarily executed
 616       if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW)
 617          return false;
 618
 619       // Check that a and b don't write to the same sources, nor that b reads
 620       // anything that a writes.
 621       if (!a->canCommuteDefDef(b) || !a->canCommuteDefSrc(b))
 622          return false;
 623
 624       // anything with MOV
 625       if (a->op == OP_MOV || b->op == OP_MOV)
 626          return true;
 627       if (clA == clB) {
 628          // only F32 arith or integer additions
 629          if (clA != OPCLASS_ARITH)
 630             return false;
 631          return (a->dType == TYPE_F32 || a->op == OP_ADD ||
 632                  b->dType == TYPE_F32 || b->op == OP_ADD);
 633       }
 634       // nothing with TEXBAR
 635       if (a->op == OP_TEXBAR || b->op == OP_TEXBAR)
 636          return false;
 637       // no loads and stores accessing the same space
 638       if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) ||
 639           (clB == OPCLASS_LOAD && clA == OPCLASS_STORE))
 640          if (a->src(0).getFile() == b->src(0).getFile())
 641             return false;
 642       // no > 32-bit ops
 643       if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 ||
 644           typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4)
 645          return false;
 646       return true;
 647    } else {
 648       return false; // info not needed (yet)
 649    }
 650 }
 651
 652 } // namespace nv50_ir