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19a606e74277d78490ad9b69dbb1550c7de0529e
[mesa.git] / src / gallium / drivers / nouveau / nv30 / nv30_screen.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26 #include <xf86drm.h>
27 #include <nouveau_drm.h>
28 #include "util/format/u_format.h"
29 #include "util/format/u_format_s3tc.h"
30 #include "util/u_screen.h"
31
32 #include "nv_object.xml.h"
33 #include "nv_m2mf.xml.h"
34 #include "nv30/nv30-40_3d.xml.h"
35 #include "nv30/nv01_2d.xml.h"
36
37 #include "nouveau_fence.h"
38 #include "nv30/nv30_screen.h"
39 #include "nv30/nv30_context.h"
40 #include "nv30/nv30_resource.h"
41 #include "nv30/nv30_format.h"
42
43 #define RANKINE_0397_CHIPSET 0x00000003
44 #define RANKINE_0497_CHIPSET 0x000001e0
45 #define RANKINE_0697_CHIPSET 0x00000010
46 #define CURIE_4097_CHIPSET 0x00000baf
47 #define CURIE_4497_CHIPSET 0x00005450
48 #define CURIE_4497_CHIPSET6X 0x00000088
49
50 static int
51 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
52 {
53 struct nv30_screen *screen = nv30_screen(pscreen);
54 struct nouveau_object *eng3d = screen->eng3d;
55 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
56
57 switch (param) {
58 /* non-boolean capabilities */
59 case PIPE_CAP_MAX_RENDER_TARGETS:
60 return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
61 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
62 return 4096;
63 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
64 return 10;
65 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
66 return 13;
67 case PIPE_CAP_GLSL_FEATURE_LEVEL:
68 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
69 return 120;
70 case PIPE_CAP_ENDIANNESS:
71 return PIPE_ENDIAN_LITTLE;
72 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
73 return 16;
74 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
75 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
76 case PIPE_CAP_MAX_VIEWPORTS:
77 return 1;
78 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
79 return 2048;
80 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
81 return 8 * 1024 * 1024;
82 case PIPE_CAP_MAX_VARYINGS:
83 return 8;
84
85 /* supported capabilities */
86 case PIPE_CAP_ANISOTROPIC_FILTER:
87 case PIPE_CAP_POINT_SPRITE:
88 case PIPE_CAP_OCCLUSION_QUERY:
89 case PIPE_CAP_QUERY_TIME_ELAPSED:
90 case PIPE_CAP_QUERY_TIMESTAMP:
91 case PIPE_CAP_TEXTURE_SWIZZLE:
92 case PIPE_CAP_DEPTH_CLIP_DISABLE:
93 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
94 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
95 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
96 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
97 case PIPE_CAP_TGSI_TEXCOORD:
98 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
99 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
100 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
101 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
102 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
103 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
104 return 1;
105 /* nv35 capabilities */
106 case PIPE_CAP_DEPTH_BOUNDS_TEST:
107 return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
108 /* nv4x capabilities */
109 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
110 case PIPE_CAP_NPOT_TEXTURES:
111 case PIPE_CAP_CONDITIONAL_RENDER:
112 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
113 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
114 case PIPE_CAP_PRIMITIVE_RESTART:
115 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
116 return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
117 /* unsupported */
118 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
119 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
120 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
121 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
122 case PIPE_CAP_VERTEX_SHADER_SATURATE:
123 case PIPE_CAP_INDEP_BLEND_ENABLE:
124 case PIPE_CAP_INDEP_BLEND_FUNC:
125 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
126 case PIPE_CAP_SHADER_STENCIL_EXPORT:
127 case PIPE_CAP_TGSI_INSTANCEID:
128 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
129 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
130 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
131 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
132 case PIPE_CAP_MIN_TEXEL_OFFSET:
133 case PIPE_CAP_MAX_TEXEL_OFFSET:
134 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
135 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
136 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
137 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
138 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
139 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
140 case PIPE_CAP_MAX_VERTEX_STREAMS:
141 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
142 case PIPE_CAP_TEXTURE_BARRIER:
143 case PIPE_CAP_SEAMLESS_CUBE_MAP:
144 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
145 case PIPE_CAP_CUBE_MAP_ARRAY:
146 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
147 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
148 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
149 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
150 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
151 case PIPE_CAP_START_INSTANCE:
152 case PIPE_CAP_TEXTURE_MULTISAMPLE:
153 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
154 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
155 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
156 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
157 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
158 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
159 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
160 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
161 case PIPE_CAP_TEXTURE_GATHER_SM5:
162 case PIPE_CAP_FAKE_SW_MSAA:
163 case PIPE_CAP_TEXTURE_QUERY_LOD:
164 case PIPE_CAP_SAMPLE_SHADING:
165 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
166 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
167 case PIPE_CAP_USER_VERTEX_BUFFERS:
168 case PIPE_CAP_COMPUTE:
169 case PIPE_CAP_DRAW_INDIRECT:
170 case PIPE_CAP_MULTI_DRAW_INDIRECT:
171 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
172 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
173 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
174 case PIPE_CAP_SAMPLER_VIEW_TARGET:
175 case PIPE_CAP_CLIP_HALFZ:
176 case PIPE_CAP_VERTEXID_NOBASE:
177 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
178 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
179 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
180 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
181 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
182 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
183 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
184 case PIPE_CAP_TGSI_TXQS:
185 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
186 case PIPE_CAP_SHAREABLE_SHADERS:
187 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
188 case PIPE_CAP_CLEAR_TEXTURE:
189 case PIPE_CAP_DRAW_PARAMETERS:
190 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
191 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
192 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
193 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
194 case PIPE_CAP_INVALIDATE_BUFFER:
195 case PIPE_CAP_GENERATE_MIPMAP:
196 case PIPE_CAP_STRING_MARKER:
197 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
198 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
199 case PIPE_CAP_QUERY_BUFFER_OBJECT:
200 case PIPE_CAP_QUERY_MEMORY_INFO:
201 case PIPE_CAP_PCI_GROUP:
202 case PIPE_CAP_PCI_BUS:
203 case PIPE_CAP_PCI_DEVICE:
204 case PIPE_CAP_PCI_FUNCTION:
205 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
206 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
207 case PIPE_CAP_CULL_DISTANCE:
208 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
209 case PIPE_CAP_TGSI_VOTE:
210 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
211 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
212 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
213 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
214 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
215 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
216 case PIPE_CAP_NATIVE_FENCE_FD:
217 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
218 case PIPE_CAP_FBFETCH:
219 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
220 case PIPE_CAP_DOUBLES:
221 case PIPE_CAP_INT64:
222 case PIPE_CAP_INT64_DIVMOD:
223 case PIPE_CAP_TGSI_TEX_TXF_LZ:
224 case PIPE_CAP_TGSI_CLOCK:
225 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
226 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
227 case PIPE_CAP_TGSI_BALLOT:
228 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
229 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
230 case PIPE_CAP_POST_DEPTH_COVERAGE:
231 case PIPE_CAP_BINDLESS_TEXTURE:
232 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
233 case PIPE_CAP_QUERY_SO_OVERFLOW:
234 case PIPE_CAP_MEMOBJ:
235 case PIPE_CAP_LOAD_CONSTBUF:
236 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
237 case PIPE_CAP_TILE_RASTER_ORDER:
238 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
239 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
240 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
241 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
242 case PIPE_CAP_FENCE_SIGNAL:
243 case PIPE_CAP_CONSTBUF0_FLAGS:
244 case PIPE_CAP_PACKED_UNIFORMS:
245 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
246 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
247 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
248 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
249 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
250 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
251 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
252 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
253 case PIPE_CAP_TGSI_DIV:
254 case PIPE_CAP_TGSI_ATOMINC_WRAP:
255 return 0;
256
257 case PIPE_CAP_MAX_GS_INVOCATIONS:
258 return 32;
259 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
260 return 1 << 27;
261 case PIPE_CAP_VENDOR_ID:
262 return 0x10de;
263 case PIPE_CAP_DEVICE_ID: {
264 uint64_t device_id;
265 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
266 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
267 return -1;
268 }
269 return device_id;
270 }
271 case PIPE_CAP_ACCELERATED:
272 return 1;
273 case PIPE_CAP_VIDEO_MEMORY:
274 return dev->vram_size >> 20;
275 case PIPE_CAP_UMA:
276 return 0;
277 default:
278 return u_pipe_screen_get_param_defaults(pscreen, param);
279 }
280 }
281
282 static float
283 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
284 {
285 struct nv30_screen *screen = nv30_screen(pscreen);
286 struct nouveau_object *eng3d = screen->eng3d;
287
288 switch (param) {
289 case PIPE_CAPF_MAX_LINE_WIDTH:
290 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
291 return 10.0;
292 case PIPE_CAPF_MAX_POINT_WIDTH:
293 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
294 return 64.0;
295 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
296 return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
297 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
298 return 15.0;
299 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
300 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
301 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
302 return 0.0;
303 default:
304 debug_printf("unknown paramf %d\n", param);
305 return 0;
306 }
307 }
308
309 static int
310 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
311 enum pipe_shader_type shader,
312 enum pipe_shader_cap param)
313 {
314 struct nv30_screen *screen = nv30_screen(pscreen);
315 struct nouveau_object *eng3d = screen->eng3d;
316
317 switch (shader) {
318 case PIPE_SHADER_VERTEX:
319 switch (param) {
320 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
321 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
322 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
323 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
324 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
325 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
326 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
327 return 0;
328 case PIPE_SHADER_CAP_MAX_INPUTS:
329 case PIPE_SHADER_CAP_MAX_OUTPUTS:
330 return 16;
331 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
332 return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
333 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
334 return 1;
335 case PIPE_SHADER_CAP_MAX_TEMPS:
336 return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
337 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
338 return 32;
339 case PIPE_SHADER_CAP_PREFERRED_IR:
340 return PIPE_SHADER_IR_TGSI;
341 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
342 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
343 return 0;
344 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
345 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
346 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
347 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
348 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
349 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
350 case PIPE_SHADER_CAP_SUBROUTINES:
351 case PIPE_SHADER_CAP_INTEGERS:
352 case PIPE_SHADER_CAP_INT64_ATOMICS:
353 case PIPE_SHADER_CAP_FP16:
354 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
355 case PIPE_SHADER_CAP_INT16:
356 case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS:
357 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
358 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
359 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
360 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
361 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
362 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
363 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
364 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
365 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
366 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
367 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
368 return 0;
369 default:
370 debug_printf("unknown vertex shader param %d\n", param);
371 return 0;
372 }
373 break;
374 case PIPE_SHADER_FRAGMENT:
375 switch (param) {
376 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
377 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
378 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
379 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
380 return 4096;
381 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
382 return 0;
383 case PIPE_SHADER_CAP_MAX_INPUTS:
384 return 8; /* should be possible to do 10 with nv4x */
385 case PIPE_SHADER_CAP_MAX_OUTPUTS:
386 return 4;
387 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
388 return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
389 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
390 return 1;
391 case PIPE_SHADER_CAP_MAX_TEMPS:
392 return 32;
393 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
394 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
395 return 16;
396 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
397 return 32;
398 case PIPE_SHADER_CAP_PREFERRED_IR:
399 return PIPE_SHADER_IR_TGSI;
400 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
401 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
402 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
403 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
404 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
405 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
406 case PIPE_SHADER_CAP_SUBROUTINES:
407 case PIPE_SHADER_CAP_INTEGERS:
408 case PIPE_SHADER_CAP_FP16:
409 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
410 case PIPE_SHADER_CAP_INT16:
411 case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS:
412 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
413 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
414 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
415 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
416 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
417 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
418 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
419 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
420 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
421 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
422 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
423 return 0;
424 default:
425 debug_printf("unknown fragment shader param %d\n", param);
426 return 0;
427 }
428 break;
429 default:
430 return 0;
431 }
432 }
433
434 static bool
435 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
436 enum pipe_format format,
437 enum pipe_texture_target target,
438 unsigned sample_count,
439 unsigned storage_sample_count,
440 unsigned bindings)
441 {
442 if (sample_count > nv30_screen(pscreen)->max_sample_count)
443 return false;
444
445 if (!(0x00000017 & (1 << sample_count)))
446 return false;
447
448 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
449 return false;
450
451 /* No way to render to a swizzled 3d texture. We don't necessarily know if
452 * it's swizzled or not here, but we have to assume anyways.
453 */
454 if (target == PIPE_TEXTURE_3D && (bindings & PIPE_BIND_RENDER_TARGET))
455 return false;
456
457 /* shared is always supported */
458 bindings &= ~PIPE_BIND_SHARED;
459
460 return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
461 }
462
463 static void
464 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
465 {
466 struct nv30_screen *screen = nv30_screen(pscreen);
467 struct nouveau_pushbuf *push = screen->base.pushbuf;
468
469 *sequence = ++screen->base.fence.sequence;
470
471 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
472 PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
473 (2 /* size */ << 18) | (7 /* subchan */ << 13));
474 PUSH_DATA (push, 0);
475 PUSH_DATA (push, *sequence);
476 }
477
478 static uint32_t
479 nv30_screen_fence_update(struct pipe_screen *pscreen)
480 {
481 struct nv30_screen *screen = nv30_screen(pscreen);
482 struct nv04_notify *fence = screen->fence->data;
483 return *(uint32_t *)((char *)screen->notify->map + fence->offset);
484 }
485
486 static void
487 nv30_screen_destroy(struct pipe_screen *pscreen)
488 {
489 struct nv30_screen *screen = nv30_screen(pscreen);
490
491 if (!nouveau_drm_screen_unref(&screen->base))
492 return;
493
494 if (screen->base.fence.current) {
495 struct nouveau_fence *current = NULL;
496
497 /* nouveau_fence_wait will create a new current fence, so wait on the
498 * _current_ one, and remove both.
499 */
500 nouveau_fence_ref(screen->base.fence.current, &current);
501 nouveau_fence_wait(current, NULL);
502 nouveau_fence_ref(NULL, &current);
503 nouveau_fence_ref(NULL, &screen->base.fence.current);
504 }
505
506 nouveau_bo_ref(NULL, &screen->notify);
507
508 nouveau_heap_destroy(&screen->query_heap);
509 nouveau_heap_destroy(&screen->vp_exec_heap);
510 nouveau_heap_destroy(&screen->vp_data_heap);
511
512 nouveau_object_del(&screen->query);
513 nouveau_object_del(&screen->fence);
514 nouveau_object_del(&screen->ntfy);
515
516 nouveau_object_del(&screen->sifm);
517 nouveau_object_del(&screen->swzsurf);
518 nouveau_object_del(&screen->surf2d);
519 nouveau_object_del(&screen->m2mf);
520 nouveau_object_del(&screen->eng3d);
521 nouveau_object_del(&screen->null);
522
523 nouveau_screen_fini(&screen->base);
524 FREE(screen);
525 }
526
527 #define FAIL_SCREEN_INIT(str, err) \
528 do { \
529 NOUVEAU_ERR(str, err); \
530 screen->base.base.context_create = NULL; \
531 return &screen->base; \
532 } while(0)
533
534 struct nouveau_screen *
535 nv30_screen_create(struct nouveau_device *dev)
536 {
537 struct nv30_screen *screen;
538 struct pipe_screen *pscreen;
539 struct nouveau_pushbuf *push;
540 struct nv04_fifo *fifo;
541 unsigned oclass = 0;
542 int ret, i;
543
544 switch (dev->chipset & 0xf0) {
545 case 0x30:
546 if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
547 oclass = NV30_3D_CLASS;
548 else
549 if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
550 oclass = NV34_3D_CLASS;
551 else
552 if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
553 oclass = NV35_3D_CLASS;
554 break;
555 case 0x40:
556 if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
557 oclass = NV40_3D_CLASS;
558 else
559 if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
560 oclass = NV44_3D_CLASS;
561 break;
562 case 0x60:
563 if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
564 oclass = NV44_3D_CLASS;
565 break;
566 default:
567 break;
568 }
569
570 if (!oclass) {
571 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
572 return NULL;
573 }
574
575 screen = CALLOC_STRUCT(nv30_screen);
576 if (!screen)
577 return NULL;
578
579 pscreen = &screen->base.base;
580 pscreen->destroy = nv30_screen_destroy;
581
582 /*
583 * Some modern apps try to use msaa without keeping in mind the
584 * restrictions on videomem of older cards. Resulting in dmesg saying:
585 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
586 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
587 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
588 *
589 * Because we are running out of video memory, after which the program
590 * using the msaa visual freezes, and eventually the entire system freezes.
591 *
592 * To work around this we do not allow msaa visauls by default and allow
593 * the user to override this via NV30_MAX_MSAA.
594 */
595 screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
596 if (screen->max_sample_count > 4)
597 screen->max_sample_count = 4;
598
599 pscreen->get_param = nv30_screen_get_param;
600 pscreen->get_paramf = nv30_screen_get_paramf;
601 pscreen->get_shader_param = nv30_screen_get_shader_param;
602 pscreen->context_create = nv30_context_create;
603 pscreen->is_format_supported = nv30_screen_is_format_supported;
604 nv30_resource_screen_init(pscreen);
605 nouveau_screen_init_vdec(&screen->base);
606
607 screen->base.fence.emit = nv30_screen_fence_emit;
608 screen->base.fence.update = nv30_screen_fence_update;
609
610 ret = nouveau_screen_init(&screen->base, dev);
611 if (ret)
612 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
613
614 screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
615 screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
616 if (oclass == NV40_3D_CLASS) {
617 screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
618 screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
619 }
620
621 fifo = screen->base.channel->data;
622 push = screen->base.pushbuf;
623 push->rsvd_kick = 16;
624
625 ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
626 NULL, 0, &screen->null);
627 if (ret)
628 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
629
630 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
631 * this means that the address pointed at by the DMA object must
632 * be 4KiB aligned, which means this object needs to be the first
633 * one allocated on the channel.
634 */
635 ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
636 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
637 .length = 32 }, sizeof(struct nv04_notify),
638 &screen->fence);
639 if (ret)
640 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
641
642 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
643 ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
644 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
645 .length = 32 }, sizeof(struct nv04_notify),
646 &screen->ntfy);
647 if (ret)
648 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
649
650 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
651 * the remainder of the "notifier block" assigned by the kernel for
652 * use as query objects
653 */
654 ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
655 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
656 .length = 4096 - 128 }, sizeof(struct nv04_notify),
657 &screen->query);
658 if (ret)
659 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
660
661 ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
662 if (ret)
663 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
664
665 list_inithead(&screen->queries);
666
667 /* Vertex program resources (code/data), currently 6 of the constant
668 * slots are reserved to implement user clipping planes
669 */
670 if (oclass < NV40_3D_CLASS) {
671 nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
672 nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
673 } else {
674 nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
675 nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
676 }
677
678 ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
679 if (ret == 0)
680 ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
681 if (ret)
682 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
683
684 ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
685 NULL, 0, &screen->eng3d);
686 if (ret)
687 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
688
689 BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
690 PUSH_DATA (push, screen->eng3d->handle);
691 BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
692 PUSH_DATA (push, screen->ntfy->handle);
693 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */
694 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */
695 PUSH_DATA (push, fifo->vram); /* COLOR1 */
696 PUSH_DATA (push, screen->null->handle); /* UNK190 */
697 PUSH_DATA (push, fifo->vram); /* COLOR0 */
698 PUSH_DATA (push, fifo->vram); /* ZETA */
699 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */
700 PUSH_DATA (push, fifo->gart); /* VTXBUF1 */
701 PUSH_DATA (push, screen->fence->handle); /* FENCE */
702 PUSH_DATA (push, screen->query->handle); /* QUERY - intr 0x80 if nullobj */
703 PUSH_DATA (push, screen->null->handle); /* UNK1AC */
704 PUSH_DATA (push, screen->null->handle); /* UNK1B0 */
705 if (screen->eng3d->oclass < NV40_3D_CLASS) {
706 BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
707 PUSH_DATA (push, 0x00100000);
708 BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
709 PUSH_DATA (push, 3);
710
711 BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
712 PUSH_DATA (push, 0);
713 BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
714 PUSH_DATA (push, fui(0.0));
715 PUSH_DATA (push, fui(0.0));
716 PUSH_DATA (push, fui(1.0));
717 BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
718 for (i = 0; i < 16; i++)
719 PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
720
721 BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
722 PUSH_DATA (push, 0);
723 } else {
724 BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
725 PUSH_DATA (push, fifo->vram);
726 PUSH_DATA (push, fifo->vram); /* COLOR3 */
727
728 BEGIN_NV04(push, SUBC_3D(0x1450), 1);
729 PUSH_DATA (push, 0x00000004);
730
731 BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
732 PUSH_DATA (push, 0x00000010);
733 PUSH_DATA (push, 0x01000100);
734 PUSH_DATA (push, 0xff800006);
735
736 /* vtxprog output routing */
737 BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
738 PUSH_DATA (push, 0x06144321);
739 BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
740 PUSH_DATA (push, 0xedcba987);
741 PUSH_DATA (push, 0x0000006f);
742 BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
743 PUSH_DATA (push, 0x00171615);
744 BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
745 PUSH_DATA (push, 0x001b1a19);
746
747 BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
748 PUSH_DATA (push, 0x0020ffff);
749 BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
750 PUSH_DATA (push, 0x01d300d4);
751
752 BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
753 PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
754 }
755
756 ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
757 NULL, 0, &screen->m2mf);
758 if (ret)
759 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
760
761 BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
762 PUSH_DATA (push, screen->m2mf->handle);
763 BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
764 PUSH_DATA (push, screen->ntfy->handle);
765
766 ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
767 NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
768 if (ret)
769 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
770
771 BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
772 PUSH_DATA (push, screen->surf2d->handle);
773 BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
774 PUSH_DATA (push, screen->ntfy->handle);
775
776 if (dev->chipset < 0x40)
777 oclass = NV30_SURFACE_SWZ_CLASS;
778 else
779 oclass = NV40_SURFACE_SWZ_CLASS;
780
781 ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
782 NULL, 0, &screen->swzsurf);
783 if (ret)
784 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
785
786 BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
787 PUSH_DATA (push, screen->swzsurf->handle);
788 BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
789 PUSH_DATA (push, screen->ntfy->handle);
790
791 if (dev->chipset < 0x40)
792 oclass = NV30_SIFM_CLASS;
793 else
794 oclass = NV40_SIFM_CLASS;
795
796 ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
797 NULL, 0, &screen->sifm);
798 if (ret)
799 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
800
801 BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
802 PUSH_DATA (push, screen->sifm->handle);
803 BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
804 PUSH_DATA (push, screen->ntfy->handle);
805 BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
806 PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
807
808 nouveau_pushbuf_kick(push, push->channel);
809
810 nouveau_fence_new(&screen->base, &screen->base.fence.current);
811 return &screen->base;
812 }