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bd25819b7177bb495e764ee30046ab537cfaf365
[mesa.git] / src / gallium / drivers / nouveau / nv30 / nv30_screen.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26 #include <xf86drm.h>
27 #include <nouveau_drm.h>
28 #include "util/u_format.h"
29 #include "util/u_format_s3tc.h"
30 #include "util/u_screen.h"
31
32 #include "nv_object.xml.h"
33 #include "nv_m2mf.xml.h"
34 #include "nv30/nv30-40_3d.xml.h"
35 #include "nv30/nv01_2d.xml.h"
36
37 #include "nouveau_fence.h"
38 #include "nv30/nv30_screen.h"
39 #include "nv30/nv30_context.h"
40 #include "nv30/nv30_resource.h"
41 #include "nv30/nv30_format.h"
42
43 #define RANKINE_0397_CHIPSET 0x00000003
44 #define RANKINE_0497_CHIPSET 0x000001e0
45 #define RANKINE_0697_CHIPSET 0x00000010
46 #define CURIE_4097_CHIPSET 0x00000baf
47 #define CURIE_4497_CHIPSET 0x00005450
48 #define CURIE_4497_CHIPSET6X 0x00000088
49
50 static int
51 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
52 {
53 struct nv30_screen *screen = nv30_screen(pscreen);
54 struct nouveau_object *eng3d = screen->eng3d;
55 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
56
57 switch (param) {
58 /* non-boolean capabilities */
59 case PIPE_CAP_MAX_RENDER_TARGETS:
60 return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
61 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
62 return 4096;
63 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
64 return 10;
65 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
66 return 13;
67 case PIPE_CAP_GLSL_FEATURE_LEVEL:
68 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
69 return 120;
70 case PIPE_CAP_ENDIANNESS:
71 return PIPE_ENDIAN_LITTLE;
72 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
73 return 16;
74 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
75 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
76 case PIPE_CAP_MAX_VIEWPORTS:
77 return 1;
78 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
79 return 2048;
80 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
81 return 8 * 1024 * 1024;
82 case PIPE_CAP_MAX_VARYINGS:
83 return 8;
84
85 /* supported capabilities */
86 case PIPE_CAP_ANISOTROPIC_FILTER:
87 case PIPE_CAP_POINT_SPRITE:
88 case PIPE_CAP_OCCLUSION_QUERY:
89 case PIPE_CAP_QUERY_TIME_ELAPSED:
90 case PIPE_CAP_QUERY_TIMESTAMP:
91 case PIPE_CAP_TEXTURE_SWIZZLE:
92 case PIPE_CAP_DEPTH_CLIP_DISABLE:
93 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
94 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
95 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
96 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
97 case PIPE_CAP_TGSI_TEXCOORD:
98 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
99 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
100 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
101 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
102 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
103 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
104 return 1;
105 /* nv35 capabilities */
106 case PIPE_CAP_DEPTH_BOUNDS_TEST:
107 return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
108 /* nv4x capabilities */
109 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
110 case PIPE_CAP_NPOT_TEXTURES:
111 case PIPE_CAP_CONDITIONAL_RENDER:
112 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
113 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
114 case PIPE_CAP_PRIMITIVE_RESTART:
115 return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
116 /* unsupported */
117 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
118 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
119 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
120 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
121 case PIPE_CAP_VERTEX_SHADER_SATURATE:
122 case PIPE_CAP_INDEP_BLEND_ENABLE:
123 case PIPE_CAP_INDEP_BLEND_FUNC:
124 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
125 case PIPE_CAP_SHADER_STENCIL_EXPORT:
126 case PIPE_CAP_TGSI_INSTANCEID:
127 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
128 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
129 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
130 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
131 case PIPE_CAP_MIN_TEXEL_OFFSET:
132 case PIPE_CAP_MAX_TEXEL_OFFSET:
133 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
134 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
135 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
136 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
137 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
138 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
139 case PIPE_CAP_MAX_VERTEX_STREAMS:
140 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
141 case PIPE_CAP_TEXTURE_BARRIER:
142 case PIPE_CAP_SEAMLESS_CUBE_MAP:
143 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
144 case PIPE_CAP_CUBE_MAP_ARRAY:
145 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
146 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
147 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
148 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
149 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
150 case PIPE_CAP_START_INSTANCE:
151 case PIPE_CAP_TEXTURE_MULTISAMPLE:
152 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
153 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
154 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
155 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
156 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
157 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
158 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
159 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
160 case PIPE_CAP_TEXTURE_GATHER_SM5:
161 case PIPE_CAP_FAKE_SW_MSAA:
162 case PIPE_CAP_TEXTURE_QUERY_LOD:
163 case PIPE_CAP_SAMPLE_SHADING:
164 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
165 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
166 case PIPE_CAP_USER_VERTEX_BUFFERS:
167 case PIPE_CAP_COMPUTE:
168 case PIPE_CAP_DRAW_INDIRECT:
169 case PIPE_CAP_MULTI_DRAW_INDIRECT:
170 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
171 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
172 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
173 case PIPE_CAP_SAMPLER_VIEW_TARGET:
174 case PIPE_CAP_CLIP_HALFZ:
175 case PIPE_CAP_VERTEXID_NOBASE:
176 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
177 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
178 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
179 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
180 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
181 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
182 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
183 case PIPE_CAP_TGSI_TXQS:
184 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
185 case PIPE_CAP_SHAREABLE_SHADERS:
186 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
187 case PIPE_CAP_CLEAR_TEXTURE:
188 case PIPE_CAP_DRAW_PARAMETERS:
189 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
190 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
191 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
192 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
193 case PIPE_CAP_INVALIDATE_BUFFER:
194 case PIPE_CAP_GENERATE_MIPMAP:
195 case PIPE_CAP_STRING_MARKER:
196 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
197 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
198 case PIPE_CAP_QUERY_BUFFER_OBJECT:
199 case PIPE_CAP_QUERY_MEMORY_INFO:
200 case PIPE_CAP_PCI_GROUP:
201 case PIPE_CAP_PCI_BUS:
202 case PIPE_CAP_PCI_DEVICE:
203 case PIPE_CAP_PCI_FUNCTION:
204 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
205 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
206 case PIPE_CAP_CULL_DISTANCE:
207 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
208 case PIPE_CAP_TGSI_VOTE:
209 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
210 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
211 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
212 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
213 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
214 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
215 case PIPE_CAP_NATIVE_FENCE_FD:
216 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
217 case PIPE_CAP_FBFETCH:
218 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
219 case PIPE_CAP_DOUBLES:
220 case PIPE_CAP_INT64:
221 case PIPE_CAP_INT64_DIVMOD:
222 case PIPE_CAP_TGSI_TEX_TXF_LZ:
223 case PIPE_CAP_TGSI_CLOCK:
224 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
225 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
226 case PIPE_CAP_TGSI_BALLOT:
227 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
228 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
229 case PIPE_CAP_POST_DEPTH_COVERAGE:
230 case PIPE_CAP_BINDLESS_TEXTURE:
231 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
232 case PIPE_CAP_QUERY_SO_OVERFLOW:
233 case PIPE_CAP_MEMOBJ:
234 case PIPE_CAP_LOAD_CONSTBUF:
235 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
236 case PIPE_CAP_TILE_RASTER_ORDER:
237 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
238 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
239 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
240 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
241 case PIPE_CAP_FENCE_SIGNAL:
242 case PIPE_CAP_CONSTBUF0_FLAGS:
243 case PIPE_CAP_PACKED_UNIFORMS:
244 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
245 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
246 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
247 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
248 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
249 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
250 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
251 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
252 case PIPE_CAP_TGSI_DIV:
253 case PIPE_CAP_TGSI_ATOMINC_WRAP:
254 return 0;
255
256 case PIPE_CAP_MAX_GS_INVOCATIONS:
257 return 32;
258 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
259 return 1 << 27;
260 case PIPE_CAP_VENDOR_ID:
261 return 0x10de;
262 case PIPE_CAP_DEVICE_ID: {
263 uint64_t device_id;
264 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
265 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
266 return -1;
267 }
268 return device_id;
269 }
270 case PIPE_CAP_ACCELERATED:
271 return 1;
272 case PIPE_CAP_VIDEO_MEMORY:
273 return dev->vram_size >> 20;
274 case PIPE_CAP_UMA:
275 return 0;
276 default:
277 return u_pipe_screen_get_param_defaults(pscreen, param);
278 }
279 }
280
281 static float
282 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
283 {
284 struct nv30_screen *screen = nv30_screen(pscreen);
285 struct nouveau_object *eng3d = screen->eng3d;
286
287 switch (param) {
288 case PIPE_CAPF_MAX_LINE_WIDTH:
289 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
290 return 10.0;
291 case PIPE_CAPF_MAX_POINT_WIDTH:
292 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
293 return 64.0;
294 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
295 return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
296 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
297 return 15.0;
298 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
299 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
300 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
301 return 0.0;
302 default:
303 debug_printf("unknown paramf %d\n", param);
304 return 0;
305 }
306 }
307
308 static int
309 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
310 enum pipe_shader_type shader,
311 enum pipe_shader_cap param)
312 {
313 struct nv30_screen *screen = nv30_screen(pscreen);
314 struct nouveau_object *eng3d = screen->eng3d;
315
316 switch (shader) {
317 case PIPE_SHADER_VERTEX:
318 switch (param) {
319 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
320 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
321 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
322 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
323 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
324 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
325 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
326 return 0;
327 case PIPE_SHADER_CAP_MAX_INPUTS:
328 case PIPE_SHADER_CAP_MAX_OUTPUTS:
329 return 16;
330 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
331 return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
332 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
333 return 1;
334 case PIPE_SHADER_CAP_MAX_TEMPS:
335 return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
336 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
337 return 32;
338 case PIPE_SHADER_CAP_PREFERRED_IR:
339 return PIPE_SHADER_IR_TGSI;
340 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
341 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
342 return 0;
343 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
344 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
345 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
346 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
347 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
348 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
349 case PIPE_SHADER_CAP_SUBROUTINES:
350 case PIPE_SHADER_CAP_INTEGERS:
351 case PIPE_SHADER_CAP_INT64_ATOMICS:
352 case PIPE_SHADER_CAP_FP16:
353 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
354 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
355 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
356 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
357 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
358 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
359 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
360 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
361 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
362 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
363 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
364 return 0;
365 default:
366 debug_printf("unknown vertex shader param %d\n", param);
367 return 0;
368 }
369 break;
370 case PIPE_SHADER_FRAGMENT:
371 switch (param) {
372 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
373 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
374 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
375 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
376 return 4096;
377 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
378 return 0;
379 case PIPE_SHADER_CAP_MAX_INPUTS:
380 return 8; /* should be possible to do 10 with nv4x */
381 case PIPE_SHADER_CAP_MAX_OUTPUTS:
382 return 4;
383 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
384 return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
385 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
386 return 1;
387 case PIPE_SHADER_CAP_MAX_TEMPS:
388 return 32;
389 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
390 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
391 return 16;
392 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
393 return 32;
394 case PIPE_SHADER_CAP_PREFERRED_IR:
395 return PIPE_SHADER_IR_TGSI;
396 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
397 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
398 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
399 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
400 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
401 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
402 case PIPE_SHADER_CAP_SUBROUTINES:
403 case PIPE_SHADER_CAP_INTEGERS:
404 case PIPE_SHADER_CAP_FP16:
405 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
406 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
407 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
408 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
409 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
410 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
411 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
412 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
413 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
414 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
415 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
416 return 0;
417 default:
418 debug_printf("unknown fragment shader param %d\n", param);
419 return 0;
420 }
421 break;
422 default:
423 return 0;
424 }
425 }
426
427 static bool
428 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
429 enum pipe_format format,
430 enum pipe_texture_target target,
431 unsigned sample_count,
432 unsigned storage_sample_count,
433 unsigned bindings)
434 {
435 if (sample_count > nv30_screen(pscreen)->max_sample_count)
436 return false;
437
438 if (!(0x00000017 & (1 << sample_count)))
439 return false;
440
441 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
442 return false;
443
444 /* No way to render to a swizzled 3d texture. We don't necessarily know if
445 * it's swizzled or not here, but we have to assume anyways.
446 */
447 if (target == PIPE_TEXTURE_3D && (bindings & PIPE_BIND_RENDER_TARGET))
448 return false;
449
450 /* shared is always supported */
451 bindings &= ~PIPE_BIND_SHARED;
452
453 return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
454 }
455
456 static void
457 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
458 {
459 struct nv30_screen *screen = nv30_screen(pscreen);
460 struct nouveau_pushbuf *push = screen->base.pushbuf;
461
462 *sequence = ++screen->base.fence.sequence;
463
464 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
465 PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
466 (2 /* size */ << 18) | (7 /* subchan */ << 13));
467 PUSH_DATA (push, 0);
468 PUSH_DATA (push, *sequence);
469 }
470
471 static uint32_t
472 nv30_screen_fence_update(struct pipe_screen *pscreen)
473 {
474 struct nv30_screen *screen = nv30_screen(pscreen);
475 struct nv04_notify *fence = screen->fence->data;
476 return *(uint32_t *)((char *)screen->notify->map + fence->offset);
477 }
478
479 static void
480 nv30_screen_destroy(struct pipe_screen *pscreen)
481 {
482 struct nv30_screen *screen = nv30_screen(pscreen);
483
484 if (!nouveau_drm_screen_unref(&screen->base))
485 return;
486
487 if (screen->base.fence.current) {
488 struct nouveau_fence *current = NULL;
489
490 /* nouveau_fence_wait will create a new current fence, so wait on the
491 * _current_ one, and remove both.
492 */
493 nouveau_fence_ref(screen->base.fence.current, &current);
494 nouveau_fence_wait(current, NULL);
495 nouveau_fence_ref(NULL, &current);
496 nouveau_fence_ref(NULL, &screen->base.fence.current);
497 }
498
499 nouveau_bo_ref(NULL, &screen->notify);
500
501 nouveau_heap_destroy(&screen->query_heap);
502 nouveau_heap_destroy(&screen->vp_exec_heap);
503 nouveau_heap_destroy(&screen->vp_data_heap);
504
505 nouveau_object_del(&screen->query);
506 nouveau_object_del(&screen->fence);
507 nouveau_object_del(&screen->ntfy);
508
509 nouveau_object_del(&screen->sifm);
510 nouveau_object_del(&screen->swzsurf);
511 nouveau_object_del(&screen->surf2d);
512 nouveau_object_del(&screen->m2mf);
513 nouveau_object_del(&screen->eng3d);
514 nouveau_object_del(&screen->null);
515
516 nouveau_screen_fini(&screen->base);
517 FREE(screen);
518 }
519
520 #define FAIL_SCREEN_INIT(str, err) \
521 do { \
522 NOUVEAU_ERR(str, err); \
523 screen->base.base.context_create = NULL; \
524 return &screen->base; \
525 } while(0)
526
527 struct nouveau_screen *
528 nv30_screen_create(struct nouveau_device *dev)
529 {
530 struct nv30_screen *screen;
531 struct pipe_screen *pscreen;
532 struct nouveau_pushbuf *push;
533 struct nv04_fifo *fifo;
534 unsigned oclass = 0;
535 int ret, i;
536
537 switch (dev->chipset & 0xf0) {
538 case 0x30:
539 if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
540 oclass = NV30_3D_CLASS;
541 else
542 if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
543 oclass = NV34_3D_CLASS;
544 else
545 if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
546 oclass = NV35_3D_CLASS;
547 break;
548 case 0x40:
549 if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
550 oclass = NV40_3D_CLASS;
551 else
552 if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
553 oclass = NV44_3D_CLASS;
554 break;
555 case 0x60:
556 if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
557 oclass = NV44_3D_CLASS;
558 break;
559 default:
560 break;
561 }
562
563 if (!oclass) {
564 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
565 return NULL;
566 }
567
568 screen = CALLOC_STRUCT(nv30_screen);
569 if (!screen)
570 return NULL;
571
572 pscreen = &screen->base.base;
573 pscreen->destroy = nv30_screen_destroy;
574
575 /*
576 * Some modern apps try to use msaa without keeping in mind the
577 * restrictions on videomem of older cards. Resulting in dmesg saying:
578 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
579 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
580 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
581 *
582 * Because we are running out of video memory, after which the program
583 * using the msaa visual freezes, and eventually the entire system freezes.
584 *
585 * To work around this we do not allow msaa visauls by default and allow
586 * the user to override this via NV30_MAX_MSAA.
587 */
588 screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
589 if (screen->max_sample_count > 4)
590 screen->max_sample_count = 4;
591
592 pscreen->get_param = nv30_screen_get_param;
593 pscreen->get_paramf = nv30_screen_get_paramf;
594 pscreen->get_shader_param = nv30_screen_get_shader_param;
595 pscreen->context_create = nv30_context_create;
596 pscreen->is_format_supported = nv30_screen_is_format_supported;
597 nv30_resource_screen_init(pscreen);
598 nouveau_screen_init_vdec(&screen->base);
599
600 screen->base.fence.emit = nv30_screen_fence_emit;
601 screen->base.fence.update = nv30_screen_fence_update;
602
603 ret = nouveau_screen_init(&screen->base, dev);
604 if (ret)
605 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
606
607 screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
608 screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
609 if (oclass == NV40_3D_CLASS) {
610 screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
611 screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
612 }
613
614 fifo = screen->base.channel->data;
615 push = screen->base.pushbuf;
616 push->rsvd_kick = 16;
617
618 ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
619 NULL, 0, &screen->null);
620 if (ret)
621 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
622
623 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
624 * this means that the address pointed at by the DMA object must
625 * be 4KiB aligned, which means this object needs to be the first
626 * one allocated on the channel.
627 */
628 ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
629 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
630 .length = 32 }, sizeof(struct nv04_notify),
631 &screen->fence);
632 if (ret)
633 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
634
635 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
636 ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
637 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
638 .length = 32 }, sizeof(struct nv04_notify),
639 &screen->ntfy);
640 if (ret)
641 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
642
643 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
644 * the remainder of the "notifier block" assigned by the kernel for
645 * use as query objects
646 */
647 ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
648 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
649 .length = 4096 - 128 }, sizeof(struct nv04_notify),
650 &screen->query);
651 if (ret)
652 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
653
654 ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
655 if (ret)
656 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
657
658 LIST_INITHEAD(&screen->queries);
659
660 /* Vertex program resources (code/data), currently 6 of the constant
661 * slots are reserved to implement user clipping planes
662 */
663 if (oclass < NV40_3D_CLASS) {
664 nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
665 nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
666 } else {
667 nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
668 nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
669 }
670
671 ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
672 if (ret == 0)
673 ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
674 if (ret)
675 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
676
677 ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
678 NULL, 0, &screen->eng3d);
679 if (ret)
680 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
681
682 BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
683 PUSH_DATA (push, screen->eng3d->handle);
684 BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
685 PUSH_DATA (push, screen->ntfy->handle);
686 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */
687 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */
688 PUSH_DATA (push, fifo->vram); /* COLOR1 */
689 PUSH_DATA (push, screen->null->handle); /* UNK190 */
690 PUSH_DATA (push, fifo->vram); /* COLOR0 */
691 PUSH_DATA (push, fifo->vram); /* ZETA */
692 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */
693 PUSH_DATA (push, fifo->gart); /* VTXBUF1 */
694 PUSH_DATA (push, screen->fence->handle); /* FENCE */
695 PUSH_DATA (push, screen->query->handle); /* QUERY - intr 0x80 if nullobj */
696 PUSH_DATA (push, screen->null->handle); /* UNK1AC */
697 PUSH_DATA (push, screen->null->handle); /* UNK1B0 */
698 if (screen->eng3d->oclass < NV40_3D_CLASS) {
699 BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
700 PUSH_DATA (push, 0x00100000);
701 BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
702 PUSH_DATA (push, 3);
703
704 BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
705 PUSH_DATA (push, 0);
706 BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
707 PUSH_DATA (push, fui(0.0));
708 PUSH_DATA (push, fui(0.0));
709 PUSH_DATA (push, fui(1.0));
710 BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
711 for (i = 0; i < 16; i++)
712 PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
713
714 BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
715 PUSH_DATA (push, 0);
716 } else {
717 BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
718 PUSH_DATA (push, fifo->vram);
719 PUSH_DATA (push, fifo->vram); /* COLOR3 */
720
721 BEGIN_NV04(push, SUBC_3D(0x1450), 1);
722 PUSH_DATA (push, 0x00000004);
723
724 BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
725 PUSH_DATA (push, 0x00000010);
726 PUSH_DATA (push, 0x01000100);
727 PUSH_DATA (push, 0xff800006);
728
729 /* vtxprog output routing */
730 BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
731 PUSH_DATA (push, 0x06144321);
732 BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
733 PUSH_DATA (push, 0xedcba987);
734 PUSH_DATA (push, 0x0000006f);
735 BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
736 PUSH_DATA (push, 0x00171615);
737 BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
738 PUSH_DATA (push, 0x001b1a19);
739
740 BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
741 PUSH_DATA (push, 0x0020ffff);
742 BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
743 PUSH_DATA (push, 0x01d300d4);
744
745 BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
746 PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
747 }
748
749 ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
750 NULL, 0, &screen->m2mf);
751 if (ret)
752 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
753
754 BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
755 PUSH_DATA (push, screen->m2mf->handle);
756 BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
757 PUSH_DATA (push, screen->ntfy->handle);
758
759 ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
760 NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
761 if (ret)
762 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
763
764 BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
765 PUSH_DATA (push, screen->surf2d->handle);
766 BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
767 PUSH_DATA (push, screen->ntfy->handle);
768
769 if (dev->chipset < 0x40)
770 oclass = NV30_SURFACE_SWZ_CLASS;
771 else
772 oclass = NV40_SURFACE_SWZ_CLASS;
773
774 ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
775 NULL, 0, &screen->swzsurf);
776 if (ret)
777 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
778
779 BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
780 PUSH_DATA (push, screen->swzsurf->handle);
781 BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
782 PUSH_DATA (push, screen->ntfy->handle);
783
784 if (dev->chipset < 0x40)
785 oclass = NV30_SIFM_CLASS;
786 else
787 oclass = NV40_SIFM_CLASS;
788
789 ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
790 NULL, 0, &screen->sifm);
791 if (ret)
792 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
793
794 BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
795 PUSH_DATA (push, screen->sifm->handle);
796 BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
797 PUSH_DATA (push, screen->ntfy->handle);
798 BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
799 PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
800
801 nouveau_pushbuf_kick(push, push->channel);
802
803 nouveau_fence_new(&screen->base, &screen->base.fence.current);
804 return &screen->base;
805 }