src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/format/u_format.h"
  27 #include "util/format/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30 #include "compiler/nir/nir.h"
  31
  32 #include "nv50/nv50_context.h"
  33 #include "nv50/nv50_screen.h"
  34
  35 #include "nouveau_vp3_video.h"
  36
  37 #include "nv_object.xml.h"
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 static bool
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned storage_sample_count,
  52                                 unsigned bindings)
  53 {
  54    if (sample_count > 8)
  55       return false;
  56    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  57       return false;
  58    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  59       return false;
  60
  61    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  62       return false;
  63
  64    switch (format) {
  65    case PIPE_FORMAT_Z16_UNORM:
  66       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  67          return false;
  68       break;
  69    default:
  70       break;
  71    }
  72
  73    if (bindings & PIPE_BIND_LINEAR)
  74       if (util_format_is_depth_or_stencil(format) ||
  75           (target != PIPE_TEXTURE_1D &&
  76            target != PIPE_TEXTURE_2D &&
  77            target != PIPE_TEXTURE_RECT) ||
  78           sample_count > 1)
  79          return false;
  80
  81    /* shared is always supported */
  82    bindings &= ~(PIPE_BIND_LINEAR |
  83                  PIPE_BIND_SHARED);
  84
  85    return (( nv50_format_table[format].usage |
  86             nv50_vertex_format[format].usage) & bindings) == bindings;
  87 }
  88
  89 static int
  90 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  91 {
  92    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  93    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  94
  95    switch (param) {
  96    /* non-boolean caps */
  97    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
  98       return 8192;
  99    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 100       return 12;
 101    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 102       return 14;
 103    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 104       return 512;
 105    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MIN_TEXEL_OFFSET:
 107       return -8;
 108    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 109    case PIPE_CAP_MAX_TEXEL_OFFSET:
 110       return 7;
 111    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 112       return 128 * 1024 * 1024;
 113    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 114       return 330;
 115    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 116       return 330;
 117    case PIPE_CAP_MAX_RENDER_TARGETS:
 118       return 8;
 119    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 120       return 1;
 121    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 122    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 123       return 8;
 124    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 125       return 4;
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 128       return 64;
 129    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 130    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 131       return 1024;
 132    case PIPE_CAP_MAX_VERTEX_STREAMS:
 133       return 1;
 134    case PIPE_CAP_MAX_GS_INVOCATIONS:
 135       return 0;
 136    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 137       return 0;
 138    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 139       return 2048;
 140    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 141       return 2047;
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145       return 16; /* 256 for binding as RT, but that's not possible in GL */
 146    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 147       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 148    case PIPE_CAP_MAX_VIEWPORTS:
 149       return NV50_MAX_VIEWPORTS;
 150    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 151       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 152    case PIPE_CAP_ENDIANNESS:
 153       return PIPE_ENDIAN_LITTLE;
 154    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 155       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 156    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 157       return NV50_MAX_WINDOW_RECTANGLES;
 158    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 159       return 16 * 1024 * 1024;
 160    case PIPE_CAP_MAX_VARYINGS:
 161       return 15;
 162    case PIPE_CAP_MAX_VERTEX_BUFFERS:
 163       return 16;
 164    case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
 165       return 512 * 1024; /* TODO: Investigate tuning this */
 166
 167    /* supported caps */
 168    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 169    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 170    case PIPE_CAP_TEXTURE_SWIZZLE:
 171    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 172    case PIPE_CAP_NPOT_TEXTURES:
 173    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 174    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 175    case PIPE_CAP_ANISOTROPIC_FILTER:
 176    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 177    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 178    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 179    case PIPE_CAP_POINT_SPRITE:
 180    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 181    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 182    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 183    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 184    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 185    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 186    case PIPE_CAP_QUERY_TIMESTAMP:
 187    case PIPE_CAP_QUERY_TIME_ELAPSED:
 188    case PIPE_CAP_OCCLUSION_QUERY:
 189    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 190    case PIPE_CAP_INDEP_BLEND_ENABLE:
 191    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 192    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 193    case PIPE_CAP_PRIMITIVE_RESTART:
 194    case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
 195    case PIPE_CAP_TGSI_INSTANCEID:
 196    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 197    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 198    case PIPE_CAP_CONDITIONAL_RENDER:
 199    case PIPE_CAP_TEXTURE_BARRIER:
 200    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 201    case PIPE_CAP_START_INSTANCE:
 202    case PIPE_CAP_USER_VERTEX_BUFFERS:
 203    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 204    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 205    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 206    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 207    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 208    case PIPE_CAP_CLIP_HALFZ:
 209    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 210    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 211    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 212    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 213    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 214    case PIPE_CAP_TGSI_TXQS:
 215    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 216    case PIPE_CAP_SHAREABLE_SHADERS:
 217    case PIPE_CAP_CLEAR_TEXTURE:
 218    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 219    case PIPE_CAP_INVALIDATE_BUFFER:
 220    case PIPE_CAP_STRING_MARKER:
 221    case PIPE_CAP_CULL_DISTANCE:
 222    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 223    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 224    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 225    case PIPE_CAP_TGSI_CLOCK:
 226    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 227    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 228    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 229    case PIPE_CAP_TGSI_DIV:
 230    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 231    case PIPE_CAP_FLATSHADE:
 232    case PIPE_CAP_ALPHA_TEST:
 233    case PIPE_CAP_POINT_SIZE_FIXED:
 234    case PIPE_CAP_TWO_SIDED_COLOR:
 235    case PIPE_CAP_CLIP_PLANES:
 236    case PIPE_CAP_PACKED_STREAM_OUTPUT:
 237    case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
 238       return 1;
 239    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 240       return 1; /* class_3d >= NVA0_3D_CLASS; */
 241    /* supported on nva0+ */
 242    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 243       return class_3d >= NVA0_3D_CLASS;
 244    /* supported on nva3+ */
 245    case PIPE_CAP_CUBE_MAP_ARRAY:
 246    case PIPE_CAP_INDEP_BLEND_FUNC:
 247    case PIPE_CAP_TEXTURE_QUERY_LOD:
 248    case PIPE_CAP_SAMPLE_SHADING:
 249    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 250       return class_3d >= NVA3_3D_CLASS;
 251
 252    /* unsupported caps */
 253    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 254    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 255    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 256    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 257    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 258    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 259    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 260    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 261    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 262    case PIPE_CAP_TGSI_TEXCOORD:
 263    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 264    case PIPE_CAP_TEXTURE_GATHER_SM5:
 265    case PIPE_CAP_FAKE_SW_MSAA:
 266    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 267    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 268    case PIPE_CAP_DRAW_INDIRECT:
 269    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 270    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 271    case PIPE_CAP_VERTEXID_NOBASE:
 272    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 273    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 274    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 275    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 276    case PIPE_CAP_DRAW_PARAMETERS:
 277    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 278    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 279    case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 280    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 281    case PIPE_CAP_GENERATE_MIPMAP:
 282    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 283    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 284    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 285    case PIPE_CAP_QUERY_MEMORY_INFO:
 286    case PIPE_CAP_PCI_GROUP:
 287    case PIPE_CAP_PCI_BUS:
 288    case PIPE_CAP_PCI_DEVICE:
 289    case PIPE_CAP_PCI_FUNCTION:
 290    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 291    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 292    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 293    case PIPE_CAP_TGSI_VOTE:
 294    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 295    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 296    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 297    case PIPE_CAP_NATIVE_FENCE_FD:
 298    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 299    case PIPE_CAP_FBFETCH:
 300    case PIPE_CAP_DOUBLES:
 301    case PIPE_CAP_INT64:
 302    case PIPE_CAP_INT64_DIVMOD:
 303    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 304    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 305    case PIPE_CAP_TGSI_BALLOT:
 306    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 307    case PIPE_CAP_POST_DEPTH_COVERAGE:
 308    case PIPE_CAP_BINDLESS_TEXTURE:
 309    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 310    case PIPE_CAP_QUERY_SO_OVERFLOW:
 311    case PIPE_CAP_MEMOBJ:
 312    case PIPE_CAP_LOAD_CONSTBUF:
 313    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 314    case PIPE_CAP_TILE_RASTER_ORDER:
 315    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 316    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 317    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 318    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 319    case PIPE_CAP_FENCE_SIGNAL:
 320    case PIPE_CAP_CONSTBUF0_FLAGS:
 321    case PIPE_CAP_PACKED_UNIFORMS:
 322    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 323    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 324    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 325    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 326    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 327    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 328    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 329    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 330    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 331    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 332    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 333    case PIPE_CAP_TGSI_ATOMFADD:
 334    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 335    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 336    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 337    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 338    case PIPE_CAP_COMPUTE:
 339    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 340    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 341    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 342    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 343    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 344    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 345    case PIPE_CAP_FBFETCH_COHERENT:
 346    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 347    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 348    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
 349    case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
 350    case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
 351    case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
 352    case PIPE_CAP_FRONTEND_NOOP:
 353    case PIPE_CAP_GL_SPIRV:
 354    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 355    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 356    case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
 357    case PIPE_CAP_PSIZ_CLAMPED:
 358    case PIPE_CAP_VIEWPORT_SWIZZLE:
 359    case PIPE_CAP_VIEWPORT_MASK:
 360       return 0;
 361
 362    case PIPE_CAP_VENDOR_ID:
 363       return 0x10de;
 364    case PIPE_CAP_DEVICE_ID: {
 365       uint64_t device_id;
 366       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 367          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 368          return -1;
 369       }
 370       return device_id;
 371    }
 372    case PIPE_CAP_ACCELERATED:
 373       return 1;
 374    case PIPE_CAP_VIDEO_MEMORY:
 375       return dev->vram_size >> 20;
 376    case PIPE_CAP_UMA:
 377       return 0;
 378
 379    default:
 380       debug_printf("%s: unhandled cap %d\n", __func__, param);
 381       /* fallthrough */
 382    /* caps where we want the default value */
 383    case PIPE_CAP_DMABUF:
 384    case PIPE_CAP_ESSL_FEATURE_LEVEL:
 385    case PIPE_CAP_THROTTLE:
 386       return u_pipe_screen_get_param_defaults(pscreen, param);
 387    }
 388 }
 389
 390 static int
 391 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 392                              enum pipe_shader_type shader,
 393                              enum pipe_shader_cap param)
 394 {
 395    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 396
 397    switch (shader) {
 398    case PIPE_SHADER_VERTEX:
 399    case PIPE_SHADER_GEOMETRY:
 400    case PIPE_SHADER_FRAGMENT:
 401       break;
 402    case PIPE_SHADER_COMPUTE:
 403    default:
 404       return 0;
 405    }
 406
 407    switch (param) {
 408    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 409    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 410    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 411    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 412       return 16384;
 413    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 414       return 4;
 415    case PIPE_SHADER_CAP_MAX_INPUTS:
 416       if (shader == PIPE_SHADER_VERTEX)
 417          return 32;
 418       return 15;
 419    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 420       return 16;
 421    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 422       return 65536;
 423    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 424       return NV50_MAX_PIPE_CONSTBUFS;
 425    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 426       return shader != PIPE_SHADER_FRAGMENT;
 427    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 428    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 429    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 430       return 1;
 431    case PIPE_SHADER_CAP_MAX_TEMPS:
 432       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 433    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 434       return 1;
 435    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 436       return 1;
 437    case PIPE_SHADER_CAP_INT64_ATOMICS:
 438    case PIPE_SHADER_CAP_FP16:
 439    case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 440    case PIPE_SHADER_CAP_INT16:
 441    case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS:
 442    case PIPE_SHADER_CAP_SUBROUTINES:
 443       return 0; /* please inline, or provide function declarations */
 444    case PIPE_SHADER_CAP_INTEGERS:
 445       return 1;
 446    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 447       return 1;
 448    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 449       /* The chip could handle more sampler views than samplers */
 450    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 451       return MIN2(16, PIPE_MAX_SAMPLERS);
 452    case PIPE_SHADER_CAP_PREFERRED_IR:
 453       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
 454    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 455       return 32;
 456    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 457    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 458    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 459    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 460    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 461    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 462    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 463    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 464    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 465    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 466    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 467       return 0;
 468    default:
 469       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 470       return 0;
 471    }
 472 }
 473
 474 static float
 475 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 476 {
 477    switch (param) {
 478    case PIPE_CAPF_MAX_LINE_WIDTH:
 479    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 480       return 10.0f;
 481    case PIPE_CAPF_MAX_POINT_WIDTH:
 482    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 483       return 64.0f;
 484    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 485       return 16.0f;
 486    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 487       return 15.0f;
 488    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 489    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 490    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 491       return 0.0f;
 492    }
 493
 494    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 495    return 0.0f;
 496 }
 497
 498 static int
 499 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 500                               enum pipe_shader_ir ir_type,
 501                               enum pipe_compute_cap param, void *data)
 502 {
 503    struct nv50_screen *screen = nv50_screen(pscreen);
 504
 505 #define RET(x) do {                  \
 506    if (data)                         \
 507       memcpy(data, x, sizeof(x));    \
 508    return sizeof(x);                 \
 509 } while (0)
 510
 511    switch (param) {
 512    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 513       RET((uint64_t []) { 2 });
 514    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 515       RET(((uint64_t []) { 65535, 65535 }));
 516    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 517       RET(((uint64_t []) { 512, 512, 64 }));
 518    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 519       RET((uint64_t []) { 512 });
 520    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 521       RET((uint64_t []) { 1ULL << 32 });
 522    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 523       RET((uint64_t []) { 16 << 10 });
 524    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 525       RET((uint64_t []) { 16 << 10 });
 526    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 527       RET((uint64_t []) { 4096 });
 528    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 529       RET((uint32_t []) { 32 });
 530    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 531       RET((uint64_t []) { 1ULL << 40 });
 532    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 533       RET((uint32_t []) { 0 });
 534    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 535       RET((uint32_t []) { screen->mp_count });
 536    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 537       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 538    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 539       RET((uint32_t []) { 32 });
 540    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 541       RET((uint64_t []) { 0 });
 542    default:
 543       return 0;
 544    }
 545
 546 #undef RET
 547 }
 548
 549 static void
 550 nv50_screen_destroy(struct pipe_screen *pscreen)
 551 {
 552    struct nv50_screen *screen = nv50_screen(pscreen);
 553
 554    if (!nouveau_drm_screen_unref(&screen->base))
 555       return;
 556
 557    if (screen->base.fence.current) {
 558       struct nouveau_fence *current = NULL;
 559
 560       /* nouveau_fence_wait will create a new current fence, so wait on the
 561        * _current_ one, and remove both.
 562        */
 563       nouveau_fence_ref(screen->base.fence.current, &current);
 564       nouveau_fence_wait(current, NULL);
 565       nouveau_fence_ref(NULL, &current);
 566       nouveau_fence_ref(NULL, &screen->base.fence.current);
 567    }
 568    if (screen->base.pushbuf)
 569       screen->base.pushbuf->user_priv = NULL;
 570
 571    if (screen->blitter)
 572       nv50_blitter_destroy(screen);
 573    if (screen->pm.prog) {
 574       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 575       nv50_program_destroy(NULL, screen->pm.prog);
 576       FREE(screen->pm.prog);
 577    }
 578
 579    nouveau_bo_ref(NULL, &screen->code);
 580    nouveau_bo_ref(NULL, &screen->tls_bo);
 581    nouveau_bo_ref(NULL, &screen->stack_bo);
 582    nouveau_bo_ref(NULL, &screen->txc);
 583    nouveau_bo_ref(NULL, &screen->uniforms);
 584    nouveau_bo_ref(NULL, &screen->fence.bo);
 585
 586    nouveau_heap_destroy(&screen->vp_code_heap);
 587    nouveau_heap_destroy(&screen->gp_code_heap);
 588    nouveau_heap_destroy(&screen->fp_code_heap);
 589
 590    FREE(screen->tic.entries);
 591
 592    nouveau_object_del(&screen->tesla);
 593    nouveau_object_del(&screen->eng2d);
 594    nouveau_object_del(&screen->m2mf);
 595    nouveau_object_del(&screen->compute);
 596    nouveau_object_del(&screen->sync);
 597
 598    nouveau_screen_fini(&screen->base);
 599
 600    FREE(screen);
 601 }
 602
 603 static void
 604 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 605 {
 606    struct nv50_screen *screen = nv50_screen(pscreen);
 607    struct nouveau_pushbuf *push = screen->base.pushbuf;
 608
 609    /* we need to do it after possible flush in MARK_RING */
 610    *sequence = ++screen->base.fence.sequence;
 611
 612    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 613    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 614    PUSH_DATAh(push, screen->fence.bo->offset);
 615    PUSH_DATA (push, screen->fence.bo->offset);
 616    PUSH_DATA (push, *sequence);
 617    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 618                     NV50_3D_QUERY_GET_UNK4 |
 619                     NV50_3D_QUERY_GET_UNIT_CROP |
 620                     NV50_3D_QUERY_GET_TYPE_QUERY |
 621                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 622                     NV50_3D_QUERY_GET_SHORT);
 623 }
 624
 625 static u32
 626 nv50_screen_fence_update(struct pipe_screen *pscreen)
 627 {
 628    return nv50_screen(pscreen)->fence.map[0];
 629 }
 630
 631 static void
 632 nv50_screen_init_hwctx(struct nv50_screen *screen)
 633 {
 634    struct nouveau_pushbuf *push = screen->base.pushbuf;
 635    struct nv04_fifo *fifo;
 636    unsigned i;
 637
 638    fifo = (struct nv04_fifo *)screen->base.channel->data;
 639
 640    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 641    PUSH_DATA (push, screen->m2mf->handle);
 642    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 643    PUSH_DATA (push, screen->sync->handle);
 644    PUSH_DATA (push, fifo->vram);
 645    PUSH_DATA (push, fifo->vram);
 646
 647    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 648    PUSH_DATA (push, screen->eng2d->handle);
 649    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 650    PUSH_DATA (push, screen->sync->handle);
 651    PUSH_DATA (push, fifo->vram);
 652    PUSH_DATA (push, fifo->vram);
 653    PUSH_DATA (push, fifo->vram);
 654    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 655    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 656    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 657    PUSH_DATA (push, 0);
 658    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 659    PUSH_DATA (push, 0);
 660    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 661    PUSH_DATA (push, 1);
 662    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 663    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 664
 665    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 666    PUSH_DATA (push, screen->tesla->handle);
 667
 668    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 669    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 670
 671    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 672    PUSH_DATA (push, screen->sync->handle);
 673    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 674    for (i = 0; i < 11; ++i)
 675       PUSH_DATA(push, fifo->vram);
 676    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 677    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 678       PUSH_DATA(push, fifo->vram);
 679
 680    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 681    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 682    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 683    PUSH_DATA (push, 0xf);
 684
 685    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 686       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 687       PUSH_DATA (push, 0x18);
 688    }
 689
 690    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 691    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 692
 693    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 694    for (i = 0; i < 8; ++i)
 695       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 696
 697    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 698    PUSH_DATA (push, 1);
 699
 700    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 701    PUSH_DATA (push, 0);
 702    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 703    PUSH_DATA (push, 0);
 704    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 705    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 706    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 707    PUSH_DATA (push, 0);
 708    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 709    PUSH_DATA (push, 1);
 710    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 711    PUSH_DATA (push, 1);
 712
 713    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 714       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 715       PUSH_DATA (push, 0);
 716    }
 717
 718    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 719    PUSH_DATA (push, 0);
 720    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 721    PUSH_DATA (push, 0);
 722    PUSH_DATA (push, 0);
 723    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 724    PUSH_DATA (push, 0x3f);
 725
 726    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 727    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 728    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 729
 730    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 731    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 732    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 733
 734    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 735    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 736    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 737
 738    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 739    PUSH_DATAh(push, screen->tls_bo->offset);
 740    PUSH_DATA (push, screen->tls_bo->offset);
 741    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 742
 743    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 744    PUSH_DATAh(push, screen->stack_bo->offset);
 745    PUSH_DATA (push, screen->stack_bo->offset);
 746    PUSH_DATA (push, 4);
 747
 748    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 749    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 750    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 751    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 752
 753    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 754    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 755    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 756    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 757
 758    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 759    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 760    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 761    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 762
 763    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 764    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 765    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 766    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 767
 768    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 769    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 770    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 771    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 772
 773    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 774    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 775    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 776    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 777    PUSH_DATAf(push, 0.0f);
 778    PUSH_DATAf(push, 0.0f);
 779    PUSH_DATAf(push, 0.0f);
 780    PUSH_DATAf(push, 0.0f);
 781    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 782    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 783    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 784
 785    nv50_upload_ms_info(push);
 786
 787    /* max TIC (bits 4:8) & TSC bindings, per program type */
 788    for (i = 0; i < 3; ++i) {
 789       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 790       PUSH_DATA (push, 0x54);
 791    }
 792
 793    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 794    PUSH_DATAh(push, screen->txc->offset);
 795    PUSH_DATA (push, screen->txc->offset);
 796    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 797
 798    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 799    PUSH_DATAh(push, screen->txc->offset + 65536);
 800    PUSH_DATA (push, screen->txc->offset + 65536);
 801    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 802
 803    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 804    PUSH_DATA (push, 0);
 805
 806    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 807    PUSH_DATA (push, 0);
 808    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 809    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 810    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 811    for (i = 0; i < 8 * 2; ++i)
 812       PUSH_DATA(push, 0);
 813    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 814    PUSH_DATA (push, 0);
 815
 816    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 817    PUSH_DATA (push, 1);
 818    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 819       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 820       PUSH_DATAf(push, 0.0f);
 821       PUSH_DATAf(push, 1.0f);
 822       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 823       PUSH_DATA (push, 8192 << 16);
 824       PUSH_DATA (push, 8192 << 16);
 825    }
 826
 827    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 828 #ifdef NV50_SCISSORS_CLIPPING
 829    PUSH_DATA (push, 0x0000);
 830 #else
 831    PUSH_DATA (push, 0x1080);
 832 #endif
 833
 834    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 835    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 836
 837    /* We use scissors instead of exact view volume clipping,
 838     * so they're always enabled.
 839     */
 840    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 841       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 842       PUSH_DATA (push, 1);
 843       PUSH_DATA (push, 8192 << 16);
 844       PUSH_DATA (push, 8192 << 16);
 845    }
 846
 847    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 848    PUSH_DATA (push, 1);
 849    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 850    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 851    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 852    PUSH_DATA (push, 0x11111111);
 853    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 854    PUSH_DATA (push, 1);
 855
 856    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 857    PUSH_DATA (push, 0);
 858    if (screen->base.class_3d >= NV84_3D_CLASS) {
 859       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 860       PUSH_DATA (push, 0);
 861    }
 862
 863    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 864    PUSH_DATA (push, 1);
 865    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 866    PUSH_DATA (push, 1);
 867
 868    PUSH_KICK (push);
 869 }
 870
 871 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 872       uint64_t *tls_size)
 873 {
 874    struct nouveau_device *dev = screen->base.device;
 875    int ret;
 876
 877    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 878          ONE_TEMP_SIZE;
 879    if (nouveau_mesa_debug)
 880       debug_printf("allocating space for %u temps\n",
 881             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 882    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 883          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 884
 885    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 886                         *tls_size, NULL, &screen->tls_bo);
 887    if (ret) {
 888       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 889       return ret;
 890    }
 891
 892    return 0;
 893 }
 894
 895 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 896 {
 897    struct nouveau_pushbuf *push = screen->base.pushbuf;
 898    int ret;
 899    uint64_t tls_size;
 900
 901    if (tls_space < screen->cur_tls_space)
 902       return 0;
 903    if (tls_space > screen->max_tls_space) {
 904       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 905        * LOCAL_WARPS_NO_CLAMP) */
 906       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 907             (unsigned)(tls_space / ONE_TEMP_SIZE),
 908             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 909       return -ENOMEM;
 910    }
 911
 912    nouveau_bo_ref(NULL, &screen->tls_bo);
 913    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 914    if (ret)
 915       return ret;
 916
 917    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 918    PUSH_DATAh(push, screen->tls_bo->offset);
 919    PUSH_DATA (push, screen->tls_bo->offset);
 920    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 921
 922    return 1;
 923 }
 924
 925 static const nir_shader_compiler_options nir_options = {
 926    .fuse_ffma = false, /* nir doesn't track mad vs fma */
 927    .lower_flrp32 = true,
 928    .lower_flrp64 = true,
 929    .lower_fpow = false,
 930    .lower_uadd_carry = true,
 931    .lower_usub_borrow = true,
 932    .lower_sub = true,
 933    .lower_ffract = true,
 934    .lower_pack_half_2x16 = true,
 935    .lower_pack_unorm_2x16 = true,
 936    .lower_pack_snorm_2x16 = true,
 937    .lower_pack_unorm_4x8 = true,
 938    .lower_pack_snorm_4x8 = true,
 939    .lower_unpack_half_2x16 = true,
 940    .lower_unpack_unorm_2x16 = true,
 941    .lower_unpack_snorm_2x16 = true,
 942    .lower_unpack_unorm_4x8 = true,
 943    .lower_unpack_snorm_4x8 = true,
 944    .lower_extract_byte = true,
 945    .lower_extract_word = true,
 946    .lower_all_io_to_temps = false,
 947    .lower_cs_local_index_from_id = true,
 948    .lower_rotate = true,
 949    .lower_to_scalar = true,
 950    .use_interpolated_input_intrinsics = true,
 951    .max_unroll_iterations = 32,
 952 };
 953
 954 static const void *
 955 nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
 956                                  enum pipe_shader_ir ir,
 957                                  enum pipe_shader_type shader)
 958 {
 959    if (ir == PIPE_SHADER_IR_NIR)
 960       return &nir_options;
 961    return NULL;
 962 }
 963
 964 struct nouveau_screen *
 965 nv50_screen_create(struct nouveau_device *dev)
 966 {
 967    struct nv50_screen *screen;
 968    struct pipe_screen *pscreen;
 969    struct nouveau_object *chan;
 970    uint64_t value;
 971    uint32_t tesla_class;
 972    unsigned stack_size;
 973    int ret;
 974
 975    screen = CALLOC_STRUCT(nv50_screen);
 976    if (!screen)
 977       return NULL;
 978    pscreen = &screen->base.base;
 979    pscreen->destroy = nv50_screen_destroy;
 980
 981    ret = nouveau_screen_init(&screen->base, dev);
 982    if (ret) {
 983       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 984       goto fail;
 985    }
 986
 987    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 988     *  admit them to VRAM.
 989     */
 990    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 991       PIPE_BIND_VERTEX_BUFFER;
 992    screen->base.sysmem_bindings |=
 993       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 994
 995    screen->base.pushbuf->user_priv = screen;
 996    screen->base.pushbuf->rsvd_kick = 5;
 997
 998    chan = screen->base.channel;
 999
1000    pscreen->context_create = nv50_create;
1001    pscreen->is_format_supported = nv50_screen_is_format_supported;
1002    pscreen->get_param = nv50_screen_get_param;
1003    pscreen->get_shader_param = nv50_screen_get_shader_param;
1004    pscreen->get_paramf = nv50_screen_get_paramf;
1005    pscreen->get_compute_param = nv50_screen_get_compute_param;
1006    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
1007    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
1008
1009    /* nir stuff */
1010    pscreen->get_compiler_options = nv50_screen_get_compiler_options;
1011
1012    nv50_screen_init_resource_functions(pscreen);
1013
1014    if (screen->base.device->chipset < 0x84 ||
1015        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
1016       /* PMPEG */
1017       nouveau_screen_init_vdec(&screen->base);
1018    } else if (screen->base.device->chipset < 0x98 ||
1019               screen->base.device->chipset == 0xa0) {
1020       /* VP2 */
1021       screen->base.base.get_video_param = nv84_screen_get_video_param;
1022       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
1023    } else {
1024       /* VP3/4 */
1025       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1026       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1027    }
1028
1029    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
1030                         NULL, &screen->fence.bo);
1031    if (ret) {
1032       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
1033       goto fail;
1034    }
1035
1036    nouveau_bo_map(screen->fence.bo, 0, NULL);
1037    screen->fence.map = screen->fence.bo->map;
1038    screen->base.fence.emit = nv50_screen_fence_emit;
1039    screen->base.fence.update = nv50_screen_fence_update;
1040
1041    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
1042                             &(struct nv04_notify){ .length = 32 },
1043                             sizeof(struct nv04_notify), &screen->sync);
1044    if (ret) {
1045       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
1046       goto fail;
1047    }
1048
1049    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
1050                             NULL, 0, &screen->m2mf);
1051    if (ret) {
1052       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
1053       goto fail;
1054    }
1055
1056    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
1057                             NULL, 0, &screen->eng2d);
1058    if (ret) {
1059       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
1060       goto fail;
1061    }
1062
1063    switch (dev->chipset & 0xf0) {
1064    case 0x50:
1065       tesla_class = NV50_3D_CLASS;
1066       break;
1067    case 0x80:
1068    case 0x90:
1069       tesla_class = NV84_3D_CLASS;
1070       break;
1071    case 0xa0:
1072       switch (dev->chipset) {
1073       case 0xa0:
1074       case 0xaa:
1075       case 0xac:
1076          tesla_class = NVA0_3D_CLASS;
1077          break;
1078       case 0xaf:
1079          tesla_class = NVAF_3D_CLASS;
1080          break;
1081       default:
1082          tesla_class = NVA3_3D_CLASS;
1083          break;
1084       }
1085       break;
1086    default:
1087       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
1088       goto fail;
1089    }
1090    screen->base.class_3d = tesla_class;
1091
1092    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
1093                             NULL, 0, &screen->tesla);
1094    if (ret) {
1095       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
1096       goto fail;
1097    }
1098
1099    /* This over-allocates by a page. The GP, which would execute at the end of
1100     * the last page, would trigger faults. The going theory is that it
1101     * prefetches up to a certain amount.
1102     */
1103    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
1104                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
1105                         NULL, &screen->code);
1106    if (ret) {
1107       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
1108       goto fail;
1109    }
1110
1111    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1112    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1113    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1114
1115    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1116
1117    screen->TPs = util_bitcount(value & 0xffff);
1118    screen->MPsInTP = util_bitcount(value & 0x0f000000);
1119
1120    screen->mp_count = screen->TPs * screen->MPsInTP;
1121
1122    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1123          STACK_WARPS_ALLOC * 64 * 8;
1124
1125    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1126                         &screen->stack_bo);
1127    if (ret) {
1128       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1129       goto fail;
1130    }
1131
1132    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1133          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1134          ONE_TEMP_SIZE;
1135    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1136    screen->max_tls_space /= 2; /* half of vram */
1137
1138    /* hw can address max 64 KiB */
1139    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1140
1141    uint64_t tls_size;
1142    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1143    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1144    if (ret)
1145       goto fail;
1146
1147    if (nouveau_mesa_debug)
1148       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1149             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1150
1151    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1152                         &screen->uniforms);
1153    if (ret) {
1154       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1155       goto fail;
1156    }
1157
1158    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1159                         &screen->txc);
1160    if (ret) {
1161       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1162       goto fail;
1163    }
1164
1165    screen->tic.entries = CALLOC(4096, sizeof(void *));
1166    screen->tsc.entries = screen->tic.entries + 2048;
1167
1168    if (!nv50_blitter_create(screen))
1169       goto fail;
1170
1171    nv50_screen_init_hwctx(screen);
1172
1173    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1174    if (ret) {
1175       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1176       goto fail;
1177    }
1178
1179    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1180
1181    return &screen->base;
1182
1183 fail:
1184    screen->base.base.context_create = NULL;
1185    return &screen->base;
1186 }
1187
1188 int
1189 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1190 {
1191    int i = screen->tic.next;
1192
1193    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1194       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1195
1196    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1197
1198    if (screen->tic.entries[i])
1199       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1200
1201    screen->tic.entries[i] = entry;
1202    return i;
1203 }
1204
1205 int
1206 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1207 {
1208    int i = screen->tsc.next;
1209
1210    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1211       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1212
1213    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1214
1215    if (screen->tsc.entries[i])
1216       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1217
1218    screen->tsc.entries[i] = entry;
1219    return i;
1220 }