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8c04cda17aae5d13827e1478aea51f06a641494a
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "util/u_screen.h"
29 #include "pipe/p_screen.h"
30 #include "compiler/nir/nir.h"
31
32 #include "nouveau_vp3_video.h"
33
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_screen.h"
36
37 #include "nvc0/mme/com9097.mme.h"
38 #include "nvc0/mme/com90c0.mme.h"
39
40 #include "nv50/g80_texture.xml.h"
41
42 static bool
43 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
44 enum pipe_format format,
45 enum pipe_texture_target target,
46 unsigned sample_count,
47 unsigned storage_sample_count,
48 unsigned bindings)
49 {
50 const struct util_format_description *desc = util_format_description(format);
51
52 if (sample_count > 8)
53 return false;
54 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
55 return false;
56
57 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
58 return false;
59
60 /* Short-circuit the rest of the logic -- this is used by the state tracker
61 * to determine valid MS levels in a no-attachments scenario.
62 */
63 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
64 return true;
65
66 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
67 if (util_format_get_blocksizebits(format) == 3 * 32)
68 return false;
69
70 if (bindings & PIPE_BIND_LINEAR)
71 if (util_format_is_depth_or_stencil(format) ||
72 (target != PIPE_TEXTURE_1D &&
73 target != PIPE_TEXTURE_2D &&
74 target != PIPE_TEXTURE_RECT) ||
75 sample_count > 1)
76 return false;
77
78 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
79 */
80 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
81 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
82 /* The claim is that this should work on GM107 but it doesn't. Need to
83 * test further and figure out if it's a nouveau issue or a HW one.
84 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
85 */
86 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
87 return false;
88
89 /* shared is always supported */
90 bindings &= ~(PIPE_BIND_LINEAR |
91 PIPE_BIND_SHARED);
92
93 if (bindings & PIPE_BIND_SHADER_IMAGE) {
94 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
95 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
96 /* This should work on Fermi, but for currently unknown reasons it
97 * does not and results in breaking reads from pbos. */
98 return false;
99 }
100 }
101
102 return (( nvc0_format_table[format].usage |
103 nvc0_vertex_format[format].usage) & bindings) == bindings;
104 }
105
106 static int
107 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
108 {
109 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
110 const struct nouveau_screen *screen = nouveau_screen(pscreen);
111 struct nouveau_device *dev = screen->device;
112
113 switch (param) {
114 /* non-boolean caps */
115 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
116 return 16384;
117 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
118 return 15;
119 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
120 return 12;
121 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
122 return 2048;
123 case PIPE_CAP_MIN_TEXEL_OFFSET:
124 return -8;
125 case PIPE_CAP_MAX_TEXEL_OFFSET:
126 return 7;
127 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
128 return -32;
129 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
130 return 31;
131 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
132 return 128 * 1024 * 1024;
133 case PIPE_CAP_GLSL_FEATURE_LEVEL:
134 return 430;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
136 return 430;
137 case PIPE_CAP_MAX_RENDER_TARGETS:
138 return 8;
139 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
140 return 1;
141 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
142 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
143 return 8;
144 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
145 return 4;
146 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
147 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
148 return 128;
149 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
150 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
151 return 1024;
152 case PIPE_CAP_MAX_VERTEX_STREAMS:
153 return 4;
154 case PIPE_CAP_MAX_GS_INVOCATIONS:
155 return 32;
156 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
157 return 1 << 27;
158 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
159 return 2048;
160 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
161 return 2047;
162 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
163 return 256;
164 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
165 if (class_3d < GM107_3D_CLASS)
166 return 256; /* IMAGE bindings require alignment to 256 */
167 return 16;
168 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
169 return 16;
170 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
171 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
172 case PIPE_CAP_MAX_VIEWPORTS:
173 return NVC0_MAX_VIEWPORTS;
174 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
175 return 4;
176 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
177 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
178 case PIPE_CAP_ENDIANNESS:
179 return PIPE_ENDIAN_LITTLE;
180 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
181 return 30;
182 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
183 return NVC0_MAX_WINDOW_RECTANGLES;
184 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
185 return class_3d >= GM200_3D_CLASS ? 8 : 0;
186 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
187 return 64 * 1024 * 1024;
188 case PIPE_CAP_MAX_VARYINGS:
189 /* NOTE: These only count our slots for GENERIC varyings.
190 * The address space may be larger, but the actual hard limit seems to be
191 * less than what the address space layout permits, so don't add TEXCOORD,
192 * COLOR, etc. here.
193 */
194 return 0x1f0 / 16;
195
196 /* supported caps */
197 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
198 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
199 case PIPE_CAP_TEXTURE_SWIZZLE:
200 case PIPE_CAP_NPOT_TEXTURES:
201 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
202 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
203 case PIPE_CAP_ANISOTROPIC_FILTER:
204 case PIPE_CAP_SEAMLESS_CUBE_MAP:
205 case PIPE_CAP_CUBE_MAP_ARRAY:
206 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
207 case PIPE_CAP_TEXTURE_MULTISAMPLE:
208 case PIPE_CAP_DEPTH_CLIP_DISABLE:
209 case PIPE_CAP_POINT_SPRITE:
210 case PIPE_CAP_TGSI_TEXCOORD:
211 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
212 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
213 case PIPE_CAP_VERTEX_SHADER_SATURATE:
214 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
215 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
216 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
217 case PIPE_CAP_QUERY_TIMESTAMP:
218 case PIPE_CAP_QUERY_TIME_ELAPSED:
219 case PIPE_CAP_OCCLUSION_QUERY:
220 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
221 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
222 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
223 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
224 case PIPE_CAP_INDEP_BLEND_ENABLE:
225 case PIPE_CAP_INDEP_BLEND_FUNC:
226 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
227 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
228 case PIPE_CAP_PRIMITIVE_RESTART:
229 case PIPE_CAP_TGSI_INSTANCEID:
230 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
231 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
232 case PIPE_CAP_CONDITIONAL_RENDER:
233 case PIPE_CAP_TEXTURE_BARRIER:
234 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
235 case PIPE_CAP_START_INSTANCE:
236 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
237 case PIPE_CAP_DRAW_INDIRECT:
238 case PIPE_CAP_USER_VERTEX_BUFFERS:
239 case PIPE_CAP_TEXTURE_QUERY_LOD:
240 case PIPE_CAP_SAMPLE_SHADING:
241 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
242 case PIPE_CAP_TEXTURE_GATHER_SM5:
243 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
244 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
245 case PIPE_CAP_SAMPLER_VIEW_TARGET:
246 case PIPE_CAP_CLIP_HALFZ:
247 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
248 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
249 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
250 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
251 case PIPE_CAP_DEPTH_BOUNDS_TEST:
252 case PIPE_CAP_TGSI_TXQS:
253 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
254 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
255 case PIPE_CAP_SHAREABLE_SHADERS:
256 case PIPE_CAP_CLEAR_TEXTURE:
257 case PIPE_CAP_DRAW_PARAMETERS:
258 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
259 case PIPE_CAP_MULTI_DRAW_INDIRECT:
260 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
261 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
262 case PIPE_CAP_QUERY_BUFFER_OBJECT:
263 case PIPE_CAP_INVALIDATE_BUFFER:
264 case PIPE_CAP_STRING_MARKER:
265 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
266 case PIPE_CAP_CULL_DISTANCE:
267 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
268 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
269 case PIPE_CAP_TGSI_VOTE:
270 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
271 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
272 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
273 case PIPE_CAP_DOUBLES:
274 case PIPE_CAP_INT64:
275 case PIPE_CAP_TGSI_TEX_TXF_LZ:
276 case PIPE_CAP_TGSI_CLOCK:
277 case PIPE_CAP_COMPUTE:
278 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
279 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
280 case PIPE_CAP_QUERY_SO_OVERFLOW:
281 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
282 case PIPE_CAP_TGSI_DIV:
283 case PIPE_CAP_TGSI_ATOMINC_WRAP:
284 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
285 return 1;
286 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
287 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
288 case PIPE_CAP_FBFETCH:
289 return class_3d >= NVE4_3D_CLASS ? 1 : 0; /* needs testing on fermi */
290 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
291 case PIPE_CAP_TGSI_BALLOT:
292 return class_3d >= NVE4_3D_CLASS;
293 case PIPE_CAP_BINDLESS_TEXTURE:
294 return class_3d >= NVE4_3D_CLASS;
295 case PIPE_CAP_TGSI_ATOMFADD:
296 return class_3d < GM107_3D_CLASS; /* needs additional lowering */
297 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
298 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
299 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
300 case PIPE_CAP_POST_DEPTH_COVERAGE:
301 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
302 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
303 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
304 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
305 return class_3d >= GM200_3D_CLASS;
306 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
307 return class_3d >= GP100_3D_CLASS;
308
309 /* caps has to be turned on with nir */
310 case PIPE_CAP_INT64_DIVMOD:
311 return screen->prefer_nir ? 1 : 0;
312
313 /* unsupported caps */
314 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
315 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
316 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
317 case PIPE_CAP_SHADER_STENCIL_EXPORT:
318 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
319 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
320 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
321 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
322 case PIPE_CAP_FAKE_SW_MSAA:
323 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
324 case PIPE_CAP_VERTEXID_NOBASE:
325 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
326 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
327 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
328 case PIPE_CAP_GENERATE_MIPMAP:
329 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
330 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
331 case PIPE_CAP_QUERY_MEMORY_INFO:
332 case PIPE_CAP_PCI_GROUP:
333 case PIPE_CAP_PCI_BUS:
334 case PIPE_CAP_PCI_DEVICE:
335 case PIPE_CAP_PCI_FUNCTION:
336 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
337 case PIPE_CAP_NATIVE_FENCE_FD:
338 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
339 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
340 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
341 case PIPE_CAP_MEMOBJ:
342 case PIPE_CAP_LOAD_CONSTBUF:
343 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
344 case PIPE_CAP_TILE_RASTER_ORDER:
345 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
346 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
347 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
348 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
349 case PIPE_CAP_FENCE_SIGNAL:
350 case PIPE_CAP_CONSTBUF0_FLAGS:
351 case PIPE_CAP_PACKED_UNIFORMS:
352 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
353 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
354 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
355 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
356 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
357 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
358 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
359 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
360 case PIPE_CAP_NIR_COMPACT_ARRAYS:
361 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
362 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
363 case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
364 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
365 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
366 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
367 case PIPE_CAP_FBFETCH_COHERENT:
368 case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
369 return 0;
370
371 case PIPE_CAP_VENDOR_ID:
372 return 0x10de;
373 case PIPE_CAP_DEVICE_ID: {
374 uint64_t device_id;
375 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
376 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
377 return -1;
378 }
379 return device_id;
380 }
381 case PIPE_CAP_ACCELERATED:
382 return 1;
383 case PIPE_CAP_VIDEO_MEMORY:
384 return dev->vram_size >> 20;
385 case PIPE_CAP_UMA:
386 return 0;
387
388 default:
389 debug_printf("%s: unhandled cap %d\n", __func__, param);
390 /* fallthrough */
391 /* caps where we want the default value */
392 case PIPE_CAP_DMABUF:
393 case PIPE_CAP_ESSL_FEATURE_LEVEL:
394 case PIPE_CAP_MAX_FRAMES_IN_FLIGHT:
395 return u_pipe_screen_get_param_defaults(pscreen, param);
396 }
397 }
398
399 static int
400 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
401 enum pipe_shader_type shader,
402 enum pipe_shader_cap param)
403 {
404 const struct nouveau_screen *screen = nouveau_screen(pscreen);
405 const uint16_t class_3d = screen->class_3d;
406
407 switch (shader) {
408 case PIPE_SHADER_VERTEX:
409 case PIPE_SHADER_GEOMETRY:
410 case PIPE_SHADER_FRAGMENT:
411 case PIPE_SHADER_COMPUTE:
412 case PIPE_SHADER_TESS_CTRL:
413 case PIPE_SHADER_TESS_EVAL:
414 break;
415 default:
416 return 0;
417 }
418
419 switch (param) {
420 case PIPE_SHADER_CAP_PREFERRED_IR:
421 return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
422 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
423 uint32_t irs = 1 << PIPE_SHADER_IR_TGSI |
424 1 << PIPE_SHADER_IR_NIR;
425 if (screen->force_enable_cl)
426 irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
427 return irs;
428 }
429 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
430 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
431 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
432 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
433 return 16384;
434 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
435 return 16;
436 case PIPE_SHADER_CAP_MAX_INPUTS:
437 return 0x200 / 16;
438 case PIPE_SHADER_CAP_MAX_OUTPUTS:
439 return 32;
440 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
441 return NVC0_MAX_CONSTBUF_SIZE;
442 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
443 return NVC0_MAX_PIPE_CONSTBUFS;
444 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
445 return shader != PIPE_SHADER_FRAGMENT;
446 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
447 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
448 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
449 return 1;
450 case PIPE_SHADER_CAP_MAX_TEMPS:
451 return NVC0_CAP_MAX_PROGRAM_TEMPS;
452 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
453 return 1;
454 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
455 return 1;
456 case PIPE_SHADER_CAP_SUBROUTINES:
457 return 1;
458 case PIPE_SHADER_CAP_INTEGERS:
459 return 1;
460 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
461 return 1;
462 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
463 return 1;
464 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
465 return 1;
466 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
467 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
468 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
469 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
470 case PIPE_SHADER_CAP_INT64_ATOMICS:
471 case PIPE_SHADER_CAP_FP16:
472 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
473 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
474 return 0;
475 case PIPE_SHADER_CAP_SCALAR_ISA:
476 return 1;
477 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
478 return NVC0_MAX_BUFFERS;
479 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
480 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
481 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
482 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
483 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
484 return 32;
485 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
486 if (class_3d >= NVE4_3D_CLASS)
487 return NVC0_MAX_IMAGES;
488 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
489 return NVC0_MAX_IMAGES;
490 return 0;
491 default:
492 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
493 return 0;
494 }
495 }
496
497 static float
498 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
499 {
500 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
501
502 switch (param) {
503 case PIPE_CAPF_MAX_LINE_WIDTH:
504 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
505 return 10.0f;
506 case PIPE_CAPF_MAX_POINT_WIDTH:
507 return 63.0f;
508 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
509 return 63.375f;
510 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
511 return 16.0f;
512 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
513 return 15.0f;
514 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
515 return 0.0f;
516 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
517 return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
518 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
519 return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
520 }
521
522 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
523 return 0.0f;
524 }
525
526 static int
527 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
528 enum pipe_shader_ir ir_type,
529 enum pipe_compute_cap param, void *data)
530 {
531 struct nvc0_screen *screen = nvc0_screen(pscreen);
532 const uint16_t obj_class = screen->compute->oclass;
533
534 #define RET(x) do { \
535 if (data) \
536 memcpy(data, x, sizeof(x)); \
537 return sizeof(x); \
538 } while (0)
539
540 switch (param) {
541 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
542 RET((uint64_t []) { 3 });
543 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
544 if (obj_class >= NVE4_COMPUTE_CLASS) {
545 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
546 } else {
547 RET(((uint64_t []) { 65535, 65535, 65535 }));
548 }
549 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
550 RET(((uint64_t []) { 1024, 1024, 64 }));
551 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
552 RET((uint64_t []) { 1024 });
553 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
554 if (obj_class >= NVE4_COMPUTE_CLASS) {
555 RET((uint64_t []) { 1024 });
556 } else {
557 RET((uint64_t []) { 512 });
558 }
559 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
560 RET((uint64_t []) { 1ULL << 40 });
561 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
562 switch (obj_class) {
563 case GM200_COMPUTE_CLASS:
564 RET((uint64_t []) { 96 << 10 });
565 break;
566 case GM107_COMPUTE_CLASS:
567 RET((uint64_t []) { 64 << 10 });
568 break;
569 default:
570 RET((uint64_t []) { 48 << 10 });
571 break;
572 }
573 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
574 RET((uint64_t []) { 512 << 10 });
575 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
576 RET((uint64_t []) { 4096 });
577 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
578 RET((uint32_t []) { 32 });
579 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
580 RET((uint64_t []) { 1ULL << 40 });
581 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
582 RET((uint32_t []) { 0 });
583 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
584 RET((uint32_t []) { screen->mp_count_compute });
585 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
586 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
587 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
588 RET((uint32_t []) { 64 });
589 default:
590 return 0;
591 }
592
593 #undef RET
594 }
595
596 static void
597 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
598 unsigned sample_count,
599 unsigned *width, unsigned *height)
600 {
601 switch (sample_count) {
602 case 0:
603 case 1:
604 /* this could be 4x4, but the GL state tracker makes it difficult to
605 * create a 1x MSAA texture and smaller grids save CB space */
606 *width = 2;
607 *height = 4;
608 break;
609 case 2:
610 *width = 2;
611 *height = 4;
612 break;
613 case 4:
614 *width = 2;
615 *height = 2;
616 break;
617 case 8:
618 *width = 1;
619 *height = 2;
620 break;
621 default:
622 assert(0);
623 }
624 }
625
626 static void
627 nvc0_screen_destroy(struct pipe_screen *pscreen)
628 {
629 struct nvc0_screen *screen = nvc0_screen(pscreen);
630
631 if (!nouveau_drm_screen_unref(&screen->base))
632 return;
633
634 if (screen->base.fence.current) {
635 struct nouveau_fence *current = NULL;
636
637 /* nouveau_fence_wait will create a new current fence, so wait on the
638 * _current_ one, and remove both.
639 */
640 nouveau_fence_ref(screen->base.fence.current, &current);
641 nouveau_fence_wait(current, NULL);
642 nouveau_fence_ref(NULL, &current);
643 nouveau_fence_ref(NULL, &screen->base.fence.current);
644 }
645 if (screen->base.pushbuf)
646 screen->base.pushbuf->user_priv = NULL;
647
648 if (screen->blitter)
649 nvc0_blitter_destroy(screen);
650 if (screen->pm.prog) {
651 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
652 nvc0_program_destroy(NULL, screen->pm.prog);
653 FREE(screen->pm.prog);
654 }
655
656 nouveau_bo_ref(NULL, &screen->text);
657 nouveau_bo_ref(NULL, &screen->uniform_bo);
658 nouveau_bo_ref(NULL, &screen->tls);
659 nouveau_bo_ref(NULL, &screen->txc);
660 nouveau_bo_ref(NULL, &screen->fence.bo);
661 nouveau_bo_ref(NULL, &screen->poly_cache);
662
663 nouveau_heap_destroy(&screen->lib_code);
664 nouveau_heap_destroy(&screen->text_heap);
665
666 FREE(screen->tic.entries);
667
668 nouveau_object_del(&screen->eng3d);
669 nouveau_object_del(&screen->eng2d);
670 nouveau_object_del(&screen->m2mf);
671 nouveau_object_del(&screen->compute);
672 nouveau_object_del(&screen->nvsw);
673
674 nouveau_screen_fini(&screen->base);
675
676 FREE(screen);
677 }
678
679 static int
680 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
681 unsigned size, const uint32_t *data)
682 {
683 struct nouveau_pushbuf *push = screen->base.pushbuf;
684
685 size /= 4;
686
687 assert((pos + size) <= 0x800);
688
689 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
690 PUSH_DATA (push, (m - 0x3800) / 8);
691 PUSH_DATA (push, pos);
692 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
693 PUSH_DATA (push, pos);
694 PUSH_DATAp(push, data, size);
695
696 return pos + size;
697 }
698
699 static void
700 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
701 {
702 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
703 PUSH_DATA (push, 0xff);
704 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
705 PUSH_DATA (push, 0xff);
706 PUSH_DATA (push, 0xff);
707 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
708 PUSH_DATA (push, 0xff);
709 PUSH_DATA (push, 0xff);
710 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
711 PUSH_DATA (push, 0x3f);
712
713 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
714 PUSH_DATA (push, (3 << 16) | 3);
715 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
716 PUSH_DATA (push, (2 << 16) | 2);
717
718 if (obj_class < GM107_3D_CLASS) {
719 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
720 PUSH_DATA (push, 0);
721 }
722 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
723 PUSH_DATA (push, 0x10);
724 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
725 PUSH_DATA (push, 0x10);
726 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
727 PUSH_DATA (push, 0x10);
728 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
729 PUSH_DATA (push, 0x10);
730 PUSH_DATA (push, 0x10);
731 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
732 PUSH_DATA (push, 0x10);
733 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
734 PUSH_DATA (push, 0xe);
735
736 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
737 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
738 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
739 PUSH_DATA (push, 0);
740 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
741 PUSH_DATA (push, 3);
742
743 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
744 PUSH_DATA (push, 0x3fffff);
745 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
746 PUSH_DATA (push, 1);
747 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
748 PUSH_DATA (push, 1);
749
750 if (obj_class < GM107_3D_CLASS) {
751 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
752 PUSH_DATA (push, 3);
753
754 if (obj_class >= NVE4_3D_CLASS) {
755 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
756 PUSH_DATA (push, 1);
757 }
758 }
759
760 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
761 * are supposed to do */
762 }
763
764 static void
765 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
766 {
767 struct nvc0_screen *screen = nvc0_screen(pscreen);
768 struct nouveau_pushbuf *push = screen->base.pushbuf;
769
770 /* we need to do it after possible flush in MARK_RING */
771 *sequence = ++screen->base.fence.sequence;
772
773 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
774 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
775 PUSH_DATAh(push, screen->fence.bo->offset);
776 PUSH_DATA (push, screen->fence.bo->offset);
777 PUSH_DATA (push, *sequence);
778 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
779 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
780 }
781
782 static u32
783 nvc0_screen_fence_update(struct pipe_screen *pscreen)
784 {
785 struct nvc0_screen *screen = nvc0_screen(pscreen);
786 return screen->fence.map[0];
787 }
788
789 static int
790 nvc0_screen_init_compute(struct nvc0_screen *screen)
791 {
792 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
793
794 switch (screen->base.device->chipset & ~0xf) {
795 case 0xc0:
796 case 0xd0:
797 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
798 case 0xe0:
799 case 0xf0:
800 case 0x100:
801 case 0x110:
802 case 0x120:
803 case 0x130:
804 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
805 default:
806 return -1;
807 }
808 }
809
810 static int
811 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
812 uint32_t lpos, uint32_t lneg, uint32_t cstack)
813 {
814 struct nouveau_bo *bo = NULL;
815 int ret;
816 uint64_t size = (lpos + lneg) * 32 + cstack;
817
818 if (size >= (1 << 20)) {
819 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
820 return -1;
821 }
822
823 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
824 size = align(size, 0x8000);
825 size *= screen->mp_count;
826
827 size = align(size, 1 << 17);
828
829 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
830 NULL, &bo);
831 if (ret)
832 return ret;
833
834 /* Make sure that the pushbuf has acquired a reference to the old tls
835 * segment, as it may have commands that will reference it.
836 */
837 if (screen->tls)
838 PUSH_REFN(screen->base.pushbuf, screen->tls,
839 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
840 nouveau_bo_ref(NULL, &screen->tls);
841 screen->tls = bo;
842 return 0;
843 }
844
845 int
846 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
847 {
848 struct nouveau_pushbuf *push = screen->base.pushbuf;
849 struct nouveau_bo *bo;
850 int ret;
851
852 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
853 1 << 17, size, NULL, &bo);
854 if (ret)
855 return ret;
856
857 /* Make sure that the pushbuf has acquired a reference to the old text
858 * segment, as it may have commands that will reference it.
859 */
860 if (screen->text)
861 PUSH_REFN(push, screen->text,
862 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
863 nouveau_bo_ref(NULL, &screen->text);
864 screen->text = bo;
865
866 nouveau_heap_destroy(&screen->lib_code);
867 nouveau_heap_destroy(&screen->text_heap);
868
869 /* XXX: getting a page fault at the end of the code buffer every few
870 * launches, don't use the last 256 bytes to work around them - prefetch ?
871 */
872 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
873
874 /* update the code segment setup */
875 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
876 PUSH_DATAh(push, screen->text->offset);
877 PUSH_DATA (push, screen->text->offset);
878 if (screen->compute) {
879 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
880 PUSH_DATAh(push, screen->text->offset);
881 PUSH_DATA (push, screen->text->offset);
882 }
883
884 return 0;
885 }
886
887 void
888 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
889 int stage, int index, int size, uint64_t addr)
890 {
891 assert(stage != 5);
892
893 struct nouveau_pushbuf *push = screen->base.pushbuf;
894
895 if (screen->base.class_3d >= GM107_3D_CLASS) {
896 struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
897
898 // TODO: Better figure out the conditions in which this is needed
899 bool serialize = binding->addr == addr && binding->size != size;
900 if (can_serialize)
901 serialize = serialize && *can_serialize;
902 if (serialize) {
903 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
904 if (can_serialize)
905 *can_serialize = false;
906 }
907
908 binding->addr = addr;
909 binding->size = size;
910 }
911
912 if (size >= 0) {
913 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
914 PUSH_DATA (push, size);
915 PUSH_DATAh(push, addr);
916 PUSH_DATA (push, addr);
917 }
918 IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
919 }
920
921 static const nir_shader_compiler_options nir_options = {
922 .lower_fdiv = false,
923 .lower_ffma = false,
924 .fuse_ffma = false, /* nir doesn't track mad vs fma */
925 .lower_flrp32 = true,
926 .lower_flrp64 = true,
927 .lower_fpow = false,
928 .lower_fsat = false,
929 .lower_fsqrt = false, // TODO: only before gm200
930 .lower_fmod = true,
931 .lower_bitfield_extract = false,
932 .lower_bitfield_extract_to_shifts = false,
933 .lower_bitfield_insert = false,
934 .lower_bitfield_insert_to_shifts = false,
935 .lower_bitfield_reverse = false,
936 .lower_bit_count = false,
937 .lower_ifind_msb = false,
938 .lower_find_lsb = false,
939 .lower_uadd_carry = true, // TODO
940 .lower_usub_borrow = true, // TODO
941 .lower_mul_high = false,
942 .lower_negate = false,
943 .lower_sub = true,
944 .lower_scmp = true, // TODO: not implemented yet
945 .lower_idiv = true,
946 .lower_isign = false, // TODO
947 .fdot_replicates = false, // TODO
948 .lower_ffloor = false, // TODO
949 .lower_ffract = true,
950 .lower_fceil = false, // TODO
951 .lower_ldexp = true,
952 .lower_pack_half_2x16 = true,
953 .lower_pack_unorm_2x16 = true,
954 .lower_pack_snorm_2x16 = true,
955 .lower_pack_unorm_4x8 = true,
956 .lower_pack_snorm_4x8 = true,
957 .lower_unpack_half_2x16 = true,
958 .lower_unpack_unorm_2x16 = true,
959 .lower_unpack_snorm_2x16 = true,
960 .lower_unpack_unorm_4x8 = true,
961 .lower_unpack_snorm_4x8 = true,
962 .lower_extract_byte = true,
963 .lower_extract_word = true,
964 .lower_all_io_to_temps = false,
965 .vertex_id_zero_based = false,
966 .lower_base_vertex = false,
967 .lower_helper_invocation = false,
968 .lower_cs_local_index_from_id = true,
969 .lower_cs_local_id_from_index = false,
970 .lower_device_index_to_zero = false, // TODO
971 .lower_wpos_pntc = false, // TODO
972 .lower_hadd = true, // TODO
973 .lower_add_sat = true, // TODO
974 .use_interpolated_input_intrinsics = true,
975 .lower_mul_2x32_64 = true, // TODO
976 .max_unroll_iterations = 32,
977 .lower_int64_options = nir_lower_divmod64, // TODO
978 .lower_doubles_options = nir_lower_dmod, // TODO
979 .lower_to_scalar = true,
980 };
981
982 static const void *
983 nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
984 enum pipe_shader_ir ir,
985 enum pipe_shader_type shader)
986 {
987 if (ir == PIPE_SHADER_IR_NIR)
988 return &nir_options;
989 return NULL;
990 }
991
992 #define FAIL_SCREEN_INIT(str, err) \
993 do { \
994 NOUVEAU_ERR(str, err); \
995 goto fail; \
996 } while(0)
997
998 struct nouveau_screen *
999 nvc0_screen_create(struct nouveau_device *dev)
1000 {
1001 struct nvc0_screen *screen;
1002 struct pipe_screen *pscreen;
1003 struct nouveau_object *chan;
1004 struct nouveau_pushbuf *push;
1005 uint64_t value;
1006 uint32_t obj_class;
1007 uint32_t flags;
1008 int ret;
1009 unsigned i;
1010
1011 switch (dev->chipset & ~0xf) {
1012 case 0xc0:
1013 case 0xd0:
1014 case 0xe0:
1015 case 0xf0:
1016 case 0x100:
1017 case 0x110:
1018 case 0x120:
1019 case 0x130:
1020 break;
1021 default:
1022 return NULL;
1023 }
1024
1025 screen = CALLOC_STRUCT(nvc0_screen);
1026 if (!screen)
1027 return NULL;
1028 pscreen = &screen->base.base;
1029 pscreen->destroy = nvc0_screen_destroy;
1030
1031 ret = nouveau_screen_init(&screen->base, dev);
1032 if (ret)
1033 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
1034 chan = screen->base.channel;
1035 push = screen->base.pushbuf;
1036 push->user_priv = screen;
1037 push->rsvd_kick = 5;
1038
1039 /* TODO: could this be higher on Kepler+? how does reclocking vs no
1040 * reclocking affect performance?
1041 * TODO: could this be higher on Fermi?
1042 */
1043 if (dev->chipset >= 0xe0)
1044 screen->base.transfer_pushbuf_threshold = 1024;
1045
1046 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1047 PIPE_BIND_SHADER_BUFFER |
1048 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
1049 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
1050 screen->base.sysmem_bindings |=
1051 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1052
1053 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
1054 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
1055 screen->base.vidmem_bindings = 0;
1056 }
1057
1058 pscreen->context_create = nvc0_create;
1059 pscreen->is_format_supported = nvc0_screen_is_format_supported;
1060 pscreen->get_param = nvc0_screen_get_param;
1061 pscreen->get_shader_param = nvc0_screen_get_shader_param;
1062 pscreen->get_paramf = nvc0_screen_get_paramf;
1063 pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
1064 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
1065 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
1066 /* nir stuff */
1067 pscreen->get_compiler_options = nvc0_screen_get_compiler_options;
1068
1069 nvc0_screen_init_resource_functions(pscreen);
1070
1071 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1072 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1073
1074 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
1075 if (screen->base.drm->version >= 0x01000202)
1076 flags |= NOUVEAU_BO_COHERENT;
1077
1078 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
1079 if (ret)
1080 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
1081 nouveau_bo_map(screen->fence.bo, 0, NULL);
1082 screen->fence.map = screen->fence.bo->map;
1083 screen->base.fence.emit = nvc0_screen_fence_emit;
1084 screen->base.fence.update = nvc0_screen_fence_update;
1085
1086
1087 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
1088 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
1089 if (ret)
1090 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
1091
1092 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
1093 PUSH_DATA (push, screen->nvsw->handle);
1094
1095 switch (dev->chipset & ~0xf) {
1096 case 0x130:
1097 case 0x120:
1098 case 0x110:
1099 case 0x100:
1100 case 0xf0:
1101 obj_class = NVF0_P2MF_CLASS;
1102 break;
1103 case 0xe0:
1104 obj_class = NVE4_P2MF_CLASS;
1105 break;
1106 default:
1107 obj_class = NVC0_M2MF_CLASS;
1108 break;
1109 }
1110 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1111 &screen->m2mf);
1112 if (ret)
1113 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1114
1115 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1116 PUSH_DATA (push, screen->m2mf->oclass);
1117 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1118 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1119 PUSH_DATA (push, 0xa0b5);
1120 }
1121
1122 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1123 &screen->eng2d);
1124 if (ret)
1125 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1126
1127 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1128 PUSH_DATA (push, screen->eng2d->oclass);
1129 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1130 PUSH_DATA (push, 0);
1131 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1132 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1133 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1134 PUSH_DATA (push, 0);
1135 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1136 PUSH_DATA (push, 0);
1137 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1138 PUSH_DATA (push, 0x3f);
1139 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1140 PUSH_DATA (push, 1);
1141 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1142 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1143
1144 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1145 PUSH_DATAh(push, screen->fence.bo->offset + 16);
1146 PUSH_DATA (push, screen->fence.bo->offset + 16);
1147
1148 switch (dev->chipset & ~0xf) {
1149 case 0x130:
1150 switch (dev->chipset) {
1151 case 0x130:
1152 case 0x13b:
1153 obj_class = GP100_3D_CLASS;
1154 break;
1155 default:
1156 obj_class = GP102_3D_CLASS;
1157 break;
1158 }
1159 break;
1160 case 0x120:
1161 obj_class = GM200_3D_CLASS;
1162 break;
1163 case 0x110:
1164 obj_class = GM107_3D_CLASS;
1165 break;
1166 case 0x100:
1167 case 0xf0:
1168 obj_class = NVF0_3D_CLASS;
1169 break;
1170 case 0xe0:
1171 switch (dev->chipset) {
1172 case 0xea:
1173 obj_class = NVEA_3D_CLASS;
1174 break;
1175 default:
1176 obj_class = NVE4_3D_CLASS;
1177 break;
1178 }
1179 break;
1180 case 0xd0:
1181 obj_class = NVC8_3D_CLASS;
1182 break;
1183 case 0xc0:
1184 default:
1185 switch (dev->chipset) {
1186 case 0xc8:
1187 obj_class = NVC8_3D_CLASS;
1188 break;
1189 case 0xc1:
1190 obj_class = NVC1_3D_CLASS;
1191 break;
1192 default:
1193 obj_class = NVC0_3D_CLASS;
1194 break;
1195 }
1196 break;
1197 }
1198 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1199 &screen->eng3d);
1200 if (ret)
1201 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1202 screen->base.class_3d = obj_class;
1203
1204 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1205 PUSH_DATA (push, screen->eng3d->oclass);
1206
1207 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1208 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1209
1210 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1211 /* kill shaders after about 1 second (at 100 MHz) */
1212 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1213 PUSH_DATA (push, 0x17);
1214 }
1215
1216 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1217 screen->base.drm->version >= 0x01000101);
1218 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1219 for (i = 0; i < 8; ++i)
1220 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1221
1222 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1223 PUSH_DATA (push, 1);
1224
1225 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1226 PUSH_DATA (push, 0);
1227 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1228 PUSH_DATA (push, 0);
1229 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1230 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1231 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1232 PUSH_DATA (push, 0);
1233 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1234 PUSH_DATA (push, 1);
1235 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1236 PUSH_DATA (push, 1);
1237 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1238 PUSH_DATA (push, 1);
1239 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1240 PUSH_DATA (push, 0);
1241 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1242 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1243 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1244 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1245 } else {
1246 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1247 PUSH_DATA (push, 15);
1248 }
1249 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1250 PUSH_DATA (push, 8); /* 128 */
1251 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1252 PUSH_DATA (push, 1);
1253 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1254 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1255 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1256 }
1257
1258 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1259
1260 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1261 if (ret)
1262 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1263
1264 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1265 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1266 &screen->uniform_bo);
1267 if (ret)
1268 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1269
1270 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1271
1272 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1273 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1274 PUSH_DATA (push, 256);
1275 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1276 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1277 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1278 PUSH_DATA (push, 0);
1279 PUSH_DATAf(push, 0.0f);
1280 PUSH_DATAf(push, 0.0f);
1281 PUSH_DATAf(push, 0.0f);
1282 PUSH_DATAf(push, 0.0f);
1283 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1284 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1285 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1286
1287 if (screen->base.drm->version >= 0x01000101) {
1288 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1289 if (ret)
1290 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1291 } else {
1292 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1293 value = (8 << 8) | 4;
1294 else
1295 value = (16 << 8) | 4;
1296 }
1297 screen->gpc_count = value & 0x000000ff;
1298 screen->mp_count = value >> 8;
1299 screen->mp_count_compute = screen->mp_count;
1300
1301 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1302 if (ret)
1303 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1304
1305 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1306 PUSH_DATAh(push, screen->tls->offset);
1307 PUSH_DATA (push, screen->tls->offset);
1308 PUSH_DATA (push, screen->tls->size >> 32);
1309 PUSH_DATA (push, screen->tls->size);
1310 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1311 PUSH_DATA (push, 0);
1312 /* Reduce likelihood of collision with real buffers by placing the hole at
1313 * the top of the 4G area. This will have to be dealt with for real
1314 * eventually by blocking off that area from the VM.
1315 */
1316 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1317 PUSH_DATA (push, 0xff << 24);
1318
1319 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1320 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1321 &screen->poly_cache);
1322 if (ret)
1323 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1324
1325 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1326 PUSH_DATAh(push, screen->poly_cache->offset);
1327 PUSH_DATA (push, screen->poly_cache->offset);
1328 PUSH_DATA (push, 3);
1329 }
1330
1331 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1332 &screen->txc);
1333 if (ret)
1334 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1335
1336 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1337 PUSH_DATAh(push, screen->txc->offset);
1338 PUSH_DATA (push, screen->txc->offset);
1339 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1340 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1341 screen->tic.maxwell = true;
1342 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1343 screen->tic.maxwell =
1344 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1345 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1346 }
1347 }
1348
1349 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1350 PUSH_DATAh(push, screen->txc->offset + 65536);
1351 PUSH_DATA (push, screen->txc->offset + 65536);
1352 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1353
1354 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1355 PUSH_DATA (push, 0);
1356 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1357 PUSH_DATA (push, 0);
1358 PUSH_DATA (push, 0);
1359 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1360 PUSH_DATA (push, 0x3f);
1361
1362 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1363 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1364 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1365 for (i = 0; i < 8 * 2; ++i)
1366 PUSH_DATA(push, 0);
1367 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1368 PUSH_DATA (push, 0);
1369 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1370 PUSH_DATA (push, 0);
1371
1372 /* neither scissors, viewport nor stencil mask should affect clears */
1373 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1374 PUSH_DATA (push, 0);
1375
1376 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1377 PUSH_DATA (push, 1);
1378 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1379 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1380 PUSH_DATAf(push, 0.0f);
1381 PUSH_DATAf(push, 1.0f);
1382 }
1383 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1384 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1385
1386 /* We use scissors instead of exact view volume clipping,
1387 * so they're always enabled.
1388 */
1389 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1390 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1391 PUSH_DATA (push, 1);
1392 PUSH_DATA (push, 16384 << 16);
1393 PUSH_DATA (push, 16384 << 16);
1394 }
1395
1396 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1397
1398 i = 0;
1399 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1400 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1401 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1402 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1403 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1404 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1405 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1406 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1407 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1408 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1409 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1410 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1411 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1412 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1413 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1414 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1415
1416 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1417 PUSH_DATA (push, 1);
1418 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1419 PUSH_DATA (push, 1);
1420 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1421 PUSH_DATA (push, 0x40);
1422 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1423 PUSH_DATA (push, 0);
1424 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1425 PUSH_DATA (push, 0x30);
1426 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1427 PUSH_DATA (push, 3);
1428 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1429 PUSH_DATA (push, 0x20);
1430 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1431 PUSH_DATA (push, 0x00);
1432 screen->save_state.patch_vertices = 3;
1433
1434 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1435 PUSH_DATA (push, 0);
1436 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1437 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1438
1439 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1440
1441 if (nvc0_screen_init_compute(screen))
1442 goto fail;
1443
1444 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1445 for (i = 0; i < 5; ++i) {
1446 unsigned j = 0;
1447 for (j = 0; j < 16; j++)
1448 screen->cb_bindings[i][j].size = -1;
1449
1450 /* TIC and TSC entries for each unit (nve4+ only) */
1451 /* auxiliary constants (6 user clip planes, base instance id) */
1452 nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1453 screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1454 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1455 unsigned j;
1456 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1457 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1458 for (j = 0; j < 8; ++j)
1459 PUSH_DATA(push, j);
1460 } else {
1461 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1462 PUSH_DATA (push, 0x54);
1463 }
1464
1465 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1466 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1467 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1468 PUSH_DATA (push, 0); /* 0 */
1469 PUSH_DATA (push, 0);
1470 PUSH_DATA (push, 1); /* 1 */
1471 PUSH_DATA (push, 0);
1472 PUSH_DATA (push, 0); /* 2 */
1473 PUSH_DATA (push, 1);
1474 PUSH_DATA (push, 1); /* 3 */
1475 PUSH_DATA (push, 1);
1476 PUSH_DATA (push, 2); /* 4 */
1477 PUSH_DATA (push, 0);
1478 PUSH_DATA (push, 3); /* 5 */
1479 PUSH_DATA (push, 0);
1480 PUSH_DATA (push, 2); /* 6 */
1481 PUSH_DATA (push, 1);
1482 PUSH_DATA (push, 3); /* 7 */
1483 PUSH_DATA (push, 1);
1484 }
1485 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1486 PUSH_DATA (push, 0);
1487
1488 PUSH_KICK (push);
1489
1490 screen->tic.entries = CALLOC(
1491 NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1492 sizeof(void *));
1493 screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1494 screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1495
1496 if (!nvc0_blitter_create(screen))
1497 goto fail;
1498
1499 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1500
1501 return &screen->base;
1502
1503 fail:
1504 screen->base.base.context_create = NULL;
1505 return &screen->base;
1506 }
1507
1508 int
1509 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1510 {
1511 int i = screen->tic.next;
1512
1513 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1514 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1515
1516 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1517
1518 if (screen->tic.entries[i])
1519 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1520
1521 screen->tic.entries[i] = entry;
1522 return i;
1523 }
1524
1525 int
1526 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1527 {
1528 int i = screen->tsc.next;
1529
1530 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1531 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1532
1533 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1534
1535 if (screen->tsc.entries[i])
1536 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1537
1538 screen->tsc.entries[i] = entry;
1539 return i;
1540 }