src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/mme/com9097.mme.h"
  36 #include "nvc0/mme/com90c0.mme.h"
  37
  38 #include "nv50/g80_texture.xml.h"
  39
  40 static boolean
  41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  42                                 enum pipe_format format,
  43                                 enum pipe_texture_target target,
  44                                 unsigned sample_count,
  45                                 unsigned storage_sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  56       return false;
  57
  58    /* Short-circuit the rest of the logic -- this is used by the state tracker
  59     * to determine valid MS levels in a no-attachments scenario.
  60     */
  61    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  62       return true;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* shared is always supported */
  88    bindings &= ~(PIPE_BIND_LINEAR |
  89                  PIPE_BIND_SHARED);
  90
  91    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  92       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  93           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  94          /* This should work on Fermi, but for currently unknown reasons it
  95           * does not and results in breaking reads from pbos. */
  96          return false;
  97       }
  98    }
  99
 100    return (( nvc0_format_table[format].usage |
 101             nvc0_vertex_format[format].usage) & bindings) == bindings;
 102 }
 103
 104 static int
 105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 108    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 109
 110    switch (param) {
 111    /* non-boolean caps */
 112    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 113    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 114       return 15;
 115    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 116       return 12;
 117    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 118       return 2048;
 119    case PIPE_CAP_MIN_TEXEL_OFFSET:
 120       return -8;
 121    case PIPE_CAP_MAX_TEXEL_OFFSET:
 122       return 7;
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124       return -32;
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126       return 31;
 127    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 128       return 128 * 1024 * 1024;
 129    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 130       return 430;
 131    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 132       return 140;
 133    case PIPE_CAP_MAX_RENDER_TARGETS:
 134       return 8;
 135    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 136       return 1;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 138       return 4;
 139    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 140    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 141       return 128;
 142    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 143    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 144       return 1024;
 145    case PIPE_CAP_MAX_VERTEX_STREAMS:
 146       return 4;
 147    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 148       return 2048;
 149    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 150       return 256;
 151    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 152       if (class_3d < GM107_3D_CLASS)
 153          return 256; /* IMAGE bindings require alignment to 256 */
 154       return 16;
 155    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 156       return 16;
 157    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 158       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 159    case PIPE_CAP_MAX_VIEWPORTS:
 160       return NVC0_MAX_VIEWPORTS;
 161    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 162       return 4;
 163    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 164       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 165    case PIPE_CAP_ENDIANNESS:
 166       return PIPE_ENDIAN_LITTLE;
 167    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 168       return 30;
 169    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 170       return NVC0_MAX_WINDOW_RECTANGLES;
 171    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 172       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 173
 174    /* supported caps */
 175    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 176    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 177    case PIPE_CAP_TEXTURE_SWIZZLE:
 178    case PIPE_CAP_NPOT_TEXTURES:
 179    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 180    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 181    case PIPE_CAP_ANISOTROPIC_FILTER:
 182    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 183    case PIPE_CAP_CUBE_MAP_ARRAY:
 184    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 185    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 186    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 187    case PIPE_CAP_POINT_SPRITE:
 188    case PIPE_CAP_TGSI_TEXCOORD:
 189    case PIPE_CAP_SM3:
 190    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 191    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 192    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 193    case PIPE_CAP_QUERY_TIMESTAMP:
 194    case PIPE_CAP_QUERY_TIME_ELAPSED:
 195    case PIPE_CAP_OCCLUSION_QUERY:
 196    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 197    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 198    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 199    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 200    case PIPE_CAP_INDEP_BLEND_ENABLE:
 201    case PIPE_CAP_INDEP_BLEND_FUNC:
 202    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 203    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 204    case PIPE_CAP_PRIMITIVE_RESTART:
 205    case PIPE_CAP_TGSI_INSTANCEID:
 206    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 207    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 208    case PIPE_CAP_CONDITIONAL_RENDER:
 209    case PIPE_CAP_TEXTURE_BARRIER:
 210    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 211    case PIPE_CAP_START_INSTANCE:
 212    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 213    case PIPE_CAP_DRAW_INDIRECT:
 214    case PIPE_CAP_USER_VERTEX_BUFFERS:
 215    case PIPE_CAP_TEXTURE_QUERY_LOD:
 216    case PIPE_CAP_SAMPLE_SHADING:
 217    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 218    case PIPE_CAP_TEXTURE_GATHER_SM5:
 219    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 220    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 221    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 222    case PIPE_CAP_CLIP_HALFZ:
 223    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 224    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 225    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 226    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 227    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 228    case PIPE_CAP_TGSI_TXQS:
 229    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 230    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 231    case PIPE_CAP_SHAREABLE_SHADERS:
 232    case PIPE_CAP_CLEAR_TEXTURE:
 233    case PIPE_CAP_DRAW_PARAMETERS:
 234    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 235    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 236    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 237    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 238    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 239    case PIPE_CAP_INVALIDATE_BUFFER:
 240    case PIPE_CAP_STRING_MARKER:
 241    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 242    case PIPE_CAP_CULL_DISTANCE:
 243    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 244    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 245    case PIPE_CAP_TGSI_VOTE:
 246    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 247    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 248    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 249    case PIPE_CAP_DOUBLES:
 250    case PIPE_CAP_INT64:
 251    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 252    case PIPE_CAP_TGSI_CLOCK:
 253    case PIPE_CAP_COMPUTE:
 254    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 255    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 256    case PIPE_CAP_QUERY_SO_OVERFLOW:
 257       return 1;
 258    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 259       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 260    case PIPE_CAP_TGSI_FS_FBFETCH:
 261       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 262    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 263    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 264    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 265    case PIPE_CAP_POST_DEPTH_COVERAGE:
 266    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 267    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 268    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 269    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 270       return class_3d >= GM200_3D_CLASS;
 271    case PIPE_CAP_MAX_GS_INVOCATIONS:
 272       return 32;
 273    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 274       return 1 << 27;
 275    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 276       return class_3d >= GP100_3D_CLASS;
 277    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 278    case PIPE_CAP_TGSI_BALLOT:
 279    case PIPE_CAP_BINDLESS_TEXTURE:
 280       return class_3d >= NVE4_3D_CLASS;
 281
 282    /* unsupported caps */
 283    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 284    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 285    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 286    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 287    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 288    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 289    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 290    case PIPE_CAP_FAKE_SW_MSAA:
 291    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 292    case PIPE_CAP_VERTEXID_NOBASE:
 293    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 294    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 295    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 296    case PIPE_CAP_GENERATE_MIPMAP:
 297    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 298    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 299    case PIPE_CAP_QUERY_MEMORY_INFO:
 300    case PIPE_CAP_PCI_GROUP:
 301    case PIPE_CAP_PCI_BUS:
 302    case PIPE_CAP_PCI_DEVICE:
 303    case PIPE_CAP_PCI_FUNCTION:
 304    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 305    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 306    case PIPE_CAP_NATIVE_FENCE_FD:
 307    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 308    case PIPE_CAP_INT64_DIVMOD:
 309    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 310    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 311    case PIPE_CAP_MEMOBJ:
 312    case PIPE_CAP_LOAD_CONSTBUF:
 313    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 314    case PIPE_CAP_TILE_RASTER_ORDER:
 315    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 316    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 317    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 318    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 319    case PIPE_CAP_FENCE_SIGNAL:
 320    case PIPE_CAP_CONSTBUF0_FLAGS:
 321    case PIPE_CAP_PACKED_UNIFORMS:
 322    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 323       return 0;
 324
 325    case PIPE_CAP_VENDOR_ID:
 326       return 0x10de;
 327    case PIPE_CAP_DEVICE_ID: {
 328       uint64_t device_id;
 329       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 330          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 331          return -1;
 332       }
 333       return device_id;
 334    }
 335    case PIPE_CAP_ACCELERATED:
 336       return 1;
 337    case PIPE_CAP_VIDEO_MEMORY:
 338       return dev->vram_size >> 20;
 339    case PIPE_CAP_UMA:
 340       return 0;
 341    }
 342
 343    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 344    return 0;
 345 }
 346
 347 static int
 348 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 349                              enum pipe_shader_type shader,
 350                              enum pipe_shader_cap param)
 351 {
 352    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 353
 354    switch (shader) {
 355    case PIPE_SHADER_VERTEX:
 356    case PIPE_SHADER_GEOMETRY:
 357    case PIPE_SHADER_FRAGMENT:
 358    case PIPE_SHADER_COMPUTE:
 359    case PIPE_SHADER_TESS_CTRL:
 360    case PIPE_SHADER_TESS_EVAL:
 361       break;
 362    default:
 363       return 0;
 364    }
 365
 366    switch (param) {
 367    case PIPE_SHADER_CAP_PREFERRED_IR:
 368       return PIPE_SHADER_IR_TGSI;
 369    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 370       return 1 << PIPE_SHADER_IR_TGSI;
 371    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 372    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 373    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 374    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 375       return 16384;
 376    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 377       return 16;
 378    case PIPE_SHADER_CAP_MAX_INPUTS:
 379       if (shader == PIPE_SHADER_VERTEX)
 380          return 32;
 381       /* NOTE: These only count our slots for GENERIC varyings.
 382        * The address space may be larger, but the actual hard limit seems to be
 383        * less than what the address space layout permits, so don't add TEXCOORD,
 384        * COLOR, etc. here.
 385        */
 386       if (shader == PIPE_SHADER_FRAGMENT)
 387          return 0x1f0 / 16;
 388       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 389        * and excludes 0x60 per-patch inputs.
 390        */
 391       return 0x200 / 16;
 392    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 393       return 32;
 394    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 395       return NVC0_MAX_CONSTBUF_SIZE;
 396    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 397       return NVC0_MAX_PIPE_CONSTBUFS;
 398    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 399       return shader != PIPE_SHADER_FRAGMENT;
 400    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 401    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 402    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 403       return 1;
 404    case PIPE_SHADER_CAP_MAX_TEMPS:
 405       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 406    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 407       return 1;
 408    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 409       return 1;
 410    case PIPE_SHADER_CAP_SUBROUTINES:
 411       return 1;
 412    case PIPE_SHADER_CAP_INTEGERS:
 413       return 1;
 414    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 415       return 1;
 416    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 417       return 1;
 418    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 419       return 1;
 420    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 421    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 422    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 423    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 424    case PIPE_SHADER_CAP_INT64_ATOMICS:
 425    case PIPE_SHADER_CAP_FP16:
 426    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 427    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 428       return 0;
 429    case PIPE_SHADER_CAP_SCALAR_ISA:
 430       return 1;
 431    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 432       return NVC0_MAX_BUFFERS;
 433    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 434       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 435    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 436       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 437    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 438       return 32;
 439    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 440       if (class_3d >= NVE4_3D_CLASS)
 441          return NVC0_MAX_IMAGES;
 442       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 443          return NVC0_MAX_IMAGES;
 444       return 0;
 445    default:
 446       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 447       return 0;
 448    }
 449 }
 450
 451 static float
 452 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 453 {
 454    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 455
 456    switch (param) {
 457    case PIPE_CAPF_MAX_LINE_WIDTH:
 458    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 459       return 10.0f;
 460    case PIPE_CAPF_MAX_POINT_WIDTH:
 461       return 63.0f;
 462    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 463       return 63.375f;
 464    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 465       return 16.0f;
 466    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 467       return 15.0f;
 468    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 469       return 0.0f;
 470    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 471       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 472    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 473       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 474    }
 475
 476    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 477    return 0.0f;
 478 }
 479
 480 static int
 481 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 482                               enum pipe_shader_ir ir_type,
 483                               enum pipe_compute_cap param, void *data)
 484 {
 485    struct nvc0_screen *screen = nvc0_screen(pscreen);
 486    const uint16_t obj_class = screen->compute->oclass;
 487
 488 #define RET(x) do {                  \
 489    if (data)                         \
 490       memcpy(data, x, sizeof(x));    \
 491    return sizeof(x);                 \
 492 } while (0)
 493
 494    switch (param) {
 495    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 496       RET((uint64_t []) { 3 });
 497    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 498       if (obj_class >= NVE4_COMPUTE_CLASS) {
 499          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 500       } else {
 501          RET(((uint64_t []) { 65535, 65535, 65535 }));
 502       }
 503    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 504       RET(((uint64_t []) { 1024, 1024, 64 }));
 505    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 506       RET((uint64_t []) { 1024 });
 507    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 508       if (obj_class >= NVE4_COMPUTE_CLASS) {
 509          RET((uint64_t []) { 1024 });
 510       } else {
 511          RET((uint64_t []) { 512 });
 512       }
 513    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 514       RET((uint64_t []) { 1ULL << 40 });
 515    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 516       switch (obj_class) {
 517       case GM200_COMPUTE_CLASS:
 518          RET((uint64_t []) { 96 << 10 });
 519          break;
 520       case GM107_COMPUTE_CLASS:
 521          RET((uint64_t []) { 64 << 10 });
 522          break;
 523       default:
 524          RET((uint64_t []) { 48 << 10 });
 525          break;
 526       }
 527    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 528       RET((uint64_t []) { 512 << 10 });
 529    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 530       RET((uint64_t []) { 4096 });
 531    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 532       RET((uint32_t []) { 32 });
 533    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 534       RET((uint64_t []) { 1ULL << 40 });
 535    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 536       RET((uint32_t []) { 0 });
 537    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 538       RET((uint32_t []) { screen->mp_count_compute });
 539    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 540       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 541    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 542       RET((uint32_t []) { 64 });
 543    default:
 544       return 0;
 545    }
 546
 547 #undef RET
 548 }
 549
 550 static void
 551 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 552                                   unsigned sample_count,
 553                                   unsigned *width, unsigned *height)
 554 {
 555    switch (sample_count) {
 556    case 0:
 557    case 1:
 558       /* this could be 4x4, but the GL state tracker makes it difficult to
 559        * create a 1x MSAA texture and smaller grids save CB space */
 560       *width = 2;
 561       *height = 4;
 562       break;
 563    case 2:
 564       *width = 2;
 565       *height = 4;
 566       break;
 567    case 4:
 568       *width = 2;
 569       *height = 2;
 570       break;
 571    case 8:
 572       *width = 1;
 573       *height = 2;
 574       break;
 575    default:
 576       assert(0);
 577    }
 578 }
 579
 580 static void
 581 nvc0_screen_destroy(struct pipe_screen *pscreen)
 582 {
 583    struct nvc0_screen *screen = nvc0_screen(pscreen);
 584
 585    if (!nouveau_drm_screen_unref(&screen->base))
 586       return;
 587
 588    if (screen->base.fence.current) {
 589       struct nouveau_fence *current = NULL;
 590
 591       /* nouveau_fence_wait will create a new current fence, so wait on the
 592        * _current_ one, and remove both.
 593        */
 594       nouveau_fence_ref(screen->base.fence.current, &current);
 595       nouveau_fence_wait(current, NULL);
 596       nouveau_fence_ref(NULL, &current);
 597       nouveau_fence_ref(NULL, &screen->base.fence.current);
 598    }
 599    if (screen->base.pushbuf)
 600       screen->base.pushbuf->user_priv = NULL;
 601
 602    if (screen->blitter)
 603       nvc0_blitter_destroy(screen);
 604    if (screen->pm.prog) {
 605       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 606       nvc0_program_destroy(NULL, screen->pm.prog);
 607       FREE(screen->pm.prog);
 608    }
 609
 610    nouveau_bo_ref(NULL, &screen->text);
 611    nouveau_bo_ref(NULL, &screen->uniform_bo);
 612    nouveau_bo_ref(NULL, &screen->tls);
 613    nouveau_bo_ref(NULL, &screen->txc);
 614    nouveau_bo_ref(NULL, &screen->fence.bo);
 615    nouveau_bo_ref(NULL, &screen->poly_cache);
 616
 617    nouveau_heap_destroy(&screen->lib_code);
 618    nouveau_heap_destroy(&screen->text_heap);
 619
 620    FREE(screen->default_tsc);
 621    FREE(screen->tic.entries);
 622
 623    nouveau_object_del(&screen->eng3d);
 624    nouveau_object_del(&screen->eng2d);
 625    nouveau_object_del(&screen->m2mf);
 626    nouveau_object_del(&screen->compute);
 627    nouveau_object_del(&screen->nvsw);
 628
 629    nouveau_screen_fini(&screen->base);
 630
 631    FREE(screen);
 632 }
 633
 634 static int
 635 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 636                      unsigned size, const uint32_t *data)
 637 {
 638    struct nouveau_pushbuf *push = screen->base.pushbuf;
 639
 640    size /= 4;
 641
 642    assert((pos + size) <= 0x800);
 643
 644    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 645    PUSH_DATA (push, (m - 0x3800) / 8);
 646    PUSH_DATA (push, pos);
 647    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 648    PUSH_DATA (push, pos);
 649    PUSH_DATAp(push, data, size);
 650
 651    return pos + size;
 652 }
 653
 654 static void
 655 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 656 {
 657    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 658    PUSH_DATA (push, 0xff);
 659    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 660    PUSH_DATA (push, 0xff);
 661    PUSH_DATA (push, 0xff);
 662    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 663    PUSH_DATA (push, 0xff);
 664    PUSH_DATA (push, 0xff);
 665    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 666    PUSH_DATA (push, 0x3f);
 667
 668    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 669    PUSH_DATA (push, (3 << 16) | 3);
 670    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 671    PUSH_DATA (push, (2 << 16) | 2);
 672
 673    if (obj_class < GM107_3D_CLASS) {
 674       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 675       PUSH_DATA (push, 0);
 676    }
 677    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 678    PUSH_DATA (push, 0x10);
 679    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 680    PUSH_DATA (push, 0x10);
 681    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 682    PUSH_DATA (push, 0x10);
 683    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 684    PUSH_DATA (push, 0x10);
 685    PUSH_DATA (push, 0x10);
 686    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 687    PUSH_DATA (push, 0x10);
 688    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 689    PUSH_DATA (push, 0xe);
 690
 691    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 692    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 693    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 694    PUSH_DATA (push, 0);
 695    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 696    PUSH_DATA (push, 3);
 697
 698    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 699    PUSH_DATA (push, 0x3fffff);
 700    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 701    PUSH_DATA (push, 1);
 702    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 703    PUSH_DATA (push, 1);
 704
 705    if (obj_class < GM107_3D_CLASS) {
 706       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 707       PUSH_DATA (push, 3);
 708
 709       if (obj_class >= NVE4_3D_CLASS) {
 710          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 711          PUSH_DATA (push, 1);
 712       }
 713    }
 714
 715    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 716     * are supposed to do */
 717 }
 718
 719 static void
 720 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 721 {
 722    struct nvc0_screen *screen = nvc0_screen(pscreen);
 723    struct nouveau_pushbuf *push = screen->base.pushbuf;
 724
 725    /* we need to do it after possible flush in MARK_RING */
 726    *sequence = ++screen->base.fence.sequence;
 727
 728    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 729    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 730    PUSH_DATAh(push, screen->fence.bo->offset);
 731    PUSH_DATA (push, screen->fence.bo->offset);
 732    PUSH_DATA (push, *sequence);
 733    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 734               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 735 }
 736
 737 static u32
 738 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 739 {
 740    struct nvc0_screen *screen = nvc0_screen(pscreen);
 741    return screen->fence.map[0];
 742 }
 743
 744 static int
 745 nvc0_screen_init_compute(struct nvc0_screen *screen)
 746 {
 747    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 748
 749    switch (screen->base.device->chipset & ~0xf) {
 750    case 0xc0:
 751    case 0xd0:
 752       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 753    case 0xe0:
 754    case 0xf0:
 755    case 0x100:
 756    case 0x110:
 757    case 0x120:
 758    case 0x130:
 759       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 760    default:
 761       return -1;
 762    }
 763 }
 764
 765 static int
 766 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 767                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 768 {
 769    struct nouveau_bo *bo = NULL;
 770    int ret;
 771    uint64_t size = (lpos + lneg) * 32 + cstack;
 772
 773    if (size >= (1 << 20)) {
 774       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 775       return -1;
 776    }
 777
 778    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 779    size  = align(size, 0x8000);
 780    size *= screen->mp_count;
 781
 782    size = align(size, 1 << 17);
 783
 784    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 785                         NULL, &bo);
 786    if (ret)
 787       return ret;
 788
 789    /* Make sure that the pushbuf has acquired a reference to the old tls
 790     * segment, as it may have commands that will reference it.
 791     */
 792    if (screen->tls)
 793       PUSH_REFN(screen->base.pushbuf, screen->tls,
 794                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 795    nouveau_bo_ref(NULL, &screen->tls);
 796    screen->tls = bo;
 797    return 0;
 798 }
 799
 800 int
 801 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 802 {
 803    struct nouveau_pushbuf *push = screen->base.pushbuf;
 804    struct nouveau_bo *bo;
 805    int ret;
 806
 807    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 808                         1 << 17, size, NULL, &bo);
 809    if (ret)
 810       return ret;
 811
 812    /* Make sure that the pushbuf has acquired a reference to the old text
 813     * segment, as it may have commands that will reference it.
 814     */
 815    if (screen->text)
 816       PUSH_REFN(push, screen->text,
 817                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 818    nouveau_bo_ref(NULL, &screen->text);
 819    screen->text = bo;
 820
 821    nouveau_heap_destroy(&screen->lib_code);
 822    nouveau_heap_destroy(&screen->text_heap);
 823
 824    /* XXX: getting a page fault at the end of the code buffer every few
 825     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 826     */
 827    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 828
 829    /* update the code segment setup */
 830    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 831    PUSH_DATAh(push, screen->text->offset);
 832    PUSH_DATA (push, screen->text->offset);
 833    if (screen->compute) {
 834       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 835       PUSH_DATAh(push, screen->text->offset);
 836       PUSH_DATA (push, screen->text->offset);
 837    }
 838
 839    return 0;
 840 }
 841
 842 void
 843 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 844                        int stage, int index, int size, uint64_t addr)
 845 {
 846    assert(stage != 5);
 847
 848    struct nouveau_pushbuf *push = screen->base.pushbuf;
 849
 850    if (screen->base.class_3d >= GM107_3D_CLASS) {
 851       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 852
 853       // TODO: Better figure out the conditions in which this is needed
 854       bool serialize = binding->addr == addr && binding->size != size;
 855       if (can_serialize)
 856          serialize = serialize && *can_serialize;
 857       if (serialize) {
 858          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 859          if (can_serialize)
 860             *can_serialize = false;
 861       }
 862
 863       binding->addr = addr;
 864       binding->size = size;
 865    }
 866
 867    if (size >= 0) {
 868       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 869       PUSH_DATA (push, size);
 870       PUSH_DATAh(push, addr);
 871       PUSH_DATA (push, addr);
 872    }
 873    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 874 }
 875
 876 #define FAIL_SCREEN_INIT(str, err)                    \
 877    do {                                               \
 878       NOUVEAU_ERR(str, err);                          \
 879       goto fail;                                      \
 880    } while(0)
 881
 882 struct nouveau_screen *
 883 nvc0_screen_create(struct nouveau_device *dev)
 884 {
 885    struct nvc0_screen *screen;
 886    struct pipe_screen *pscreen;
 887    struct nouveau_object *chan;
 888    struct nouveau_pushbuf *push;
 889    uint64_t value;
 890    uint32_t obj_class;
 891    uint32_t flags;
 892    int ret;
 893    unsigned i;
 894
 895    switch (dev->chipset & ~0xf) {
 896    case 0xc0:
 897    case 0xd0:
 898    case 0xe0:
 899    case 0xf0:
 900    case 0x100:
 901    case 0x110:
 902    case 0x120:
 903    case 0x130:
 904       break;
 905    default:
 906       return NULL;
 907    }
 908
 909    screen = CALLOC_STRUCT(nvc0_screen);
 910    if (!screen)
 911       return NULL;
 912    pscreen = &screen->base.base;
 913    pscreen->destroy = nvc0_screen_destroy;
 914
 915    ret = nouveau_screen_init(&screen->base, dev);
 916    if (ret)
 917       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 918    chan = screen->base.channel;
 919    push = screen->base.pushbuf;
 920    push->user_priv = screen;
 921    push->rsvd_kick = 5;
 922
 923    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 924       PIPE_BIND_SHADER_BUFFER |
 925       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 926       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 927    screen->base.sysmem_bindings |=
 928       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 929
 930    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 931       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 932       screen->base.vidmem_bindings = 0;
 933    }
 934
 935    pscreen->context_create = nvc0_create;
 936    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 937    pscreen->get_param = nvc0_screen_get_param;
 938    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 939    pscreen->get_paramf = nvc0_screen_get_paramf;
 940    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
 941    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 942    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 943
 944    nvc0_screen_init_resource_functions(pscreen);
 945
 946    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 947    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 948
 949    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 950    if (screen->base.drm->version >= 0x01000202)
 951       flags |= NOUVEAU_BO_COHERENT;
 952
 953    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 954    if (ret)
 955       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 956    nouveau_bo_map(screen->fence.bo, 0, NULL);
 957    screen->fence.map = screen->fence.bo->map;
 958    screen->base.fence.emit = nvc0_screen_fence_emit;
 959    screen->base.fence.update = nvc0_screen_fence_update;
 960
 961
 962    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 963                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 964    if (ret)
 965       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 966
 967    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 968    PUSH_DATA (push, screen->nvsw->handle);
 969
 970    switch (dev->chipset & ~0xf) {
 971    case 0x130:
 972    case 0x120:
 973    case 0x110:
 974    case 0x100:
 975    case 0xf0:
 976       obj_class = NVF0_P2MF_CLASS;
 977       break;
 978    case 0xe0:
 979       obj_class = NVE4_P2MF_CLASS;
 980       break;
 981    default:
 982       obj_class = NVC0_M2MF_CLASS;
 983       break;
 984    }
 985    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 986                             &screen->m2mf);
 987    if (ret)
 988       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 989
 990    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 991    PUSH_DATA (push, screen->m2mf->oclass);
 992    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 993       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 994       PUSH_DATA (push, 0xa0b5);
 995    }
 996
 997    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 998                             &screen->eng2d);
 999    if (ret)
1000       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1001
1002    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1003    PUSH_DATA (push, screen->eng2d->oclass);
1004    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1005    PUSH_DATA (push, 0);
1006    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1007    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1008    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1009    PUSH_DATA (push, 0);
1010    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1011    PUSH_DATA (push, 0);
1012    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1013    PUSH_DATA (push, 0x3f);
1014    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1015    PUSH_DATA (push, 1);
1016    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1017    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1018
1019    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1020    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1021    PUSH_DATA (push, screen->fence.bo->offset + 16);
1022
1023    switch (dev->chipset & ~0xf) {
1024    case 0x130:
1025       switch (dev->chipset) {
1026       case 0x130:
1027       case 0x13b:
1028          obj_class = GP100_3D_CLASS;
1029          break;
1030       default:
1031          obj_class = GP102_3D_CLASS;
1032          break;
1033       }
1034       break;
1035    case 0x120:
1036       obj_class = GM200_3D_CLASS;
1037       break;
1038    case 0x110:
1039       obj_class = GM107_3D_CLASS;
1040       break;
1041    case 0x100:
1042    case 0xf0:
1043       obj_class = NVF0_3D_CLASS;
1044       break;
1045    case 0xe0:
1046       switch (dev->chipset) {
1047       case 0xea:
1048          obj_class = NVEA_3D_CLASS;
1049          break;
1050       default:
1051          obj_class = NVE4_3D_CLASS;
1052          break;
1053       }
1054       break;
1055    case 0xd0:
1056       obj_class = NVC8_3D_CLASS;
1057       break;
1058    case 0xc0:
1059    default:
1060       switch (dev->chipset) {
1061       case 0xc8:
1062          obj_class = NVC8_3D_CLASS;
1063          break;
1064       case 0xc1:
1065          obj_class = NVC1_3D_CLASS;
1066          break;
1067       default:
1068          obj_class = NVC0_3D_CLASS;
1069          break;
1070       }
1071       break;
1072    }
1073    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1074                             &screen->eng3d);
1075    if (ret)
1076       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1077    screen->base.class_3d = obj_class;
1078
1079    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1080    PUSH_DATA (push, screen->eng3d->oclass);
1081
1082    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1083    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1084
1085    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1086       /* kill shaders after about 1 second (at 100 MHz) */
1087       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1088       PUSH_DATA (push, 0x17);
1089    }
1090
1091    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1092                     screen->base.drm->version >= 0x01000101);
1093    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1094    for (i = 0; i < 8; ++i)
1095       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1096
1097    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1098    PUSH_DATA (push, 1);
1099
1100    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1101    PUSH_DATA (push, 0);
1102    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1103    PUSH_DATA (push, 0);
1104    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1105    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1106    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1107    PUSH_DATA (push, 0);
1108    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1109    PUSH_DATA (push, 1);
1110    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1111    PUSH_DATA (push, 1);
1112    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1113    PUSH_DATA (push, 1);
1114    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1115    PUSH_DATA (push, 0);
1116    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1117    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1118    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1119       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1120    } else {
1121       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1122       PUSH_DATA (push, 15);
1123    }
1124    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1125    PUSH_DATA (push, 8); /* 128 */
1126    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1127    PUSH_DATA (push, 1);
1128    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1129       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1130       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1131    }
1132
1133    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1134
1135    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1136    if (ret)
1137       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1138
1139    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1140    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1141                         &screen->uniform_bo);
1142    if (ret)
1143       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1144
1145    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1146
1147    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1148    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1149    PUSH_DATA (push, 256);
1150    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1151    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1152    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1153    PUSH_DATA (push, 0);
1154    PUSH_DATAf(push, 0.0f);
1155    PUSH_DATAf(push, 0.0f);
1156    PUSH_DATAf(push, 0.0f);
1157    PUSH_DATAf(push, 0.0f);
1158    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1159    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1160    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1161
1162    if (screen->base.drm->version >= 0x01000101) {
1163       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1164       if (ret)
1165          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1166    } else {
1167       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1168          value = (8 << 8) | 4;
1169       else
1170          value = (16 << 8) | 4;
1171    }
1172    screen->gpc_count = value & 0x000000ff;
1173    screen->mp_count = value >> 8;
1174    screen->mp_count_compute = screen->mp_count;
1175
1176    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1177    if (ret)
1178       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1179
1180    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1181    PUSH_DATAh(push, screen->tls->offset);
1182    PUSH_DATA (push, screen->tls->offset);
1183    PUSH_DATA (push, screen->tls->size >> 32);
1184    PUSH_DATA (push, screen->tls->size);
1185    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1186    PUSH_DATA (push, 0);
1187    /* Reduce likelihood of collision with real buffers by placing the hole at
1188     * the top of the 4G area. This will have to be dealt with for real
1189     * eventually by blocking off that area from the VM.
1190     */
1191    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1192    PUSH_DATA (push, 0xff << 24);
1193
1194    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1195       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1196                            &screen->poly_cache);
1197       if (ret)
1198          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1199
1200       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1201       PUSH_DATAh(push, screen->poly_cache->offset);
1202       PUSH_DATA (push, screen->poly_cache->offset);
1203       PUSH_DATA (push, 3);
1204    }
1205
1206    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1207                         &screen->txc);
1208    if (ret)
1209       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1210
1211    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1212    PUSH_DATAh(push, screen->txc->offset);
1213    PUSH_DATA (push, screen->txc->offset);
1214    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1215    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1216       screen->tic.maxwell = true;
1217       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1218          screen->tic.maxwell =
1219             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1220          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1221       }
1222    }
1223
1224    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1225    PUSH_DATAh(push, screen->txc->offset + 65536);
1226    PUSH_DATA (push, screen->txc->offset + 65536);
1227    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1228
1229    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1230    PUSH_DATA (push, 0);
1231    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1232    PUSH_DATA (push, 0);
1233    PUSH_DATA (push, 0);
1234    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1235    PUSH_DATA (push, 0x3f);
1236
1237    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1238    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1239    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1240    for (i = 0; i < 8 * 2; ++i)
1241       PUSH_DATA(push, 0);
1242    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1243    PUSH_DATA (push, 0);
1244    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1245    PUSH_DATA (push, 0);
1246
1247    /* neither scissors, viewport nor stencil mask should affect clears */
1248    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1249    PUSH_DATA (push, 0);
1250
1251    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1252    PUSH_DATA (push, 1);
1253    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1254       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1255       PUSH_DATAf(push, 0.0f);
1256       PUSH_DATAf(push, 1.0f);
1257    }
1258    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1259    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1260
1261    /* We use scissors instead of exact view volume clipping,
1262     * so they're always enabled.
1263     */
1264    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1265       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1266       PUSH_DATA (push, 1);
1267       PUSH_DATA (push, 8192 << 16);
1268       PUSH_DATA (push, 8192 << 16);
1269    }
1270
1271 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1272
1273    i = 0;
1274    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1275    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1276    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1277    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1278    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1279    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1280    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1281    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1282    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1283    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1284    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1285    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1286    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1287    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1288
1289    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1290    PUSH_DATA (push, 1);
1291    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1292    PUSH_DATA (push, 1);
1293    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1294    PUSH_DATA (push, 0x40);
1295    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1296    PUSH_DATA (push, 0);
1297    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1298    PUSH_DATA (push, 0x30);
1299    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1300    PUSH_DATA (push, 3);
1301    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1302    PUSH_DATA (push, 0x20);
1303    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1304    PUSH_DATA (push, 0x00);
1305    screen->save_state.patch_vertices = 3;
1306
1307    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1308    PUSH_DATA (push, 0);
1309    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1310    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1311
1312    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1313
1314    if (nvc0_screen_init_compute(screen))
1315       goto fail;
1316
1317    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1318    for (i = 0; i < 5; ++i) {
1319       unsigned j = 0;
1320       for (j = 0; j < 16; j++)
1321          screen->cb_bindings[i][j].size = -1;
1322
1323       /* TIC and TSC entries for each unit (nve4+ only) */
1324       /* auxiliary constants (6 user clip planes, base instance id) */
1325       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1326                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1327       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1328          unsigned j;
1329          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1330          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1331          for (j = 0; j < 8; ++j)
1332             PUSH_DATA(push, j);
1333       } else {
1334          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1335          PUSH_DATA (push, 0x54);
1336       }
1337
1338       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1339       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1340       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1341       PUSH_DATA (push, 0); /* 0 */
1342       PUSH_DATA (push, 0);
1343       PUSH_DATA (push, 1); /* 1 */
1344       PUSH_DATA (push, 0);
1345       PUSH_DATA (push, 0); /* 2 */
1346       PUSH_DATA (push, 1);
1347       PUSH_DATA (push, 1); /* 3 */
1348       PUSH_DATA (push, 1);
1349       PUSH_DATA (push, 2); /* 4 */
1350       PUSH_DATA (push, 0);
1351       PUSH_DATA (push, 3); /* 5 */
1352       PUSH_DATA (push, 0);
1353       PUSH_DATA (push, 2); /* 6 */
1354       PUSH_DATA (push, 1);
1355       PUSH_DATA (push, 3); /* 7 */
1356       PUSH_DATA (push, 1);
1357    }
1358    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1359    PUSH_DATA (push, 0);
1360
1361    PUSH_KICK (push);
1362
1363    screen->tic.entries = CALLOC(
1364          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1365          sizeof(void *));
1366    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1367    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1368
1369    if (!nvc0_blitter_create(screen))
1370       goto fail;
1371
1372    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1373    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1374
1375    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1376
1377    return &screen->base;
1378
1379 fail:
1380    screen->base.base.context_create = NULL;
1381    return &screen->base;
1382 }
1383
1384 int
1385 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1386 {
1387    int i = screen->tic.next;
1388
1389    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1390       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1391
1392    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1393
1394    if (screen->tic.entries[i])
1395       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1396
1397    screen->tic.entries[i] = entry;
1398    return i;
1399 }
1400
1401 int
1402 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1403 {
1404    int i = screen->tsc.next;
1405
1406    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1407       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1408
1409    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1410
1411    if (screen->tsc.entries[i])
1412       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1413
1414    screen->tsc.entries[i] = entry;
1415    return i;
1416 }