src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30
  31 #include "nouveau_vp3_video.h"
  32
  33 #include "nvc0/nvc0_context.h"
  34 #include "nvc0/nvc0_screen.h"
  35
  36 #include "nvc0/mme/com9097.mme.h"
  37 #include "nvc0/mme/com90c0.mme.h"
  38
  39 #include "nv50/g80_texture.xml.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned storage_sample_count,
  47                                 unsigned bindings)
  48 {
  49    const struct util_format_description *desc = util_format_description(format);
  50
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55
  56    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  57       return false;
  58
  59    /* Short-circuit the rest of the logic -- this is used by the state tracker
  60     * to determine valid MS levels in a no-attachments scenario.
  61     */
  62    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  63       return true;
  64
  65    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  66       if (util_format_get_blocksizebits(format) == 3 * 32)
  67          return false;
  68
  69    if (bindings & PIPE_BIND_LINEAR)
  70       if (util_format_is_depth_or_stencil(format) ||
  71           (target != PIPE_TEXTURE_1D &&
  72            target != PIPE_TEXTURE_2D &&
  73            target != PIPE_TEXTURE_RECT) ||
  74           sample_count > 1)
  75          return false;
  76
  77    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  78     */
  79    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  80         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  81        /* The claim is that this should work on GM107 but it doesn't. Need to
  82         * test further and figure out if it's a nouveau issue or a HW one.
  83        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  84         */
  85        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  86       return false;
  87
  88    /* shared is always supported */
  89    bindings &= ~(PIPE_BIND_LINEAR |
  90                  PIPE_BIND_SHARED);
  91
  92    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  93       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  94           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  95          /* This should work on Fermi, but for currently unknown reasons it
  96           * does not and results in breaking reads from pbos. */
  97          return false;
  98       }
  99    }
 100
 101    return (( nvc0_format_table[format].usage |
 102             nvc0_vertex_format[format].usage) & bindings) == bindings;
 103 }
 104
 105 static int
 106 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 107 {
 108    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 109    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 110
 111    switch (param) {
 112    /* non-boolean caps */
 113    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 114    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 115       return 15;
 116    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 117       return 12;
 118    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 119       return 2048;
 120    case PIPE_CAP_MIN_TEXEL_OFFSET:
 121       return -8;
 122    case PIPE_CAP_MAX_TEXEL_OFFSET:
 123       return 7;
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125       return -32;
 126    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 127       return 31;
 128    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 129       return 128 * 1024 * 1024;
 130    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 131       return 430;
 132    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 133       return 430;
 134    case PIPE_CAP_MAX_RENDER_TARGETS:
 135       return 8;
 136    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 137       return 1;
 138    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 139    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 140       return 8;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 145       return 128;
 146    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 147    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 148       return 1024;
 149    case PIPE_CAP_MAX_VERTEX_STREAMS:
 150       return 4;
 151    case PIPE_CAP_MAX_GS_INVOCATIONS:
 152       return 32;
 153    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 154       return 1 << 27;
 155    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 156       return 2048;
 157    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 158       return 256;
 159    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 160       if (class_3d < GM107_3D_CLASS)
 161          return 256; /* IMAGE bindings require alignment to 256 */
 162       return 16;
 163    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 164       return 16;
 165    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 166       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 167    case PIPE_CAP_MAX_VIEWPORTS:
 168       return NVC0_MAX_VIEWPORTS;
 169    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 170       return 4;
 171    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 172       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 173    case PIPE_CAP_ENDIANNESS:
 174       return PIPE_ENDIAN_LITTLE;
 175    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 176       return 30;
 177    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 178       return NVC0_MAX_WINDOW_RECTANGLES;
 179    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 180       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 181
 182    /* supported caps */
 183    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 184    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 185    case PIPE_CAP_TEXTURE_SWIZZLE:
 186    case PIPE_CAP_NPOT_TEXTURES:
 187    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 188    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 189    case PIPE_CAP_ANISOTROPIC_FILTER:
 190    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 191    case PIPE_CAP_CUBE_MAP_ARRAY:
 192    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 193    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 194    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 195    case PIPE_CAP_POINT_SPRITE:
 196    case PIPE_CAP_TGSI_TEXCOORD:
 197    case PIPE_CAP_SM3:
 198    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 199    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 200    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 201    case PIPE_CAP_QUERY_TIMESTAMP:
 202    case PIPE_CAP_QUERY_TIME_ELAPSED:
 203    case PIPE_CAP_OCCLUSION_QUERY:
 204    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 205    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 206    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 207    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 208    case PIPE_CAP_INDEP_BLEND_ENABLE:
 209    case PIPE_CAP_INDEP_BLEND_FUNC:
 210    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 211    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 212    case PIPE_CAP_PRIMITIVE_RESTART:
 213    case PIPE_CAP_TGSI_INSTANCEID:
 214    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 215    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 216    case PIPE_CAP_CONDITIONAL_RENDER:
 217    case PIPE_CAP_TEXTURE_BARRIER:
 218    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 219    case PIPE_CAP_START_INSTANCE:
 220    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 221    case PIPE_CAP_DRAW_INDIRECT:
 222    case PIPE_CAP_USER_VERTEX_BUFFERS:
 223    case PIPE_CAP_TEXTURE_QUERY_LOD:
 224    case PIPE_CAP_SAMPLE_SHADING:
 225    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 226    case PIPE_CAP_TEXTURE_GATHER_SM5:
 227    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 228    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 229    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 230    case PIPE_CAP_CLIP_HALFZ:
 231    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 232    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 233    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 234    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 235    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 236    case PIPE_CAP_TGSI_TXQS:
 237    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 238    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 239    case PIPE_CAP_SHAREABLE_SHADERS:
 240    case PIPE_CAP_CLEAR_TEXTURE:
 241    case PIPE_CAP_DRAW_PARAMETERS:
 242    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 243    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 244    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 245    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 246    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 247    case PIPE_CAP_INVALIDATE_BUFFER:
 248    case PIPE_CAP_STRING_MARKER:
 249    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 250    case PIPE_CAP_CULL_DISTANCE:
 251    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 252    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 253    case PIPE_CAP_TGSI_VOTE:
 254    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 255    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 256    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 257    case PIPE_CAP_DOUBLES:
 258    case PIPE_CAP_INT64:
 259    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 260    case PIPE_CAP_TGSI_CLOCK:
 261    case PIPE_CAP_COMPUTE:
 262    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 263    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 264    case PIPE_CAP_QUERY_SO_OVERFLOW:
 265       return 1;
 266    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 267       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 268    case PIPE_CAP_TGSI_FS_FBFETCH:
 269       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 270    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 271    case PIPE_CAP_TGSI_BALLOT:
 272    case PIPE_CAP_BINDLESS_TEXTURE:
 273       return class_3d >= NVE4_3D_CLASS;
 274    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 275    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 276    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 277    case PIPE_CAP_POST_DEPTH_COVERAGE:
 278    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 279    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 280    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 281    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 282       return class_3d >= GM200_3D_CLASS;
 283    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 284       return class_3d >= GP100_3D_CLASS;
 285
 286    /* unsupported caps */
 287    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 288    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 289    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 290    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 291    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 292    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 293    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 294    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 295    case PIPE_CAP_FAKE_SW_MSAA:
 296    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 297    case PIPE_CAP_VERTEXID_NOBASE:
 298    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 299    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 300    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 301    case PIPE_CAP_GENERATE_MIPMAP:
 302    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 303    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 304    case PIPE_CAP_QUERY_MEMORY_INFO:
 305    case PIPE_CAP_PCI_GROUP:
 306    case PIPE_CAP_PCI_BUS:
 307    case PIPE_CAP_PCI_DEVICE:
 308    case PIPE_CAP_PCI_FUNCTION:
 309    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 310    case PIPE_CAP_NATIVE_FENCE_FD:
 311    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 312    case PIPE_CAP_INT64_DIVMOD:
 313    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 314    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 315    case PIPE_CAP_MEMOBJ:
 316    case PIPE_CAP_LOAD_CONSTBUF:
 317    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 318    case PIPE_CAP_TILE_RASTER_ORDER:
 319    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 320    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 321    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 322    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 323    case PIPE_CAP_FENCE_SIGNAL:
 324    case PIPE_CAP_CONSTBUF0_FLAGS:
 325    case PIPE_CAP_PACKED_UNIFORMS:
 326    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 327    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 328    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 329    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 330    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 331       return 0;
 332
 333    case PIPE_CAP_VENDOR_ID:
 334       return 0x10de;
 335    case PIPE_CAP_DEVICE_ID: {
 336       uint64_t device_id;
 337       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 338          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 339          return -1;
 340       }
 341       return device_id;
 342    }
 343    case PIPE_CAP_ACCELERATED:
 344       return 1;
 345    case PIPE_CAP_VIDEO_MEMORY:
 346       return dev->vram_size >> 20;
 347    case PIPE_CAP_UMA:
 348       return 0;
 349    default:
 350       debug_printf("%s: unhandled cap %d\n", __func__, param);
 351       return u_pipe_screen_get_param_defaults(pscreen, param);
 352    }
 353 }
 354
 355 static int
 356 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 357                              enum pipe_shader_type shader,
 358                              enum pipe_shader_cap param)
 359 {
 360    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 361
 362    switch (shader) {
 363    case PIPE_SHADER_VERTEX:
 364    case PIPE_SHADER_GEOMETRY:
 365    case PIPE_SHADER_FRAGMENT:
 366    case PIPE_SHADER_COMPUTE:
 367    case PIPE_SHADER_TESS_CTRL:
 368    case PIPE_SHADER_TESS_EVAL:
 369       break;
 370    default:
 371       return 0;
 372    }
 373
 374    switch (param) {
 375    case PIPE_SHADER_CAP_PREFERRED_IR:
 376       return PIPE_SHADER_IR_TGSI;
 377    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 378       return 1 << PIPE_SHADER_IR_TGSI;
 379    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 380    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 381    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 382    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 383       return 16384;
 384    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 385       return 16;
 386    case PIPE_SHADER_CAP_MAX_INPUTS:
 387       if (shader == PIPE_SHADER_VERTEX)
 388          return 32;
 389       /* NOTE: These only count our slots for GENERIC varyings.
 390        * The address space may be larger, but the actual hard limit seems to be
 391        * less than what the address space layout permits, so don't add TEXCOORD,
 392        * COLOR, etc. here.
 393        */
 394       if (shader == PIPE_SHADER_FRAGMENT)
 395          return 0x1f0 / 16;
 396       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 397        * and excludes 0x60 per-patch inputs.
 398        */
 399       return 0x200 / 16;
 400    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 401       return 32;
 402    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 403       return NVC0_MAX_CONSTBUF_SIZE;
 404    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 405       return NVC0_MAX_PIPE_CONSTBUFS;
 406    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 407       return shader != PIPE_SHADER_FRAGMENT;
 408    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 409    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 410    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 411       return 1;
 412    case PIPE_SHADER_CAP_MAX_TEMPS:
 413       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 414    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 415       return 1;
 416    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 417       return 1;
 418    case PIPE_SHADER_CAP_SUBROUTINES:
 419       return 1;
 420    case PIPE_SHADER_CAP_INTEGERS:
 421       return 1;
 422    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 423       return 1;
 424    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 425       return 1;
 426    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 427       return 1;
 428    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 429    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 430    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 431    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 432    case PIPE_SHADER_CAP_INT64_ATOMICS:
 433    case PIPE_SHADER_CAP_FP16:
 434    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 435    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 436       return 0;
 437    case PIPE_SHADER_CAP_SCALAR_ISA:
 438       return 1;
 439    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 440       return NVC0_MAX_BUFFERS;
 441    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 442       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 443    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 444       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 445    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 446       return 32;
 447    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 448       if (class_3d >= NVE4_3D_CLASS)
 449          return NVC0_MAX_IMAGES;
 450       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 451          return NVC0_MAX_IMAGES;
 452       return 0;
 453    default:
 454       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 455       return 0;
 456    }
 457 }
 458
 459 static float
 460 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 461 {
 462    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 463
 464    switch (param) {
 465    case PIPE_CAPF_MAX_LINE_WIDTH:
 466    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 467       return 10.0f;
 468    case PIPE_CAPF_MAX_POINT_WIDTH:
 469       return 63.0f;
 470    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 471       return 63.375f;
 472    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 473       return 16.0f;
 474    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 475       return 15.0f;
 476    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 477       return 0.0f;
 478    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 479       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 480    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 481       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 482    }
 483
 484    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 485    return 0.0f;
 486 }
 487
 488 static int
 489 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 490                               enum pipe_shader_ir ir_type,
 491                               enum pipe_compute_cap param, void *data)
 492 {
 493    struct nvc0_screen *screen = nvc0_screen(pscreen);
 494    const uint16_t obj_class = screen->compute->oclass;
 495
 496 #define RET(x) do {                  \
 497    if (data)                         \
 498       memcpy(data, x, sizeof(x));    \
 499    return sizeof(x);                 \
 500 } while (0)
 501
 502    switch (param) {
 503    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 504       RET((uint64_t []) { 3 });
 505    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 506       if (obj_class >= NVE4_COMPUTE_CLASS) {
 507          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 508       } else {
 509          RET(((uint64_t []) { 65535, 65535, 65535 }));
 510       }
 511    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 512       RET(((uint64_t []) { 1024, 1024, 64 }));
 513    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 514       RET((uint64_t []) { 1024 });
 515    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 516       if (obj_class >= NVE4_COMPUTE_CLASS) {
 517          RET((uint64_t []) { 1024 });
 518       } else {
 519          RET((uint64_t []) { 512 });
 520       }
 521    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 522       RET((uint64_t []) { 1ULL << 40 });
 523    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 524       switch (obj_class) {
 525       case GM200_COMPUTE_CLASS:
 526          RET((uint64_t []) { 96 << 10 });
 527          break;
 528       case GM107_COMPUTE_CLASS:
 529          RET((uint64_t []) { 64 << 10 });
 530          break;
 531       default:
 532          RET((uint64_t []) { 48 << 10 });
 533          break;
 534       }
 535    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 536       RET((uint64_t []) { 512 << 10 });
 537    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 538       RET((uint64_t []) { 4096 });
 539    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 540       RET((uint32_t []) { 32 });
 541    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 542       RET((uint64_t []) { 1ULL << 40 });
 543    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 544       RET((uint32_t []) { 0 });
 545    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 546       RET((uint32_t []) { screen->mp_count_compute });
 547    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 548       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 549    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 550       RET((uint32_t []) { 64 });
 551    default:
 552       return 0;
 553    }
 554
 555 #undef RET
 556 }
 557
 558 static void
 559 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 560                                   unsigned sample_count,
 561                                   unsigned *width, unsigned *height)
 562 {
 563    switch (sample_count) {
 564    case 0:
 565    case 1:
 566       /* this could be 4x4, but the GL state tracker makes it difficult to
 567        * create a 1x MSAA texture and smaller grids save CB space */
 568       *width = 2;
 569       *height = 4;
 570       break;
 571    case 2:
 572       *width = 2;
 573       *height = 4;
 574       break;
 575    case 4:
 576       *width = 2;
 577       *height = 2;
 578       break;
 579    case 8:
 580       *width = 1;
 581       *height = 2;
 582       break;
 583    default:
 584       assert(0);
 585    }
 586 }
 587
 588 static void
 589 nvc0_screen_destroy(struct pipe_screen *pscreen)
 590 {
 591    struct nvc0_screen *screen = nvc0_screen(pscreen);
 592
 593    if (!nouveau_drm_screen_unref(&screen->base))
 594       return;
 595
 596    if (screen->base.fence.current) {
 597       struct nouveau_fence *current = NULL;
 598
 599       /* nouveau_fence_wait will create a new current fence, so wait on the
 600        * _current_ one, and remove both.
 601        */
 602       nouveau_fence_ref(screen->base.fence.current, &current);
 603       nouveau_fence_wait(current, NULL);
 604       nouveau_fence_ref(NULL, &current);
 605       nouveau_fence_ref(NULL, &screen->base.fence.current);
 606    }
 607    if (screen->base.pushbuf)
 608       screen->base.pushbuf->user_priv = NULL;
 609
 610    if (screen->blitter)
 611       nvc0_blitter_destroy(screen);
 612    if (screen->pm.prog) {
 613       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 614       nvc0_program_destroy(NULL, screen->pm.prog);
 615       FREE(screen->pm.prog);
 616    }
 617
 618    nouveau_bo_ref(NULL, &screen->text);
 619    nouveau_bo_ref(NULL, &screen->uniform_bo);
 620    nouveau_bo_ref(NULL, &screen->tls);
 621    nouveau_bo_ref(NULL, &screen->txc);
 622    nouveau_bo_ref(NULL, &screen->fence.bo);
 623    nouveau_bo_ref(NULL, &screen->poly_cache);
 624
 625    nouveau_heap_destroy(&screen->lib_code);
 626    nouveau_heap_destroy(&screen->text_heap);
 627
 628    FREE(screen->default_tsc);
 629    FREE(screen->tic.entries);
 630
 631    nouveau_object_del(&screen->eng3d);
 632    nouveau_object_del(&screen->eng2d);
 633    nouveau_object_del(&screen->m2mf);
 634    nouveau_object_del(&screen->compute);
 635    nouveau_object_del(&screen->nvsw);
 636
 637    nouveau_screen_fini(&screen->base);
 638
 639    FREE(screen);
 640 }
 641
 642 static int
 643 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 644                      unsigned size, const uint32_t *data)
 645 {
 646    struct nouveau_pushbuf *push = screen->base.pushbuf;
 647
 648    size /= 4;
 649
 650    assert((pos + size) <= 0x800);
 651
 652    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 653    PUSH_DATA (push, (m - 0x3800) / 8);
 654    PUSH_DATA (push, pos);
 655    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 656    PUSH_DATA (push, pos);
 657    PUSH_DATAp(push, data, size);
 658
 659    return pos + size;
 660 }
 661
 662 static void
 663 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 664 {
 665    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 666    PUSH_DATA (push, 0xff);
 667    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 668    PUSH_DATA (push, 0xff);
 669    PUSH_DATA (push, 0xff);
 670    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 671    PUSH_DATA (push, 0xff);
 672    PUSH_DATA (push, 0xff);
 673    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 674    PUSH_DATA (push, 0x3f);
 675
 676    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 677    PUSH_DATA (push, (3 << 16) | 3);
 678    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 679    PUSH_DATA (push, (2 << 16) | 2);
 680
 681    if (obj_class < GM107_3D_CLASS) {
 682       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 683       PUSH_DATA (push, 0);
 684    }
 685    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 686    PUSH_DATA (push, 0x10);
 687    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 688    PUSH_DATA (push, 0x10);
 689    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 690    PUSH_DATA (push, 0x10);
 691    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 692    PUSH_DATA (push, 0x10);
 693    PUSH_DATA (push, 0x10);
 694    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 695    PUSH_DATA (push, 0x10);
 696    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 697    PUSH_DATA (push, 0xe);
 698
 699    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 700    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 701    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 702    PUSH_DATA (push, 0);
 703    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 704    PUSH_DATA (push, 3);
 705
 706    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 707    PUSH_DATA (push, 0x3fffff);
 708    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 709    PUSH_DATA (push, 1);
 710    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 711    PUSH_DATA (push, 1);
 712
 713    if (obj_class < GM107_3D_CLASS) {
 714       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 715       PUSH_DATA (push, 3);
 716
 717       if (obj_class >= NVE4_3D_CLASS) {
 718          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 719          PUSH_DATA (push, 1);
 720       }
 721    }
 722
 723    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 724     * are supposed to do */
 725 }
 726
 727 static void
 728 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 729 {
 730    struct nvc0_screen *screen = nvc0_screen(pscreen);
 731    struct nouveau_pushbuf *push = screen->base.pushbuf;
 732
 733    /* we need to do it after possible flush in MARK_RING */
 734    *sequence = ++screen->base.fence.sequence;
 735
 736    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 737    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 738    PUSH_DATAh(push, screen->fence.bo->offset);
 739    PUSH_DATA (push, screen->fence.bo->offset);
 740    PUSH_DATA (push, *sequence);
 741    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 742               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 743 }
 744
 745 static u32
 746 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 747 {
 748    struct nvc0_screen *screen = nvc0_screen(pscreen);
 749    return screen->fence.map[0];
 750 }
 751
 752 static int
 753 nvc0_screen_init_compute(struct nvc0_screen *screen)
 754 {
 755    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 756
 757    switch (screen->base.device->chipset & ~0xf) {
 758    case 0xc0:
 759    case 0xd0:
 760       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 761    case 0xe0:
 762    case 0xf0:
 763    case 0x100:
 764    case 0x110:
 765    case 0x120:
 766    case 0x130:
 767       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 768    default:
 769       return -1;
 770    }
 771 }
 772
 773 static int
 774 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 775                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 776 {
 777    struct nouveau_bo *bo = NULL;
 778    int ret;
 779    uint64_t size = (lpos + lneg) * 32 + cstack;
 780
 781    if (size >= (1 << 20)) {
 782       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 783       return -1;
 784    }
 785
 786    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 787    size  = align(size, 0x8000);
 788    size *= screen->mp_count;
 789
 790    size = align(size, 1 << 17);
 791
 792    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 793                         NULL, &bo);
 794    if (ret)
 795       return ret;
 796
 797    /* Make sure that the pushbuf has acquired a reference to the old tls
 798     * segment, as it may have commands that will reference it.
 799     */
 800    if (screen->tls)
 801       PUSH_REFN(screen->base.pushbuf, screen->tls,
 802                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 803    nouveau_bo_ref(NULL, &screen->tls);
 804    screen->tls = bo;
 805    return 0;
 806 }
 807
 808 int
 809 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 810 {
 811    struct nouveau_pushbuf *push = screen->base.pushbuf;
 812    struct nouveau_bo *bo;
 813    int ret;
 814
 815    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 816                         1 << 17, size, NULL, &bo);
 817    if (ret)
 818       return ret;
 819
 820    /* Make sure that the pushbuf has acquired a reference to the old text
 821     * segment, as it may have commands that will reference it.
 822     */
 823    if (screen->text)
 824       PUSH_REFN(push, screen->text,
 825                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 826    nouveau_bo_ref(NULL, &screen->text);
 827    screen->text = bo;
 828
 829    nouveau_heap_destroy(&screen->lib_code);
 830    nouveau_heap_destroy(&screen->text_heap);
 831
 832    /* XXX: getting a page fault at the end of the code buffer every few
 833     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 834     */
 835    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 836
 837    /* update the code segment setup */
 838    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 839    PUSH_DATAh(push, screen->text->offset);
 840    PUSH_DATA (push, screen->text->offset);
 841    if (screen->compute) {
 842       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 843       PUSH_DATAh(push, screen->text->offset);
 844       PUSH_DATA (push, screen->text->offset);
 845    }
 846
 847    return 0;
 848 }
 849
 850 void
 851 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 852                        int stage, int index, int size, uint64_t addr)
 853 {
 854    assert(stage != 5);
 855
 856    struct nouveau_pushbuf *push = screen->base.pushbuf;
 857
 858    if (screen->base.class_3d >= GM107_3D_CLASS) {
 859       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 860
 861       // TODO: Better figure out the conditions in which this is needed
 862       bool serialize = binding->addr == addr && binding->size != size;
 863       if (can_serialize)
 864          serialize = serialize && *can_serialize;
 865       if (serialize) {
 866          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 867          if (can_serialize)
 868             *can_serialize = false;
 869       }
 870
 871       binding->addr = addr;
 872       binding->size = size;
 873    }
 874
 875    if (size >= 0) {
 876       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 877       PUSH_DATA (push, size);
 878       PUSH_DATAh(push, addr);
 879       PUSH_DATA (push, addr);
 880    }
 881    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 882 }
 883
 884 #define FAIL_SCREEN_INIT(str, err)                    \
 885    do {                                               \
 886       NOUVEAU_ERR(str, err);                          \
 887       goto fail;                                      \
 888    } while(0)
 889
 890 struct nouveau_screen *
 891 nvc0_screen_create(struct nouveau_device *dev)
 892 {
 893    struct nvc0_screen *screen;
 894    struct pipe_screen *pscreen;
 895    struct nouveau_object *chan;
 896    struct nouveau_pushbuf *push;
 897    uint64_t value;
 898    uint32_t obj_class;
 899    uint32_t flags;
 900    int ret;
 901    unsigned i;
 902
 903    switch (dev->chipset & ~0xf) {
 904    case 0xc0:
 905    case 0xd0:
 906    case 0xe0:
 907    case 0xf0:
 908    case 0x100:
 909    case 0x110:
 910    case 0x120:
 911    case 0x130:
 912       break;
 913    default:
 914       return NULL;
 915    }
 916
 917    screen = CALLOC_STRUCT(nvc0_screen);
 918    if (!screen)
 919       return NULL;
 920    pscreen = &screen->base.base;
 921    pscreen->destroy = nvc0_screen_destroy;
 922
 923    ret = nouveau_screen_init(&screen->base, dev);
 924    if (ret)
 925       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 926    chan = screen->base.channel;
 927    push = screen->base.pushbuf;
 928    push->user_priv = screen;
 929    push->rsvd_kick = 5;
 930
 931    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 932       PIPE_BIND_SHADER_BUFFER |
 933       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 934       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 935    screen->base.sysmem_bindings |=
 936       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 937
 938    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 939       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 940       screen->base.vidmem_bindings = 0;
 941    }
 942
 943    pscreen->context_create = nvc0_create;
 944    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 945    pscreen->get_param = nvc0_screen_get_param;
 946    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 947    pscreen->get_paramf = nvc0_screen_get_paramf;
 948    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
 949    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 950    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 951
 952    nvc0_screen_init_resource_functions(pscreen);
 953
 954    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 955    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 956
 957    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 958    if (screen->base.drm->version >= 0x01000202)
 959       flags |= NOUVEAU_BO_COHERENT;
 960
 961    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 962    if (ret)
 963       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 964    nouveau_bo_map(screen->fence.bo, 0, NULL);
 965    screen->fence.map = screen->fence.bo->map;
 966    screen->base.fence.emit = nvc0_screen_fence_emit;
 967    screen->base.fence.update = nvc0_screen_fence_update;
 968
 969
 970    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 971                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 972    if (ret)
 973       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 974
 975    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 976    PUSH_DATA (push, screen->nvsw->handle);
 977
 978    switch (dev->chipset & ~0xf) {
 979    case 0x130:
 980    case 0x120:
 981    case 0x110:
 982    case 0x100:
 983    case 0xf0:
 984       obj_class = NVF0_P2MF_CLASS;
 985       break;
 986    case 0xe0:
 987       obj_class = NVE4_P2MF_CLASS;
 988       break;
 989    default:
 990       obj_class = NVC0_M2MF_CLASS;
 991       break;
 992    }
 993    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 994                             &screen->m2mf);
 995    if (ret)
 996       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 997
 998    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 999    PUSH_DATA (push, screen->m2mf->oclass);
1000    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1001       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1002       PUSH_DATA (push, 0xa0b5);
1003    }
1004
1005    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1006                             &screen->eng2d);
1007    if (ret)
1008       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1009
1010    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1011    PUSH_DATA (push, screen->eng2d->oclass);
1012    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1013    PUSH_DATA (push, 0);
1014    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1015    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1016    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1017    PUSH_DATA (push, 0);
1018    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1019    PUSH_DATA (push, 0);
1020    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1021    PUSH_DATA (push, 0x3f);
1022    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1023    PUSH_DATA (push, 1);
1024    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1025    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1026
1027    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1028    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1029    PUSH_DATA (push, screen->fence.bo->offset + 16);
1030
1031    switch (dev->chipset & ~0xf) {
1032    case 0x130:
1033       switch (dev->chipset) {
1034       case 0x130:
1035       case 0x13b:
1036          obj_class = GP100_3D_CLASS;
1037          break;
1038       default:
1039          obj_class = GP102_3D_CLASS;
1040          break;
1041       }
1042       break;
1043    case 0x120:
1044       obj_class = GM200_3D_CLASS;
1045       break;
1046    case 0x110:
1047       obj_class = GM107_3D_CLASS;
1048       break;
1049    case 0x100:
1050    case 0xf0:
1051       obj_class = NVF0_3D_CLASS;
1052       break;
1053    case 0xe0:
1054       switch (dev->chipset) {
1055       case 0xea:
1056          obj_class = NVEA_3D_CLASS;
1057          break;
1058       default:
1059          obj_class = NVE4_3D_CLASS;
1060          break;
1061       }
1062       break;
1063    case 0xd0:
1064       obj_class = NVC8_3D_CLASS;
1065       break;
1066    case 0xc0:
1067    default:
1068       switch (dev->chipset) {
1069       case 0xc8:
1070          obj_class = NVC8_3D_CLASS;
1071          break;
1072       case 0xc1:
1073          obj_class = NVC1_3D_CLASS;
1074          break;
1075       default:
1076          obj_class = NVC0_3D_CLASS;
1077          break;
1078       }
1079       break;
1080    }
1081    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1082                             &screen->eng3d);
1083    if (ret)
1084       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1085    screen->base.class_3d = obj_class;
1086
1087    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1088    PUSH_DATA (push, screen->eng3d->oclass);
1089
1090    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1091    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1092
1093    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1094       /* kill shaders after about 1 second (at 100 MHz) */
1095       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1096       PUSH_DATA (push, 0x17);
1097    }
1098
1099    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1100                     screen->base.drm->version >= 0x01000101);
1101    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1102    for (i = 0; i < 8; ++i)
1103       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1104
1105    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1106    PUSH_DATA (push, 1);
1107
1108    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1109    PUSH_DATA (push, 0);
1110    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1111    PUSH_DATA (push, 0);
1112    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1113    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1114    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1115    PUSH_DATA (push, 0);
1116    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1117    PUSH_DATA (push, 1);
1118    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1119    PUSH_DATA (push, 1);
1120    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1121    PUSH_DATA (push, 1);
1122    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1123    PUSH_DATA (push, 0);
1124    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1125    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1126    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1127       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1128    } else {
1129       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1130       PUSH_DATA (push, 15);
1131    }
1132    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1133    PUSH_DATA (push, 8); /* 128 */
1134    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1135    PUSH_DATA (push, 1);
1136    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1137       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1138       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1139    }
1140
1141    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1142
1143    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1144    if (ret)
1145       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1146
1147    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1148    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1149                         &screen->uniform_bo);
1150    if (ret)
1151       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1152
1153    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1154
1155    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1156    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1157    PUSH_DATA (push, 256);
1158    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1159    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1160    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1161    PUSH_DATA (push, 0);
1162    PUSH_DATAf(push, 0.0f);
1163    PUSH_DATAf(push, 0.0f);
1164    PUSH_DATAf(push, 0.0f);
1165    PUSH_DATAf(push, 0.0f);
1166    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1167    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1168    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1169
1170    if (screen->base.drm->version >= 0x01000101) {
1171       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1172       if (ret)
1173          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1174    } else {
1175       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1176          value = (8 << 8) | 4;
1177       else
1178          value = (16 << 8) | 4;
1179    }
1180    screen->gpc_count = value & 0x000000ff;
1181    screen->mp_count = value >> 8;
1182    screen->mp_count_compute = screen->mp_count;
1183
1184    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1185    if (ret)
1186       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1187
1188    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1189    PUSH_DATAh(push, screen->tls->offset);
1190    PUSH_DATA (push, screen->tls->offset);
1191    PUSH_DATA (push, screen->tls->size >> 32);
1192    PUSH_DATA (push, screen->tls->size);
1193    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1194    PUSH_DATA (push, 0);
1195    /* Reduce likelihood of collision with real buffers by placing the hole at
1196     * the top of the 4G area. This will have to be dealt with for real
1197     * eventually by blocking off that area from the VM.
1198     */
1199    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1200    PUSH_DATA (push, 0xff << 24);
1201
1202    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1203       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1204                            &screen->poly_cache);
1205       if (ret)
1206          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1207
1208       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1209       PUSH_DATAh(push, screen->poly_cache->offset);
1210       PUSH_DATA (push, screen->poly_cache->offset);
1211       PUSH_DATA (push, 3);
1212    }
1213
1214    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1215                         &screen->txc);
1216    if (ret)
1217       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1218
1219    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1220    PUSH_DATAh(push, screen->txc->offset);
1221    PUSH_DATA (push, screen->txc->offset);
1222    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1223    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1224       screen->tic.maxwell = true;
1225       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1226          screen->tic.maxwell =
1227             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1228          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1229       }
1230    }
1231
1232    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1233    PUSH_DATAh(push, screen->txc->offset + 65536);
1234    PUSH_DATA (push, screen->txc->offset + 65536);
1235    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1236
1237    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1238    PUSH_DATA (push, 0);
1239    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1240    PUSH_DATA (push, 0);
1241    PUSH_DATA (push, 0);
1242    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1243    PUSH_DATA (push, 0x3f);
1244
1245    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1246    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1247    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1248    for (i = 0; i < 8 * 2; ++i)
1249       PUSH_DATA(push, 0);
1250    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1251    PUSH_DATA (push, 0);
1252    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1253    PUSH_DATA (push, 0);
1254
1255    /* neither scissors, viewport nor stencil mask should affect clears */
1256    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1257    PUSH_DATA (push, 0);
1258
1259    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1260    PUSH_DATA (push, 1);
1261    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1262       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1263       PUSH_DATAf(push, 0.0f);
1264       PUSH_DATAf(push, 1.0f);
1265    }
1266    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1267    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1268
1269    /* We use scissors instead of exact view volume clipping,
1270     * so they're always enabled.
1271     */
1272    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1273       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1274       PUSH_DATA (push, 1);
1275       PUSH_DATA (push, 8192 << 16);
1276       PUSH_DATA (push, 8192 << 16);
1277    }
1278
1279 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1280
1281    i = 0;
1282    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1283    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1284    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1285    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1286    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1287    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1288    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1289    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1290    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1291    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1292    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1293    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1294    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1295    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1296
1297    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1298    PUSH_DATA (push, 1);
1299    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1300    PUSH_DATA (push, 1);
1301    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1302    PUSH_DATA (push, 0x40);
1303    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1304    PUSH_DATA (push, 0);
1305    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1306    PUSH_DATA (push, 0x30);
1307    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1308    PUSH_DATA (push, 3);
1309    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1310    PUSH_DATA (push, 0x20);
1311    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1312    PUSH_DATA (push, 0x00);
1313    screen->save_state.patch_vertices = 3;
1314
1315    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1316    PUSH_DATA (push, 0);
1317    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1318    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1319
1320    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1321
1322    if (nvc0_screen_init_compute(screen))
1323       goto fail;
1324
1325    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1326    for (i = 0; i < 5; ++i) {
1327       unsigned j = 0;
1328       for (j = 0; j < 16; j++)
1329          screen->cb_bindings[i][j].size = -1;
1330
1331       /* TIC and TSC entries for each unit (nve4+ only) */
1332       /* auxiliary constants (6 user clip planes, base instance id) */
1333       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1334                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1335       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1336          unsigned j;
1337          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1338          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1339          for (j = 0; j < 8; ++j)
1340             PUSH_DATA(push, j);
1341       } else {
1342          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1343          PUSH_DATA (push, 0x54);
1344       }
1345
1346       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1347       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1348       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1349       PUSH_DATA (push, 0); /* 0 */
1350       PUSH_DATA (push, 0);
1351       PUSH_DATA (push, 1); /* 1 */
1352       PUSH_DATA (push, 0);
1353       PUSH_DATA (push, 0); /* 2 */
1354       PUSH_DATA (push, 1);
1355       PUSH_DATA (push, 1); /* 3 */
1356       PUSH_DATA (push, 1);
1357       PUSH_DATA (push, 2); /* 4 */
1358       PUSH_DATA (push, 0);
1359       PUSH_DATA (push, 3); /* 5 */
1360       PUSH_DATA (push, 0);
1361       PUSH_DATA (push, 2); /* 6 */
1362       PUSH_DATA (push, 1);
1363       PUSH_DATA (push, 3); /* 7 */
1364       PUSH_DATA (push, 1);
1365    }
1366    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1367    PUSH_DATA (push, 0);
1368
1369    PUSH_KICK (push);
1370
1371    screen->tic.entries = CALLOC(
1372          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1373          sizeof(void *));
1374    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1375    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1376
1377    if (!nvc0_blitter_create(screen))
1378       goto fail;
1379
1380    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1381    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1382
1383    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1384
1385    return &screen->base;
1386
1387 fail:
1388    screen->base.base.context_create = NULL;
1389    return &screen->base;
1390 }
1391
1392 int
1393 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1394 {
1395    int i = screen->tic.next;
1396
1397    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1398       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1399
1400    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1401
1402    if (screen->tic.entries[i])
1403       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1404
1405    screen->tic.entries[i] = entry;
1406    return i;
1407 }
1408
1409 int
1410 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1411 {
1412    int i = screen->tsc.next;
1413
1414    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1415       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1416
1417    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1418
1419    if (screen->tsc.entries[i])
1420       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1421
1422    screen->tsc.entries[i] = entry;
1423    return i;
1424 }