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gallium: add PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36 #include "nvc0/mme/com90c0.mme.h"
37
38 #include "nv50/g80_texture.xml.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 const struct util_format_description *desc = util_format_description(format);
48
49 if (sample_count > 8)
50 return false;
51 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
52 return false;
53
54 /* Short-circuit the rest of the logic -- this is used by the state tracker
55 * to determine valid MS levels in a no-attachments scenario.
56 */
57 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
58 return true;
59
60 if (!util_format_is_supported(format, bindings))
61 return false;
62
63 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
64 if (util_format_get_blocksizebits(format) == 3 * 32)
65 return false;
66
67 if (bindings & PIPE_BIND_LINEAR)
68 if (util_format_is_depth_or_stencil(format) ||
69 (target != PIPE_TEXTURE_1D &&
70 target != PIPE_TEXTURE_2D &&
71 target != PIPE_TEXTURE_RECT) ||
72 sample_count > 1)
73 return false;
74
75 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
76 */
77 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
78 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
79 /* The claim is that this should work on GM107 but it doesn't. Need to
80 * test further and figure out if it's a nouveau issue or a HW one.
81 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
82 */
83 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
84 return false;
85
86 /* shared is always supported */
87 bindings &= ~(PIPE_BIND_LINEAR |
88 PIPE_BIND_SHARED);
89
90 if (bindings & PIPE_BIND_SHADER_IMAGE) {
91 if (sample_count > 1 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
99 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
100 /* This should work on Fermi, but for currently unknown reasons it
101 * does not and results in breaking reads from pbos. */
102 return false;
103 }
104 }
105
106 return (( nvc0_format_table[format].usage |
107 nvc0_vertex_format[format].usage) & bindings) == bindings;
108 }
109
110 static int
111 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
112 {
113 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
114 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
115
116 switch (param) {
117 /* non-boolean caps */
118 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
119 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
120 return 15;
121 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
122 return 12;
123 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
124 return 2048;
125 case PIPE_CAP_MIN_TEXEL_OFFSET:
126 return -8;
127 case PIPE_CAP_MAX_TEXEL_OFFSET:
128 return 7;
129 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
130 return -32;
131 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
132 return 31;
133 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
134 return 128 * 1024 * 1024;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL:
136 return 430;
137 case PIPE_CAP_MAX_RENDER_TARGETS:
138 return 8;
139 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
140 return 1;
141 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
142 return 4;
143 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
144 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
145 return 128;
146 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
147 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
148 return 1024;
149 case PIPE_CAP_MAX_VERTEX_STREAMS:
150 return 4;
151 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
152 return 2048;
153 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
154 return 256;
155 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
156 if (class_3d < GM107_3D_CLASS)
157 return 256; /* IMAGE bindings require alignment to 256 */
158 return 16;
159 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
160 return 16;
161 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
162 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
163 case PIPE_CAP_MAX_VIEWPORTS:
164 return NVC0_MAX_VIEWPORTS;
165 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
166 return 4;
167 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
168 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
169 case PIPE_CAP_ENDIANNESS:
170 return PIPE_ENDIAN_LITTLE;
171 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
172 return 30;
173 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
174 return NVC0_MAX_WINDOW_RECTANGLES;
175
176 /* supported caps */
177 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
178 case PIPE_CAP_TEXTURE_SWIZZLE:
179 case PIPE_CAP_TEXTURE_SHADOW_MAP:
180 case PIPE_CAP_NPOT_TEXTURES:
181 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
182 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
183 case PIPE_CAP_ANISOTROPIC_FILTER:
184 case PIPE_CAP_SEAMLESS_CUBE_MAP:
185 case PIPE_CAP_CUBE_MAP_ARRAY:
186 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
187 case PIPE_CAP_TEXTURE_MULTISAMPLE:
188 case PIPE_CAP_TWO_SIDED_STENCIL:
189 case PIPE_CAP_DEPTH_CLIP_DISABLE:
190 case PIPE_CAP_POINT_SPRITE:
191 case PIPE_CAP_TGSI_TEXCOORD:
192 case PIPE_CAP_SM3:
193 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
194 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
195 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
196 case PIPE_CAP_QUERY_TIMESTAMP:
197 case PIPE_CAP_QUERY_TIME_ELAPSED:
198 case PIPE_CAP_OCCLUSION_QUERY:
199 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
200 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
201 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
202 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
203 case PIPE_CAP_INDEP_BLEND_ENABLE:
204 case PIPE_CAP_INDEP_BLEND_FUNC:
205 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
206 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
207 case PIPE_CAP_PRIMITIVE_RESTART:
208 case PIPE_CAP_TGSI_INSTANCEID:
209 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
210 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
211 case PIPE_CAP_CONDITIONAL_RENDER:
212 case PIPE_CAP_TEXTURE_BARRIER:
213 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
214 case PIPE_CAP_START_INSTANCE:
215 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
216 case PIPE_CAP_DRAW_INDIRECT:
217 case PIPE_CAP_USER_CONSTANT_BUFFERS:
218 case PIPE_CAP_USER_VERTEX_BUFFERS:
219 case PIPE_CAP_TEXTURE_QUERY_LOD:
220 case PIPE_CAP_SAMPLE_SHADING:
221 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
222 case PIPE_CAP_TEXTURE_GATHER_SM5:
223 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
224 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
225 case PIPE_CAP_SAMPLER_VIEW_TARGET:
226 case PIPE_CAP_CLIP_HALFZ:
227 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
228 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
229 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
230 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
231 case PIPE_CAP_DEPTH_BOUNDS_TEST:
232 case PIPE_CAP_TGSI_TXQS:
233 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
234 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
235 case PIPE_CAP_SHAREABLE_SHADERS:
236 case PIPE_CAP_CLEAR_TEXTURE:
237 case PIPE_CAP_DRAW_PARAMETERS:
238 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
239 case PIPE_CAP_MULTI_DRAW_INDIRECT:
240 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
241 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
242 case PIPE_CAP_QUERY_BUFFER_OBJECT:
243 case PIPE_CAP_INVALIDATE_BUFFER:
244 case PIPE_CAP_STRING_MARKER:
245 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
246 case PIPE_CAP_CULL_DISTANCE:
247 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
248 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
249 case PIPE_CAP_TGSI_VOTE:
250 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
251 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
252 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
253 case PIPE_CAP_DOUBLES:
254 case PIPE_CAP_INT64:
255 case PIPE_CAP_TGSI_TEX_TXF_LZ:
256 case PIPE_CAP_TGSI_CLOCK:
257 case PIPE_CAP_COMPUTE:
258 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
259 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
260 return 1;
261 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
262 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
263 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
264 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
265 case PIPE_CAP_TGSI_FS_FBFETCH:
266 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
267 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
268 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
269 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
270 case PIPE_CAP_POST_DEPTH_COVERAGE:
271 return class_3d >= GM200_3D_CLASS;
272 case PIPE_CAP_TGSI_BALLOT:
273 return class_3d >= NVE4_3D_CLASS;
274
275 /* unsupported caps */
276 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
277 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
278 case PIPE_CAP_SHADER_STENCIL_EXPORT:
279 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
280 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
281 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
282 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
283 case PIPE_CAP_FAKE_SW_MSAA:
284 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
285 case PIPE_CAP_VERTEXID_NOBASE:
286 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
287 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
288 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
289 case PIPE_CAP_GENERATE_MIPMAP:
290 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
291 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
292 case PIPE_CAP_QUERY_MEMORY_INFO:
293 case PIPE_CAP_PCI_GROUP:
294 case PIPE_CAP_PCI_BUS:
295 case PIPE_CAP_PCI_DEVICE:
296 case PIPE_CAP_PCI_FUNCTION:
297 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
298 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
299 case PIPE_CAP_NATIVE_FENCE_FD:
300 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
301 case PIPE_CAP_INT64_DIVMOD:
302 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
303 case PIPE_CAP_BINDLESS_TEXTURE:
304 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
305 case PIPE_CAP_QUERY_SO_OVERFLOW:
306 case PIPE_CAP_MEMOBJ:
307 case PIPE_CAP_LOAD_CONSTBUF:
308 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
309 case PIPE_CAP_TILE_RASTER_ORDER:
310 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
311 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
312 return 0;
313
314 case PIPE_CAP_VENDOR_ID:
315 return 0x10de;
316 case PIPE_CAP_DEVICE_ID: {
317 uint64_t device_id;
318 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
319 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
320 return -1;
321 }
322 return device_id;
323 }
324 case PIPE_CAP_ACCELERATED:
325 return 1;
326 case PIPE_CAP_VIDEO_MEMORY:
327 return dev->vram_size >> 20;
328 case PIPE_CAP_UMA:
329 return 0;
330 }
331
332 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
333 return 0;
334 }
335
336 static int
337 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
338 enum pipe_shader_type shader,
339 enum pipe_shader_cap param)
340 {
341 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
342
343 switch (shader) {
344 case PIPE_SHADER_VERTEX:
345 case PIPE_SHADER_GEOMETRY:
346 case PIPE_SHADER_FRAGMENT:
347 case PIPE_SHADER_COMPUTE:
348 case PIPE_SHADER_TESS_CTRL:
349 case PIPE_SHADER_TESS_EVAL:
350 break;
351 default:
352 return 0;
353 }
354
355 switch (param) {
356 case PIPE_SHADER_CAP_PREFERRED_IR:
357 return PIPE_SHADER_IR_TGSI;
358 case PIPE_SHADER_CAP_SUPPORTED_IRS:
359 return 1 << PIPE_SHADER_IR_TGSI;
360 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
361 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
362 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
363 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
364 return 16384;
365 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
366 return 16;
367 case PIPE_SHADER_CAP_MAX_INPUTS:
368 if (shader == PIPE_SHADER_VERTEX)
369 return 32;
370 /* NOTE: These only count our slots for GENERIC varyings.
371 * The address space may be larger, but the actual hard limit seems to be
372 * less than what the address space layout permits, so don't add TEXCOORD,
373 * COLOR, etc. here.
374 */
375 if (shader == PIPE_SHADER_FRAGMENT)
376 return 0x1f0 / 16;
377 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
378 * and excludes 0x60 per-patch inputs.
379 */
380 return 0x200 / 16;
381 case PIPE_SHADER_CAP_MAX_OUTPUTS:
382 return 32;
383 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
384 return 65536;
385 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
386 return NVC0_MAX_PIPE_CONSTBUFS;
387 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
388 return shader != PIPE_SHADER_FRAGMENT;
389 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
390 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
391 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
392 return 1;
393 case PIPE_SHADER_CAP_MAX_TEMPS:
394 return NVC0_CAP_MAX_PROGRAM_TEMPS;
395 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
396 return 1;
397 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
398 return 1;
399 case PIPE_SHADER_CAP_SUBROUTINES:
400 return 1;
401 case PIPE_SHADER_CAP_INTEGERS:
402 return 1;
403 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
404 return 1;
405 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
406 return 1;
407 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
408 return 1;
409 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
410 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
411 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
412 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
413 case PIPE_SHADER_CAP_INT64_ATOMICS:
414 case PIPE_SHADER_CAP_FP16:
415 return 0;
416 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
417 return NVC0_MAX_BUFFERS;
418 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
419 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
420 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
421 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
422 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
423 return 32;
424 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
425 if (class_3d >= NVE4_3D_CLASS)
426 return NVC0_MAX_IMAGES;
427 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
428 return NVC0_MAX_IMAGES;
429 return 0;
430 default:
431 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
432 return 0;
433 }
434 }
435
436 static float
437 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
438 {
439 switch (param) {
440 case PIPE_CAPF_MAX_LINE_WIDTH:
441 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
442 return 10.0f;
443 case PIPE_CAPF_MAX_POINT_WIDTH:
444 return 63.0f;
445 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
446 return 63.375f;
447 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
448 return 16.0f;
449 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
450 return 15.0f;
451 case PIPE_CAPF_GUARD_BAND_LEFT:
452 case PIPE_CAPF_GUARD_BAND_TOP:
453 return 0.0f;
454 case PIPE_CAPF_GUARD_BAND_RIGHT:
455 case PIPE_CAPF_GUARD_BAND_BOTTOM:
456 return 0.0f; /* that or infinity */
457 }
458
459 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
460 return 0.0f;
461 }
462
463 static int
464 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
465 enum pipe_shader_ir ir_type,
466 enum pipe_compute_cap param, void *data)
467 {
468 struct nvc0_screen *screen = nvc0_screen(pscreen);
469 const uint16_t obj_class = screen->compute->oclass;
470
471 #define RET(x) do { \
472 if (data) \
473 memcpy(data, x, sizeof(x)); \
474 return sizeof(x); \
475 } while (0)
476
477 switch (param) {
478 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
479 RET((uint64_t []) { 3 });
480 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
481 if (obj_class >= NVE4_COMPUTE_CLASS) {
482 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
483 } else {
484 RET(((uint64_t []) { 65535, 65535, 65535 }));
485 }
486 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
487 RET(((uint64_t []) { 1024, 1024, 64 }));
488 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
489 RET((uint64_t []) { 1024 });
490 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
491 if (obj_class >= NVE4_COMPUTE_CLASS) {
492 RET((uint64_t []) { 1024 });
493 } else {
494 RET((uint64_t []) { 512 });
495 }
496 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
497 RET((uint64_t []) { 1ULL << 40 });
498 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
499 switch (obj_class) {
500 case GM200_COMPUTE_CLASS:
501 RET((uint64_t []) { 96 << 10 });
502 break;
503 case GM107_COMPUTE_CLASS:
504 RET((uint64_t []) { 64 << 10 });
505 break;
506 default:
507 RET((uint64_t []) { 48 << 10 });
508 break;
509 }
510 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
511 RET((uint64_t []) { 512 << 10 });
512 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
513 RET((uint64_t []) { 4096 });
514 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
515 RET((uint32_t []) { 32 });
516 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
517 RET((uint64_t []) { 1ULL << 40 });
518 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
519 RET((uint32_t []) { 0 });
520 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
521 RET((uint32_t []) { screen->mp_count_compute });
522 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
523 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
524 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
525 RET((uint32_t []) { 64 });
526 default:
527 return 0;
528 }
529
530 #undef RET
531 }
532
533 static void
534 nvc0_screen_destroy(struct pipe_screen *pscreen)
535 {
536 struct nvc0_screen *screen = nvc0_screen(pscreen);
537
538 if (!nouveau_drm_screen_unref(&screen->base))
539 return;
540
541 if (screen->base.fence.current) {
542 struct nouveau_fence *current = NULL;
543
544 /* nouveau_fence_wait will create a new current fence, so wait on the
545 * _current_ one, and remove both.
546 */
547 nouveau_fence_ref(screen->base.fence.current, &current);
548 nouveau_fence_wait(current, NULL);
549 nouveau_fence_ref(NULL, &current);
550 nouveau_fence_ref(NULL, &screen->base.fence.current);
551 }
552 if (screen->base.pushbuf)
553 screen->base.pushbuf->user_priv = NULL;
554
555 if (screen->blitter)
556 nvc0_blitter_destroy(screen);
557 if (screen->pm.prog) {
558 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
559 nvc0_program_destroy(NULL, screen->pm.prog);
560 FREE(screen->pm.prog);
561 }
562
563 nouveau_bo_ref(NULL, &screen->text);
564 nouveau_bo_ref(NULL, &screen->uniform_bo);
565 nouveau_bo_ref(NULL, &screen->tls);
566 nouveau_bo_ref(NULL, &screen->txc);
567 nouveau_bo_ref(NULL, &screen->fence.bo);
568 nouveau_bo_ref(NULL, &screen->poly_cache);
569
570 nouveau_heap_destroy(&screen->lib_code);
571 nouveau_heap_destroy(&screen->text_heap);
572
573 FREE(screen->default_tsc);
574 FREE(screen->tic.entries);
575
576 nouveau_object_del(&screen->eng3d);
577 nouveau_object_del(&screen->eng2d);
578 nouveau_object_del(&screen->m2mf);
579 nouveau_object_del(&screen->compute);
580 nouveau_object_del(&screen->nvsw);
581
582 nouveau_screen_fini(&screen->base);
583
584 FREE(screen);
585 }
586
587 static int
588 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
589 unsigned size, const uint32_t *data)
590 {
591 struct nouveau_pushbuf *push = screen->base.pushbuf;
592
593 size /= 4;
594
595 assert((pos + size) <= 0x800);
596
597 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
598 PUSH_DATA (push, (m - 0x3800) / 8);
599 PUSH_DATA (push, pos);
600 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
601 PUSH_DATA (push, pos);
602 PUSH_DATAp(push, data, size);
603
604 return pos + size;
605 }
606
607 static void
608 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
609 {
610 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
611 PUSH_DATA (push, 0xff);
612 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
613 PUSH_DATA (push, 0xff);
614 PUSH_DATA (push, 0xff);
615 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
616 PUSH_DATA (push, 0xff);
617 PUSH_DATA (push, 0xff);
618 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
619 PUSH_DATA (push, 0x3f);
620
621 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
622 PUSH_DATA (push, (3 << 16) | 3);
623 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
624 PUSH_DATA (push, (2 << 16) | 2);
625
626 if (obj_class < GM107_3D_CLASS) {
627 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
628 PUSH_DATA (push, 0);
629 }
630 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
631 PUSH_DATA (push, 0x10);
632 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
633 PUSH_DATA (push, 0x10);
634 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
635 PUSH_DATA (push, 0x10);
636 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
637 PUSH_DATA (push, 0x10);
638 PUSH_DATA (push, 0x10);
639 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
640 PUSH_DATA (push, 0x10);
641 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
642 PUSH_DATA (push, 0xe);
643
644 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
645 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
646 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
647 PUSH_DATA (push, 0);
648 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
649 PUSH_DATA (push, 3);
650
651 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
652 PUSH_DATA (push, 0x3fffff);
653 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
654 PUSH_DATA (push, 1);
655 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
656 PUSH_DATA (push, 1);
657
658 if (obj_class < GM107_3D_CLASS) {
659 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
660 PUSH_DATA (push, 3);
661
662 if (obj_class >= NVE4_3D_CLASS) {
663 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
664 PUSH_DATA (push, 1);
665 }
666 }
667
668 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
669 * are supposed to do */
670 }
671
672 static void
673 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
674 {
675 struct nvc0_screen *screen = nvc0_screen(pscreen);
676 struct nouveau_pushbuf *push = screen->base.pushbuf;
677
678 /* we need to do it after possible flush in MARK_RING */
679 *sequence = ++screen->base.fence.sequence;
680
681 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
682 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
683 PUSH_DATAh(push, screen->fence.bo->offset);
684 PUSH_DATA (push, screen->fence.bo->offset);
685 PUSH_DATA (push, *sequence);
686 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
687 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
688 }
689
690 static u32
691 nvc0_screen_fence_update(struct pipe_screen *pscreen)
692 {
693 struct nvc0_screen *screen = nvc0_screen(pscreen);
694 return screen->fence.map[0];
695 }
696
697 static int
698 nvc0_screen_init_compute(struct nvc0_screen *screen)
699 {
700 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
701
702 switch (screen->base.device->chipset & ~0xf) {
703 case 0xc0:
704 case 0xd0:
705 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
706 case 0xe0:
707 case 0xf0:
708 case 0x100:
709 case 0x110:
710 case 0x120:
711 case 0x130:
712 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
713 default:
714 return -1;
715 }
716 }
717
718 static int
719 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
720 uint32_t lpos, uint32_t lneg, uint32_t cstack)
721 {
722 struct nouveau_bo *bo = NULL;
723 int ret;
724 uint64_t size = (lpos + lneg) * 32 + cstack;
725
726 if (size >= (1 << 20)) {
727 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
728 return -1;
729 }
730
731 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
732 size = align(size, 0x8000);
733 size *= screen->mp_count;
734
735 size = align(size, 1 << 17);
736
737 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
738 NULL, &bo);
739 if (ret)
740 return ret;
741 nouveau_bo_ref(NULL, &screen->tls);
742 screen->tls = bo;
743 return 0;
744 }
745
746 int
747 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
748 {
749 struct nouveau_pushbuf *push = screen->base.pushbuf;
750 struct nouveau_bo *bo;
751 int ret;
752
753 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
754 1 << 17, size, NULL, &bo);
755 if (ret)
756 return ret;
757
758 nouveau_bo_ref(NULL, &screen->text);
759 screen->text = bo;
760
761 nouveau_heap_destroy(&screen->lib_code);
762 nouveau_heap_destroy(&screen->text_heap);
763
764 /* XXX: getting a page fault at the end of the code buffer every few
765 * launches, don't use the last 256 bytes to work around them - prefetch ?
766 */
767 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
768
769 /* update the code segment setup */
770 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
771 PUSH_DATAh(push, screen->text->offset);
772 PUSH_DATA (push, screen->text->offset);
773 if (screen->compute) {
774 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
775 PUSH_DATAh(push, screen->text->offset);
776 PUSH_DATA (push, screen->text->offset);
777 }
778
779 return 0;
780 }
781
782 #define FAIL_SCREEN_INIT(str, err) \
783 do { \
784 NOUVEAU_ERR(str, err); \
785 goto fail; \
786 } while(0)
787
788 struct nouveau_screen *
789 nvc0_screen_create(struct nouveau_device *dev)
790 {
791 struct nvc0_screen *screen;
792 struct pipe_screen *pscreen;
793 struct nouveau_object *chan;
794 struct nouveau_pushbuf *push;
795 uint64_t value;
796 uint32_t obj_class;
797 uint32_t flags;
798 int ret;
799 unsigned i;
800
801 switch (dev->chipset & ~0xf) {
802 case 0xc0:
803 case 0xd0:
804 case 0xe0:
805 case 0xf0:
806 case 0x100:
807 case 0x110:
808 case 0x120:
809 case 0x130:
810 break;
811 default:
812 return NULL;
813 }
814
815 screen = CALLOC_STRUCT(nvc0_screen);
816 if (!screen)
817 return NULL;
818 pscreen = &screen->base.base;
819 pscreen->destroy = nvc0_screen_destroy;
820
821 ret = nouveau_screen_init(&screen->base, dev);
822 if (ret)
823 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
824 chan = screen->base.channel;
825 push = screen->base.pushbuf;
826 push->user_priv = screen;
827 push->rsvd_kick = 5;
828
829 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
830 PIPE_BIND_SHADER_BUFFER |
831 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
832 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
833 screen->base.sysmem_bindings |=
834 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
835
836 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
837 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
838 screen->base.vidmem_bindings = 0;
839 }
840
841 pscreen->context_create = nvc0_create;
842 pscreen->is_format_supported = nvc0_screen_is_format_supported;
843 pscreen->get_param = nvc0_screen_get_param;
844 pscreen->get_shader_param = nvc0_screen_get_shader_param;
845 pscreen->get_paramf = nvc0_screen_get_paramf;
846 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
847 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
848
849 nvc0_screen_init_resource_functions(pscreen);
850
851 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
852 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
853
854 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
855 if (screen->base.drm->version >= 0x01000202)
856 flags |= NOUVEAU_BO_COHERENT;
857
858 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
859 if (ret)
860 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
861 nouveau_bo_map(screen->fence.bo, 0, NULL);
862 screen->fence.map = screen->fence.bo->map;
863 screen->base.fence.emit = nvc0_screen_fence_emit;
864 screen->base.fence.update = nvc0_screen_fence_update;
865
866
867 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
868 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
869 if (ret)
870 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
871
872 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
873 PUSH_DATA (push, screen->nvsw->handle);
874
875 switch (dev->chipset & ~0xf) {
876 case 0x130:
877 case 0x120:
878 case 0x110:
879 case 0x100:
880 case 0xf0:
881 obj_class = NVF0_P2MF_CLASS;
882 break;
883 case 0xe0:
884 obj_class = NVE4_P2MF_CLASS;
885 break;
886 default:
887 obj_class = NVC0_M2MF_CLASS;
888 break;
889 }
890 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
891 &screen->m2mf);
892 if (ret)
893 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
894
895 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
896 PUSH_DATA (push, screen->m2mf->oclass);
897 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
898 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
899 PUSH_DATA (push, 0xa0b5);
900 }
901
902 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
903 &screen->eng2d);
904 if (ret)
905 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
906
907 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
908 PUSH_DATA (push, screen->eng2d->oclass);
909 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
910 PUSH_DATA (push, 0);
911 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
912 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
913 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
914 PUSH_DATA (push, 0);
915 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
916 PUSH_DATA (push, 0);
917 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
918 PUSH_DATA (push, 0x3f);
919 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
920 PUSH_DATA (push, 1);
921 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
922 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
923
924 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
925 PUSH_DATAh(push, screen->fence.bo->offset + 16);
926 PUSH_DATA (push, screen->fence.bo->offset + 16);
927
928 switch (dev->chipset & ~0xf) {
929 case 0x130:
930 switch (dev->chipset) {
931 case 0x130:
932 case 0x13b:
933 obj_class = GP100_3D_CLASS;
934 break;
935 default:
936 obj_class = GP102_3D_CLASS;
937 break;
938 }
939 break;
940 case 0x120:
941 obj_class = GM200_3D_CLASS;
942 break;
943 case 0x110:
944 obj_class = GM107_3D_CLASS;
945 break;
946 case 0x100:
947 case 0xf0:
948 obj_class = NVF0_3D_CLASS;
949 break;
950 case 0xe0:
951 switch (dev->chipset) {
952 case 0xea:
953 obj_class = NVEA_3D_CLASS;
954 break;
955 default:
956 obj_class = NVE4_3D_CLASS;
957 break;
958 }
959 break;
960 case 0xd0:
961 obj_class = NVC8_3D_CLASS;
962 break;
963 case 0xc0:
964 default:
965 switch (dev->chipset) {
966 case 0xc8:
967 obj_class = NVC8_3D_CLASS;
968 break;
969 case 0xc1:
970 obj_class = NVC1_3D_CLASS;
971 break;
972 default:
973 obj_class = NVC0_3D_CLASS;
974 break;
975 }
976 break;
977 }
978 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
979 &screen->eng3d);
980 if (ret)
981 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
982 screen->base.class_3d = obj_class;
983
984 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
985 PUSH_DATA (push, screen->eng3d->oclass);
986
987 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
988 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
989
990 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
991 /* kill shaders after about 1 second (at 100 MHz) */
992 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
993 PUSH_DATA (push, 0x17);
994 }
995
996 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
997 screen->base.drm->version >= 0x01000101);
998 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
999 for (i = 0; i < 8; ++i)
1000 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1001
1002 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1003 PUSH_DATA (push, 1);
1004
1005 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1006 PUSH_DATA (push, 0);
1007 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1008 PUSH_DATA (push, 0);
1009 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1010 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1011 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1012 PUSH_DATA (push, 0);
1013 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1014 PUSH_DATA (push, 1);
1015 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1016 PUSH_DATA (push, 1);
1017 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1018 PUSH_DATA (push, 1);
1019 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1020 PUSH_DATA (push, 0);
1021 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1022 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1023 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1024 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1025 } else {
1026 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1027 PUSH_DATA (push, 15);
1028 }
1029 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1030 PUSH_DATA (push, 8); /* 128 */
1031 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1032 PUSH_DATA (push, 1);
1033 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1034 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1035 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1036 }
1037
1038 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1039
1040 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1041 if (ret)
1042 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1043
1044 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1045 &screen->uniform_bo);
1046 if (ret)
1047 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1048
1049 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1050
1051 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1052 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1053 PUSH_DATA (push, 256);
1054 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1055 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1056 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1057 PUSH_DATA (push, 0);
1058 PUSH_DATAf(push, 0.0f);
1059 PUSH_DATAf(push, 0.0f);
1060 PUSH_DATAf(push, 0.0f);
1061 PUSH_DATAf(push, 0.0f);
1062 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1063 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1064 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1065
1066 if (screen->base.drm->version >= 0x01000101) {
1067 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1068 if (ret)
1069 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1070 } else {
1071 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1072 value = (8 << 8) | 4;
1073 else
1074 value = (16 << 8) | 4;
1075 }
1076 screen->gpc_count = value & 0x000000ff;
1077 screen->mp_count = value >> 8;
1078 screen->mp_count_compute = screen->mp_count;
1079
1080 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1081 if (ret)
1082 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1083
1084 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1085 PUSH_DATAh(push, screen->tls->offset);
1086 PUSH_DATA (push, screen->tls->offset);
1087 PUSH_DATA (push, screen->tls->size >> 32);
1088 PUSH_DATA (push, screen->tls->size);
1089 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1090 PUSH_DATA (push, 0);
1091 /* Reduce likelihood of collision with real buffers by placing the hole at
1092 * the top of the 4G area. This will have to be dealt with for real
1093 * eventually by blocking off that area from the VM.
1094 */
1095 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1096 PUSH_DATA (push, 0xff << 24);
1097
1098 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1099 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1100 &screen->poly_cache);
1101 if (ret)
1102 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1103
1104 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1105 PUSH_DATAh(push, screen->poly_cache->offset);
1106 PUSH_DATA (push, screen->poly_cache->offset);
1107 PUSH_DATA (push, 3);
1108 }
1109
1110 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1111 &screen->txc);
1112 if (ret)
1113 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1114
1115 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1116 PUSH_DATAh(push, screen->txc->offset);
1117 PUSH_DATA (push, screen->txc->offset);
1118 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1119 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1120 screen->tic.maxwell = true;
1121 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1122 screen->tic.maxwell =
1123 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1124 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1125 }
1126 }
1127
1128 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1129 PUSH_DATAh(push, screen->txc->offset + 65536);
1130 PUSH_DATA (push, screen->txc->offset + 65536);
1131 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1132
1133 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1134 PUSH_DATA (push, 0);
1135 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1136 PUSH_DATA (push, 0);
1137 PUSH_DATA (push, 0);
1138 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1139 PUSH_DATA (push, 0x3f);
1140
1141 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1142 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1143 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1144 for (i = 0; i < 8 * 2; ++i)
1145 PUSH_DATA(push, 0);
1146 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1147 PUSH_DATA (push, 0);
1148 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1149 PUSH_DATA (push, 0);
1150
1151 /* neither scissors, viewport nor stencil mask should affect clears */
1152 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1153 PUSH_DATA (push, 0);
1154
1155 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1156 PUSH_DATA (push, 1);
1157 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1158 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1159 PUSH_DATAf(push, 0.0f);
1160 PUSH_DATAf(push, 1.0f);
1161 }
1162 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1163 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1164
1165 /* We use scissors instead of exact view volume clipping,
1166 * so they're always enabled.
1167 */
1168 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1169 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1170 PUSH_DATA (push, 1);
1171 PUSH_DATA (push, 8192 << 16);
1172 PUSH_DATA (push, 8192 << 16);
1173 }
1174
1175 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1176
1177 i = 0;
1178 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1179 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1180 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1181 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1182 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1183 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1184 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1185 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1186 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1187 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1188 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1189 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1190 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1191
1192 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1193 PUSH_DATA (push, 1);
1194 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1195 PUSH_DATA (push, 1);
1196 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1197 PUSH_DATA (push, 0x40);
1198 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1199 PUSH_DATA (push, 0);
1200 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1201 PUSH_DATA (push, 0x30);
1202 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1203 PUSH_DATA (push, 3);
1204 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1205 PUSH_DATA (push, 0x20);
1206 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1207 PUSH_DATA (push, 0x00);
1208 screen->save_state.patch_vertices = 3;
1209
1210 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1211 PUSH_DATA (push, 0);
1212 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1213 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1214
1215 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1216
1217 if (nvc0_screen_init_compute(screen))
1218 goto fail;
1219
1220 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1221 for (i = 0; i < 5; ++i) {
1222 /* TIC and TSC entries for each unit (nve4+ only) */
1223 /* auxiliary constants (6 user clip planes, base instance id) */
1224 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1225 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1226 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1227 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1228 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1229 PUSH_DATA (push, (15 << 4) | 1);
1230 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1231 unsigned j;
1232 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1233 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1234 for (j = 0; j < 8; ++j)
1235 PUSH_DATA(push, j);
1236 } else {
1237 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1238 PUSH_DATA (push, 0x54);
1239 }
1240
1241 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1242 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1243 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1244 PUSH_DATA (push, 0); /* 0 */
1245 PUSH_DATA (push, 0);
1246 PUSH_DATA (push, 1); /* 1 */
1247 PUSH_DATA (push, 0);
1248 PUSH_DATA (push, 0); /* 2 */
1249 PUSH_DATA (push, 1);
1250 PUSH_DATA (push, 1); /* 3 */
1251 PUSH_DATA (push, 1);
1252 PUSH_DATA (push, 2); /* 4 */
1253 PUSH_DATA (push, 0);
1254 PUSH_DATA (push, 3); /* 5 */
1255 PUSH_DATA (push, 0);
1256 PUSH_DATA (push, 2); /* 6 */
1257 PUSH_DATA (push, 1);
1258 PUSH_DATA (push, 3); /* 7 */
1259 PUSH_DATA (push, 1);
1260 }
1261 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1262 PUSH_DATA (push, 0);
1263
1264 PUSH_KICK (push);
1265
1266 screen->tic.entries = CALLOC(4096, sizeof(void *));
1267 screen->tsc.entries = screen->tic.entries + 2048;
1268
1269 if (!nvc0_blitter_create(screen))
1270 goto fail;
1271
1272 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1273 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1274
1275 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1276
1277 return &screen->base;
1278
1279 fail:
1280 screen->base.base.context_create = NULL;
1281 return &screen->base;
1282 }
1283
1284 int
1285 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1286 {
1287 int i = screen->tic.next;
1288
1289 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1290 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1291
1292 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1293
1294 if (screen->tic.entries[i])
1295 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1296
1297 screen->tic.entries[i] = entry;
1298 return i;
1299 }
1300
1301 int
1302 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1303 {
1304 int i = screen->tsc.next;
1305
1306 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1307 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1308
1309 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1310
1311 if (screen->tsc.entries[i])
1312 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1313
1314 screen->tsc.entries[i] = entry;
1315 return i;
1316 }