src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 #include "nv50/g80_texture.xml.h"
  42
  43 static boolean
  44 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  45                                 enum pipe_format format,
  46                                 enum pipe_texture_target target,
  47                                 unsigned sample_count,
  48                                 unsigned bindings)
  49 {
  50    const struct util_format_description *desc = util_format_description(format);
  51
  52    if (sample_count > 8)
  53       return false;
  54    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  55       return false;
  56
  57    /* Short-circuit the rest of the logic -- this is used by the state tracker
  58     * to determine valid MS levels in a no-attachments scenario.
  59     */
  60    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  61       return true;
  62
  63    if (!util_format_is_supported(format, bindings))
  64       return false;
  65
  66    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  67       if (util_format_get_blocksizebits(format) == 3 * 32)
  68          return false;
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  79     */
  80    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  81         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  82        /* The claim is that this should work on GM107 but it doesn't. Need to
  83         * test further and figure out if it's a nouveau issue or a HW one.
  84        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  85         */
  86        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  87       return false;
  88
  89    /* shared is always supported */
  90    bindings &= ~(PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
  94        nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  95       /* MS images are currently unsupported on Maxwell because they have to
  96        * be handled explicitly. */
  97       return false;
  98    }
  99
 100    return (( nvc0_format_table[format].usage |
 101             nvc0_vertex_format[format].usage) & bindings) == bindings;
 102 }
 103
 104 static int
 105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 108    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 109
 110    switch (param) {
 111    /* non-boolean caps */
 112    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 113    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 114       return 15;
 115    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 116       return 12;
 117    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 118       return 2048;
 119    case PIPE_CAP_MIN_TEXEL_OFFSET:
 120       return -8;
 121    case PIPE_CAP_MAX_TEXEL_OFFSET:
 122       return 7;
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124       return -32;
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126       return 31;
 127    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 128       return 128 * 1024 * 1024;
 129    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 130       return 430;
 131    case PIPE_CAP_MAX_RENDER_TARGETS:
 132       return 8;
 133    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 134       return 1;
 135    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 136       return 4;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 138    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 139       return 128;
 140    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 141    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 142       return 1024;
 143    case PIPE_CAP_MAX_VERTEX_STREAMS:
 144       return 4;
 145    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 146       return 2048;
 147    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 148       return 256;
 149    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 150       if (class_3d < NVE4_3D_CLASS)
 151          return 256; /* IMAGE bindings require alignment to 256 */
 152       return 16;
 153    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 154       return 16;
 155    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 156       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 157    case PIPE_CAP_MAX_VIEWPORTS:
 158       return NVC0_MAX_VIEWPORTS;
 159    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 160       return 4;
 161    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 162       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 163    case PIPE_CAP_ENDIANNESS:
 164       return PIPE_ENDIAN_LITTLE;
 165    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 166       return 30;
 167    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 168       return NVC0_MAX_WINDOW_RECTANGLES;
 169
 170    /* supported caps */
 171    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 172    case PIPE_CAP_TEXTURE_SWIZZLE:
 173    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 174    case PIPE_CAP_NPOT_TEXTURES:
 175    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 176    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 177    case PIPE_CAP_ANISOTROPIC_FILTER:
 178    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 179    case PIPE_CAP_CUBE_MAP_ARRAY:
 180    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 181    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 182    case PIPE_CAP_TWO_SIDED_STENCIL:
 183    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 184    case PIPE_CAP_POINT_SPRITE:
 185    case PIPE_CAP_TGSI_TEXCOORD:
 186    case PIPE_CAP_SM3:
 187    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 188    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 189    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 190    case PIPE_CAP_QUERY_TIMESTAMP:
 191    case PIPE_CAP_QUERY_TIME_ELAPSED:
 192    case PIPE_CAP_OCCLUSION_QUERY:
 193    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 194    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 195    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 196    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 197    case PIPE_CAP_INDEP_BLEND_ENABLE:
 198    case PIPE_CAP_INDEP_BLEND_FUNC:
 199    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 200    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 201    case PIPE_CAP_PRIMITIVE_RESTART:
 202    case PIPE_CAP_TGSI_INSTANCEID:
 203    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 204    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 205    case PIPE_CAP_CONDITIONAL_RENDER:
 206    case PIPE_CAP_TEXTURE_BARRIER:
 207    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 208    case PIPE_CAP_START_INSTANCE:
 209    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 210    case PIPE_CAP_DRAW_INDIRECT:
 211    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 212    case PIPE_CAP_USER_VERTEX_BUFFERS:
 213    case PIPE_CAP_TEXTURE_QUERY_LOD:
 214    case PIPE_CAP_SAMPLE_SHADING:
 215    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 216    case PIPE_CAP_TEXTURE_GATHER_SM5:
 217    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 218    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 219    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 220    case PIPE_CAP_CLIP_HALFZ:
 221    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 222    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 223    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 224    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 225    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 226    case PIPE_CAP_TGSI_TXQS:
 227    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 228    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 229    case PIPE_CAP_SHAREABLE_SHADERS:
 230    case PIPE_CAP_CLEAR_TEXTURE:
 231    case PIPE_CAP_DRAW_PARAMETERS:
 232    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 233    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 235    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 236    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 237    case PIPE_CAP_INVALIDATE_BUFFER:
 238    case PIPE_CAP_STRING_MARKER:
 239    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 240    case PIPE_CAP_CULL_DISTANCE:
 241    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 242    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 243    case PIPE_CAP_TGSI_VOTE:
 244    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 245    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 246    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 247    case PIPE_CAP_DOUBLES:
 248    case PIPE_CAP_INT64:
 249    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 250       return 1;
 251    case PIPE_CAP_COMPUTE:
 252       return (class_3d < GP100_3D_CLASS);
 253    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 254       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 255    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 256       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 257    case PIPE_CAP_TGSI_FS_FBFETCH:
 258       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 259    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 260       return class_3d >= GM200_3D_CLASS;
 261
 262    /* unsupported caps */
 263    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 264    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 265    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 266    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 267    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 268    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 269    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 270    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 271    case PIPE_CAP_FAKE_SW_MSAA:
 272    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 273    case PIPE_CAP_VERTEXID_NOBASE:
 274    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 275    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 276    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 277    case PIPE_CAP_GENERATE_MIPMAP:
 278    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 279    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 280    case PIPE_CAP_QUERY_MEMORY_INFO:
 281    case PIPE_CAP_PCI_GROUP:
 282    case PIPE_CAP_PCI_BUS:
 283    case PIPE_CAP_PCI_DEVICE:
 284    case PIPE_CAP_PCI_FUNCTION:
 285    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 286    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 287    case PIPE_CAP_NATIVE_FENCE_FD:
 288    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 289    case PIPE_CAP_INT64_DIVMOD:
 290    case PIPE_CAP_TGSI_CLOCK:
 291       return 0;
 292
 293    case PIPE_CAP_VENDOR_ID:
 294       return 0x10de;
 295    case PIPE_CAP_DEVICE_ID: {
 296       uint64_t device_id;
 297       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 298          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 299          return -1;
 300       }
 301       return device_id;
 302    }
 303    case PIPE_CAP_ACCELERATED:
 304       return 1;
 305    case PIPE_CAP_VIDEO_MEMORY:
 306       return dev->vram_size >> 20;
 307    case PIPE_CAP_UMA:
 308       return 0;
 309    }
 310
 311    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 312    return 0;
 313 }
 314
 315 static int
 316 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 317                              enum pipe_shader_type shader,
 318                              enum pipe_shader_cap param)
 319 {
 320    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 321
 322    switch (shader) {
 323    case PIPE_SHADER_VERTEX:
 324    case PIPE_SHADER_GEOMETRY:
 325    case PIPE_SHADER_FRAGMENT:
 326    case PIPE_SHADER_COMPUTE:
 327    case PIPE_SHADER_TESS_CTRL:
 328    case PIPE_SHADER_TESS_EVAL:
 329       break;
 330    default:
 331       return 0;
 332    }
 333
 334    switch (param) {
 335    case PIPE_SHADER_CAP_PREFERRED_IR:
 336       return PIPE_SHADER_IR_TGSI;
 337    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 338       return 1 << PIPE_SHADER_IR_TGSI;
 339    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 340    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 341    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 342    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 343       return 16384;
 344    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 345       return 16;
 346    case PIPE_SHADER_CAP_MAX_INPUTS:
 347       if (shader == PIPE_SHADER_VERTEX)
 348          return 32;
 349       /* NOTE: These only count our slots for GENERIC varyings.
 350        * The address space may be larger, but the actual hard limit seems to be
 351        * less than what the address space layout permits, so don't add TEXCOORD,
 352        * COLOR, etc. here.
 353        */
 354       if (shader == PIPE_SHADER_FRAGMENT)
 355          return 0x1f0 / 16;
 356       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 357        * and excludes 0x60 per-patch inputs.
 358        */
 359       return 0x200 / 16;
 360    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 361       return 32;
 362    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 363       return 65536;
 364    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 365       return NVC0_MAX_PIPE_CONSTBUFS;
 366    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 367       return shader != PIPE_SHADER_FRAGMENT;
 368    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 369    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 370    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 371       return 1;
 372    case PIPE_SHADER_CAP_MAX_TEMPS:
 373       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 374    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 375       return 1;
 376    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 377       return 1;
 378    case PIPE_SHADER_CAP_SUBROUTINES:
 379       return 1;
 380    case PIPE_SHADER_CAP_INTEGERS:
 381       return 1;
 382    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 383       return 1;
 384    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 385       return 1;
 386    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 387    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 388    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 389       return 0;
 390    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 391       return NVC0_MAX_BUFFERS;
 392    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 393       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 394    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 395       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 396    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 397       return 32;
 398    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 399       if (class_3d >= NVE4_3D_CLASS)
 400          return NVC0_MAX_IMAGES;
 401       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 402          return NVC0_MAX_IMAGES;
 403       return 0;
 404    default:
 405       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 406       return 0;
 407    }
 408 }
 409
 410 static float
 411 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 412 {
 413    switch (param) {
 414    case PIPE_CAPF_MAX_LINE_WIDTH:
 415    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 416       return 10.0f;
 417    case PIPE_CAPF_MAX_POINT_WIDTH:
 418       return 63.0f;
 419    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 420       return 63.375f;
 421    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 422       return 16.0f;
 423    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 424       return 15.0f;
 425    case PIPE_CAPF_GUARD_BAND_LEFT:
 426    case PIPE_CAPF_GUARD_BAND_TOP:
 427       return 0.0f;
 428    case PIPE_CAPF_GUARD_BAND_RIGHT:
 429    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 430       return 0.0f; /* that or infinity */
 431    }
 432
 433    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 434    return 0.0f;
 435 }
 436
 437 static int
 438 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 439                               enum pipe_shader_ir ir_type,
 440                               enum pipe_compute_cap param, void *data)
 441 {
 442    struct nvc0_screen *screen = nvc0_screen(pscreen);
 443    const uint16_t obj_class = screen->compute->oclass;
 444
 445 #define RET(x) do {                  \
 446    if (data)                         \
 447       memcpy(data, x, sizeof(x));    \
 448    return sizeof(x);                 \
 449 } while (0)
 450
 451    switch (param) {
 452    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 453       RET((uint64_t []) { 3 });
 454    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 455       if (obj_class >= NVE4_COMPUTE_CLASS) {
 456          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 457       } else {
 458          RET(((uint64_t []) { 65535, 65535, 65535 }));
 459       }
 460    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 461       RET(((uint64_t []) { 1024, 1024, 64 }));
 462    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 463       RET((uint64_t []) { 1024 });
 464    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 465       if (obj_class >= NVE4_COMPUTE_CLASS) {
 466          RET((uint64_t []) { 1024 });
 467       } else {
 468          RET((uint64_t []) { 512 });
 469       }
 470    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 471       RET((uint64_t []) { 1ULL << 40 });
 472    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 473       switch (obj_class) {
 474       case GM200_COMPUTE_CLASS:
 475          RET((uint64_t []) { 96 << 10 });
 476          break;
 477       case GM107_COMPUTE_CLASS:
 478          RET((uint64_t []) { 64 << 10 });
 479          break;
 480       default:
 481          RET((uint64_t []) { 48 << 10 });
 482          break;
 483       }
 484    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 485       RET((uint64_t []) { 512 << 10 });
 486    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 487       RET((uint64_t []) { 4096 });
 488    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 489       RET((uint32_t []) { 32 });
 490    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 491       RET((uint64_t []) { 1ULL << 40 });
 492    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 493       RET((uint32_t []) { 0 });
 494    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 495       RET((uint32_t []) { screen->mp_count_compute });
 496    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 497       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 498    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 499       RET((uint32_t []) { 64 });
 500    default:
 501       return 0;
 502    }
 503
 504 #undef RET
 505 }
 506
 507 static void
 508 nvc0_screen_destroy(struct pipe_screen *pscreen)
 509 {
 510    struct nvc0_screen *screen = nvc0_screen(pscreen);
 511
 512    if (!nouveau_drm_screen_unref(&screen->base))
 513       return;
 514
 515    if (screen->base.fence.current) {
 516       struct nouveau_fence *current = NULL;
 517
 518       /* nouveau_fence_wait will create a new current fence, so wait on the
 519        * _current_ one, and remove both.
 520        */
 521       nouveau_fence_ref(screen->base.fence.current, &current);
 522       nouveau_fence_wait(current, NULL);
 523       nouveau_fence_ref(NULL, &current);
 524       nouveau_fence_ref(NULL, &screen->base.fence.current);
 525    }
 526    if (screen->base.pushbuf)
 527       screen->base.pushbuf->user_priv = NULL;
 528
 529    if (screen->blitter)
 530       nvc0_blitter_destroy(screen);
 531    if (screen->pm.prog) {
 532       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 533       nvc0_program_destroy(NULL, screen->pm.prog);
 534       FREE(screen->pm.prog);
 535    }
 536
 537    nouveau_bo_ref(NULL, &screen->text);
 538    nouveau_bo_ref(NULL, &screen->uniform_bo);
 539    nouveau_bo_ref(NULL, &screen->tls);
 540    nouveau_bo_ref(NULL, &screen->txc);
 541    nouveau_bo_ref(NULL, &screen->fence.bo);
 542    nouveau_bo_ref(NULL, &screen->poly_cache);
 543
 544    nouveau_heap_destroy(&screen->lib_code);
 545    nouveau_heap_destroy(&screen->text_heap);
 546
 547    FREE(screen->default_tsc);
 548    FREE(screen->tic.entries);
 549
 550    nouveau_object_del(&screen->eng3d);
 551    nouveau_object_del(&screen->eng2d);
 552    nouveau_object_del(&screen->m2mf);
 553    nouveau_object_del(&screen->compute);
 554    nouveau_object_del(&screen->nvsw);
 555
 556    nouveau_screen_fini(&screen->base);
 557
 558    FREE(screen);
 559 }
 560
 561 static int
 562 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 563                      unsigned size, const uint32_t *data)
 564 {
 565    struct nouveau_pushbuf *push = screen->base.pushbuf;
 566
 567    size /= 4;
 568
 569    assert((pos + size) <= 0x800);
 570
 571    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 572    PUSH_DATA (push, (m - 0x3800) / 8);
 573    PUSH_DATA (push, pos);
 574    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 575    PUSH_DATA (push, pos);
 576    PUSH_DATAp(push, data, size);
 577
 578    return pos + size;
 579 }
 580
 581 static void
 582 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 583 {
 584    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 585    PUSH_DATA (push, 0xff);
 586    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 587    PUSH_DATA (push, 0xff);
 588    PUSH_DATA (push, 0xff);
 589    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 590    PUSH_DATA (push, 0xff);
 591    PUSH_DATA (push, 0xff);
 592    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 593    PUSH_DATA (push, 0x3f);
 594
 595    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 596    PUSH_DATA (push, (3 << 16) | 3);
 597    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 598    PUSH_DATA (push, (2 << 16) | 2);
 599
 600    if (obj_class < GM107_3D_CLASS) {
 601       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 602       PUSH_DATA (push, 0);
 603    }
 604    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 605    PUSH_DATA (push, 0x10);
 606    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 607    PUSH_DATA (push, 0x10);
 608    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 609    PUSH_DATA (push, 0x10);
 610    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 611    PUSH_DATA (push, 0x10);
 612    PUSH_DATA (push, 0x10);
 613    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 614    PUSH_DATA (push, 0x10);
 615    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 616    PUSH_DATA (push, 0xe);
 617
 618    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 619    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 620    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 621    PUSH_DATA (push, 0);
 622    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 623    PUSH_DATA (push, 3);
 624
 625    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 626    PUSH_DATA (push, 0x3fffff);
 627    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 628    PUSH_DATA (push, 1);
 629    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 630    PUSH_DATA (push, 1);
 631
 632    if (obj_class < GM107_3D_CLASS) {
 633       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 634       PUSH_DATA (push, 3);
 635
 636       if (obj_class >= NVE4_3D_CLASS) {
 637          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 638          PUSH_DATA (push, 1);
 639       }
 640    }
 641
 642    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 643     * are supposed to do */
 644 }
 645
 646 static void
 647 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 648 {
 649    struct nvc0_screen *screen = nvc0_screen(pscreen);
 650    struct nouveau_pushbuf *push = screen->base.pushbuf;
 651
 652    /* we need to do it after possible flush in MARK_RING */
 653    *sequence = ++screen->base.fence.sequence;
 654
 655    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 656    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 657    PUSH_DATAh(push, screen->fence.bo->offset);
 658    PUSH_DATA (push, screen->fence.bo->offset);
 659    PUSH_DATA (push, *sequence);
 660    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 661               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 662 }
 663
 664 static u32
 665 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 666 {
 667    struct nvc0_screen *screen = nvc0_screen(pscreen);
 668    return screen->fence.map[0];
 669 }
 670
 671 static int
 672 nvc0_screen_init_compute(struct nvc0_screen *screen)
 673 {
 674    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 675
 676    switch (screen->base.device->chipset & ~0xf) {
 677    case 0xc0:
 678    case 0xd0:
 679       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 680    case 0xe0:
 681    case 0xf0:
 682    case 0x100:
 683    case 0x110:
 684    case 0x120:
 685       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 686    case 0x130:
 687       return 0;
 688    default:
 689       return -1;
 690    }
 691 }
 692
 693 static int
 694 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 695                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 696 {
 697    struct nouveau_bo *bo = NULL;
 698    int ret;
 699    uint64_t size = (lpos + lneg) * 32 + cstack;
 700
 701    if (size >= (1 << 20)) {
 702       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 703       return -1;
 704    }
 705
 706    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 707    size  = align(size, 0x8000);
 708    size *= screen->mp_count;
 709
 710    size = align(size, 1 << 17);
 711
 712    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 713                         NULL, &bo);
 714    if (ret)
 715       return ret;
 716    nouveau_bo_ref(NULL, &screen->tls);
 717    screen->tls = bo;
 718    return 0;
 719 }
 720
 721 int
 722 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 723 {
 724    struct nouveau_pushbuf *push = screen->base.pushbuf;
 725    struct nouveau_bo *bo;
 726    int ret;
 727
 728    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 729                         1 << 17, size, NULL, &bo);
 730    if (ret)
 731       return ret;
 732
 733    nouveau_bo_ref(NULL, &screen->text);
 734    screen->text = bo;
 735
 736    nouveau_heap_destroy(&screen->lib_code);
 737    nouveau_heap_destroy(&screen->text_heap);
 738
 739    /* XXX: getting a page fault at the end of the code buffer every few
 740     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 741     */
 742    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 743
 744    /* update the code segment setup */
 745    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 746    PUSH_DATAh(push, screen->text->offset);
 747    PUSH_DATA (push, screen->text->offset);
 748    if (screen->compute) {
 749       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 750       PUSH_DATAh(push, screen->text->offset);
 751       PUSH_DATA (push, screen->text->offset);
 752    }
 753
 754    return 0;
 755 }
 756
 757 #define FAIL_SCREEN_INIT(str, err)                    \
 758    do {                                               \
 759       NOUVEAU_ERR(str, err);                          \
 760       goto fail;                                      \
 761    } while(0)
 762
 763 struct nouveau_screen *
 764 nvc0_screen_create(struct nouveau_device *dev)
 765 {
 766    struct nvc0_screen *screen;
 767    struct pipe_screen *pscreen;
 768    struct nouveau_object *chan;
 769    struct nouveau_pushbuf *push;
 770    uint64_t value;
 771    uint32_t obj_class;
 772    uint32_t flags;
 773    int ret;
 774    unsigned i;
 775
 776    switch (dev->chipset & ~0xf) {
 777    case 0xc0:
 778    case 0xd0:
 779    case 0xe0:
 780    case 0xf0:
 781    case 0x100:
 782    case 0x110:
 783    case 0x120:
 784    case 0x130:
 785       break;
 786    default:
 787       return NULL;
 788    }
 789
 790    screen = CALLOC_STRUCT(nvc0_screen);
 791    if (!screen)
 792       return NULL;
 793    pscreen = &screen->base.base;
 794    pscreen->destroy = nvc0_screen_destroy;
 795
 796    ret = nouveau_screen_init(&screen->base, dev);
 797    if (ret)
 798       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 799    chan = screen->base.channel;
 800    push = screen->base.pushbuf;
 801    push->user_priv = screen;
 802    push->rsvd_kick = 5;
 803
 804    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 805       PIPE_BIND_SHADER_BUFFER |
 806       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 807       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 808    screen->base.sysmem_bindings |=
 809       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 810
 811    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 812       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 813       screen->base.vidmem_bindings = 0;
 814    }
 815
 816    pscreen->context_create = nvc0_create;
 817    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 818    pscreen->get_param = nvc0_screen_get_param;
 819    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 820    pscreen->get_paramf = nvc0_screen_get_paramf;
 821    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 822    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 823
 824    nvc0_screen_init_resource_functions(pscreen);
 825
 826    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 827    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 828
 829    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 830    if (screen->base.drm->version >= 0x01000202)
 831       flags |= NOUVEAU_BO_COHERENT;
 832
 833    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 834    if (ret)
 835       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 836    nouveau_bo_map(screen->fence.bo, 0, NULL);
 837    screen->fence.map = screen->fence.bo->map;
 838    screen->base.fence.emit = nvc0_screen_fence_emit;
 839    screen->base.fence.update = nvc0_screen_fence_update;
 840
 841
 842    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 843                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 844    if (ret)
 845       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 846
 847    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 848    PUSH_DATA (push, screen->nvsw->handle);
 849
 850    switch (dev->chipset & ~0xf) {
 851    case 0x130:
 852    case 0x120:
 853    case 0x110:
 854    case 0x100:
 855    case 0xf0:
 856       obj_class = NVF0_P2MF_CLASS;
 857       break;
 858    case 0xe0:
 859       obj_class = NVE4_P2MF_CLASS;
 860       break;
 861    default:
 862       obj_class = NVC0_M2MF_CLASS;
 863       break;
 864    }
 865    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 866                             &screen->m2mf);
 867    if (ret)
 868       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 869
 870    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 871    PUSH_DATA (push, screen->m2mf->oclass);
 872    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 873       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 874       PUSH_DATA (push, 0xa0b5);
 875    }
 876
 877    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 878                             &screen->eng2d);
 879    if (ret)
 880       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 881
 882    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 883    PUSH_DATA (push, screen->eng2d->oclass);
 884    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 885    PUSH_DATA (push, 0);
 886    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 887    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 888    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 889    PUSH_DATA (push, 0);
 890    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 891    PUSH_DATA (push, 0);
 892    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 893    PUSH_DATA (push, 0x3f);
 894    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 895    PUSH_DATA (push, 1);
 896    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 897    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 898
 899    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 900    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 901    PUSH_DATA (push, screen->fence.bo->offset + 16);
 902
 903    switch (dev->chipset & ~0xf) {
 904    case 0x130:
 905       switch (dev->chipset) {
 906       case 0x130:
 907          obj_class = GP100_3D_CLASS;
 908          break;
 909       default:
 910          obj_class = GP102_3D_CLASS;
 911          break;
 912       }
 913       break;
 914    case 0x120:
 915       obj_class = GM200_3D_CLASS;
 916       break;
 917    case 0x110:
 918       obj_class = GM107_3D_CLASS;
 919       break;
 920    case 0x100:
 921    case 0xf0:
 922       obj_class = NVF0_3D_CLASS;
 923       break;
 924    case 0xe0:
 925       switch (dev->chipset) {
 926       case 0xea:
 927          obj_class = NVEA_3D_CLASS;
 928          break;
 929       default:
 930          obj_class = NVE4_3D_CLASS;
 931          break;
 932       }
 933       break;
 934    case 0xd0:
 935       obj_class = NVC8_3D_CLASS;
 936       break;
 937    case 0xc0:
 938    default:
 939       switch (dev->chipset) {
 940       case 0xc8:
 941          obj_class = NVC8_3D_CLASS;
 942          break;
 943       case 0xc1:
 944          obj_class = NVC1_3D_CLASS;
 945          break;
 946       default:
 947          obj_class = NVC0_3D_CLASS;
 948          break;
 949       }
 950       break;
 951    }
 952    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 953                             &screen->eng3d);
 954    if (ret)
 955       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 956    screen->base.class_3d = obj_class;
 957
 958    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 959    PUSH_DATA (push, screen->eng3d->oclass);
 960
 961    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 962    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 963
 964    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 965       /* kill shaders after about 1 second (at 100 MHz) */
 966       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 967       PUSH_DATA (push, 0x17);
 968    }
 969
 970    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 971                     screen->base.drm->version >= 0x01000101);
 972    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 973    for (i = 0; i < 8; ++i)
 974       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 975
 976    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 977    PUSH_DATA (push, 1);
 978
 979    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 980    PUSH_DATA (push, 0);
 981    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 982    PUSH_DATA (push, 0);
 983    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 984    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 985    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 986    PUSH_DATA (push, 0);
 987    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 988    PUSH_DATA (push, 1);
 989    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 990    PUSH_DATA (push, 1);
 991    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 992    PUSH_DATA (push, 1);
 993    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 994    PUSH_DATA (push, 0);
 995    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 996    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 997    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 998       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 999    } else {
1000       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1001       PUSH_DATA (push, 15);
1002    }
1003    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1004    PUSH_DATA (push, 8); /* 128 */
1005    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1006    PUSH_DATA (push, 1);
1007    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1008       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1009       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1010    }
1011
1012    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1013
1014    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1015    if (ret)
1016       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1017
1018    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1019                         &screen->uniform_bo);
1020    if (ret)
1021       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1022
1023    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1024
1025    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1026    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1027    PUSH_DATA (push, 256);
1028    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1029    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1030    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1031    PUSH_DATA (push, 0);
1032    PUSH_DATAf(push, 0.0f);
1033    PUSH_DATAf(push, 0.0f);
1034    PUSH_DATAf(push, 0.0f);
1035    PUSH_DATAf(push, 0.0f);
1036    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1037    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1038    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1039
1040    if (screen->base.drm->version >= 0x01000101) {
1041       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1042       if (ret)
1043          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1044    } else {
1045       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1046          value = (8 << 8) | 4;
1047       else
1048          value = (16 << 8) | 4;
1049    }
1050    screen->gpc_count = value & 0x000000ff;
1051    screen->mp_count = value >> 8;
1052    screen->mp_count_compute = screen->mp_count;
1053
1054    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1055    if (ret)
1056       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1057
1058    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1059    PUSH_DATAh(push, screen->tls->offset);
1060    PUSH_DATA (push, screen->tls->offset);
1061    PUSH_DATA (push, screen->tls->size >> 32);
1062    PUSH_DATA (push, screen->tls->size);
1063    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1064    PUSH_DATA (push, 0);
1065    /* Reduce likelihood of collision with real buffers by placing the hole at
1066     * the top of the 4G area. This will have to be dealt with for real
1067     * eventually by blocking off that area from the VM.
1068     */
1069    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1070    PUSH_DATA (push, 0xff << 24);
1071
1072    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1073       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1074                            &screen->poly_cache);
1075       if (ret)
1076          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1077
1078       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1079       PUSH_DATAh(push, screen->poly_cache->offset);
1080       PUSH_DATA (push, screen->poly_cache->offset);
1081       PUSH_DATA (push, 3);
1082    }
1083
1084    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1085                         &screen->txc);
1086    if (ret)
1087       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1088
1089    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1090    PUSH_DATAh(push, screen->txc->offset);
1091    PUSH_DATA (push, screen->txc->offset);
1092    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1093    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1094       screen->tic.maxwell = true;
1095       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1096          screen->tic.maxwell =
1097             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1098          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1099       }
1100    }
1101
1102    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1103    PUSH_DATAh(push, screen->txc->offset + 65536);
1104    PUSH_DATA (push, screen->txc->offset + 65536);
1105    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1106
1107    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1108    PUSH_DATA (push, 0);
1109    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1110    PUSH_DATA (push, 0);
1111    PUSH_DATA (push, 0);
1112    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1113    PUSH_DATA (push, 0x3f);
1114
1115    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1116    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1117    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1118    for (i = 0; i < 8 * 2; ++i)
1119       PUSH_DATA(push, 0);
1120    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1121    PUSH_DATA (push, 0);
1122    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1123    PUSH_DATA (push, 0);
1124
1125    /* neither scissors, viewport nor stencil mask should affect clears */
1126    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1127    PUSH_DATA (push, 0);
1128
1129    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1130    PUSH_DATA (push, 1);
1131    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1132       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1133       PUSH_DATAf(push, 0.0f);
1134       PUSH_DATAf(push, 1.0f);
1135    }
1136    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1137    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1138
1139    /* We use scissors instead of exact view volume clipping,
1140     * so they're always enabled.
1141     */
1142    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1143       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1144       PUSH_DATA (push, 1);
1145       PUSH_DATA (push, 8192 << 16);
1146       PUSH_DATA (push, 8192 << 16);
1147    }
1148
1149 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1150
1151    i = 0;
1152    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1153    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1154    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1155    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1156    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1157    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1158    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1159    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1160    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1161    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1162    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1163    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1164    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1165
1166    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1167    PUSH_DATA (push, 1);
1168    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1169    PUSH_DATA (push, 1);
1170    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1171    PUSH_DATA (push, 0x40);
1172    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1173    PUSH_DATA (push, 0);
1174    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1175    PUSH_DATA (push, 0x30);
1176    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1177    PUSH_DATA (push, 3);
1178    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1179    PUSH_DATA (push, 0x20);
1180    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1181    PUSH_DATA (push, 0x00);
1182    screen->save_state.patch_vertices = 3;
1183
1184    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1185    PUSH_DATA (push, 0);
1186    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1187    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1188
1189    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1190
1191    if (nvc0_screen_init_compute(screen))
1192       goto fail;
1193
1194    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1195    for (i = 0; i < 5; ++i) {
1196       /* TIC and TSC entries for each unit (nve4+ only) */
1197       /* auxiliary constants (6 user clip planes, base instance id) */
1198       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1199       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1200       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1201       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1202       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1203       PUSH_DATA (push, (15 << 4) | 1);
1204       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1205          unsigned j;
1206          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1207          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1208          for (j = 0; j < 8; ++j)
1209             PUSH_DATA(push, j);
1210       } else {
1211          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1212          PUSH_DATA (push, 0x54);
1213       }
1214
1215       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1216       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1217       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1218       PUSH_DATA (push, 0); /* 0 */
1219       PUSH_DATA (push, 0);
1220       PUSH_DATA (push, 1); /* 1 */
1221       PUSH_DATA (push, 0);
1222       PUSH_DATA (push, 0); /* 2 */
1223       PUSH_DATA (push, 1);
1224       PUSH_DATA (push, 1); /* 3 */
1225       PUSH_DATA (push, 1);
1226       PUSH_DATA (push, 2); /* 4 */
1227       PUSH_DATA (push, 0);
1228       PUSH_DATA (push, 3); /* 5 */
1229       PUSH_DATA (push, 0);
1230       PUSH_DATA (push, 2); /* 6 */
1231       PUSH_DATA (push, 1);
1232       PUSH_DATA (push, 3); /* 7 */
1233       PUSH_DATA (push, 1);
1234    }
1235    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1236    PUSH_DATA (push, 0);
1237
1238    PUSH_KICK (push);
1239
1240    screen->tic.entries = CALLOC(4096, sizeof(void *));
1241    screen->tsc.entries = screen->tic.entries + 2048;
1242
1243    if (!nvc0_blitter_create(screen))
1244       goto fail;
1245
1246    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1247    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1248
1249    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1250
1251    return &screen->base;
1252
1253 fail:
1254    screen->base.base.context_create = NULL;
1255    return &screen->base;
1256 }
1257
1258 int
1259 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1260 {
1261    int i = screen->tic.next;
1262
1263    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1264       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1265
1266    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1267
1268    if (screen->tic.entries[i])
1269       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1270
1271    screen->tic.entries[i] = entry;
1272    return i;
1273 }
1274
1275 int
1276 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1277 {
1278    int i = screen->tsc.next;
1279
1280    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1281       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1282
1283    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1284
1285    if (screen->tsc.entries[i])
1286       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1287
1288    screen->tsc.entries[i] = entry;
1289    return i;
1290 }