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gallium: add PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36 #include "nvc0/mme/com90c0.mme.h"
37
38 #include "nv50/g80_texture.xml.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 const struct util_format_description *desc = util_format_description(format);
48
49 if (sample_count > 8)
50 return false;
51 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
52 return false;
53
54 /* Short-circuit the rest of the logic -- this is used by the state tracker
55 * to determine valid MS levels in a no-attachments scenario.
56 */
57 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
58 return true;
59
60 if (!util_format_is_supported(format, bindings))
61 return false;
62
63 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
64 if (util_format_get_blocksizebits(format) == 3 * 32)
65 return false;
66
67 if (bindings & PIPE_BIND_LINEAR)
68 if (util_format_is_depth_or_stencil(format) ||
69 (target != PIPE_TEXTURE_1D &&
70 target != PIPE_TEXTURE_2D &&
71 target != PIPE_TEXTURE_RECT) ||
72 sample_count > 1)
73 return false;
74
75 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
76 */
77 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
78 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
79 /* The claim is that this should work on GM107 but it doesn't. Need to
80 * test further and figure out if it's a nouveau issue or a HW one.
81 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
82 */
83 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
84 return false;
85
86 /* shared is always supported */
87 bindings &= ~(PIPE_BIND_LINEAR |
88 PIPE_BIND_SHARED);
89
90 if (bindings & PIPE_BIND_SHADER_IMAGE) {
91 if (sample_count > 0 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
99 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
100 /* This should work on Fermi, but for currently unknown reasons it
101 * does not and results in breaking reads from pbos. */
102 return false;
103 }
104 }
105
106 return (( nvc0_format_table[format].usage |
107 nvc0_vertex_format[format].usage) & bindings) == bindings;
108 }
109
110 static int
111 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
112 {
113 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
114 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
115
116 switch (param) {
117 /* non-boolean caps */
118 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
119 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
120 return 15;
121 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
122 return 12;
123 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
124 return 2048;
125 case PIPE_CAP_MIN_TEXEL_OFFSET:
126 return -8;
127 case PIPE_CAP_MAX_TEXEL_OFFSET:
128 return 7;
129 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
130 return -32;
131 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
132 return 31;
133 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
134 return 128 * 1024 * 1024;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL:
136 return 430;
137 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
138 return 140;
139 case PIPE_CAP_MAX_RENDER_TARGETS:
140 return 8;
141 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
142 return 1;
143 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
144 return 4;
145 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
146 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
147 return 128;
148 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
149 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
150 return 1024;
151 case PIPE_CAP_MAX_VERTEX_STREAMS:
152 return 4;
153 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
154 return 2048;
155 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
156 return 256;
157 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
158 if (class_3d < GM107_3D_CLASS)
159 return 256; /* IMAGE bindings require alignment to 256 */
160 return 16;
161 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
162 return 16;
163 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
164 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
165 case PIPE_CAP_MAX_VIEWPORTS:
166 return NVC0_MAX_VIEWPORTS;
167 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
168 return 4;
169 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
170 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
171 case PIPE_CAP_ENDIANNESS:
172 return PIPE_ENDIAN_LITTLE;
173 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
174 return 30;
175 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
176 return NVC0_MAX_WINDOW_RECTANGLES;
177 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
178 return class_3d >= GM200_3D_CLASS ? 8 : 0;
179
180 /* supported caps */
181 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
182 case PIPE_CAP_TEXTURE_SWIZZLE:
183 case PIPE_CAP_NPOT_TEXTURES:
184 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
185 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
186 case PIPE_CAP_ANISOTROPIC_FILTER:
187 case PIPE_CAP_SEAMLESS_CUBE_MAP:
188 case PIPE_CAP_CUBE_MAP_ARRAY:
189 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
190 case PIPE_CAP_TEXTURE_MULTISAMPLE:
191 case PIPE_CAP_DEPTH_CLIP_DISABLE:
192 case PIPE_CAP_POINT_SPRITE:
193 case PIPE_CAP_TGSI_TEXCOORD:
194 case PIPE_CAP_SM3:
195 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
196 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
197 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
198 case PIPE_CAP_QUERY_TIMESTAMP:
199 case PIPE_CAP_QUERY_TIME_ELAPSED:
200 case PIPE_CAP_OCCLUSION_QUERY:
201 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
202 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
203 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
204 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
205 case PIPE_CAP_INDEP_BLEND_ENABLE:
206 case PIPE_CAP_INDEP_BLEND_FUNC:
207 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
208 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
209 case PIPE_CAP_PRIMITIVE_RESTART:
210 case PIPE_CAP_TGSI_INSTANCEID:
211 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
212 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
213 case PIPE_CAP_CONDITIONAL_RENDER:
214 case PIPE_CAP_TEXTURE_BARRIER:
215 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
216 case PIPE_CAP_START_INSTANCE:
217 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
218 case PIPE_CAP_DRAW_INDIRECT:
219 case PIPE_CAP_USER_VERTEX_BUFFERS:
220 case PIPE_CAP_TEXTURE_QUERY_LOD:
221 case PIPE_CAP_SAMPLE_SHADING:
222 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
223 case PIPE_CAP_TEXTURE_GATHER_SM5:
224 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
225 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
226 case PIPE_CAP_SAMPLER_VIEW_TARGET:
227 case PIPE_CAP_CLIP_HALFZ:
228 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
229 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
230 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
231 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
232 case PIPE_CAP_DEPTH_BOUNDS_TEST:
233 case PIPE_CAP_TGSI_TXQS:
234 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
235 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
236 case PIPE_CAP_SHAREABLE_SHADERS:
237 case PIPE_CAP_CLEAR_TEXTURE:
238 case PIPE_CAP_DRAW_PARAMETERS:
239 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
240 case PIPE_CAP_MULTI_DRAW_INDIRECT:
241 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
242 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
243 case PIPE_CAP_QUERY_BUFFER_OBJECT:
244 case PIPE_CAP_INVALIDATE_BUFFER:
245 case PIPE_CAP_STRING_MARKER:
246 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
247 case PIPE_CAP_CULL_DISTANCE:
248 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
249 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
250 case PIPE_CAP_TGSI_VOTE:
251 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
252 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
253 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
254 case PIPE_CAP_DOUBLES:
255 case PIPE_CAP_INT64:
256 case PIPE_CAP_TGSI_TEX_TXF_LZ:
257 case PIPE_CAP_TGSI_CLOCK:
258 case PIPE_CAP_COMPUTE:
259 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
260 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
261 case PIPE_CAP_QUERY_SO_OVERFLOW:
262 return 1;
263 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
264 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
265 case PIPE_CAP_TGSI_FS_FBFETCH:
266 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
267 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
268 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
269 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
270 case PIPE_CAP_POST_DEPTH_COVERAGE:
271 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
272 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
273 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
274 return class_3d >= GM200_3D_CLASS;
275 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
276 return class_3d >= GP100_3D_CLASS;
277 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
278 case PIPE_CAP_TGSI_BALLOT:
279 case PIPE_CAP_BINDLESS_TEXTURE:
280 return class_3d >= NVE4_3D_CLASS;
281
282 /* unsupported caps */
283 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
284 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
285 case PIPE_CAP_SHADER_STENCIL_EXPORT:
286 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
287 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
288 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
289 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
290 case PIPE_CAP_FAKE_SW_MSAA:
291 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
292 case PIPE_CAP_VERTEXID_NOBASE:
293 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
294 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
295 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
296 case PIPE_CAP_GENERATE_MIPMAP:
297 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
298 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
299 case PIPE_CAP_QUERY_MEMORY_INFO:
300 case PIPE_CAP_PCI_GROUP:
301 case PIPE_CAP_PCI_BUS:
302 case PIPE_CAP_PCI_DEVICE:
303 case PIPE_CAP_PCI_FUNCTION:
304 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
305 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
306 case PIPE_CAP_NATIVE_FENCE_FD:
307 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
308 case PIPE_CAP_INT64_DIVMOD:
309 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
310 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
311 case PIPE_CAP_MEMOBJ:
312 case PIPE_CAP_LOAD_CONSTBUF:
313 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
314 case PIPE_CAP_TILE_RASTER_ORDER:
315 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
316 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
317 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
318 case PIPE_CAP_FENCE_SIGNAL:
319 case PIPE_CAP_CONSTBUF0_FLAGS:
320 case PIPE_CAP_PACKED_UNIFORMS:
321 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
322 return 0;
323
324 case PIPE_CAP_VENDOR_ID:
325 return 0x10de;
326 case PIPE_CAP_DEVICE_ID: {
327 uint64_t device_id;
328 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
329 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
330 return -1;
331 }
332 return device_id;
333 }
334 case PIPE_CAP_ACCELERATED:
335 return 1;
336 case PIPE_CAP_VIDEO_MEMORY:
337 return dev->vram_size >> 20;
338 case PIPE_CAP_UMA:
339 return 0;
340 }
341
342 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
343 return 0;
344 }
345
346 static int
347 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
348 enum pipe_shader_type shader,
349 enum pipe_shader_cap param)
350 {
351 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
352
353 switch (shader) {
354 case PIPE_SHADER_VERTEX:
355 case PIPE_SHADER_GEOMETRY:
356 case PIPE_SHADER_FRAGMENT:
357 case PIPE_SHADER_COMPUTE:
358 case PIPE_SHADER_TESS_CTRL:
359 case PIPE_SHADER_TESS_EVAL:
360 break;
361 default:
362 return 0;
363 }
364
365 switch (param) {
366 case PIPE_SHADER_CAP_PREFERRED_IR:
367 return PIPE_SHADER_IR_TGSI;
368 case PIPE_SHADER_CAP_SUPPORTED_IRS:
369 return 1 << PIPE_SHADER_IR_TGSI;
370 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
371 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
372 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
373 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
374 return 16384;
375 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
376 return 16;
377 case PIPE_SHADER_CAP_MAX_INPUTS:
378 if (shader == PIPE_SHADER_VERTEX)
379 return 32;
380 /* NOTE: These only count our slots for GENERIC varyings.
381 * The address space may be larger, but the actual hard limit seems to be
382 * less than what the address space layout permits, so don't add TEXCOORD,
383 * COLOR, etc. here.
384 */
385 if (shader == PIPE_SHADER_FRAGMENT)
386 return 0x1f0 / 16;
387 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
388 * and excludes 0x60 per-patch inputs.
389 */
390 return 0x200 / 16;
391 case PIPE_SHADER_CAP_MAX_OUTPUTS:
392 return 32;
393 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
394 return 65536;
395 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
396 return NVC0_MAX_PIPE_CONSTBUFS;
397 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
398 return shader != PIPE_SHADER_FRAGMENT;
399 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
400 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
401 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
402 return 1;
403 case PIPE_SHADER_CAP_MAX_TEMPS:
404 return NVC0_CAP_MAX_PROGRAM_TEMPS;
405 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
406 return 1;
407 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
408 return 1;
409 case PIPE_SHADER_CAP_SUBROUTINES:
410 return 1;
411 case PIPE_SHADER_CAP_INTEGERS:
412 return 1;
413 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
414 return 1;
415 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
416 return 1;
417 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
418 return 1;
419 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
420 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
421 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
422 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
423 case PIPE_SHADER_CAP_INT64_ATOMICS:
424 case PIPE_SHADER_CAP_FP16:
425 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
426 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
427 return 0;
428 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
429 return NVC0_MAX_BUFFERS;
430 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
431 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
432 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
433 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
434 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
435 return 32;
436 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
437 if (class_3d >= NVE4_3D_CLASS)
438 return NVC0_MAX_IMAGES;
439 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
440 return NVC0_MAX_IMAGES;
441 return 0;
442 default:
443 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
444 return 0;
445 }
446 }
447
448 static float
449 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
450 {
451 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
452
453 switch (param) {
454 case PIPE_CAPF_MAX_LINE_WIDTH:
455 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
456 return 10.0f;
457 case PIPE_CAPF_MAX_POINT_WIDTH:
458 return 63.0f;
459 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
460 return 63.375f;
461 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
462 return 16.0f;
463 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
464 return 15.0f;
465 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
466 return 0.0f;
467 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
468 return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
469 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
470 return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
471 }
472
473 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
474 return 0.0f;
475 }
476
477 static int
478 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
479 enum pipe_shader_ir ir_type,
480 enum pipe_compute_cap param, void *data)
481 {
482 struct nvc0_screen *screen = nvc0_screen(pscreen);
483 const uint16_t obj_class = screen->compute->oclass;
484
485 #define RET(x) do { \
486 if (data) \
487 memcpy(data, x, sizeof(x)); \
488 return sizeof(x); \
489 } while (0)
490
491 switch (param) {
492 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
493 RET((uint64_t []) { 3 });
494 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
495 if (obj_class >= NVE4_COMPUTE_CLASS) {
496 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
497 } else {
498 RET(((uint64_t []) { 65535, 65535, 65535 }));
499 }
500 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
501 RET(((uint64_t []) { 1024, 1024, 64 }));
502 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
503 RET((uint64_t []) { 1024 });
504 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
505 if (obj_class >= NVE4_COMPUTE_CLASS) {
506 RET((uint64_t []) { 1024 });
507 } else {
508 RET((uint64_t []) { 512 });
509 }
510 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
511 RET((uint64_t []) { 1ULL << 40 });
512 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
513 switch (obj_class) {
514 case GM200_COMPUTE_CLASS:
515 RET((uint64_t []) { 96 << 10 });
516 break;
517 case GM107_COMPUTE_CLASS:
518 RET((uint64_t []) { 64 << 10 });
519 break;
520 default:
521 RET((uint64_t []) { 48 << 10 });
522 break;
523 }
524 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
525 RET((uint64_t []) { 512 << 10 });
526 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
527 RET((uint64_t []) { 4096 });
528 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
529 RET((uint32_t []) { 32 });
530 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
531 RET((uint64_t []) { 1ULL << 40 });
532 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
533 RET((uint32_t []) { 0 });
534 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
535 RET((uint32_t []) { screen->mp_count_compute });
536 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
537 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
538 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
539 RET((uint32_t []) { 64 });
540 default:
541 return 0;
542 }
543
544 #undef RET
545 }
546
547 static void
548 nvc0_screen_destroy(struct pipe_screen *pscreen)
549 {
550 struct nvc0_screen *screen = nvc0_screen(pscreen);
551
552 if (!nouveau_drm_screen_unref(&screen->base))
553 return;
554
555 if (screen->base.fence.current) {
556 struct nouveau_fence *current = NULL;
557
558 /* nouveau_fence_wait will create a new current fence, so wait on the
559 * _current_ one, and remove both.
560 */
561 nouveau_fence_ref(screen->base.fence.current, &current);
562 nouveau_fence_wait(current, NULL);
563 nouveau_fence_ref(NULL, &current);
564 nouveau_fence_ref(NULL, &screen->base.fence.current);
565 }
566 if (screen->base.pushbuf)
567 screen->base.pushbuf->user_priv = NULL;
568
569 if (screen->blitter)
570 nvc0_blitter_destroy(screen);
571 if (screen->pm.prog) {
572 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
573 nvc0_program_destroy(NULL, screen->pm.prog);
574 FREE(screen->pm.prog);
575 }
576
577 nouveau_bo_ref(NULL, &screen->text);
578 nouveau_bo_ref(NULL, &screen->uniform_bo);
579 nouveau_bo_ref(NULL, &screen->tls);
580 nouveau_bo_ref(NULL, &screen->txc);
581 nouveau_bo_ref(NULL, &screen->fence.bo);
582 nouveau_bo_ref(NULL, &screen->poly_cache);
583
584 nouveau_heap_destroy(&screen->lib_code);
585 nouveau_heap_destroy(&screen->text_heap);
586
587 FREE(screen->default_tsc);
588 FREE(screen->tic.entries);
589
590 nouveau_object_del(&screen->eng3d);
591 nouveau_object_del(&screen->eng2d);
592 nouveau_object_del(&screen->m2mf);
593 nouveau_object_del(&screen->compute);
594 nouveau_object_del(&screen->nvsw);
595
596 nouveau_screen_fini(&screen->base);
597
598 FREE(screen);
599 }
600
601 static int
602 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
603 unsigned size, const uint32_t *data)
604 {
605 struct nouveau_pushbuf *push = screen->base.pushbuf;
606
607 size /= 4;
608
609 assert((pos + size) <= 0x800);
610
611 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
612 PUSH_DATA (push, (m - 0x3800) / 8);
613 PUSH_DATA (push, pos);
614 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
615 PUSH_DATA (push, pos);
616 PUSH_DATAp(push, data, size);
617
618 return pos + size;
619 }
620
621 static void
622 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
623 {
624 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
625 PUSH_DATA (push, 0xff);
626 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
627 PUSH_DATA (push, 0xff);
628 PUSH_DATA (push, 0xff);
629 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
630 PUSH_DATA (push, 0xff);
631 PUSH_DATA (push, 0xff);
632 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
633 PUSH_DATA (push, 0x3f);
634
635 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
636 PUSH_DATA (push, (3 << 16) | 3);
637 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
638 PUSH_DATA (push, (2 << 16) | 2);
639
640 if (obj_class < GM107_3D_CLASS) {
641 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
642 PUSH_DATA (push, 0);
643 }
644 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
645 PUSH_DATA (push, 0x10);
646 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
647 PUSH_DATA (push, 0x10);
648 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
649 PUSH_DATA (push, 0x10);
650 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
651 PUSH_DATA (push, 0x10);
652 PUSH_DATA (push, 0x10);
653 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
654 PUSH_DATA (push, 0x10);
655 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
656 PUSH_DATA (push, 0xe);
657
658 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
659 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
660 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
661 PUSH_DATA (push, 0);
662 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
663 PUSH_DATA (push, 3);
664
665 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
666 PUSH_DATA (push, 0x3fffff);
667 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
668 PUSH_DATA (push, 1);
669 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
670 PUSH_DATA (push, 1);
671
672 if (obj_class < GM107_3D_CLASS) {
673 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
674 PUSH_DATA (push, 3);
675
676 if (obj_class >= NVE4_3D_CLASS) {
677 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
678 PUSH_DATA (push, 1);
679 }
680 }
681
682 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
683 * are supposed to do */
684 }
685
686 static void
687 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
688 {
689 struct nvc0_screen *screen = nvc0_screen(pscreen);
690 struct nouveau_pushbuf *push = screen->base.pushbuf;
691
692 /* we need to do it after possible flush in MARK_RING */
693 *sequence = ++screen->base.fence.sequence;
694
695 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
696 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
697 PUSH_DATAh(push, screen->fence.bo->offset);
698 PUSH_DATA (push, screen->fence.bo->offset);
699 PUSH_DATA (push, *sequence);
700 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
701 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
702 }
703
704 static u32
705 nvc0_screen_fence_update(struct pipe_screen *pscreen)
706 {
707 struct nvc0_screen *screen = nvc0_screen(pscreen);
708 return screen->fence.map[0];
709 }
710
711 static int
712 nvc0_screen_init_compute(struct nvc0_screen *screen)
713 {
714 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
715
716 switch (screen->base.device->chipset & ~0xf) {
717 case 0xc0:
718 case 0xd0:
719 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
720 case 0xe0:
721 case 0xf0:
722 case 0x100:
723 case 0x110:
724 case 0x120:
725 case 0x130:
726 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
727 default:
728 return -1;
729 }
730 }
731
732 static int
733 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
734 uint32_t lpos, uint32_t lneg, uint32_t cstack)
735 {
736 struct nouveau_bo *bo = NULL;
737 int ret;
738 uint64_t size = (lpos + lneg) * 32 + cstack;
739
740 if (size >= (1 << 20)) {
741 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
742 return -1;
743 }
744
745 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
746 size = align(size, 0x8000);
747 size *= screen->mp_count;
748
749 size = align(size, 1 << 17);
750
751 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
752 NULL, &bo);
753 if (ret)
754 return ret;
755
756 /* Make sure that the pushbuf has acquired a reference to the old tls
757 * segment, as it may have commands that will reference it.
758 */
759 if (screen->tls)
760 PUSH_REFN(screen->base.pushbuf, screen->tls,
761 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
762 nouveau_bo_ref(NULL, &screen->tls);
763 screen->tls = bo;
764 return 0;
765 }
766
767 int
768 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
769 {
770 struct nouveau_pushbuf *push = screen->base.pushbuf;
771 struct nouveau_bo *bo;
772 int ret;
773
774 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
775 1 << 17, size, NULL, &bo);
776 if (ret)
777 return ret;
778
779 /* Make sure that the pushbuf has acquired a reference to the old text
780 * segment, as it may have commands that will reference it.
781 */
782 if (screen->text)
783 PUSH_REFN(push, screen->text,
784 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
785 nouveau_bo_ref(NULL, &screen->text);
786 screen->text = bo;
787
788 nouveau_heap_destroy(&screen->lib_code);
789 nouveau_heap_destroy(&screen->text_heap);
790
791 /* XXX: getting a page fault at the end of the code buffer every few
792 * launches, don't use the last 256 bytes to work around them - prefetch ?
793 */
794 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
795
796 /* update the code segment setup */
797 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
798 PUSH_DATAh(push, screen->text->offset);
799 PUSH_DATA (push, screen->text->offset);
800 if (screen->compute) {
801 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
802 PUSH_DATAh(push, screen->text->offset);
803 PUSH_DATA (push, screen->text->offset);
804 }
805
806 return 0;
807 }
808
809 #define FAIL_SCREEN_INIT(str, err) \
810 do { \
811 NOUVEAU_ERR(str, err); \
812 goto fail; \
813 } while(0)
814
815 struct nouveau_screen *
816 nvc0_screen_create(struct nouveau_device *dev)
817 {
818 struct nvc0_screen *screen;
819 struct pipe_screen *pscreen;
820 struct nouveau_object *chan;
821 struct nouveau_pushbuf *push;
822 uint64_t value;
823 uint32_t obj_class;
824 uint32_t flags;
825 int ret;
826 unsigned i;
827
828 switch (dev->chipset & ~0xf) {
829 case 0xc0:
830 case 0xd0:
831 case 0xe0:
832 case 0xf0:
833 case 0x100:
834 case 0x110:
835 case 0x120:
836 case 0x130:
837 break;
838 default:
839 return NULL;
840 }
841
842 screen = CALLOC_STRUCT(nvc0_screen);
843 if (!screen)
844 return NULL;
845 pscreen = &screen->base.base;
846 pscreen->destroy = nvc0_screen_destroy;
847
848 ret = nouveau_screen_init(&screen->base, dev);
849 if (ret)
850 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
851 chan = screen->base.channel;
852 push = screen->base.pushbuf;
853 push->user_priv = screen;
854 push->rsvd_kick = 5;
855
856 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
857 PIPE_BIND_SHADER_BUFFER |
858 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
859 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
860 screen->base.sysmem_bindings |=
861 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
862
863 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
864 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
865 screen->base.vidmem_bindings = 0;
866 }
867
868 pscreen->context_create = nvc0_create;
869 pscreen->is_format_supported = nvc0_screen_is_format_supported;
870 pscreen->get_param = nvc0_screen_get_param;
871 pscreen->get_shader_param = nvc0_screen_get_shader_param;
872 pscreen->get_paramf = nvc0_screen_get_paramf;
873 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
874 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
875
876 nvc0_screen_init_resource_functions(pscreen);
877
878 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
879 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
880
881 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
882 if (screen->base.drm->version >= 0x01000202)
883 flags |= NOUVEAU_BO_COHERENT;
884
885 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
886 if (ret)
887 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
888 nouveau_bo_map(screen->fence.bo, 0, NULL);
889 screen->fence.map = screen->fence.bo->map;
890 screen->base.fence.emit = nvc0_screen_fence_emit;
891 screen->base.fence.update = nvc0_screen_fence_update;
892
893
894 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
895 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
896 if (ret)
897 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
898
899 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
900 PUSH_DATA (push, screen->nvsw->handle);
901
902 switch (dev->chipset & ~0xf) {
903 case 0x130:
904 case 0x120:
905 case 0x110:
906 case 0x100:
907 case 0xf0:
908 obj_class = NVF0_P2MF_CLASS;
909 break;
910 case 0xe0:
911 obj_class = NVE4_P2MF_CLASS;
912 break;
913 default:
914 obj_class = NVC0_M2MF_CLASS;
915 break;
916 }
917 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
918 &screen->m2mf);
919 if (ret)
920 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
921
922 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
923 PUSH_DATA (push, screen->m2mf->oclass);
924 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
925 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
926 PUSH_DATA (push, 0xa0b5);
927 }
928
929 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
930 &screen->eng2d);
931 if (ret)
932 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
933
934 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
935 PUSH_DATA (push, screen->eng2d->oclass);
936 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
937 PUSH_DATA (push, 0);
938 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
939 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
940 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
941 PUSH_DATA (push, 0);
942 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
943 PUSH_DATA (push, 0);
944 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
945 PUSH_DATA (push, 0x3f);
946 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
947 PUSH_DATA (push, 1);
948 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
949 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
950
951 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
952 PUSH_DATAh(push, screen->fence.bo->offset + 16);
953 PUSH_DATA (push, screen->fence.bo->offset + 16);
954
955 switch (dev->chipset & ~0xf) {
956 case 0x130:
957 switch (dev->chipset) {
958 case 0x130:
959 case 0x13b:
960 obj_class = GP100_3D_CLASS;
961 break;
962 default:
963 obj_class = GP102_3D_CLASS;
964 break;
965 }
966 break;
967 case 0x120:
968 obj_class = GM200_3D_CLASS;
969 break;
970 case 0x110:
971 obj_class = GM107_3D_CLASS;
972 break;
973 case 0x100:
974 case 0xf0:
975 obj_class = NVF0_3D_CLASS;
976 break;
977 case 0xe0:
978 switch (dev->chipset) {
979 case 0xea:
980 obj_class = NVEA_3D_CLASS;
981 break;
982 default:
983 obj_class = NVE4_3D_CLASS;
984 break;
985 }
986 break;
987 case 0xd0:
988 obj_class = NVC8_3D_CLASS;
989 break;
990 case 0xc0:
991 default:
992 switch (dev->chipset) {
993 case 0xc8:
994 obj_class = NVC8_3D_CLASS;
995 break;
996 case 0xc1:
997 obj_class = NVC1_3D_CLASS;
998 break;
999 default:
1000 obj_class = NVC0_3D_CLASS;
1001 break;
1002 }
1003 break;
1004 }
1005 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1006 &screen->eng3d);
1007 if (ret)
1008 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1009 screen->base.class_3d = obj_class;
1010
1011 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1012 PUSH_DATA (push, screen->eng3d->oclass);
1013
1014 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1015 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1016
1017 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1018 /* kill shaders after about 1 second (at 100 MHz) */
1019 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1020 PUSH_DATA (push, 0x17);
1021 }
1022
1023 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1024 screen->base.drm->version >= 0x01000101);
1025 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1026 for (i = 0; i < 8; ++i)
1027 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1028
1029 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1030 PUSH_DATA (push, 1);
1031
1032 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1033 PUSH_DATA (push, 0);
1034 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1035 PUSH_DATA (push, 0);
1036 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1037 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1038 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1039 PUSH_DATA (push, 0);
1040 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1041 PUSH_DATA (push, 1);
1042 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1043 PUSH_DATA (push, 1);
1044 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1045 PUSH_DATA (push, 1);
1046 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1047 PUSH_DATA (push, 0);
1048 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1049 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1050 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1051 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1052 } else {
1053 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1054 PUSH_DATA (push, 15);
1055 }
1056 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1057 PUSH_DATA (push, 8); /* 128 */
1058 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1059 PUSH_DATA (push, 1);
1060 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1061 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1062 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1063 }
1064
1065 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1066
1067 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1068 if (ret)
1069 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1070
1071 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1072 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1073 &screen->uniform_bo);
1074 if (ret)
1075 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1076
1077 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1078
1079 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1080 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1081 PUSH_DATA (push, 256);
1082 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1083 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1084 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1085 PUSH_DATA (push, 0);
1086 PUSH_DATAf(push, 0.0f);
1087 PUSH_DATAf(push, 0.0f);
1088 PUSH_DATAf(push, 0.0f);
1089 PUSH_DATAf(push, 0.0f);
1090 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1091 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1092 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1093
1094 if (screen->base.drm->version >= 0x01000101) {
1095 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1096 if (ret)
1097 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1098 } else {
1099 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1100 value = (8 << 8) | 4;
1101 else
1102 value = (16 << 8) | 4;
1103 }
1104 screen->gpc_count = value & 0x000000ff;
1105 screen->mp_count = value >> 8;
1106 screen->mp_count_compute = screen->mp_count;
1107
1108 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1109 if (ret)
1110 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1111
1112 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1113 PUSH_DATAh(push, screen->tls->offset);
1114 PUSH_DATA (push, screen->tls->offset);
1115 PUSH_DATA (push, screen->tls->size >> 32);
1116 PUSH_DATA (push, screen->tls->size);
1117 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1118 PUSH_DATA (push, 0);
1119 /* Reduce likelihood of collision with real buffers by placing the hole at
1120 * the top of the 4G area. This will have to be dealt with for real
1121 * eventually by blocking off that area from the VM.
1122 */
1123 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1124 PUSH_DATA (push, 0xff << 24);
1125
1126 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1127 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1128 &screen->poly_cache);
1129 if (ret)
1130 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1131
1132 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1133 PUSH_DATAh(push, screen->poly_cache->offset);
1134 PUSH_DATA (push, screen->poly_cache->offset);
1135 PUSH_DATA (push, 3);
1136 }
1137
1138 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1139 &screen->txc);
1140 if (ret)
1141 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1142
1143 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1144 PUSH_DATAh(push, screen->txc->offset);
1145 PUSH_DATA (push, screen->txc->offset);
1146 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1147 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1148 screen->tic.maxwell = true;
1149 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1150 screen->tic.maxwell =
1151 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1152 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1153 }
1154 }
1155
1156 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1157 PUSH_DATAh(push, screen->txc->offset + 65536);
1158 PUSH_DATA (push, screen->txc->offset + 65536);
1159 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1160
1161 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1162 PUSH_DATA (push, 0);
1163 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1164 PUSH_DATA (push, 0);
1165 PUSH_DATA (push, 0);
1166 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1167 PUSH_DATA (push, 0x3f);
1168
1169 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1170 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1171 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1172 for (i = 0; i < 8 * 2; ++i)
1173 PUSH_DATA(push, 0);
1174 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1175 PUSH_DATA (push, 0);
1176 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1177 PUSH_DATA (push, 0);
1178
1179 /* neither scissors, viewport nor stencil mask should affect clears */
1180 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1181 PUSH_DATA (push, 0);
1182
1183 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1184 PUSH_DATA (push, 1);
1185 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1186 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1187 PUSH_DATAf(push, 0.0f);
1188 PUSH_DATAf(push, 1.0f);
1189 }
1190 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1191 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1192
1193 /* We use scissors instead of exact view volume clipping,
1194 * so they're always enabled.
1195 */
1196 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1197 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1198 PUSH_DATA (push, 1);
1199 PUSH_DATA (push, 8192 << 16);
1200 PUSH_DATA (push, 8192 << 16);
1201 }
1202
1203 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1204
1205 i = 0;
1206 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1207 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1208 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1209 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1210 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1211 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1212 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1213 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1214 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1215 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1216 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1217 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1218 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1219 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1220
1221 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1222 PUSH_DATA (push, 1);
1223 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1224 PUSH_DATA (push, 1);
1225 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1226 PUSH_DATA (push, 0x40);
1227 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1228 PUSH_DATA (push, 0);
1229 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1230 PUSH_DATA (push, 0x30);
1231 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1232 PUSH_DATA (push, 3);
1233 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1234 PUSH_DATA (push, 0x20);
1235 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1236 PUSH_DATA (push, 0x00);
1237 screen->save_state.patch_vertices = 3;
1238
1239 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1240 PUSH_DATA (push, 0);
1241 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1242 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1243
1244 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1245
1246 if (nvc0_screen_init_compute(screen))
1247 goto fail;
1248
1249 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1250 for (i = 0; i < 5; ++i) {
1251 /* TIC and TSC entries for each unit (nve4+ only) */
1252 /* auxiliary constants (6 user clip planes, base instance id) */
1253 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1254 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1255 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1256 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1257 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1258 PUSH_DATA (push, (15 << 4) | 1);
1259 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1260 unsigned j;
1261 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1262 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1263 for (j = 0; j < 8; ++j)
1264 PUSH_DATA(push, j);
1265 } else {
1266 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1267 PUSH_DATA (push, 0x54);
1268 }
1269
1270 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1271 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1272 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1273 PUSH_DATA (push, 0); /* 0 */
1274 PUSH_DATA (push, 0);
1275 PUSH_DATA (push, 1); /* 1 */
1276 PUSH_DATA (push, 0);
1277 PUSH_DATA (push, 0); /* 2 */
1278 PUSH_DATA (push, 1);
1279 PUSH_DATA (push, 1); /* 3 */
1280 PUSH_DATA (push, 1);
1281 PUSH_DATA (push, 2); /* 4 */
1282 PUSH_DATA (push, 0);
1283 PUSH_DATA (push, 3); /* 5 */
1284 PUSH_DATA (push, 0);
1285 PUSH_DATA (push, 2); /* 6 */
1286 PUSH_DATA (push, 1);
1287 PUSH_DATA (push, 3); /* 7 */
1288 PUSH_DATA (push, 1);
1289 }
1290 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1291 PUSH_DATA (push, 0);
1292
1293 PUSH_KICK (push);
1294
1295 screen->tic.entries = CALLOC(
1296 NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1297 sizeof(void *));
1298 screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1299 screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1300
1301 if (!nvc0_blitter_create(screen))
1302 goto fail;
1303
1304 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1305 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1306
1307 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1308
1309 return &screen->base;
1310
1311 fail:
1312 screen->base.base.context_create = NULL;
1313 return &screen->base;
1314 }
1315
1316 int
1317 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1318 {
1319 int i = screen->tic.next;
1320
1321 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1322 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1323
1324 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1325
1326 if (screen->tic.entries[i])
1327 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1328
1329 screen->tic.entries[i] = entry;
1330 return i;
1331 }
1332
1333 int
1334 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1335 {
1336 int i = screen->tsc.next;
1337
1338 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1339 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1340
1341 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1342
1343 if (screen->tsc.entries[i])
1344 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1345
1346 screen->tsc.entries[i] = entry;
1347 return i;
1348 }