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gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 #include "nv50/g80_texture.xml.h"
42
43 static boolean
44 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
45 enum pipe_format format,
46 enum pipe_texture_target target,
47 unsigned sample_count,
48 unsigned bindings)
49 {
50 const struct util_format_description *desc = util_format_description(format);
51
52 if (sample_count > 8)
53 return false;
54 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
55 return false;
56
57 /* Short-circuit the rest of the logic -- this is used by the state tracker
58 * to determine valid MS levels in a no-attachments scenario.
59 */
60 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
61 return true;
62
63 if (!util_format_is_supported(format, bindings))
64 return false;
65
66 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
67 if (util_format_get_blocksizebits(format) == 3 * 32)
68 return false;
69
70 if (bindings & PIPE_BIND_LINEAR)
71 if (util_format_is_depth_or_stencil(format) ||
72 (target != PIPE_TEXTURE_1D &&
73 target != PIPE_TEXTURE_2D &&
74 target != PIPE_TEXTURE_RECT) ||
75 sample_count > 1)
76 return false;
77
78 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
79 */
80 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
81 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
82 /* The claim is that this should work on GM107 but it doesn't. Need to
83 * test further and figure out if it's a nouveau issue or a HW one.
84 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
85 */
86 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
87 return false;
88
89 /* shared is always supported */
90 bindings &= ~(PIPE_BIND_LINEAR |
91 PIPE_BIND_SHARED);
92
93 if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
94 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
95 /* MS images are currently unsupported on Maxwell because they have to
96 * be handled explicitly. */
97 return false;
98 }
99
100 return (( nvc0_format_table[format].usage |
101 nvc0_vertex_format[format].usage) & bindings) == bindings;
102 }
103
104 static int
105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
106 {
107 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
108 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
109
110 switch (param) {
111 /* non-boolean caps */
112 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
113 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
114 return 15;
115 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
116 return 12;
117 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
118 return 2048;
119 case PIPE_CAP_MIN_TEXEL_OFFSET:
120 return -8;
121 case PIPE_CAP_MAX_TEXEL_OFFSET:
122 return 7;
123 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
124 return -32;
125 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
126 return 31;
127 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
128 return 128 * 1024 * 1024;
129 case PIPE_CAP_GLSL_FEATURE_LEVEL:
130 return 430;
131 case PIPE_CAP_MAX_RENDER_TARGETS:
132 return 8;
133 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
134 return 1;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
136 return 4;
137 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
138 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
139 return 128;
140 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
141 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
142 return 1024;
143 case PIPE_CAP_MAX_VERTEX_STREAMS:
144 return 4;
145 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
146 return 2048;
147 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
148 return 256;
149 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
150 if (class_3d < GM107_3D_CLASS)
151 return 256; /* IMAGE bindings require alignment to 256 */
152 return 16;
153 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
154 return 16;
155 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
156 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
157 case PIPE_CAP_MAX_VIEWPORTS:
158 return NVC0_MAX_VIEWPORTS;
159 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
160 return 4;
161 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
162 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
163 case PIPE_CAP_ENDIANNESS:
164 return PIPE_ENDIAN_LITTLE;
165 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
166 return 30;
167 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
168 return NVC0_MAX_WINDOW_RECTANGLES;
169
170 /* supported caps */
171 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
172 case PIPE_CAP_TEXTURE_SWIZZLE:
173 case PIPE_CAP_TEXTURE_SHADOW_MAP:
174 case PIPE_CAP_NPOT_TEXTURES:
175 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
176 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
177 case PIPE_CAP_ANISOTROPIC_FILTER:
178 case PIPE_CAP_SEAMLESS_CUBE_MAP:
179 case PIPE_CAP_CUBE_MAP_ARRAY:
180 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
181 case PIPE_CAP_TEXTURE_MULTISAMPLE:
182 case PIPE_CAP_TWO_SIDED_STENCIL:
183 case PIPE_CAP_DEPTH_CLIP_DISABLE:
184 case PIPE_CAP_POINT_SPRITE:
185 case PIPE_CAP_TGSI_TEXCOORD:
186 case PIPE_CAP_SM3:
187 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
188 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
189 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
190 case PIPE_CAP_QUERY_TIMESTAMP:
191 case PIPE_CAP_QUERY_TIME_ELAPSED:
192 case PIPE_CAP_OCCLUSION_QUERY:
193 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
194 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
195 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
196 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
197 case PIPE_CAP_INDEP_BLEND_ENABLE:
198 case PIPE_CAP_INDEP_BLEND_FUNC:
199 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
200 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
201 case PIPE_CAP_PRIMITIVE_RESTART:
202 case PIPE_CAP_TGSI_INSTANCEID:
203 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
204 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
205 case PIPE_CAP_CONDITIONAL_RENDER:
206 case PIPE_CAP_TEXTURE_BARRIER:
207 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
208 case PIPE_CAP_START_INSTANCE:
209 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
210 case PIPE_CAP_DRAW_INDIRECT:
211 case PIPE_CAP_USER_CONSTANT_BUFFERS:
212 case PIPE_CAP_USER_VERTEX_BUFFERS:
213 case PIPE_CAP_TEXTURE_QUERY_LOD:
214 case PIPE_CAP_SAMPLE_SHADING:
215 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
216 case PIPE_CAP_TEXTURE_GATHER_SM5:
217 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
218 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
219 case PIPE_CAP_SAMPLER_VIEW_TARGET:
220 case PIPE_CAP_CLIP_HALFZ:
221 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
222 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
223 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
224 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
225 case PIPE_CAP_DEPTH_BOUNDS_TEST:
226 case PIPE_CAP_TGSI_TXQS:
227 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
228 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
229 case PIPE_CAP_SHAREABLE_SHADERS:
230 case PIPE_CAP_CLEAR_TEXTURE:
231 case PIPE_CAP_DRAW_PARAMETERS:
232 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
233 case PIPE_CAP_MULTI_DRAW_INDIRECT:
234 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
235 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
236 case PIPE_CAP_QUERY_BUFFER_OBJECT:
237 case PIPE_CAP_INVALIDATE_BUFFER:
238 case PIPE_CAP_STRING_MARKER:
239 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
240 case PIPE_CAP_CULL_DISTANCE:
241 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
242 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
243 case PIPE_CAP_TGSI_VOTE:
244 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
245 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
246 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
247 case PIPE_CAP_DOUBLES:
248 case PIPE_CAP_INT64:
249 case PIPE_CAP_TGSI_TEX_TXF_LZ:
250 case PIPE_CAP_TGSI_CLOCK:
251 return 1;
252 case PIPE_CAP_COMPUTE:
253 return (class_3d < GP100_3D_CLASS);
254 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
255 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
256 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
257 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
258 case PIPE_CAP_TGSI_FS_FBFETCH:
259 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
260 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
261 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
262 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
263 return class_3d >= GM200_3D_CLASS;
264 case PIPE_CAP_TGSI_BALLOT:
265 return class_3d >= NVE4_3D_CLASS;
266
267 /* unsupported caps */
268 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
269 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
270 case PIPE_CAP_SHADER_STENCIL_EXPORT:
271 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
272 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
273 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
274 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
275 case PIPE_CAP_FAKE_SW_MSAA:
276 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
277 case PIPE_CAP_VERTEXID_NOBASE:
278 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
279 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
280 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
281 case PIPE_CAP_GENERATE_MIPMAP:
282 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
283 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
284 case PIPE_CAP_QUERY_MEMORY_INFO:
285 case PIPE_CAP_PCI_GROUP:
286 case PIPE_CAP_PCI_BUS:
287 case PIPE_CAP_PCI_DEVICE:
288 case PIPE_CAP_PCI_FUNCTION:
289 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
290 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
291 case PIPE_CAP_NATIVE_FENCE_FD:
292 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
293 case PIPE_CAP_INT64_DIVMOD:
294 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
295 return 0;
296
297 case PIPE_CAP_VENDOR_ID:
298 return 0x10de;
299 case PIPE_CAP_DEVICE_ID: {
300 uint64_t device_id;
301 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
302 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
303 return -1;
304 }
305 return device_id;
306 }
307 case PIPE_CAP_ACCELERATED:
308 return 1;
309 case PIPE_CAP_VIDEO_MEMORY:
310 return dev->vram_size >> 20;
311 case PIPE_CAP_UMA:
312 return 0;
313 }
314
315 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
316 return 0;
317 }
318
319 static int
320 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
321 enum pipe_shader_type shader,
322 enum pipe_shader_cap param)
323 {
324 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
325
326 switch (shader) {
327 case PIPE_SHADER_VERTEX:
328 case PIPE_SHADER_GEOMETRY:
329 case PIPE_SHADER_FRAGMENT:
330 case PIPE_SHADER_COMPUTE:
331 case PIPE_SHADER_TESS_CTRL:
332 case PIPE_SHADER_TESS_EVAL:
333 break;
334 default:
335 return 0;
336 }
337
338 switch (param) {
339 case PIPE_SHADER_CAP_PREFERRED_IR:
340 return PIPE_SHADER_IR_TGSI;
341 case PIPE_SHADER_CAP_SUPPORTED_IRS:
342 return 1 << PIPE_SHADER_IR_TGSI;
343 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
344 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
345 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
346 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
347 return 16384;
348 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
349 return 16;
350 case PIPE_SHADER_CAP_MAX_INPUTS:
351 if (shader == PIPE_SHADER_VERTEX)
352 return 32;
353 /* NOTE: These only count our slots for GENERIC varyings.
354 * The address space may be larger, but the actual hard limit seems to be
355 * less than what the address space layout permits, so don't add TEXCOORD,
356 * COLOR, etc. here.
357 */
358 if (shader == PIPE_SHADER_FRAGMENT)
359 return 0x1f0 / 16;
360 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
361 * and excludes 0x60 per-patch inputs.
362 */
363 return 0x200 / 16;
364 case PIPE_SHADER_CAP_MAX_OUTPUTS:
365 return 32;
366 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
367 return 65536;
368 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
369 return NVC0_MAX_PIPE_CONSTBUFS;
370 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
371 return shader != PIPE_SHADER_FRAGMENT;
372 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
373 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
374 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
375 return 1;
376 case PIPE_SHADER_CAP_MAX_TEMPS:
377 return NVC0_CAP_MAX_PROGRAM_TEMPS;
378 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
379 return 1;
380 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
381 return 1;
382 case PIPE_SHADER_CAP_SUBROUTINES:
383 return 1;
384 case PIPE_SHADER_CAP_INTEGERS:
385 return 1;
386 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
387 return 1;
388 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
389 return 1;
390 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
391 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
392 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
393 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
394 return 0;
395 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
396 return NVC0_MAX_BUFFERS;
397 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
398 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
399 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
400 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
401 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
402 return 32;
403 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
404 if (class_3d >= NVE4_3D_CLASS)
405 return NVC0_MAX_IMAGES;
406 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
407 return NVC0_MAX_IMAGES;
408 return 0;
409 default:
410 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
411 return 0;
412 }
413 }
414
415 static float
416 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
417 {
418 switch (param) {
419 case PIPE_CAPF_MAX_LINE_WIDTH:
420 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
421 return 10.0f;
422 case PIPE_CAPF_MAX_POINT_WIDTH:
423 return 63.0f;
424 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
425 return 63.375f;
426 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
427 return 16.0f;
428 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
429 return 15.0f;
430 case PIPE_CAPF_GUARD_BAND_LEFT:
431 case PIPE_CAPF_GUARD_BAND_TOP:
432 return 0.0f;
433 case PIPE_CAPF_GUARD_BAND_RIGHT:
434 case PIPE_CAPF_GUARD_BAND_BOTTOM:
435 return 0.0f; /* that or infinity */
436 }
437
438 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
439 return 0.0f;
440 }
441
442 static int
443 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
444 enum pipe_shader_ir ir_type,
445 enum pipe_compute_cap param, void *data)
446 {
447 struct nvc0_screen *screen = nvc0_screen(pscreen);
448 const uint16_t obj_class = screen->compute->oclass;
449
450 #define RET(x) do { \
451 if (data) \
452 memcpy(data, x, sizeof(x)); \
453 return sizeof(x); \
454 } while (0)
455
456 switch (param) {
457 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
458 RET((uint64_t []) { 3 });
459 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
460 if (obj_class >= NVE4_COMPUTE_CLASS) {
461 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
462 } else {
463 RET(((uint64_t []) { 65535, 65535, 65535 }));
464 }
465 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
466 RET(((uint64_t []) { 1024, 1024, 64 }));
467 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
468 RET((uint64_t []) { 1024 });
469 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
470 if (obj_class >= NVE4_COMPUTE_CLASS) {
471 RET((uint64_t []) { 1024 });
472 } else {
473 RET((uint64_t []) { 512 });
474 }
475 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
476 RET((uint64_t []) { 1ULL << 40 });
477 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
478 switch (obj_class) {
479 case GM200_COMPUTE_CLASS:
480 RET((uint64_t []) { 96 << 10 });
481 break;
482 case GM107_COMPUTE_CLASS:
483 RET((uint64_t []) { 64 << 10 });
484 break;
485 default:
486 RET((uint64_t []) { 48 << 10 });
487 break;
488 }
489 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
490 RET((uint64_t []) { 512 << 10 });
491 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
492 RET((uint64_t []) { 4096 });
493 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
494 RET((uint32_t []) { 32 });
495 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
496 RET((uint64_t []) { 1ULL << 40 });
497 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
498 RET((uint32_t []) { 0 });
499 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
500 RET((uint32_t []) { screen->mp_count_compute });
501 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
502 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
503 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
504 RET((uint32_t []) { 64 });
505 default:
506 return 0;
507 }
508
509 #undef RET
510 }
511
512 static void
513 nvc0_screen_destroy(struct pipe_screen *pscreen)
514 {
515 struct nvc0_screen *screen = nvc0_screen(pscreen);
516
517 if (!nouveau_drm_screen_unref(&screen->base))
518 return;
519
520 if (screen->base.fence.current) {
521 struct nouveau_fence *current = NULL;
522
523 /* nouveau_fence_wait will create a new current fence, so wait on the
524 * _current_ one, and remove both.
525 */
526 nouveau_fence_ref(screen->base.fence.current, &current);
527 nouveau_fence_wait(current, NULL);
528 nouveau_fence_ref(NULL, &current);
529 nouveau_fence_ref(NULL, &screen->base.fence.current);
530 }
531 if (screen->base.pushbuf)
532 screen->base.pushbuf->user_priv = NULL;
533
534 if (screen->blitter)
535 nvc0_blitter_destroy(screen);
536 if (screen->pm.prog) {
537 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
538 nvc0_program_destroy(NULL, screen->pm.prog);
539 FREE(screen->pm.prog);
540 }
541
542 nouveau_bo_ref(NULL, &screen->text);
543 nouveau_bo_ref(NULL, &screen->uniform_bo);
544 nouveau_bo_ref(NULL, &screen->tls);
545 nouveau_bo_ref(NULL, &screen->txc);
546 nouveau_bo_ref(NULL, &screen->fence.bo);
547 nouveau_bo_ref(NULL, &screen->poly_cache);
548
549 nouveau_heap_destroy(&screen->lib_code);
550 nouveau_heap_destroy(&screen->text_heap);
551
552 FREE(screen->default_tsc);
553 FREE(screen->tic.entries);
554
555 nouveau_object_del(&screen->eng3d);
556 nouveau_object_del(&screen->eng2d);
557 nouveau_object_del(&screen->m2mf);
558 nouveau_object_del(&screen->compute);
559 nouveau_object_del(&screen->nvsw);
560
561 nouveau_screen_fini(&screen->base);
562
563 FREE(screen);
564 }
565
566 static int
567 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
568 unsigned size, const uint32_t *data)
569 {
570 struct nouveau_pushbuf *push = screen->base.pushbuf;
571
572 size /= 4;
573
574 assert((pos + size) <= 0x800);
575
576 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
577 PUSH_DATA (push, (m - 0x3800) / 8);
578 PUSH_DATA (push, pos);
579 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
580 PUSH_DATA (push, pos);
581 PUSH_DATAp(push, data, size);
582
583 return pos + size;
584 }
585
586 static void
587 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
588 {
589 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
590 PUSH_DATA (push, 0xff);
591 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
592 PUSH_DATA (push, 0xff);
593 PUSH_DATA (push, 0xff);
594 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
595 PUSH_DATA (push, 0xff);
596 PUSH_DATA (push, 0xff);
597 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
598 PUSH_DATA (push, 0x3f);
599
600 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
601 PUSH_DATA (push, (3 << 16) | 3);
602 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
603 PUSH_DATA (push, (2 << 16) | 2);
604
605 if (obj_class < GM107_3D_CLASS) {
606 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
607 PUSH_DATA (push, 0);
608 }
609 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
610 PUSH_DATA (push, 0x10);
611 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
612 PUSH_DATA (push, 0x10);
613 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
614 PUSH_DATA (push, 0x10);
615 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
616 PUSH_DATA (push, 0x10);
617 PUSH_DATA (push, 0x10);
618 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
619 PUSH_DATA (push, 0x10);
620 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
621 PUSH_DATA (push, 0xe);
622
623 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
624 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
625 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
626 PUSH_DATA (push, 0);
627 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
628 PUSH_DATA (push, 3);
629
630 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
631 PUSH_DATA (push, 0x3fffff);
632 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
633 PUSH_DATA (push, 1);
634 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
635 PUSH_DATA (push, 1);
636
637 if (obj_class < GM107_3D_CLASS) {
638 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
639 PUSH_DATA (push, 3);
640
641 if (obj_class >= NVE4_3D_CLASS) {
642 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
643 PUSH_DATA (push, 1);
644 }
645 }
646
647 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
648 * are supposed to do */
649 }
650
651 static void
652 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
653 {
654 struct nvc0_screen *screen = nvc0_screen(pscreen);
655 struct nouveau_pushbuf *push = screen->base.pushbuf;
656
657 /* we need to do it after possible flush in MARK_RING */
658 *sequence = ++screen->base.fence.sequence;
659
660 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
661 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
662 PUSH_DATAh(push, screen->fence.bo->offset);
663 PUSH_DATA (push, screen->fence.bo->offset);
664 PUSH_DATA (push, *sequence);
665 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
666 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
667 }
668
669 static u32
670 nvc0_screen_fence_update(struct pipe_screen *pscreen)
671 {
672 struct nvc0_screen *screen = nvc0_screen(pscreen);
673 return screen->fence.map[0];
674 }
675
676 static int
677 nvc0_screen_init_compute(struct nvc0_screen *screen)
678 {
679 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
680
681 switch (screen->base.device->chipset & ~0xf) {
682 case 0xc0:
683 case 0xd0:
684 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
685 case 0xe0:
686 case 0xf0:
687 case 0x100:
688 case 0x110:
689 case 0x120:
690 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
691 case 0x130:
692 return 0;
693 default:
694 return -1;
695 }
696 }
697
698 static int
699 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
700 uint32_t lpos, uint32_t lneg, uint32_t cstack)
701 {
702 struct nouveau_bo *bo = NULL;
703 int ret;
704 uint64_t size = (lpos + lneg) * 32 + cstack;
705
706 if (size >= (1 << 20)) {
707 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
708 return -1;
709 }
710
711 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
712 size = align(size, 0x8000);
713 size *= screen->mp_count;
714
715 size = align(size, 1 << 17);
716
717 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
718 NULL, &bo);
719 if (ret)
720 return ret;
721 nouveau_bo_ref(NULL, &screen->tls);
722 screen->tls = bo;
723 return 0;
724 }
725
726 int
727 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
728 {
729 struct nouveau_pushbuf *push = screen->base.pushbuf;
730 struct nouveau_bo *bo;
731 int ret;
732
733 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
734 1 << 17, size, NULL, &bo);
735 if (ret)
736 return ret;
737
738 nouveau_bo_ref(NULL, &screen->text);
739 screen->text = bo;
740
741 nouveau_heap_destroy(&screen->lib_code);
742 nouveau_heap_destroy(&screen->text_heap);
743
744 /* XXX: getting a page fault at the end of the code buffer every few
745 * launches, don't use the last 256 bytes to work around them - prefetch ?
746 */
747 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
748
749 /* update the code segment setup */
750 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
751 PUSH_DATAh(push, screen->text->offset);
752 PUSH_DATA (push, screen->text->offset);
753 if (screen->compute) {
754 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
755 PUSH_DATAh(push, screen->text->offset);
756 PUSH_DATA (push, screen->text->offset);
757 }
758
759 return 0;
760 }
761
762 #define FAIL_SCREEN_INIT(str, err) \
763 do { \
764 NOUVEAU_ERR(str, err); \
765 goto fail; \
766 } while(0)
767
768 struct nouveau_screen *
769 nvc0_screen_create(struct nouveau_device *dev)
770 {
771 struct nvc0_screen *screen;
772 struct pipe_screen *pscreen;
773 struct nouveau_object *chan;
774 struct nouveau_pushbuf *push;
775 uint64_t value;
776 uint32_t obj_class;
777 uint32_t flags;
778 int ret;
779 unsigned i;
780
781 switch (dev->chipset & ~0xf) {
782 case 0xc0:
783 case 0xd0:
784 case 0xe0:
785 case 0xf0:
786 case 0x100:
787 case 0x110:
788 case 0x120:
789 case 0x130:
790 break;
791 default:
792 return NULL;
793 }
794
795 screen = CALLOC_STRUCT(nvc0_screen);
796 if (!screen)
797 return NULL;
798 pscreen = &screen->base.base;
799 pscreen->destroy = nvc0_screen_destroy;
800
801 ret = nouveau_screen_init(&screen->base, dev);
802 if (ret)
803 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
804 chan = screen->base.channel;
805 push = screen->base.pushbuf;
806 push->user_priv = screen;
807 push->rsvd_kick = 5;
808
809 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
810 PIPE_BIND_SHADER_BUFFER |
811 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
812 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
813 screen->base.sysmem_bindings |=
814 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
815
816 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
817 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
818 screen->base.vidmem_bindings = 0;
819 }
820
821 pscreen->context_create = nvc0_create;
822 pscreen->is_format_supported = nvc0_screen_is_format_supported;
823 pscreen->get_param = nvc0_screen_get_param;
824 pscreen->get_shader_param = nvc0_screen_get_shader_param;
825 pscreen->get_paramf = nvc0_screen_get_paramf;
826 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
827 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
828
829 nvc0_screen_init_resource_functions(pscreen);
830
831 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
832 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
833
834 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
835 if (screen->base.drm->version >= 0x01000202)
836 flags |= NOUVEAU_BO_COHERENT;
837
838 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
839 if (ret)
840 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
841 nouveau_bo_map(screen->fence.bo, 0, NULL);
842 screen->fence.map = screen->fence.bo->map;
843 screen->base.fence.emit = nvc0_screen_fence_emit;
844 screen->base.fence.update = nvc0_screen_fence_update;
845
846
847 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
848 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
849 if (ret)
850 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
851
852 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
853 PUSH_DATA (push, screen->nvsw->handle);
854
855 switch (dev->chipset & ~0xf) {
856 case 0x130:
857 case 0x120:
858 case 0x110:
859 case 0x100:
860 case 0xf0:
861 obj_class = NVF0_P2MF_CLASS;
862 break;
863 case 0xe0:
864 obj_class = NVE4_P2MF_CLASS;
865 break;
866 default:
867 obj_class = NVC0_M2MF_CLASS;
868 break;
869 }
870 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
871 &screen->m2mf);
872 if (ret)
873 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
874
875 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
876 PUSH_DATA (push, screen->m2mf->oclass);
877 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
878 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
879 PUSH_DATA (push, 0xa0b5);
880 }
881
882 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
883 &screen->eng2d);
884 if (ret)
885 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
886
887 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
888 PUSH_DATA (push, screen->eng2d->oclass);
889 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
890 PUSH_DATA (push, 0);
891 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
892 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
893 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
894 PUSH_DATA (push, 0);
895 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
896 PUSH_DATA (push, 0);
897 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
898 PUSH_DATA (push, 0x3f);
899 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
900 PUSH_DATA (push, 1);
901 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
902 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
903
904 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
905 PUSH_DATAh(push, screen->fence.bo->offset + 16);
906 PUSH_DATA (push, screen->fence.bo->offset + 16);
907
908 switch (dev->chipset & ~0xf) {
909 case 0x130:
910 switch (dev->chipset) {
911 case 0x130:
912 obj_class = GP100_3D_CLASS;
913 break;
914 default:
915 obj_class = GP102_3D_CLASS;
916 break;
917 }
918 break;
919 case 0x120:
920 obj_class = GM200_3D_CLASS;
921 break;
922 case 0x110:
923 obj_class = GM107_3D_CLASS;
924 break;
925 case 0x100:
926 case 0xf0:
927 obj_class = NVF0_3D_CLASS;
928 break;
929 case 0xe0:
930 switch (dev->chipset) {
931 case 0xea:
932 obj_class = NVEA_3D_CLASS;
933 break;
934 default:
935 obj_class = NVE4_3D_CLASS;
936 break;
937 }
938 break;
939 case 0xd0:
940 obj_class = NVC8_3D_CLASS;
941 break;
942 case 0xc0:
943 default:
944 switch (dev->chipset) {
945 case 0xc8:
946 obj_class = NVC8_3D_CLASS;
947 break;
948 case 0xc1:
949 obj_class = NVC1_3D_CLASS;
950 break;
951 default:
952 obj_class = NVC0_3D_CLASS;
953 break;
954 }
955 break;
956 }
957 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
958 &screen->eng3d);
959 if (ret)
960 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
961 screen->base.class_3d = obj_class;
962
963 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
964 PUSH_DATA (push, screen->eng3d->oclass);
965
966 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
967 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
968
969 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
970 /* kill shaders after about 1 second (at 100 MHz) */
971 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
972 PUSH_DATA (push, 0x17);
973 }
974
975 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
976 screen->base.drm->version >= 0x01000101);
977 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
978 for (i = 0; i < 8; ++i)
979 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
980
981 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
982 PUSH_DATA (push, 1);
983
984 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
985 PUSH_DATA (push, 0);
986 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
987 PUSH_DATA (push, 0);
988 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
989 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
990 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
991 PUSH_DATA (push, 0);
992 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
993 PUSH_DATA (push, 1);
994 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
995 PUSH_DATA (push, 1);
996 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
997 PUSH_DATA (push, 1);
998 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
999 PUSH_DATA (push, 0);
1000 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1001 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1002 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1003 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1004 } else {
1005 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1006 PUSH_DATA (push, 15);
1007 }
1008 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1009 PUSH_DATA (push, 8); /* 128 */
1010 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1011 PUSH_DATA (push, 1);
1012 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1013 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1014 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1015 }
1016
1017 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1018
1019 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1020 if (ret)
1021 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1022
1023 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1024 &screen->uniform_bo);
1025 if (ret)
1026 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1027
1028 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1029
1030 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1031 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1032 PUSH_DATA (push, 256);
1033 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1034 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1035 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1036 PUSH_DATA (push, 0);
1037 PUSH_DATAf(push, 0.0f);
1038 PUSH_DATAf(push, 0.0f);
1039 PUSH_DATAf(push, 0.0f);
1040 PUSH_DATAf(push, 0.0f);
1041 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1042 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1043 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1044
1045 if (screen->base.drm->version >= 0x01000101) {
1046 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1047 if (ret)
1048 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1049 } else {
1050 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1051 value = (8 << 8) | 4;
1052 else
1053 value = (16 << 8) | 4;
1054 }
1055 screen->gpc_count = value & 0x000000ff;
1056 screen->mp_count = value >> 8;
1057 screen->mp_count_compute = screen->mp_count;
1058
1059 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1060 if (ret)
1061 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1062
1063 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1064 PUSH_DATAh(push, screen->tls->offset);
1065 PUSH_DATA (push, screen->tls->offset);
1066 PUSH_DATA (push, screen->tls->size >> 32);
1067 PUSH_DATA (push, screen->tls->size);
1068 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1069 PUSH_DATA (push, 0);
1070 /* Reduce likelihood of collision with real buffers by placing the hole at
1071 * the top of the 4G area. This will have to be dealt with for real
1072 * eventually by blocking off that area from the VM.
1073 */
1074 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1075 PUSH_DATA (push, 0xff << 24);
1076
1077 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1078 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1079 &screen->poly_cache);
1080 if (ret)
1081 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1082
1083 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1084 PUSH_DATAh(push, screen->poly_cache->offset);
1085 PUSH_DATA (push, screen->poly_cache->offset);
1086 PUSH_DATA (push, 3);
1087 }
1088
1089 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1090 &screen->txc);
1091 if (ret)
1092 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1093
1094 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1095 PUSH_DATAh(push, screen->txc->offset);
1096 PUSH_DATA (push, screen->txc->offset);
1097 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1098 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1099 screen->tic.maxwell = true;
1100 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1101 screen->tic.maxwell =
1102 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1103 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1104 }
1105 }
1106
1107 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1108 PUSH_DATAh(push, screen->txc->offset + 65536);
1109 PUSH_DATA (push, screen->txc->offset + 65536);
1110 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1111
1112 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1113 PUSH_DATA (push, 0);
1114 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1115 PUSH_DATA (push, 0);
1116 PUSH_DATA (push, 0);
1117 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1118 PUSH_DATA (push, 0x3f);
1119
1120 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1121 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1122 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1123 for (i = 0; i < 8 * 2; ++i)
1124 PUSH_DATA(push, 0);
1125 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1126 PUSH_DATA (push, 0);
1127 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1128 PUSH_DATA (push, 0);
1129
1130 /* neither scissors, viewport nor stencil mask should affect clears */
1131 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1132 PUSH_DATA (push, 0);
1133
1134 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1135 PUSH_DATA (push, 1);
1136 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1137 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1138 PUSH_DATAf(push, 0.0f);
1139 PUSH_DATAf(push, 1.0f);
1140 }
1141 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1142 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1143
1144 /* We use scissors instead of exact view volume clipping,
1145 * so they're always enabled.
1146 */
1147 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1148 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1149 PUSH_DATA (push, 1);
1150 PUSH_DATA (push, 8192 << 16);
1151 PUSH_DATA (push, 8192 << 16);
1152 }
1153
1154 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1155
1156 i = 0;
1157 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1158 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1159 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1160 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1161 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1162 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1163 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1164 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1165 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1166 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1167 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1168 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1169 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1170
1171 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1172 PUSH_DATA (push, 1);
1173 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1174 PUSH_DATA (push, 1);
1175 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1176 PUSH_DATA (push, 0x40);
1177 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1178 PUSH_DATA (push, 0);
1179 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1180 PUSH_DATA (push, 0x30);
1181 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1182 PUSH_DATA (push, 3);
1183 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1184 PUSH_DATA (push, 0x20);
1185 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1186 PUSH_DATA (push, 0x00);
1187 screen->save_state.patch_vertices = 3;
1188
1189 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1190 PUSH_DATA (push, 0);
1191 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1192 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1193
1194 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1195
1196 if (nvc0_screen_init_compute(screen))
1197 goto fail;
1198
1199 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1200 for (i = 0; i < 5; ++i) {
1201 /* TIC and TSC entries for each unit (nve4+ only) */
1202 /* auxiliary constants (6 user clip planes, base instance id) */
1203 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1204 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1205 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1206 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1207 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1208 PUSH_DATA (push, (15 << 4) | 1);
1209 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1210 unsigned j;
1211 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1212 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1213 for (j = 0; j < 8; ++j)
1214 PUSH_DATA(push, j);
1215 } else {
1216 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1217 PUSH_DATA (push, 0x54);
1218 }
1219
1220 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1221 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1222 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1223 PUSH_DATA (push, 0); /* 0 */
1224 PUSH_DATA (push, 0);
1225 PUSH_DATA (push, 1); /* 1 */
1226 PUSH_DATA (push, 0);
1227 PUSH_DATA (push, 0); /* 2 */
1228 PUSH_DATA (push, 1);
1229 PUSH_DATA (push, 1); /* 3 */
1230 PUSH_DATA (push, 1);
1231 PUSH_DATA (push, 2); /* 4 */
1232 PUSH_DATA (push, 0);
1233 PUSH_DATA (push, 3); /* 5 */
1234 PUSH_DATA (push, 0);
1235 PUSH_DATA (push, 2); /* 6 */
1236 PUSH_DATA (push, 1);
1237 PUSH_DATA (push, 3); /* 7 */
1238 PUSH_DATA (push, 1);
1239 }
1240 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1241 PUSH_DATA (push, 0);
1242
1243 PUSH_KICK (push);
1244
1245 screen->tic.entries = CALLOC(4096, sizeof(void *));
1246 screen->tsc.entries = screen->tic.entries + 2048;
1247
1248 if (!nvc0_blitter_create(screen))
1249 goto fail;
1250
1251 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1252 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1253
1254 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1255
1256 return &screen->base;
1257
1258 fail:
1259 screen->base.base.context_create = NULL;
1260 return &screen->base;
1261 }
1262
1263 int
1264 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1265 {
1266 int i = screen->tic.next;
1267
1268 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1269 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1270
1271 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1272
1273 if (screen->tic.entries[i])
1274 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1275
1276 screen->tic.entries[i] = entry;
1277 return i;
1278 }
1279
1280 int
1281 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1282 {
1283 int i = screen->tsc.next;
1284
1285 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1286 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1287
1288 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1289
1290 if (screen->tsc.entries[i])
1291 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1292
1293 screen->tsc.entries[i] = entry;
1294 return i;
1295 }