src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30
  31 #include "nouveau_vp3_video.h"
  32
  33 #include "nvc0/nvc0_context.h"
  34 #include "nvc0/nvc0_screen.h"
  35
  36 #include "nvc0/mme/com9097.mme.h"
  37 #include "nvc0/mme/com90c0.mme.h"
  38
  39 #include "nv50/g80_texture.xml.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned storage_sample_count,
  47                                 unsigned bindings)
  48 {
  49    const struct util_format_description *desc = util_format_description(format);
  50
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55
  56    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  57       return false;
  58
  59    /* Short-circuit the rest of the logic -- this is used by the state tracker
  60     * to determine valid MS levels in a no-attachments scenario.
  61     */
  62    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  63       return true;
  64
  65    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  66       if (util_format_get_blocksizebits(format) == 3 * 32)
  67          return false;
  68
  69    if (bindings & PIPE_BIND_LINEAR)
  70       if (util_format_is_depth_or_stencil(format) ||
  71           (target != PIPE_TEXTURE_1D &&
  72            target != PIPE_TEXTURE_2D &&
  73            target != PIPE_TEXTURE_RECT) ||
  74           sample_count > 1)
  75          return false;
  76
  77    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  78     */
  79    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  80         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  81        /* The claim is that this should work on GM107 but it doesn't. Need to
  82         * test further and figure out if it's a nouveau issue or a HW one.
  83        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  84         */
  85        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  86       return false;
  87
  88    /* shared is always supported */
  89    bindings &= ~(PIPE_BIND_LINEAR |
  90                  PIPE_BIND_SHARED);
  91
  92    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  93       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  94           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
  95          /* This should work on Fermi, but for currently unknown reasons it
  96           * does not and results in breaking reads from pbos. */
  97          return false;
  98       }
  99    }
 100
 101    return (( nvc0_format_table[format].usage |
 102             nvc0_vertex_format[format].usage) & bindings) == bindings;
 103 }
 104
 105 static int
 106 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 107 {
 108    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 109    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 110
 111    switch (param) {
 112    /* non-boolean caps */
 113    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 114    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 115       return 15;
 116    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 117       return 12;
 118    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 119       return 2048;
 120    case PIPE_CAP_MIN_TEXEL_OFFSET:
 121       return -8;
 122    case PIPE_CAP_MAX_TEXEL_OFFSET:
 123       return 7;
 124    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 125       return -32;
 126    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 127       return 31;
 128    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 129       return 128 * 1024 * 1024;
 130    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 131       return 430;
 132    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 133       return 430;
 134    case PIPE_CAP_MAX_RENDER_TARGETS:
 135       return 8;
 136    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 137       return 1;
 138    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 139    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 140       return 8;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 145       return 128;
 146    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 147    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 148       return 1024;
 149    case PIPE_CAP_MAX_VERTEX_STREAMS:
 150       return 4;
 151    case PIPE_CAP_MAX_GS_INVOCATIONS:
 152       return 32;
 153    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 154       return 1 << 27;
 155    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 156       return 2048;
 157    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 158       return 2047;
 159    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 160       return 256;
 161    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 162       if (class_3d < GM107_3D_CLASS)
 163          return 256; /* IMAGE bindings require alignment to 256 */
 164       return 16;
 165    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 166       return 16;
 167    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 168       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 169    case PIPE_CAP_MAX_VIEWPORTS:
 170       return NVC0_MAX_VIEWPORTS;
 171    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 172       return 4;
 173    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 174       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 175    case PIPE_CAP_ENDIANNESS:
 176       return PIPE_ENDIAN_LITTLE;
 177    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 178       return 30;
 179    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 180       return NVC0_MAX_WINDOW_RECTANGLES;
 181    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 182       return class_3d >= GM200_3D_CLASS ? 8 : 0;
 183    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 184       return 64 * 1024 * 1024;
 185
 186    /* supported caps */
 187    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 188    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 189    case PIPE_CAP_TEXTURE_SWIZZLE:
 190    case PIPE_CAP_NPOT_TEXTURES:
 191    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 192    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 193    case PIPE_CAP_ANISOTROPIC_FILTER:
 194    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 195    case PIPE_CAP_CUBE_MAP_ARRAY:
 196    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 197    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 198    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 199    case PIPE_CAP_POINT_SPRITE:
 200    case PIPE_CAP_TGSI_TEXCOORD:
 201    case PIPE_CAP_SM3:
 202    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 203    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 204    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 205    case PIPE_CAP_QUERY_TIMESTAMP:
 206    case PIPE_CAP_QUERY_TIME_ELAPSED:
 207    case PIPE_CAP_OCCLUSION_QUERY:
 208    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 209    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 210    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 211    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 212    case PIPE_CAP_INDEP_BLEND_ENABLE:
 213    case PIPE_CAP_INDEP_BLEND_FUNC:
 214    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 215    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 216    case PIPE_CAP_PRIMITIVE_RESTART:
 217    case PIPE_CAP_TGSI_INSTANCEID:
 218    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 219    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 220    case PIPE_CAP_CONDITIONAL_RENDER:
 221    case PIPE_CAP_TEXTURE_BARRIER:
 222    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 223    case PIPE_CAP_START_INSTANCE:
 224    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 225    case PIPE_CAP_DRAW_INDIRECT:
 226    case PIPE_CAP_USER_VERTEX_BUFFERS:
 227    case PIPE_CAP_TEXTURE_QUERY_LOD:
 228    case PIPE_CAP_SAMPLE_SHADING:
 229    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 230    case PIPE_CAP_TEXTURE_GATHER_SM5:
 231    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 232    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 233    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 234    case PIPE_CAP_CLIP_HALFZ:
 235    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 236    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 237    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 238    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 239    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 240    case PIPE_CAP_TGSI_TXQS:
 241    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 242    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 243    case PIPE_CAP_SHAREABLE_SHADERS:
 244    case PIPE_CAP_CLEAR_TEXTURE:
 245    case PIPE_CAP_DRAW_PARAMETERS:
 246    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 247    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 248    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 249    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 250    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 251    case PIPE_CAP_INVALIDATE_BUFFER:
 252    case PIPE_CAP_STRING_MARKER:
 253    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 254    case PIPE_CAP_CULL_DISTANCE:
 255    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 256    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 257    case PIPE_CAP_TGSI_VOTE:
 258    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 259    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 260    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 261    case PIPE_CAP_DOUBLES:
 262    case PIPE_CAP_INT64:
 263    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 264    case PIPE_CAP_TGSI_CLOCK:
 265    case PIPE_CAP_COMPUTE:
 266    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 267    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 268    case PIPE_CAP_QUERY_SO_OVERFLOW:
 269       return 1;
 270    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 271       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 272    case PIPE_CAP_TGSI_FS_FBFETCH:
 273       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 274    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 275    case PIPE_CAP_TGSI_BALLOT:
 276    case PIPE_CAP_BINDLESS_TEXTURE:
 277       return class_3d >= NVE4_3D_CLASS;
 278    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 279    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 280    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 281    case PIPE_CAP_POST_DEPTH_COVERAGE:
 282    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 283    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 284    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 285    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 286       return class_3d >= GM200_3D_CLASS;
 287    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 288       return class_3d >= GP100_3D_CLASS;
 289
 290    /* unsupported caps */
 291    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 292    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 293    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 294    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 295    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 296    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 297    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 298    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 299    case PIPE_CAP_FAKE_SW_MSAA:
 300    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 301    case PIPE_CAP_VERTEXID_NOBASE:
 302    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 303    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 304    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 305    case PIPE_CAP_GENERATE_MIPMAP:
 306    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 307    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 308    case PIPE_CAP_QUERY_MEMORY_INFO:
 309    case PIPE_CAP_PCI_GROUP:
 310    case PIPE_CAP_PCI_BUS:
 311    case PIPE_CAP_PCI_DEVICE:
 312    case PIPE_CAP_PCI_FUNCTION:
 313    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 314    case PIPE_CAP_NATIVE_FENCE_FD:
 315    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 316    case PIPE_CAP_INT64_DIVMOD:
 317    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 318    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 319    case PIPE_CAP_MEMOBJ:
 320    case PIPE_CAP_LOAD_CONSTBUF:
 321    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 322    case PIPE_CAP_TILE_RASTER_ORDER:
 323    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 324    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 325    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 326    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 327    case PIPE_CAP_FENCE_SIGNAL:
 328    case PIPE_CAP_CONSTBUF0_FLAGS:
 329    case PIPE_CAP_PACKED_UNIFORMS:
 330    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 331    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 332    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 333    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 334       return 0;
 335
 336    case PIPE_CAP_VENDOR_ID:
 337       return 0x10de;
 338    case PIPE_CAP_DEVICE_ID: {
 339       uint64_t device_id;
 340       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 341          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 342          return -1;
 343       }
 344       return device_id;
 345    }
 346    case PIPE_CAP_ACCELERATED:
 347       return 1;
 348    case PIPE_CAP_VIDEO_MEMORY:
 349       return dev->vram_size >> 20;
 350    case PIPE_CAP_UMA:
 351       return 0;
 352    default:
 353       debug_printf("%s: unhandled cap %d\n", __func__, param);
 354       return u_pipe_screen_get_param_defaults(pscreen, param);
 355    }
 356 }
 357
 358 static int
 359 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 360                              enum pipe_shader_type shader,
 361                              enum pipe_shader_cap param)
 362 {
 363    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 364
 365    switch (shader) {
 366    case PIPE_SHADER_VERTEX:
 367    case PIPE_SHADER_GEOMETRY:
 368    case PIPE_SHADER_FRAGMENT:
 369    case PIPE_SHADER_COMPUTE:
 370    case PIPE_SHADER_TESS_CTRL:
 371    case PIPE_SHADER_TESS_EVAL:
 372       break;
 373    default:
 374       return 0;
 375    }
 376
 377    switch (param) {
 378    case PIPE_SHADER_CAP_PREFERRED_IR:
 379       return PIPE_SHADER_IR_TGSI;
 380    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 381       return 1 << PIPE_SHADER_IR_TGSI;
 382    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 383    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 384    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 385    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 386       return 16384;
 387    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 388       return 16;
 389    case PIPE_SHADER_CAP_MAX_INPUTS:
 390       if (shader == PIPE_SHADER_VERTEX)
 391          return 32;
 392       /* NOTE: These only count our slots for GENERIC varyings.
 393        * The address space may be larger, but the actual hard limit seems to be
 394        * less than what the address space layout permits, so don't add TEXCOORD,
 395        * COLOR, etc. here.
 396        */
 397       if (shader == PIPE_SHADER_FRAGMENT)
 398          return 0x1f0 / 16;
 399       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 400        * and excludes 0x60 per-patch inputs.
 401        */
 402       return 0x200 / 16;
 403    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 404       return 32;
 405    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 406       return NVC0_MAX_CONSTBUF_SIZE;
 407    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 408       return NVC0_MAX_PIPE_CONSTBUFS;
 409    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 410       return shader != PIPE_SHADER_FRAGMENT;
 411    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 412    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 413    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 414       return 1;
 415    case PIPE_SHADER_CAP_MAX_TEMPS:
 416       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 417    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 418       return 1;
 419    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 420       return 1;
 421    case PIPE_SHADER_CAP_SUBROUTINES:
 422       return 1;
 423    case PIPE_SHADER_CAP_INTEGERS:
 424       return 1;
 425    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 426       return 1;
 427    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 428       return 1;
 429    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 430       return 1;
 431    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 432    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 433    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 434    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 435    case PIPE_SHADER_CAP_INT64_ATOMICS:
 436    case PIPE_SHADER_CAP_FP16:
 437    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 438    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 439       return 0;
 440    case PIPE_SHADER_CAP_SCALAR_ISA:
 441       return 1;
 442    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 443       return NVC0_MAX_BUFFERS;
 444    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 445       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 446    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 447       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 448    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 449       return 32;
 450    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 451       if (class_3d >= NVE4_3D_CLASS)
 452          return NVC0_MAX_IMAGES;
 453       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 454          return NVC0_MAX_IMAGES;
 455       return 0;
 456    default:
 457       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 458       return 0;
 459    }
 460 }
 461
 462 static float
 463 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 464 {
 465    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 466
 467    switch (param) {
 468    case PIPE_CAPF_MAX_LINE_WIDTH:
 469    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 470       return 10.0f;
 471    case PIPE_CAPF_MAX_POINT_WIDTH:
 472       return 63.0f;
 473    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 474       return 63.375f;
 475    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 476       return 16.0f;
 477    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 478       return 15.0f;
 479    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 480       return 0.0f;
 481    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 482       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
 483    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 484       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
 485    }
 486
 487    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 488    return 0.0f;
 489 }
 490
 491 static int
 492 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 493                               enum pipe_shader_ir ir_type,
 494                               enum pipe_compute_cap param, void *data)
 495 {
 496    struct nvc0_screen *screen = nvc0_screen(pscreen);
 497    const uint16_t obj_class = screen->compute->oclass;
 498
 499 #define RET(x) do {                  \
 500    if (data)                         \
 501       memcpy(data, x, sizeof(x));    \
 502    return sizeof(x);                 \
 503 } while (0)
 504
 505    switch (param) {
 506    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 507       RET((uint64_t []) { 3 });
 508    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 509       if (obj_class >= NVE4_COMPUTE_CLASS) {
 510          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 511       } else {
 512          RET(((uint64_t []) { 65535, 65535, 65535 }));
 513       }
 514    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 515       RET(((uint64_t []) { 1024, 1024, 64 }));
 516    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 517       RET((uint64_t []) { 1024 });
 518    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 519       if (obj_class >= NVE4_COMPUTE_CLASS) {
 520          RET((uint64_t []) { 1024 });
 521       } else {
 522          RET((uint64_t []) { 512 });
 523       }
 524    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 525       RET((uint64_t []) { 1ULL << 40 });
 526    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 527       switch (obj_class) {
 528       case GM200_COMPUTE_CLASS:
 529          RET((uint64_t []) { 96 << 10 });
 530          break;
 531       case GM107_COMPUTE_CLASS:
 532          RET((uint64_t []) { 64 << 10 });
 533          break;
 534       default:
 535          RET((uint64_t []) { 48 << 10 });
 536          break;
 537       }
 538    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 539       RET((uint64_t []) { 512 << 10 });
 540    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 541       RET((uint64_t []) { 4096 });
 542    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 543       RET((uint32_t []) { 32 });
 544    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 545       RET((uint64_t []) { 1ULL << 40 });
 546    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 547       RET((uint32_t []) { 0 });
 548    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 549       RET((uint32_t []) { screen->mp_count_compute });
 550    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 551       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 552    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 553       RET((uint32_t []) { 64 });
 554    default:
 555       return 0;
 556    }
 557
 558 #undef RET
 559 }
 560
 561 static void
 562 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
 563                                   unsigned sample_count,
 564                                   unsigned *width, unsigned *height)
 565 {
 566    switch (sample_count) {
 567    case 0:
 568    case 1:
 569       /* this could be 4x4, but the GL state tracker makes it difficult to
 570        * create a 1x MSAA texture and smaller grids save CB space */
 571       *width = 2;
 572       *height = 4;
 573       break;
 574    case 2:
 575       *width = 2;
 576       *height = 4;
 577       break;
 578    case 4:
 579       *width = 2;
 580       *height = 2;
 581       break;
 582    case 8:
 583       *width = 1;
 584       *height = 2;
 585       break;
 586    default:
 587       assert(0);
 588    }
 589 }
 590
 591 static void
 592 nvc0_screen_destroy(struct pipe_screen *pscreen)
 593 {
 594    struct nvc0_screen *screen = nvc0_screen(pscreen);
 595
 596    if (!nouveau_drm_screen_unref(&screen->base))
 597       return;
 598
 599    if (screen->base.fence.current) {
 600       struct nouveau_fence *current = NULL;
 601
 602       /* nouveau_fence_wait will create a new current fence, so wait on the
 603        * _current_ one, and remove both.
 604        */
 605       nouveau_fence_ref(screen->base.fence.current, &current);
 606       nouveau_fence_wait(current, NULL);
 607       nouveau_fence_ref(NULL, &current);
 608       nouveau_fence_ref(NULL, &screen->base.fence.current);
 609    }
 610    if (screen->base.pushbuf)
 611       screen->base.pushbuf->user_priv = NULL;
 612
 613    if (screen->blitter)
 614       nvc0_blitter_destroy(screen);
 615    if (screen->pm.prog) {
 616       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 617       nvc0_program_destroy(NULL, screen->pm.prog);
 618       FREE(screen->pm.prog);
 619    }
 620
 621    nouveau_bo_ref(NULL, &screen->text);
 622    nouveau_bo_ref(NULL, &screen->uniform_bo);
 623    nouveau_bo_ref(NULL, &screen->tls);
 624    nouveau_bo_ref(NULL, &screen->txc);
 625    nouveau_bo_ref(NULL, &screen->fence.bo);
 626    nouveau_bo_ref(NULL, &screen->poly_cache);
 627
 628    nouveau_heap_destroy(&screen->lib_code);
 629    nouveau_heap_destroy(&screen->text_heap);
 630
 631    FREE(screen->tic.entries);
 632
 633    nouveau_object_del(&screen->eng3d);
 634    nouveau_object_del(&screen->eng2d);
 635    nouveau_object_del(&screen->m2mf);
 636    nouveau_object_del(&screen->compute);
 637    nouveau_object_del(&screen->nvsw);
 638
 639    nouveau_screen_fini(&screen->base);
 640
 641    FREE(screen);
 642 }
 643
 644 static int
 645 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 646                      unsigned size, const uint32_t *data)
 647 {
 648    struct nouveau_pushbuf *push = screen->base.pushbuf;
 649
 650    size /= 4;
 651
 652    assert((pos + size) <= 0x800);
 653
 654    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 655    PUSH_DATA (push, (m - 0x3800) / 8);
 656    PUSH_DATA (push, pos);
 657    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 658    PUSH_DATA (push, pos);
 659    PUSH_DATAp(push, data, size);
 660
 661    return pos + size;
 662 }
 663
 664 static void
 665 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 666 {
 667    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 668    PUSH_DATA (push, 0xff);
 669    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 670    PUSH_DATA (push, 0xff);
 671    PUSH_DATA (push, 0xff);
 672    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 673    PUSH_DATA (push, 0xff);
 674    PUSH_DATA (push, 0xff);
 675    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 676    PUSH_DATA (push, 0x3f);
 677
 678    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 679    PUSH_DATA (push, (3 << 16) | 3);
 680    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 681    PUSH_DATA (push, (2 << 16) | 2);
 682
 683    if (obj_class < GM107_3D_CLASS) {
 684       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 685       PUSH_DATA (push, 0);
 686    }
 687    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 688    PUSH_DATA (push, 0x10);
 689    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 690    PUSH_DATA (push, 0x10);
 691    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 692    PUSH_DATA (push, 0x10);
 693    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 694    PUSH_DATA (push, 0x10);
 695    PUSH_DATA (push, 0x10);
 696    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 697    PUSH_DATA (push, 0x10);
 698    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 699    PUSH_DATA (push, 0xe);
 700
 701    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 702    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 703    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 704    PUSH_DATA (push, 0);
 705    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 706    PUSH_DATA (push, 3);
 707
 708    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 709    PUSH_DATA (push, 0x3fffff);
 710    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 711    PUSH_DATA (push, 1);
 712    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 713    PUSH_DATA (push, 1);
 714
 715    if (obj_class < GM107_3D_CLASS) {
 716       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 717       PUSH_DATA (push, 3);
 718
 719       if (obj_class >= NVE4_3D_CLASS) {
 720          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 721          PUSH_DATA (push, 1);
 722       }
 723    }
 724
 725    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 726     * are supposed to do */
 727 }
 728
 729 static void
 730 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 731 {
 732    struct nvc0_screen *screen = nvc0_screen(pscreen);
 733    struct nouveau_pushbuf *push = screen->base.pushbuf;
 734
 735    /* we need to do it after possible flush in MARK_RING */
 736    *sequence = ++screen->base.fence.sequence;
 737
 738    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 739    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 740    PUSH_DATAh(push, screen->fence.bo->offset);
 741    PUSH_DATA (push, screen->fence.bo->offset);
 742    PUSH_DATA (push, *sequence);
 743    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 744               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 745 }
 746
 747 static u32
 748 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 749 {
 750    struct nvc0_screen *screen = nvc0_screen(pscreen);
 751    return screen->fence.map[0];
 752 }
 753
 754 static int
 755 nvc0_screen_init_compute(struct nvc0_screen *screen)
 756 {
 757    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 758
 759    switch (screen->base.device->chipset & ~0xf) {
 760    case 0xc0:
 761    case 0xd0:
 762       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 763    case 0xe0:
 764    case 0xf0:
 765    case 0x100:
 766    case 0x110:
 767    case 0x120:
 768    case 0x130:
 769       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 770    default:
 771       return -1;
 772    }
 773 }
 774
 775 static int
 776 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 777                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 778 {
 779    struct nouveau_bo *bo = NULL;
 780    int ret;
 781    uint64_t size = (lpos + lneg) * 32 + cstack;
 782
 783    if (size >= (1 << 20)) {
 784       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 785       return -1;
 786    }
 787
 788    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 789    size  = align(size, 0x8000);
 790    size *= screen->mp_count;
 791
 792    size = align(size, 1 << 17);
 793
 794    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 795                         NULL, &bo);
 796    if (ret)
 797       return ret;
 798
 799    /* Make sure that the pushbuf has acquired a reference to the old tls
 800     * segment, as it may have commands that will reference it.
 801     */
 802    if (screen->tls)
 803       PUSH_REFN(screen->base.pushbuf, screen->tls,
 804                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 805    nouveau_bo_ref(NULL, &screen->tls);
 806    screen->tls = bo;
 807    return 0;
 808 }
 809
 810 int
 811 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 812 {
 813    struct nouveau_pushbuf *push = screen->base.pushbuf;
 814    struct nouveau_bo *bo;
 815    int ret;
 816
 817    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 818                         1 << 17, size, NULL, &bo);
 819    if (ret)
 820       return ret;
 821
 822    /* Make sure that the pushbuf has acquired a reference to the old text
 823     * segment, as it may have commands that will reference it.
 824     */
 825    if (screen->text)
 826       PUSH_REFN(push, screen->text,
 827                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 828    nouveau_bo_ref(NULL, &screen->text);
 829    screen->text = bo;
 830
 831    nouveau_heap_destroy(&screen->lib_code);
 832    nouveau_heap_destroy(&screen->text_heap);
 833
 834    /* XXX: getting a page fault at the end of the code buffer every few
 835     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 836     */
 837    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 838
 839    /* update the code segment setup */
 840    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 841    PUSH_DATAh(push, screen->text->offset);
 842    PUSH_DATA (push, screen->text->offset);
 843    if (screen->compute) {
 844       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 845       PUSH_DATAh(push, screen->text->offset);
 846       PUSH_DATA (push, screen->text->offset);
 847    }
 848
 849    return 0;
 850 }
 851
 852 void
 853 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
 854                        int stage, int index, int size, uint64_t addr)
 855 {
 856    assert(stage != 5);
 857
 858    struct nouveau_pushbuf *push = screen->base.pushbuf;
 859
 860    if (screen->base.class_3d >= GM107_3D_CLASS) {
 861       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
 862
 863       // TODO: Better figure out the conditions in which this is needed
 864       bool serialize = binding->addr == addr && binding->size != size;
 865       if (can_serialize)
 866          serialize = serialize && *can_serialize;
 867       if (serialize) {
 868          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
 869          if (can_serialize)
 870             *can_serialize = false;
 871       }
 872
 873       binding->addr = addr;
 874       binding->size = size;
 875    }
 876
 877    if (size >= 0) {
 878       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 879       PUSH_DATA (push, size);
 880       PUSH_DATAh(push, addr);
 881       PUSH_DATA (push, addr);
 882    }
 883    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
 884 }
 885
 886 #define FAIL_SCREEN_INIT(str, err)                    \
 887    do {                                               \
 888       NOUVEAU_ERR(str, err);                          \
 889       goto fail;                                      \
 890    } while(0)
 891
 892 struct nouveau_screen *
 893 nvc0_screen_create(struct nouveau_device *dev)
 894 {
 895    struct nvc0_screen *screen;
 896    struct pipe_screen *pscreen;
 897    struct nouveau_object *chan;
 898    struct nouveau_pushbuf *push;
 899    uint64_t value;
 900    uint32_t obj_class;
 901    uint32_t flags;
 902    int ret;
 903    unsigned i;
 904
 905    switch (dev->chipset & ~0xf) {
 906    case 0xc0:
 907    case 0xd0:
 908    case 0xe0:
 909    case 0xf0:
 910    case 0x100:
 911    case 0x110:
 912    case 0x120:
 913    case 0x130:
 914       break;
 915    default:
 916       return NULL;
 917    }
 918
 919    screen = CALLOC_STRUCT(nvc0_screen);
 920    if (!screen)
 921       return NULL;
 922    pscreen = &screen->base.base;
 923    pscreen->destroy = nvc0_screen_destroy;
 924
 925    ret = nouveau_screen_init(&screen->base, dev);
 926    if (ret)
 927       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 928    chan = screen->base.channel;
 929    push = screen->base.pushbuf;
 930    push->user_priv = screen;
 931    push->rsvd_kick = 5;
 932
 933    /* TODO: could this be higher on Kepler+? how does reclocking vs no
 934     * reclocking affect performance?
 935     * TODO: could this be higher on Fermi?
 936     */
 937    if (dev->chipset >= 0xe0)
 938       screen->base.transfer_pushbuf_threshold = 1024;
 939
 940    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 941       PIPE_BIND_SHADER_BUFFER |
 942       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 943       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 944    screen->base.sysmem_bindings |=
 945       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 946
 947    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 948       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 949       screen->base.vidmem_bindings = 0;
 950    }
 951
 952    pscreen->context_create = nvc0_create;
 953    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 954    pscreen->get_param = nvc0_screen_get_param;
 955    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 956    pscreen->get_paramf = nvc0_screen_get_paramf;
 957    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
 958    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 959    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 960
 961    nvc0_screen_init_resource_functions(pscreen);
 962
 963    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 964    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 965
 966    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 967    if (screen->base.drm->version >= 0x01000202)
 968       flags |= NOUVEAU_BO_COHERENT;
 969
 970    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 971    if (ret)
 972       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 973    nouveau_bo_map(screen->fence.bo, 0, NULL);
 974    screen->fence.map = screen->fence.bo->map;
 975    screen->base.fence.emit = nvc0_screen_fence_emit;
 976    screen->base.fence.update = nvc0_screen_fence_update;
 977
 978
 979    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 980                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 981    if (ret)
 982       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 983
 984    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 985    PUSH_DATA (push, screen->nvsw->handle);
 986
 987    switch (dev->chipset & ~0xf) {
 988    case 0x130:
 989    case 0x120:
 990    case 0x110:
 991    case 0x100:
 992    case 0xf0:
 993       obj_class = NVF0_P2MF_CLASS;
 994       break;
 995    case 0xe0:
 996       obj_class = NVE4_P2MF_CLASS;
 997       break;
 998    default:
 999       obj_class = NVC0_M2MF_CLASS;
1000       break;
1001    }
1002    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1003                             &screen->m2mf);
1004    if (ret)
1005       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1006
1007    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1008    PUSH_DATA (push, screen->m2mf->oclass);
1009    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1010       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1011       PUSH_DATA (push, 0xa0b5);
1012    }
1013
1014    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1015                             &screen->eng2d);
1016    if (ret)
1017       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1018
1019    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1020    PUSH_DATA (push, screen->eng2d->oclass);
1021    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1022    PUSH_DATA (push, 0);
1023    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1024    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1025    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1026    PUSH_DATA (push, 0);
1027    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1028    PUSH_DATA (push, 0);
1029    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1030    PUSH_DATA (push, 0x3f);
1031    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1032    PUSH_DATA (push, 1);
1033    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1034    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1035
1036    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1037    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1038    PUSH_DATA (push, screen->fence.bo->offset + 16);
1039
1040    switch (dev->chipset & ~0xf) {
1041    case 0x130:
1042       switch (dev->chipset) {
1043       case 0x130:
1044       case 0x13b:
1045          obj_class = GP100_3D_CLASS;
1046          break;
1047       default:
1048          obj_class = GP102_3D_CLASS;
1049          break;
1050       }
1051       break;
1052    case 0x120:
1053       obj_class = GM200_3D_CLASS;
1054       break;
1055    case 0x110:
1056       obj_class = GM107_3D_CLASS;
1057       break;
1058    case 0x100:
1059    case 0xf0:
1060       obj_class = NVF0_3D_CLASS;
1061       break;
1062    case 0xe0:
1063       switch (dev->chipset) {
1064       case 0xea:
1065          obj_class = NVEA_3D_CLASS;
1066          break;
1067       default:
1068          obj_class = NVE4_3D_CLASS;
1069          break;
1070       }
1071       break;
1072    case 0xd0:
1073       obj_class = NVC8_3D_CLASS;
1074       break;
1075    case 0xc0:
1076    default:
1077       switch (dev->chipset) {
1078       case 0xc8:
1079          obj_class = NVC8_3D_CLASS;
1080          break;
1081       case 0xc1:
1082          obj_class = NVC1_3D_CLASS;
1083          break;
1084       default:
1085          obj_class = NVC0_3D_CLASS;
1086          break;
1087       }
1088       break;
1089    }
1090    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1091                             &screen->eng3d);
1092    if (ret)
1093       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1094    screen->base.class_3d = obj_class;
1095
1096    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1097    PUSH_DATA (push, screen->eng3d->oclass);
1098
1099    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1100    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1101
1102    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1103       /* kill shaders after about 1 second (at 100 MHz) */
1104       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1105       PUSH_DATA (push, 0x17);
1106    }
1107
1108    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1109                     screen->base.drm->version >= 0x01000101);
1110    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1111    for (i = 0; i < 8; ++i)
1112       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1113
1114    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1115    PUSH_DATA (push, 1);
1116
1117    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1118    PUSH_DATA (push, 0);
1119    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1120    PUSH_DATA (push, 0);
1121    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1122    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1123    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1124    PUSH_DATA (push, 0);
1125    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1126    PUSH_DATA (push, 1);
1127    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1128    PUSH_DATA (push, 1);
1129    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1130    PUSH_DATA (push, 1);
1131    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1132    PUSH_DATA (push, 0);
1133    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1134    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1135    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1136       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1137    } else {
1138       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1139       PUSH_DATA (push, 15);
1140    }
1141    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1142    PUSH_DATA (push, 8); /* 128 */
1143    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1144    PUSH_DATA (push, 1);
1145    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1146       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1147       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1148    }
1149
1150    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1151
1152    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1153    if (ret)
1154       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1155
1156    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1157    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1158                         &screen->uniform_bo);
1159    if (ret)
1160       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1161
1162    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1163
1164    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1165    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1166    PUSH_DATA (push, 256);
1167    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1168    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1169    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1170    PUSH_DATA (push, 0);
1171    PUSH_DATAf(push, 0.0f);
1172    PUSH_DATAf(push, 0.0f);
1173    PUSH_DATAf(push, 0.0f);
1174    PUSH_DATAf(push, 0.0f);
1175    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1176    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1177    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1178
1179    if (screen->base.drm->version >= 0x01000101) {
1180       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1181       if (ret)
1182          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1183    } else {
1184       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1185          value = (8 << 8) | 4;
1186       else
1187          value = (16 << 8) | 4;
1188    }
1189    screen->gpc_count = value & 0x000000ff;
1190    screen->mp_count = value >> 8;
1191    screen->mp_count_compute = screen->mp_count;
1192
1193    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1194    if (ret)
1195       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1196
1197    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1198    PUSH_DATAh(push, screen->tls->offset);
1199    PUSH_DATA (push, screen->tls->offset);
1200    PUSH_DATA (push, screen->tls->size >> 32);
1201    PUSH_DATA (push, screen->tls->size);
1202    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1203    PUSH_DATA (push, 0);
1204    /* Reduce likelihood of collision with real buffers by placing the hole at
1205     * the top of the 4G area. This will have to be dealt with for real
1206     * eventually by blocking off that area from the VM.
1207     */
1208    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1209    PUSH_DATA (push, 0xff << 24);
1210
1211    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1212       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1213                            &screen->poly_cache);
1214       if (ret)
1215          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1216
1217       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1218       PUSH_DATAh(push, screen->poly_cache->offset);
1219       PUSH_DATA (push, screen->poly_cache->offset);
1220       PUSH_DATA (push, 3);
1221    }
1222
1223    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1224                         &screen->txc);
1225    if (ret)
1226       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1227
1228    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1229    PUSH_DATAh(push, screen->txc->offset);
1230    PUSH_DATA (push, screen->txc->offset);
1231    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1232    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1233       screen->tic.maxwell = true;
1234       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1235          screen->tic.maxwell =
1236             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1237          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1238       }
1239    }
1240
1241    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1242    PUSH_DATAh(push, screen->txc->offset + 65536);
1243    PUSH_DATA (push, screen->txc->offset + 65536);
1244    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1245
1246    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1247    PUSH_DATA (push, 0);
1248    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1249    PUSH_DATA (push, 0);
1250    PUSH_DATA (push, 0);
1251    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1252    PUSH_DATA (push, 0x3f);
1253
1254    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1255    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1256    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1257    for (i = 0; i < 8 * 2; ++i)
1258       PUSH_DATA(push, 0);
1259    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1260    PUSH_DATA (push, 0);
1261    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1262    PUSH_DATA (push, 0);
1263
1264    /* neither scissors, viewport nor stencil mask should affect clears */
1265    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1266    PUSH_DATA (push, 0);
1267
1268    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1269    PUSH_DATA (push, 1);
1270    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1271       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1272       PUSH_DATAf(push, 0.0f);
1273       PUSH_DATAf(push, 1.0f);
1274    }
1275    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1276    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1277
1278    /* We use scissors instead of exact view volume clipping,
1279     * so they're always enabled.
1280     */
1281    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1282       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1283       PUSH_DATA (push, 1);
1284       PUSH_DATA (push, 8192 << 16);
1285       PUSH_DATA (push, 8192 << 16);
1286    }
1287
1288 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1289
1290    i = 0;
1291    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1292    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1293    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1294    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1295    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1296    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1297    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1298    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1299    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1300    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1301    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1302    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1303    MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1304    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1305
1306    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1307    PUSH_DATA (push, 1);
1308    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1309    PUSH_DATA (push, 1);
1310    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1311    PUSH_DATA (push, 0x40);
1312    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1313    PUSH_DATA (push, 0);
1314    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1315    PUSH_DATA (push, 0x30);
1316    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1317    PUSH_DATA (push, 3);
1318    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1319    PUSH_DATA (push, 0x20);
1320    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1321    PUSH_DATA (push, 0x00);
1322    screen->save_state.patch_vertices = 3;
1323
1324    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1325    PUSH_DATA (push, 0);
1326    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1327    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1328
1329    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1330
1331    if (nvc0_screen_init_compute(screen))
1332       goto fail;
1333
1334    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1335    for (i = 0; i < 5; ++i) {
1336       unsigned j = 0;
1337       for (j = 0; j < 16; j++)
1338          screen->cb_bindings[i][j].size = -1;
1339
1340       /* TIC and TSC entries for each unit (nve4+ only) */
1341       /* auxiliary constants (6 user clip planes, base instance id) */
1342       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1343                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1344       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1345          unsigned j;
1346          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1347          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1348          for (j = 0; j < 8; ++j)
1349             PUSH_DATA(push, j);
1350       } else {
1351          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1352          PUSH_DATA (push, 0x54);
1353       }
1354
1355       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1356       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1357       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1358       PUSH_DATA (push, 0); /* 0 */
1359       PUSH_DATA (push, 0);
1360       PUSH_DATA (push, 1); /* 1 */
1361       PUSH_DATA (push, 0);
1362       PUSH_DATA (push, 0); /* 2 */
1363       PUSH_DATA (push, 1);
1364       PUSH_DATA (push, 1); /* 3 */
1365       PUSH_DATA (push, 1);
1366       PUSH_DATA (push, 2); /* 4 */
1367       PUSH_DATA (push, 0);
1368       PUSH_DATA (push, 3); /* 5 */
1369       PUSH_DATA (push, 0);
1370       PUSH_DATA (push, 2); /* 6 */
1371       PUSH_DATA (push, 1);
1372       PUSH_DATA (push, 3); /* 7 */
1373       PUSH_DATA (push, 1);
1374    }
1375    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1376    PUSH_DATA (push, 0);
1377
1378    PUSH_KICK (push);
1379
1380    screen->tic.entries = CALLOC(
1381          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1382          sizeof(void *));
1383    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1384    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1385
1386    if (!nvc0_blitter_create(screen))
1387       goto fail;
1388
1389    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1390
1391    return &screen->base;
1392
1393 fail:
1394    screen->base.base.context_create = NULL;
1395    return &screen->base;
1396 }
1397
1398 int
1399 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1400 {
1401    int i = screen->tic.next;
1402
1403    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1404       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1405
1406    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1407
1408    if (screen->tic.entries[i])
1409       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1410
1411    screen->tic.entries[i] = entry;
1412    return i;
1413 }
1414
1415 int
1416 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1417 {
1418    int i = screen->tsc.next;
1419
1420    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1421       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1422
1423    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1424
1425    if (screen->tsc.entries[i])
1426       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1427
1428    screen->tsc.entries[i] = entry;
1429    return i;
1430 }