src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/mme/com9097.mme.h"
  36 #include "nvc0/mme/com90c0.mme.h"
  37
  38 #include "nv50/g80_texture.xml.h"
  39
  40 static boolean
  41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  42                                 enum pipe_format format,
  43                                 enum pipe_texture_target target,
  44                                 unsigned sample_count,
  45                                 unsigned bindings)
  46 {
  47    const struct util_format_description *desc = util_format_description(format);
  48
  49    if (sample_count > 8)
  50       return false;
  51    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  52       return false;
  53
  54    /* Short-circuit the rest of the logic -- this is used by the state tracker
  55     * to determine valid MS levels in a no-attachments scenario.
  56     */
  57    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  58       return true;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return false;
  62
  63    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  64       if (util_format_get_blocksizebits(format) == 3 * 32)
  65          return false;
  66
  67    if (bindings & PIPE_BIND_LINEAR)
  68       if (util_format_is_depth_or_stencil(format) ||
  69           (target != PIPE_TEXTURE_1D &&
  70            target != PIPE_TEXTURE_2D &&
  71            target != PIPE_TEXTURE_RECT) ||
  72           sample_count > 1)
  73          return false;
  74
  75    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  76     */
  77    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  78         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  79        /* The claim is that this should work on GM107 but it doesn't. Need to
  80         * test further and figure out if it's a nouveau issue or a HW one.
  81        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  82         */
  83        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  84       return false;
  85
  86    /* shared is always supported */
  87    bindings &= ~(PIPE_BIND_LINEAR |
  88                  PIPE_BIND_SHARED);
  89
  90    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  91       if (sample_count > 0 &&
  92           nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  93          /* MS images are currently unsupported on Maxwell because they have to
  94           * be handled explicitly. */
  95          return false;
  96       }
  97
  98       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  99           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
 100          /* This should work on Fermi, but for currently unknown reasons it
 101           * does not and results in breaking reads from pbos. */
 102          return false;
 103       }
 104    }
 105
 106    return (( nvc0_format_table[format].usage |
 107             nvc0_vertex_format[format].usage) & bindings) == bindings;
 108 }
 109
 110 static int
 111 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 112 {
 113    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 114    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 115
 116    switch (param) {
 117    /* non-boolean caps */
 118    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 119    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 120       return 15;
 121    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 122       return 12;
 123    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 124       return 2048;
 125    case PIPE_CAP_MIN_TEXEL_OFFSET:
 126       return -8;
 127    case PIPE_CAP_MAX_TEXEL_OFFSET:
 128       return 7;
 129    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 130       return -32;
 131    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 132       return 31;
 133    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 134       return 128 * 1024 * 1024;
 135    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 136       return 430;
 137    case PIPE_CAP_MAX_RENDER_TARGETS:
 138       return 8;
 139    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 140       return 1;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 145       return 128;
 146    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 147    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 148       return 1024;
 149    case PIPE_CAP_MAX_VERTEX_STREAMS:
 150       return 4;
 151    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 152       return 2048;
 153    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 154       return 256;
 155    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 156       if (class_3d < GM107_3D_CLASS)
 157          return 256; /* IMAGE bindings require alignment to 256 */
 158       return 16;
 159    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 160       return 16;
 161    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 162       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 163    case PIPE_CAP_MAX_VIEWPORTS:
 164       return NVC0_MAX_VIEWPORTS;
 165    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 166       return 4;
 167    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 168       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 169    case PIPE_CAP_ENDIANNESS:
 170       return PIPE_ENDIAN_LITTLE;
 171    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 172       return 30;
 173    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 174       return NVC0_MAX_WINDOW_RECTANGLES;
 175
 176    /* supported caps */
 177    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 178    case PIPE_CAP_TEXTURE_SWIZZLE:
 179    case PIPE_CAP_NPOT_TEXTURES:
 180    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 181    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 182    case PIPE_CAP_ANISOTROPIC_FILTER:
 183    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 184    case PIPE_CAP_CUBE_MAP_ARRAY:
 185    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 186    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 187    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 188    case PIPE_CAP_POINT_SPRITE:
 189    case PIPE_CAP_TGSI_TEXCOORD:
 190    case PIPE_CAP_SM3:
 191    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 192    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 193    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 194    case PIPE_CAP_QUERY_TIMESTAMP:
 195    case PIPE_CAP_QUERY_TIME_ELAPSED:
 196    case PIPE_CAP_OCCLUSION_QUERY:
 197    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 198    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 199    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 200    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 201    case PIPE_CAP_INDEP_BLEND_ENABLE:
 202    case PIPE_CAP_INDEP_BLEND_FUNC:
 203    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 204    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 205    case PIPE_CAP_PRIMITIVE_RESTART:
 206    case PIPE_CAP_TGSI_INSTANCEID:
 207    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 208    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 209    case PIPE_CAP_CONDITIONAL_RENDER:
 210    case PIPE_CAP_TEXTURE_BARRIER:
 211    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 212    case PIPE_CAP_START_INSTANCE:
 213    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 214    case PIPE_CAP_DRAW_INDIRECT:
 215    case PIPE_CAP_USER_VERTEX_BUFFERS:
 216    case PIPE_CAP_TEXTURE_QUERY_LOD:
 217    case PIPE_CAP_SAMPLE_SHADING:
 218    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 219    case PIPE_CAP_TEXTURE_GATHER_SM5:
 220    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 221    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 222    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 223    case PIPE_CAP_CLIP_HALFZ:
 224    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 225    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 226    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 227    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 228    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 229    case PIPE_CAP_TGSI_TXQS:
 230    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 231    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 232    case PIPE_CAP_SHAREABLE_SHADERS:
 233    case PIPE_CAP_CLEAR_TEXTURE:
 234    case PIPE_CAP_DRAW_PARAMETERS:
 235    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 236    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 237    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 238    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 239    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 240    case PIPE_CAP_INVALIDATE_BUFFER:
 241    case PIPE_CAP_STRING_MARKER:
 242    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 243    case PIPE_CAP_CULL_DISTANCE:
 244    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 245    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 246    case PIPE_CAP_TGSI_VOTE:
 247    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 248    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 249    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 250    case PIPE_CAP_DOUBLES:
 251    case PIPE_CAP_INT64:
 252    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 253    case PIPE_CAP_TGSI_CLOCK:
 254    case PIPE_CAP_COMPUTE:
 255    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 256    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 257       return 1;
 258    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 259       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 260    case PIPE_CAP_TGSI_FS_FBFETCH:
 261       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 262    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 263    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 264    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 265    case PIPE_CAP_POST_DEPTH_COVERAGE:
 266       return class_3d >= GM200_3D_CLASS;
 267    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 268    case PIPE_CAP_TGSI_BALLOT:
 269       return class_3d >= NVE4_3D_CLASS;
 270    case PIPE_CAP_BINDLESS_TEXTURE:
 271       return class_3d >= NVE4_3D_CLASS && class_3d < GM107_3D_CLASS;
 272
 273    /* unsupported caps */
 274    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 275    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 276    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 277    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 278    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 279    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 280    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 281    case PIPE_CAP_FAKE_SW_MSAA:
 282    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 283    case PIPE_CAP_VERTEXID_NOBASE:
 284    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 285    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 286    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 287    case PIPE_CAP_GENERATE_MIPMAP:
 288    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 289    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 290    case PIPE_CAP_QUERY_MEMORY_INFO:
 291    case PIPE_CAP_PCI_GROUP:
 292    case PIPE_CAP_PCI_BUS:
 293    case PIPE_CAP_PCI_DEVICE:
 294    case PIPE_CAP_PCI_FUNCTION:
 295    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 296    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 297    case PIPE_CAP_NATIVE_FENCE_FD:
 298    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 299    case PIPE_CAP_INT64_DIVMOD:
 300    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 301    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 302    case PIPE_CAP_QUERY_SO_OVERFLOW:
 303    case PIPE_CAP_MEMOBJ:
 304    case PIPE_CAP_LOAD_CONSTBUF:
 305    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 306    case PIPE_CAP_TILE_RASTER_ORDER:
 307    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 308    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 309    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 310    case PIPE_CAP_FENCE_SIGNAL:
 311    case PIPE_CAP_CONSTBUF0_FLAGS:
 312       return 0;
 313
 314    case PIPE_CAP_VENDOR_ID:
 315       return 0x10de;
 316    case PIPE_CAP_DEVICE_ID: {
 317       uint64_t device_id;
 318       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 319          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 320          return -1;
 321       }
 322       return device_id;
 323    }
 324    case PIPE_CAP_ACCELERATED:
 325       return 1;
 326    case PIPE_CAP_VIDEO_MEMORY:
 327       return dev->vram_size >> 20;
 328    case PIPE_CAP_UMA:
 329       return 0;
 330    }
 331
 332    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 333    return 0;
 334 }
 335
 336 static int
 337 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 338                              enum pipe_shader_type shader,
 339                              enum pipe_shader_cap param)
 340 {
 341    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 342
 343    switch (shader) {
 344    case PIPE_SHADER_VERTEX:
 345    case PIPE_SHADER_GEOMETRY:
 346    case PIPE_SHADER_FRAGMENT:
 347    case PIPE_SHADER_COMPUTE:
 348    case PIPE_SHADER_TESS_CTRL:
 349    case PIPE_SHADER_TESS_EVAL:
 350       break;
 351    default:
 352       return 0;
 353    }
 354
 355    switch (param) {
 356    case PIPE_SHADER_CAP_PREFERRED_IR:
 357       return PIPE_SHADER_IR_TGSI;
 358    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 359       return 1 << PIPE_SHADER_IR_TGSI;
 360    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 361    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 362    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 363    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 364       return 16384;
 365    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 366       return 16;
 367    case PIPE_SHADER_CAP_MAX_INPUTS:
 368       if (shader == PIPE_SHADER_VERTEX)
 369          return 32;
 370       /* NOTE: These only count our slots for GENERIC varyings.
 371        * The address space may be larger, but the actual hard limit seems to be
 372        * less than what the address space layout permits, so don't add TEXCOORD,
 373        * COLOR, etc. here.
 374        */
 375       if (shader == PIPE_SHADER_FRAGMENT)
 376          return 0x1f0 / 16;
 377       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 378        * and excludes 0x60 per-patch inputs.
 379        */
 380       return 0x200 / 16;
 381    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 382       return 32;
 383    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 384       return 65536;
 385    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 386       return NVC0_MAX_PIPE_CONSTBUFS;
 387    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 388       return shader != PIPE_SHADER_FRAGMENT;
 389    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 390    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 391    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 392       return 1;
 393    case PIPE_SHADER_CAP_MAX_TEMPS:
 394       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 395    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 396       return 1;
 397    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 398       return 1;
 399    case PIPE_SHADER_CAP_SUBROUTINES:
 400       return 1;
 401    case PIPE_SHADER_CAP_INTEGERS:
 402       return 1;
 403    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 404       return 1;
 405    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 406       return 1;
 407    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 408       return 1;
 409    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 410    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 411    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 412    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 413    case PIPE_SHADER_CAP_INT64_ATOMICS:
 414    case PIPE_SHADER_CAP_FP16:
 415    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 416    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 417       return 0;
 418    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 419       return NVC0_MAX_BUFFERS;
 420    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 421       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 422    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 423       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 424    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 425       return 32;
 426    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 427       if (class_3d >= NVE4_3D_CLASS)
 428          return NVC0_MAX_IMAGES;
 429       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 430          return NVC0_MAX_IMAGES;
 431       return 0;
 432    default:
 433       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 434       return 0;
 435    }
 436 }
 437
 438 static float
 439 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 440 {
 441    switch (param) {
 442    case PIPE_CAPF_MAX_LINE_WIDTH:
 443    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 444       return 10.0f;
 445    case PIPE_CAPF_MAX_POINT_WIDTH:
 446       return 63.0f;
 447    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 448       return 63.375f;
 449    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 450       return 16.0f;
 451    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 452       return 15.0f;
 453    }
 454
 455    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 456    return 0.0f;
 457 }
 458
 459 static int
 460 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 461                               enum pipe_shader_ir ir_type,
 462                               enum pipe_compute_cap param, void *data)
 463 {
 464    struct nvc0_screen *screen = nvc0_screen(pscreen);
 465    const uint16_t obj_class = screen->compute->oclass;
 466
 467 #define RET(x) do {                  \
 468    if (data)                         \
 469       memcpy(data, x, sizeof(x));    \
 470    return sizeof(x);                 \
 471 } while (0)
 472
 473    switch (param) {
 474    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 475       RET((uint64_t []) { 3 });
 476    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 477       if (obj_class >= NVE4_COMPUTE_CLASS) {
 478          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 479       } else {
 480          RET(((uint64_t []) { 65535, 65535, 65535 }));
 481       }
 482    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 483       RET(((uint64_t []) { 1024, 1024, 64 }));
 484    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 485       RET((uint64_t []) { 1024 });
 486    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 487       if (obj_class >= NVE4_COMPUTE_CLASS) {
 488          RET((uint64_t []) { 1024 });
 489       } else {
 490          RET((uint64_t []) { 512 });
 491       }
 492    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 493       RET((uint64_t []) { 1ULL << 40 });
 494    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 495       switch (obj_class) {
 496       case GM200_COMPUTE_CLASS:
 497          RET((uint64_t []) { 96 << 10 });
 498          break;
 499       case GM107_COMPUTE_CLASS:
 500          RET((uint64_t []) { 64 << 10 });
 501          break;
 502       default:
 503          RET((uint64_t []) { 48 << 10 });
 504          break;
 505       }
 506    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 507       RET((uint64_t []) { 512 << 10 });
 508    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 509       RET((uint64_t []) { 4096 });
 510    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 511       RET((uint32_t []) { 32 });
 512    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 513       RET((uint64_t []) { 1ULL << 40 });
 514    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 515       RET((uint32_t []) { 0 });
 516    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 517       RET((uint32_t []) { screen->mp_count_compute });
 518    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 519       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 520    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 521       RET((uint32_t []) { 64 });
 522    default:
 523       return 0;
 524    }
 525
 526 #undef RET
 527 }
 528
 529 static void
 530 nvc0_screen_destroy(struct pipe_screen *pscreen)
 531 {
 532    struct nvc0_screen *screen = nvc0_screen(pscreen);
 533
 534    if (!nouveau_drm_screen_unref(&screen->base))
 535       return;
 536
 537    if (screen->base.fence.current) {
 538       struct nouveau_fence *current = NULL;
 539
 540       /* nouveau_fence_wait will create a new current fence, so wait on the
 541        * _current_ one, and remove both.
 542        */
 543       nouveau_fence_ref(screen->base.fence.current, &current);
 544       nouveau_fence_wait(current, NULL);
 545       nouveau_fence_ref(NULL, &current);
 546       nouveau_fence_ref(NULL, &screen->base.fence.current);
 547    }
 548    if (screen->base.pushbuf)
 549       screen->base.pushbuf->user_priv = NULL;
 550
 551    if (screen->blitter)
 552       nvc0_blitter_destroy(screen);
 553    if (screen->pm.prog) {
 554       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 555       nvc0_program_destroy(NULL, screen->pm.prog);
 556       FREE(screen->pm.prog);
 557    }
 558
 559    nouveau_bo_ref(NULL, &screen->text);
 560    nouveau_bo_ref(NULL, &screen->uniform_bo);
 561    nouveau_bo_ref(NULL, &screen->tls);
 562    nouveau_bo_ref(NULL, &screen->txc);
 563    nouveau_bo_ref(NULL, &screen->fence.bo);
 564    nouveau_bo_ref(NULL, &screen->poly_cache);
 565
 566    nouveau_heap_destroy(&screen->lib_code);
 567    nouveau_heap_destroy(&screen->text_heap);
 568
 569    FREE(screen->default_tsc);
 570    FREE(screen->tic.entries);
 571
 572    nouveau_object_del(&screen->eng3d);
 573    nouveau_object_del(&screen->eng2d);
 574    nouveau_object_del(&screen->m2mf);
 575    nouveau_object_del(&screen->compute);
 576    nouveau_object_del(&screen->nvsw);
 577
 578    nouveau_screen_fini(&screen->base);
 579
 580    FREE(screen);
 581 }
 582
 583 static int
 584 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 585                      unsigned size, const uint32_t *data)
 586 {
 587    struct nouveau_pushbuf *push = screen->base.pushbuf;
 588
 589    size /= 4;
 590
 591    assert((pos + size) <= 0x800);
 592
 593    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 594    PUSH_DATA (push, (m - 0x3800) / 8);
 595    PUSH_DATA (push, pos);
 596    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 597    PUSH_DATA (push, pos);
 598    PUSH_DATAp(push, data, size);
 599
 600    return pos + size;
 601 }
 602
 603 static void
 604 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 605 {
 606    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 607    PUSH_DATA (push, 0xff);
 608    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 609    PUSH_DATA (push, 0xff);
 610    PUSH_DATA (push, 0xff);
 611    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 612    PUSH_DATA (push, 0xff);
 613    PUSH_DATA (push, 0xff);
 614    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 615    PUSH_DATA (push, 0x3f);
 616
 617    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 618    PUSH_DATA (push, (3 << 16) | 3);
 619    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 620    PUSH_DATA (push, (2 << 16) | 2);
 621
 622    if (obj_class < GM107_3D_CLASS) {
 623       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 624       PUSH_DATA (push, 0);
 625    }
 626    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 627    PUSH_DATA (push, 0x10);
 628    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 629    PUSH_DATA (push, 0x10);
 630    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 631    PUSH_DATA (push, 0x10);
 632    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 633    PUSH_DATA (push, 0x10);
 634    PUSH_DATA (push, 0x10);
 635    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 636    PUSH_DATA (push, 0x10);
 637    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 638    PUSH_DATA (push, 0xe);
 639
 640    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 641    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 642    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 643    PUSH_DATA (push, 0);
 644    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 645    PUSH_DATA (push, 3);
 646
 647    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 648    PUSH_DATA (push, 0x3fffff);
 649    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 650    PUSH_DATA (push, 1);
 651    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 652    PUSH_DATA (push, 1);
 653
 654    if (obj_class < GM107_3D_CLASS) {
 655       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 656       PUSH_DATA (push, 3);
 657
 658       if (obj_class >= NVE4_3D_CLASS) {
 659          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 660          PUSH_DATA (push, 1);
 661       }
 662    }
 663
 664    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 665     * are supposed to do */
 666 }
 667
 668 static void
 669 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 670 {
 671    struct nvc0_screen *screen = nvc0_screen(pscreen);
 672    struct nouveau_pushbuf *push = screen->base.pushbuf;
 673
 674    /* we need to do it after possible flush in MARK_RING */
 675    *sequence = ++screen->base.fence.sequence;
 676
 677    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 678    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 679    PUSH_DATAh(push, screen->fence.bo->offset);
 680    PUSH_DATA (push, screen->fence.bo->offset);
 681    PUSH_DATA (push, *sequence);
 682    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 683               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 684 }
 685
 686 static u32
 687 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 688 {
 689    struct nvc0_screen *screen = nvc0_screen(pscreen);
 690    return screen->fence.map[0];
 691 }
 692
 693 static int
 694 nvc0_screen_init_compute(struct nvc0_screen *screen)
 695 {
 696    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 697
 698    switch (screen->base.device->chipset & ~0xf) {
 699    case 0xc0:
 700    case 0xd0:
 701       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 702    case 0xe0:
 703    case 0xf0:
 704    case 0x100:
 705    case 0x110:
 706    case 0x120:
 707    case 0x130:
 708       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 709    default:
 710       return -1;
 711    }
 712 }
 713
 714 static int
 715 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 716                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 717 {
 718    struct nouveau_bo *bo = NULL;
 719    int ret;
 720    uint64_t size = (lpos + lneg) * 32 + cstack;
 721
 722    if (size >= (1 << 20)) {
 723       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 724       return -1;
 725    }
 726
 727    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 728    size  = align(size, 0x8000);
 729    size *= screen->mp_count;
 730
 731    size = align(size, 1 << 17);
 732
 733    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 734                         NULL, &bo);
 735    if (ret)
 736       return ret;
 737
 738    /* Make sure that the pushbuf has acquired a reference to the old tls
 739     * segment, as it may have commands that will reference it.
 740     */
 741    if (screen->tls)
 742       PUSH_REFN(screen->base.pushbuf, screen->tls,
 743                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
 744    nouveau_bo_ref(NULL, &screen->tls);
 745    screen->tls = bo;
 746    return 0;
 747 }
 748
 749 int
 750 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 751 {
 752    struct nouveau_pushbuf *push = screen->base.pushbuf;
 753    struct nouveau_bo *bo;
 754    int ret;
 755
 756    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 757                         1 << 17, size, NULL, &bo);
 758    if (ret)
 759       return ret;
 760
 761    /* Make sure that the pushbuf has acquired a reference to the old text
 762     * segment, as it may have commands that will reference it.
 763     */
 764    if (screen->text)
 765       PUSH_REFN(push, screen->text,
 766                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
 767    nouveau_bo_ref(NULL, &screen->text);
 768    screen->text = bo;
 769
 770    nouveau_heap_destroy(&screen->lib_code);
 771    nouveau_heap_destroy(&screen->text_heap);
 772
 773    /* XXX: getting a page fault at the end of the code buffer every few
 774     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 775     */
 776    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 777
 778    /* update the code segment setup */
 779    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 780    PUSH_DATAh(push, screen->text->offset);
 781    PUSH_DATA (push, screen->text->offset);
 782    if (screen->compute) {
 783       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 784       PUSH_DATAh(push, screen->text->offset);
 785       PUSH_DATA (push, screen->text->offset);
 786    }
 787
 788    return 0;
 789 }
 790
 791 #define FAIL_SCREEN_INIT(str, err)                    \
 792    do {                                               \
 793       NOUVEAU_ERR(str, err);                          \
 794       goto fail;                                      \
 795    } while(0)
 796
 797 struct nouveau_screen *
 798 nvc0_screen_create(struct nouveau_device *dev)
 799 {
 800    struct nvc0_screen *screen;
 801    struct pipe_screen *pscreen;
 802    struct nouveau_object *chan;
 803    struct nouveau_pushbuf *push;
 804    uint64_t value;
 805    uint32_t obj_class;
 806    uint32_t flags;
 807    int ret;
 808    unsigned i;
 809
 810    switch (dev->chipset & ~0xf) {
 811    case 0xc0:
 812    case 0xd0:
 813    case 0xe0:
 814    case 0xf0:
 815    case 0x100:
 816    case 0x110:
 817    case 0x120:
 818    case 0x130:
 819       break;
 820    default:
 821       return NULL;
 822    }
 823
 824    screen = CALLOC_STRUCT(nvc0_screen);
 825    if (!screen)
 826       return NULL;
 827    pscreen = &screen->base.base;
 828    pscreen->destroy = nvc0_screen_destroy;
 829
 830    ret = nouveau_screen_init(&screen->base, dev);
 831    if (ret)
 832       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 833    chan = screen->base.channel;
 834    push = screen->base.pushbuf;
 835    push->user_priv = screen;
 836    push->rsvd_kick = 5;
 837
 838    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 839       PIPE_BIND_SHADER_BUFFER |
 840       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 841       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 842    screen->base.sysmem_bindings |=
 843       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 844
 845    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 846       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 847       screen->base.vidmem_bindings = 0;
 848    }
 849
 850    pscreen->context_create = nvc0_create;
 851    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 852    pscreen->get_param = nvc0_screen_get_param;
 853    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 854    pscreen->get_paramf = nvc0_screen_get_paramf;
 855    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 856    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 857
 858    nvc0_screen_init_resource_functions(pscreen);
 859
 860    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 861    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 862
 863    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 864    if (screen->base.drm->version >= 0x01000202)
 865       flags |= NOUVEAU_BO_COHERENT;
 866
 867    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 868    if (ret)
 869       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 870    nouveau_bo_map(screen->fence.bo, 0, NULL);
 871    screen->fence.map = screen->fence.bo->map;
 872    screen->base.fence.emit = nvc0_screen_fence_emit;
 873    screen->base.fence.update = nvc0_screen_fence_update;
 874
 875
 876    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 877                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 878    if (ret)
 879       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 880
 881    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 882    PUSH_DATA (push, screen->nvsw->handle);
 883
 884    switch (dev->chipset & ~0xf) {
 885    case 0x130:
 886    case 0x120:
 887    case 0x110:
 888    case 0x100:
 889    case 0xf0:
 890       obj_class = NVF0_P2MF_CLASS;
 891       break;
 892    case 0xe0:
 893       obj_class = NVE4_P2MF_CLASS;
 894       break;
 895    default:
 896       obj_class = NVC0_M2MF_CLASS;
 897       break;
 898    }
 899    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 900                             &screen->m2mf);
 901    if (ret)
 902       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 903
 904    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 905    PUSH_DATA (push, screen->m2mf->oclass);
 906    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 907       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 908       PUSH_DATA (push, 0xa0b5);
 909    }
 910
 911    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 912                             &screen->eng2d);
 913    if (ret)
 914       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 915
 916    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 917    PUSH_DATA (push, screen->eng2d->oclass);
 918    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 919    PUSH_DATA (push, 0);
 920    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 921    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 922    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 923    PUSH_DATA (push, 0);
 924    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 925    PUSH_DATA (push, 0);
 926    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 927    PUSH_DATA (push, 0x3f);
 928    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 929    PUSH_DATA (push, 1);
 930    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 931    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 932
 933    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 934    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 935    PUSH_DATA (push, screen->fence.bo->offset + 16);
 936
 937    switch (dev->chipset & ~0xf) {
 938    case 0x130:
 939       switch (dev->chipset) {
 940       case 0x130:
 941       case 0x13b:
 942          obj_class = GP100_3D_CLASS;
 943          break;
 944       default:
 945          obj_class = GP102_3D_CLASS;
 946          break;
 947       }
 948       break;
 949    case 0x120:
 950       obj_class = GM200_3D_CLASS;
 951       break;
 952    case 0x110:
 953       obj_class = GM107_3D_CLASS;
 954       break;
 955    case 0x100:
 956    case 0xf0:
 957       obj_class = NVF0_3D_CLASS;
 958       break;
 959    case 0xe0:
 960       switch (dev->chipset) {
 961       case 0xea:
 962          obj_class = NVEA_3D_CLASS;
 963          break;
 964       default:
 965          obj_class = NVE4_3D_CLASS;
 966          break;
 967       }
 968       break;
 969    case 0xd0:
 970       obj_class = NVC8_3D_CLASS;
 971       break;
 972    case 0xc0:
 973    default:
 974       switch (dev->chipset) {
 975       case 0xc8:
 976          obj_class = NVC8_3D_CLASS;
 977          break;
 978       case 0xc1:
 979          obj_class = NVC1_3D_CLASS;
 980          break;
 981       default:
 982          obj_class = NVC0_3D_CLASS;
 983          break;
 984       }
 985       break;
 986    }
 987    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 988                             &screen->eng3d);
 989    if (ret)
 990       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 991    screen->base.class_3d = obj_class;
 992
 993    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 994    PUSH_DATA (push, screen->eng3d->oclass);
 995
 996    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 997    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 998
 999    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1000       /* kill shaders after about 1 second (at 100 MHz) */
1001       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1002       PUSH_DATA (push, 0x17);
1003    }
1004
1005    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1006                     screen->base.drm->version >= 0x01000101);
1007    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1008    for (i = 0; i < 8; ++i)
1009       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1010
1011    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1012    PUSH_DATA (push, 1);
1013
1014    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1015    PUSH_DATA (push, 0);
1016    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1017    PUSH_DATA (push, 0);
1018    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1019    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1020    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1021    PUSH_DATA (push, 0);
1022    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1023    PUSH_DATA (push, 1);
1024    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1025    PUSH_DATA (push, 1);
1026    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1027    PUSH_DATA (push, 1);
1028    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1029    PUSH_DATA (push, 0);
1030    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1031    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1032    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1033       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1034    } else {
1035       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1036       PUSH_DATA (push, 15);
1037    }
1038    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1039    PUSH_DATA (push, 8); /* 128 */
1040    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1041    PUSH_DATA (push, 1);
1042    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1043       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1044       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1045    }
1046
1047    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1048
1049    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1050    if (ret)
1051       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1052
1053    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1054    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1055                         &screen->uniform_bo);
1056    if (ret)
1057       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1058
1059    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1060
1061    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1062    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1063    PUSH_DATA (push, 256);
1064    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1065    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1066    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1067    PUSH_DATA (push, 0);
1068    PUSH_DATAf(push, 0.0f);
1069    PUSH_DATAf(push, 0.0f);
1070    PUSH_DATAf(push, 0.0f);
1071    PUSH_DATAf(push, 0.0f);
1072    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1073    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1074    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1075
1076    if (screen->base.drm->version >= 0x01000101) {
1077       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1078       if (ret)
1079          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1080    } else {
1081       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1082          value = (8 << 8) | 4;
1083       else
1084          value = (16 << 8) | 4;
1085    }
1086    screen->gpc_count = value & 0x000000ff;
1087    screen->mp_count = value >> 8;
1088    screen->mp_count_compute = screen->mp_count;
1089
1090    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1091    if (ret)
1092       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1093
1094    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1095    PUSH_DATAh(push, screen->tls->offset);
1096    PUSH_DATA (push, screen->tls->offset);
1097    PUSH_DATA (push, screen->tls->size >> 32);
1098    PUSH_DATA (push, screen->tls->size);
1099    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1100    PUSH_DATA (push, 0);
1101    /* Reduce likelihood of collision with real buffers by placing the hole at
1102     * the top of the 4G area. This will have to be dealt with for real
1103     * eventually by blocking off that area from the VM.
1104     */
1105    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1106    PUSH_DATA (push, 0xff << 24);
1107
1108    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1109       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1110                            &screen->poly_cache);
1111       if (ret)
1112          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1113
1114       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1115       PUSH_DATAh(push, screen->poly_cache->offset);
1116       PUSH_DATA (push, screen->poly_cache->offset);
1117       PUSH_DATA (push, 3);
1118    }
1119
1120    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1121                         &screen->txc);
1122    if (ret)
1123       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1124
1125    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1126    PUSH_DATAh(push, screen->txc->offset);
1127    PUSH_DATA (push, screen->txc->offset);
1128    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1129    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1130       screen->tic.maxwell = true;
1131       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1132          screen->tic.maxwell =
1133             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1134          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1135       }
1136    }
1137
1138    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1139    PUSH_DATAh(push, screen->txc->offset + 65536);
1140    PUSH_DATA (push, screen->txc->offset + 65536);
1141    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1142
1143    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1144    PUSH_DATA (push, 0);
1145    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1146    PUSH_DATA (push, 0);
1147    PUSH_DATA (push, 0);
1148    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1149    PUSH_DATA (push, 0x3f);
1150
1151    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1152    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1153    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1154    for (i = 0; i < 8 * 2; ++i)
1155       PUSH_DATA(push, 0);
1156    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1157    PUSH_DATA (push, 0);
1158    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1159    PUSH_DATA (push, 0);
1160
1161    /* neither scissors, viewport nor stencil mask should affect clears */
1162    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1163    PUSH_DATA (push, 0);
1164
1165    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1166    PUSH_DATA (push, 1);
1167    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1168       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1169       PUSH_DATAf(push, 0.0f);
1170       PUSH_DATAf(push, 1.0f);
1171    }
1172    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1173    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1174
1175    /* We use scissors instead of exact view volume clipping,
1176     * so they're always enabled.
1177     */
1178    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1179       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1180       PUSH_DATA (push, 1);
1181       PUSH_DATA (push, 8192 << 16);
1182       PUSH_DATA (push, 8192 << 16);
1183    }
1184
1185 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1186
1187    i = 0;
1188    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1189    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1190    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1191    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1192    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1193    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1194    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1195    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1196    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1197    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1198    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1199    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1200    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1201
1202    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1203    PUSH_DATA (push, 1);
1204    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1205    PUSH_DATA (push, 1);
1206    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1207    PUSH_DATA (push, 0x40);
1208    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1209    PUSH_DATA (push, 0);
1210    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1211    PUSH_DATA (push, 0x30);
1212    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1213    PUSH_DATA (push, 3);
1214    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1215    PUSH_DATA (push, 0x20);
1216    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1217    PUSH_DATA (push, 0x00);
1218    screen->save_state.patch_vertices = 3;
1219
1220    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1221    PUSH_DATA (push, 0);
1222    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1223    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1224
1225    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1226
1227    if (nvc0_screen_init_compute(screen))
1228       goto fail;
1229
1230    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1231    for (i = 0; i < 5; ++i) {
1232       /* TIC and TSC entries for each unit (nve4+ only) */
1233       /* auxiliary constants (6 user clip planes, base instance id) */
1234       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1235       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1236       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1237       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1238       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1239       PUSH_DATA (push, (15 << 4) | 1);
1240       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1241          unsigned j;
1242          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1243          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1244          for (j = 0; j < 8; ++j)
1245             PUSH_DATA(push, j);
1246       } else {
1247          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1248          PUSH_DATA (push, 0x54);
1249       }
1250
1251       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1252       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1253       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1254       PUSH_DATA (push, 0); /* 0 */
1255       PUSH_DATA (push, 0);
1256       PUSH_DATA (push, 1); /* 1 */
1257       PUSH_DATA (push, 0);
1258       PUSH_DATA (push, 0); /* 2 */
1259       PUSH_DATA (push, 1);
1260       PUSH_DATA (push, 1); /* 3 */
1261       PUSH_DATA (push, 1);
1262       PUSH_DATA (push, 2); /* 4 */
1263       PUSH_DATA (push, 0);
1264       PUSH_DATA (push, 3); /* 5 */
1265       PUSH_DATA (push, 0);
1266       PUSH_DATA (push, 2); /* 6 */
1267       PUSH_DATA (push, 1);
1268       PUSH_DATA (push, 3); /* 7 */
1269       PUSH_DATA (push, 1);
1270    }
1271    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1272    PUSH_DATA (push, 0);
1273
1274    PUSH_KICK (push);
1275
1276    screen->tic.entries = CALLOC(
1277          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1278          sizeof(void *));
1279    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1280    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1281
1282    if (!nvc0_blitter_create(screen))
1283       goto fail;
1284
1285    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1286    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1287
1288    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1289
1290    return &screen->base;
1291
1292 fail:
1293    screen->base.base.context_create = NULL;
1294    return &screen->base;
1295 }
1296
1297 int
1298 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1299 {
1300    int i = screen->tic.next;
1301
1302    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1303       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1304
1305    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1306
1307    if (screen->tic.entries[i])
1308       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1309
1310    screen->tic.entries[i] = entry;
1311    return i;
1312 }
1313
1314 int
1315 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1316 {
1317    int i = screen->tsc.next;
1318
1319    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1320       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1321
1322    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1323
1324    if (screen->tsc.entries[i])
1325       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1326
1327    screen->tsc.entries[i] = entry;
1328    return i;
1329 }