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nvc0: use PascalB for most Pascal boards
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 #include "nv50/g80_texture.xml.h"
42
43 static boolean
44 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
45 enum pipe_format format,
46 enum pipe_texture_target target,
47 unsigned sample_count,
48 unsigned bindings)
49 {
50 const struct util_format_description *desc = util_format_description(format);
51
52 if (sample_count > 8)
53 return false;
54 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
55 return false;
56
57 /* Short-circuit the rest of the logic -- this is used by the state tracker
58 * to determine valid MS levels in a no-attachments scenario.
59 */
60 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
61 return true;
62
63 if (!util_format_is_supported(format, bindings))
64 return false;
65
66 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
67 if (util_format_get_blocksizebits(format) == 3 * 32)
68 return false;
69
70 if (bindings & PIPE_BIND_LINEAR)
71 if (util_format_is_depth_or_stencil(format) ||
72 (target != PIPE_TEXTURE_1D &&
73 target != PIPE_TEXTURE_2D &&
74 target != PIPE_TEXTURE_RECT) ||
75 sample_count > 1)
76 return false;
77
78 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
79 */
80 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
81 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
82 /* The claim is that this should work on GM107 but it doesn't. Need to
83 * test further and figure out if it's a nouveau issue or a HW one.
84 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
85 */
86 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
87 return false;
88
89 /* shared is always supported */
90 bindings &= ~(PIPE_BIND_LINEAR |
91 PIPE_BIND_SHARED);
92
93 if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
94 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
95 /* MS images are currently unsupported on Maxwell because they have to
96 * be handled explicitly. */
97 return false;
98 }
99
100 return (( nvc0_format_table[format].usage |
101 nvc0_vertex_format[format].usage) & bindings) == bindings;
102 }
103
104 static int
105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
106 {
107 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
108 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
109
110 switch (param) {
111 /* non-boolean caps */
112 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
113 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
114 return 15;
115 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
116 return 12;
117 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
118 return 2048;
119 case PIPE_CAP_MIN_TEXEL_OFFSET:
120 return -8;
121 case PIPE_CAP_MAX_TEXEL_OFFSET:
122 return 7;
123 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
124 return -32;
125 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
126 return 31;
127 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
128 return 128 * 1024 * 1024;
129 case PIPE_CAP_GLSL_FEATURE_LEVEL:
130 return 430;
131 case PIPE_CAP_MAX_RENDER_TARGETS:
132 return 8;
133 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
134 return 1;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
136 return 4;
137 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
138 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
139 return 128;
140 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
141 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
142 return 1024;
143 case PIPE_CAP_MAX_VERTEX_STREAMS:
144 return 4;
145 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
146 return 2048;
147 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
148 return 256;
149 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
150 return 16; /* 256 for binding as RT, but that's not possible in GL */
151 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
152 return 16;
153 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
154 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
155 case PIPE_CAP_MAX_VIEWPORTS:
156 return NVC0_MAX_VIEWPORTS;
157 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
158 return 4;
159 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
160 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
161 case PIPE_CAP_ENDIANNESS:
162 return PIPE_ENDIAN_LITTLE;
163 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
164 return 30;
165 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
166 return NVC0_MAX_WINDOW_RECTANGLES;
167
168 /* supported caps */
169 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
170 case PIPE_CAP_TEXTURE_SWIZZLE:
171 case PIPE_CAP_TEXTURE_SHADOW_MAP:
172 case PIPE_CAP_NPOT_TEXTURES:
173 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
174 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
175 case PIPE_CAP_ANISOTROPIC_FILTER:
176 case PIPE_CAP_SEAMLESS_CUBE_MAP:
177 case PIPE_CAP_CUBE_MAP_ARRAY:
178 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
179 case PIPE_CAP_TEXTURE_MULTISAMPLE:
180 case PIPE_CAP_TWO_SIDED_STENCIL:
181 case PIPE_CAP_DEPTH_CLIP_DISABLE:
182 case PIPE_CAP_POINT_SPRITE:
183 case PIPE_CAP_TGSI_TEXCOORD:
184 case PIPE_CAP_SM3:
185 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
186 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
187 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
188 case PIPE_CAP_QUERY_TIMESTAMP:
189 case PIPE_CAP_QUERY_TIME_ELAPSED:
190 case PIPE_CAP_OCCLUSION_QUERY:
191 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
192 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
193 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
194 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
195 case PIPE_CAP_INDEP_BLEND_ENABLE:
196 case PIPE_CAP_INDEP_BLEND_FUNC:
197 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
198 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
199 case PIPE_CAP_PRIMITIVE_RESTART:
200 case PIPE_CAP_TGSI_INSTANCEID:
201 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
202 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
203 case PIPE_CAP_CONDITIONAL_RENDER:
204 case PIPE_CAP_TEXTURE_BARRIER:
205 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
206 case PIPE_CAP_START_INSTANCE:
207 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
208 case PIPE_CAP_DRAW_INDIRECT:
209 case PIPE_CAP_USER_CONSTANT_BUFFERS:
210 case PIPE_CAP_USER_INDEX_BUFFERS:
211 case PIPE_CAP_USER_VERTEX_BUFFERS:
212 case PIPE_CAP_TEXTURE_QUERY_LOD:
213 case PIPE_CAP_SAMPLE_SHADING:
214 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
215 case PIPE_CAP_TEXTURE_GATHER_SM5:
216 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
217 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
218 case PIPE_CAP_SAMPLER_VIEW_TARGET:
219 case PIPE_CAP_CLIP_HALFZ:
220 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
221 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
222 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
223 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
224 case PIPE_CAP_DEPTH_BOUNDS_TEST:
225 case PIPE_CAP_TGSI_TXQS:
226 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
227 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
228 case PIPE_CAP_SHAREABLE_SHADERS:
229 case PIPE_CAP_CLEAR_TEXTURE:
230 case PIPE_CAP_DRAW_PARAMETERS:
231 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
232 case PIPE_CAP_MULTI_DRAW_INDIRECT:
233 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
234 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
235 case PIPE_CAP_QUERY_BUFFER_OBJECT:
236 case PIPE_CAP_INVALIDATE_BUFFER:
237 case PIPE_CAP_STRING_MARKER:
238 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
239 case PIPE_CAP_CULL_DISTANCE:
240 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
241 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
242 case PIPE_CAP_TGSI_VOTE:
243 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
244 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
245 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
246 case PIPE_CAP_DOUBLES:
247 case PIPE_CAP_INT64:
248 return 1;
249 case PIPE_CAP_COMPUTE:
250 return (class_3d < GP100_3D_CLASS);
251 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
252 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
253 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
254 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
255 case PIPE_CAP_TGSI_FS_FBFETCH:
256 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
257
258 /* unsupported caps */
259 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
260 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
261 case PIPE_CAP_SHADER_STENCIL_EXPORT:
262 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
263 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
264 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
265 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
266 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
267 case PIPE_CAP_FAKE_SW_MSAA:
268 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
269 case PIPE_CAP_VERTEXID_NOBASE:
270 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
271 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
272 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
273 case PIPE_CAP_GENERATE_MIPMAP:
274 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
275 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
276 case PIPE_CAP_QUERY_MEMORY_INFO:
277 case PIPE_CAP_PCI_GROUP:
278 case PIPE_CAP_PCI_BUS:
279 case PIPE_CAP_PCI_DEVICE:
280 case PIPE_CAP_PCI_FUNCTION:
281 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
282 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
283 case PIPE_CAP_NATIVE_FENCE_FD:
284 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
285 case PIPE_CAP_INT64_DIVMOD:
286 return 0;
287
288 case PIPE_CAP_VENDOR_ID:
289 return 0x10de;
290 case PIPE_CAP_DEVICE_ID: {
291 uint64_t device_id;
292 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
293 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
294 return -1;
295 }
296 return device_id;
297 }
298 case PIPE_CAP_ACCELERATED:
299 return 1;
300 case PIPE_CAP_VIDEO_MEMORY:
301 return dev->vram_size >> 20;
302 case PIPE_CAP_UMA:
303 return 0;
304 }
305
306 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
307 return 0;
308 }
309
310 static int
311 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
312 enum pipe_shader_cap param)
313 {
314 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
315
316 switch (shader) {
317 case PIPE_SHADER_VERTEX:
318 case PIPE_SHADER_GEOMETRY:
319 case PIPE_SHADER_FRAGMENT:
320 case PIPE_SHADER_COMPUTE:
321 case PIPE_SHADER_TESS_CTRL:
322 case PIPE_SHADER_TESS_EVAL:
323 break;
324 default:
325 return 0;
326 }
327
328 switch (param) {
329 case PIPE_SHADER_CAP_PREFERRED_IR:
330 return PIPE_SHADER_IR_TGSI;
331 case PIPE_SHADER_CAP_SUPPORTED_IRS:
332 return 1 << PIPE_SHADER_IR_TGSI;
333 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
334 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
335 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
336 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
337 return 16384;
338 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
339 return 16;
340 case PIPE_SHADER_CAP_MAX_INPUTS:
341 if (shader == PIPE_SHADER_VERTEX)
342 return 32;
343 /* NOTE: These only count our slots for GENERIC varyings.
344 * The address space may be larger, but the actual hard limit seems to be
345 * less than what the address space layout permits, so don't add TEXCOORD,
346 * COLOR, etc. here.
347 */
348 if (shader == PIPE_SHADER_FRAGMENT)
349 return 0x1f0 / 16;
350 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
351 * and excludes 0x60 per-patch inputs.
352 */
353 return 0x200 / 16;
354 case PIPE_SHADER_CAP_MAX_OUTPUTS:
355 return 32;
356 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
357 return 65536;
358 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
359 return NVC0_MAX_PIPE_CONSTBUFS;
360 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
361 return shader != PIPE_SHADER_FRAGMENT;
362 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
363 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
364 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
365 return 1;
366 case PIPE_SHADER_CAP_MAX_PREDS:
367 return 0;
368 case PIPE_SHADER_CAP_MAX_TEMPS:
369 return NVC0_CAP_MAX_PROGRAM_TEMPS;
370 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
371 return 1;
372 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
373 return 1;
374 case PIPE_SHADER_CAP_SUBROUTINES:
375 return 1;
376 case PIPE_SHADER_CAP_INTEGERS:
377 return 1;
378 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
379 return 1;
380 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
381 return 1;
382 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
383 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
384 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
385 return 0;
386 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
387 return NVC0_MAX_BUFFERS;
388 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
389 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
390 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
391 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
392 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
393 return 32;
394 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
395 if (class_3d >= NVE4_3D_CLASS)
396 return NVC0_MAX_IMAGES;
397 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
398 return NVC0_MAX_IMAGES;
399 return 0;
400 default:
401 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
402 return 0;
403 }
404 }
405
406 static float
407 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
408 {
409 switch (param) {
410 case PIPE_CAPF_MAX_LINE_WIDTH:
411 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
412 return 10.0f;
413 case PIPE_CAPF_MAX_POINT_WIDTH:
414 return 63.0f;
415 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
416 return 63.375f;
417 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
418 return 16.0f;
419 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
420 return 15.0f;
421 case PIPE_CAPF_GUARD_BAND_LEFT:
422 case PIPE_CAPF_GUARD_BAND_TOP:
423 return 0.0f;
424 case PIPE_CAPF_GUARD_BAND_RIGHT:
425 case PIPE_CAPF_GUARD_BAND_BOTTOM:
426 return 0.0f; /* that or infinity */
427 }
428
429 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
430 return 0.0f;
431 }
432
433 static int
434 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
435 enum pipe_shader_ir ir_type,
436 enum pipe_compute_cap param, void *data)
437 {
438 struct nvc0_screen *screen = nvc0_screen(pscreen);
439 const uint16_t obj_class = screen->compute->oclass;
440
441 #define RET(x) do { \
442 if (data) \
443 memcpy(data, x, sizeof(x)); \
444 return sizeof(x); \
445 } while (0)
446
447 switch (param) {
448 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
449 RET((uint64_t []) { 3 });
450 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
451 if (obj_class >= NVE4_COMPUTE_CLASS) {
452 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
453 } else {
454 RET(((uint64_t []) { 65535, 65535, 65535 }));
455 }
456 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
457 RET(((uint64_t []) { 1024, 1024, 64 }));
458 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
459 RET((uint64_t []) { 1024 });
460 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
461 if (obj_class >= NVE4_COMPUTE_CLASS) {
462 RET((uint64_t []) { 1024 });
463 } else {
464 RET((uint64_t []) { 512 });
465 }
466 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
467 RET((uint64_t []) { 1ULL << 40 });
468 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
469 switch (obj_class) {
470 case GM200_COMPUTE_CLASS:
471 RET((uint64_t []) { 96 << 10 });
472 break;
473 case GM107_COMPUTE_CLASS:
474 RET((uint64_t []) { 64 << 10 });
475 break;
476 default:
477 RET((uint64_t []) { 48 << 10 });
478 break;
479 }
480 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
481 RET((uint64_t []) { 512 << 10 });
482 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
483 RET((uint64_t []) { 4096 });
484 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
485 RET((uint32_t []) { 32 });
486 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
487 RET((uint64_t []) { 1ULL << 40 });
488 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
489 RET((uint32_t []) { 0 });
490 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
491 RET((uint32_t []) { screen->mp_count_compute });
492 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
493 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
494 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
495 RET((uint32_t []) { 64 });
496 default:
497 return 0;
498 }
499
500 #undef RET
501 }
502
503 static void
504 nvc0_screen_destroy(struct pipe_screen *pscreen)
505 {
506 struct nvc0_screen *screen = nvc0_screen(pscreen);
507
508 if (!nouveau_drm_screen_unref(&screen->base))
509 return;
510
511 if (screen->base.fence.current) {
512 struct nouveau_fence *current = NULL;
513
514 /* nouveau_fence_wait will create a new current fence, so wait on the
515 * _current_ one, and remove both.
516 */
517 nouveau_fence_ref(screen->base.fence.current, &current);
518 nouveau_fence_wait(current, NULL);
519 nouveau_fence_ref(NULL, &current);
520 nouveau_fence_ref(NULL, &screen->base.fence.current);
521 }
522 if (screen->base.pushbuf)
523 screen->base.pushbuf->user_priv = NULL;
524
525 if (screen->blitter)
526 nvc0_blitter_destroy(screen);
527 if (screen->pm.prog) {
528 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
529 nvc0_program_destroy(NULL, screen->pm.prog);
530 FREE(screen->pm.prog);
531 }
532
533 nouveau_bo_ref(NULL, &screen->text);
534 nouveau_bo_ref(NULL, &screen->uniform_bo);
535 nouveau_bo_ref(NULL, &screen->tls);
536 nouveau_bo_ref(NULL, &screen->txc);
537 nouveau_bo_ref(NULL, &screen->fence.bo);
538 nouveau_bo_ref(NULL, &screen->poly_cache);
539
540 nouveau_heap_destroy(&screen->lib_code);
541 nouveau_heap_destroy(&screen->text_heap);
542
543 FREE(screen->default_tsc);
544 FREE(screen->tic.entries);
545
546 nouveau_object_del(&screen->eng3d);
547 nouveau_object_del(&screen->eng2d);
548 nouveau_object_del(&screen->m2mf);
549 nouveau_object_del(&screen->compute);
550 nouveau_object_del(&screen->nvsw);
551
552 nouveau_screen_fini(&screen->base);
553
554 FREE(screen);
555 }
556
557 static int
558 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
559 unsigned size, const uint32_t *data)
560 {
561 struct nouveau_pushbuf *push = screen->base.pushbuf;
562
563 size /= 4;
564
565 assert((pos + size) <= 0x800);
566
567 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
568 PUSH_DATA (push, (m - 0x3800) / 8);
569 PUSH_DATA (push, pos);
570 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
571 PUSH_DATA (push, pos);
572 PUSH_DATAp(push, data, size);
573
574 return pos + size;
575 }
576
577 static void
578 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
579 {
580 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
581 PUSH_DATA (push, 0xff);
582 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
583 PUSH_DATA (push, 0xff);
584 PUSH_DATA (push, 0xff);
585 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
586 PUSH_DATA (push, 0xff);
587 PUSH_DATA (push, 0xff);
588 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
589 PUSH_DATA (push, 0x3f);
590
591 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
592 PUSH_DATA (push, (3 << 16) | 3);
593 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
594 PUSH_DATA (push, (2 << 16) | 2);
595
596 if (obj_class < GM107_3D_CLASS) {
597 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
598 PUSH_DATA (push, 0);
599 }
600 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
601 PUSH_DATA (push, 0x10);
602 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
603 PUSH_DATA (push, 0x10);
604 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
605 PUSH_DATA (push, 0x10);
606 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
607 PUSH_DATA (push, 0x10);
608 PUSH_DATA (push, 0x10);
609 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
610 PUSH_DATA (push, 0x10);
611 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
612 PUSH_DATA (push, 0xe);
613
614 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
615 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
616 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
617 PUSH_DATA (push, 0);
618 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
619 PUSH_DATA (push, 3);
620
621 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
622 PUSH_DATA (push, 0x3fffff);
623 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
624 PUSH_DATA (push, 1);
625 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
626 PUSH_DATA (push, 1);
627
628 if (obj_class < GM107_3D_CLASS) {
629 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
630 PUSH_DATA (push, 3);
631
632 if (obj_class >= NVE4_3D_CLASS) {
633 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
634 PUSH_DATA (push, 1);
635 }
636 }
637
638 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
639 * are supposed to do */
640 }
641
642 static void
643 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
644 {
645 struct nvc0_screen *screen = nvc0_screen(pscreen);
646 struct nouveau_pushbuf *push = screen->base.pushbuf;
647
648 /* we need to do it after possible flush in MARK_RING */
649 *sequence = ++screen->base.fence.sequence;
650
651 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
652 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
653 PUSH_DATAh(push, screen->fence.bo->offset);
654 PUSH_DATA (push, screen->fence.bo->offset);
655 PUSH_DATA (push, *sequence);
656 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
657 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
658 }
659
660 static u32
661 nvc0_screen_fence_update(struct pipe_screen *pscreen)
662 {
663 struct nvc0_screen *screen = nvc0_screen(pscreen);
664 return screen->fence.map[0];
665 }
666
667 static int
668 nvc0_screen_init_compute(struct nvc0_screen *screen)
669 {
670 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
671
672 switch (screen->base.device->chipset & ~0xf) {
673 case 0xc0:
674 case 0xd0:
675 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
676 case 0xe0:
677 case 0xf0:
678 case 0x100:
679 case 0x110:
680 case 0x120:
681 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
682 case 0x130:
683 return 0;
684 default:
685 return -1;
686 }
687 }
688
689 static int
690 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
691 uint32_t lpos, uint32_t lneg, uint32_t cstack)
692 {
693 struct nouveau_bo *bo = NULL;
694 int ret;
695 uint64_t size = (lpos + lneg) * 32 + cstack;
696
697 if (size >= (1 << 20)) {
698 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
699 return -1;
700 }
701
702 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
703 size = align(size, 0x8000);
704 size *= screen->mp_count;
705
706 size = align(size, 1 << 17);
707
708 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
709 NULL, &bo);
710 if (ret)
711 return ret;
712 nouveau_bo_ref(NULL, &screen->tls);
713 screen->tls = bo;
714 return 0;
715 }
716
717 int
718 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
719 {
720 struct nouveau_pushbuf *push = screen->base.pushbuf;
721 struct nouveau_bo *bo;
722 int ret;
723
724 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
725 1 << 17, size, NULL, &bo);
726 if (ret)
727 return ret;
728
729 nouveau_bo_ref(NULL, &screen->text);
730 screen->text = bo;
731
732 nouveau_heap_destroy(&screen->lib_code);
733 nouveau_heap_destroy(&screen->text_heap);
734
735 /* XXX: getting a page fault at the end of the code buffer every few
736 * launches, don't use the last 256 bytes to work around them - prefetch ?
737 */
738 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
739
740 /* update the code segment setup */
741 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
742 PUSH_DATAh(push, screen->text->offset);
743 PUSH_DATA (push, screen->text->offset);
744 if (screen->compute) {
745 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
746 PUSH_DATAh(push, screen->text->offset);
747 PUSH_DATA (push, screen->text->offset);
748 }
749
750 return 0;
751 }
752
753 #define FAIL_SCREEN_INIT(str, err) \
754 do { \
755 NOUVEAU_ERR(str, err); \
756 goto fail; \
757 } while(0)
758
759 struct nouveau_screen *
760 nvc0_screen_create(struct nouveau_device *dev)
761 {
762 struct nvc0_screen *screen;
763 struct pipe_screen *pscreen;
764 struct nouveau_object *chan;
765 struct nouveau_pushbuf *push;
766 uint64_t value;
767 uint32_t obj_class;
768 uint32_t flags;
769 int ret;
770 unsigned i;
771
772 switch (dev->chipset & ~0xf) {
773 case 0xc0:
774 case 0xd0:
775 case 0xe0:
776 case 0xf0:
777 case 0x100:
778 case 0x110:
779 case 0x120:
780 case 0x130:
781 break;
782 default:
783 return NULL;
784 }
785
786 screen = CALLOC_STRUCT(nvc0_screen);
787 if (!screen)
788 return NULL;
789 pscreen = &screen->base.base;
790 pscreen->destroy = nvc0_screen_destroy;
791
792 ret = nouveau_screen_init(&screen->base, dev);
793 if (ret)
794 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
795 chan = screen->base.channel;
796 push = screen->base.pushbuf;
797 push->user_priv = screen;
798 push->rsvd_kick = 5;
799
800 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
801 PIPE_BIND_SHADER_BUFFER |
802 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
803 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
804 screen->base.sysmem_bindings |=
805 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
806
807 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
808 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
809 screen->base.vidmem_bindings = 0;
810 }
811
812 pscreen->context_create = nvc0_create;
813 pscreen->is_format_supported = nvc0_screen_is_format_supported;
814 pscreen->get_param = nvc0_screen_get_param;
815 pscreen->get_shader_param = nvc0_screen_get_shader_param;
816 pscreen->get_paramf = nvc0_screen_get_paramf;
817 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
818 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
819
820 nvc0_screen_init_resource_functions(pscreen);
821
822 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
823 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
824
825 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
826 if (screen->base.drm->version >= 0x01000202)
827 flags |= NOUVEAU_BO_COHERENT;
828
829 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
830 if (ret)
831 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
832 nouveau_bo_map(screen->fence.bo, 0, NULL);
833 screen->fence.map = screen->fence.bo->map;
834 screen->base.fence.emit = nvc0_screen_fence_emit;
835 screen->base.fence.update = nvc0_screen_fence_update;
836
837
838 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
839 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
840 if (ret)
841 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
842
843 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
844 PUSH_DATA (push, screen->nvsw->handle);
845
846 switch (dev->chipset & ~0xf) {
847 case 0x130:
848 case 0x120:
849 case 0x110:
850 case 0x100:
851 case 0xf0:
852 obj_class = NVF0_P2MF_CLASS;
853 break;
854 case 0xe0:
855 obj_class = NVE4_P2MF_CLASS;
856 break;
857 default:
858 obj_class = NVC0_M2MF_CLASS;
859 break;
860 }
861 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
862 &screen->m2mf);
863 if (ret)
864 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
865
866 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
867 PUSH_DATA (push, screen->m2mf->oclass);
868 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
869 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
870 PUSH_DATA (push, 0xa0b5);
871 }
872
873 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
874 &screen->eng2d);
875 if (ret)
876 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
877
878 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
879 PUSH_DATA (push, screen->eng2d->oclass);
880 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
881 PUSH_DATA (push, 0);
882 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
883 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
884 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
885 PUSH_DATA (push, 0);
886 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
887 PUSH_DATA (push, 0);
888 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
889 PUSH_DATA (push, 0x3f);
890 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
891 PUSH_DATA (push, 1);
892 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
893 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
894
895 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
896 PUSH_DATAh(push, screen->fence.bo->offset + 16);
897 PUSH_DATA (push, screen->fence.bo->offset + 16);
898
899 switch (dev->chipset & ~0xf) {
900 case 0x130:
901 switch (dev->chipset) {
902 case 0x130:
903 obj_class = GP100_3D_CLASS;
904 break;
905 default:
906 obj_class = GP102_3D_CLASS;
907 break;
908 }
909 break;
910 case 0x120:
911 obj_class = GM200_3D_CLASS;
912 break;
913 case 0x110:
914 obj_class = GM107_3D_CLASS;
915 break;
916 case 0x100:
917 case 0xf0:
918 obj_class = NVF0_3D_CLASS;
919 break;
920 case 0xe0:
921 switch (dev->chipset) {
922 case 0xea:
923 obj_class = NVEA_3D_CLASS;
924 break;
925 default:
926 obj_class = NVE4_3D_CLASS;
927 break;
928 }
929 break;
930 case 0xd0:
931 obj_class = NVC8_3D_CLASS;
932 break;
933 case 0xc0:
934 default:
935 switch (dev->chipset) {
936 case 0xc8:
937 obj_class = NVC8_3D_CLASS;
938 break;
939 case 0xc1:
940 obj_class = NVC1_3D_CLASS;
941 break;
942 default:
943 obj_class = NVC0_3D_CLASS;
944 break;
945 }
946 break;
947 }
948 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
949 &screen->eng3d);
950 if (ret)
951 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
952 screen->base.class_3d = obj_class;
953
954 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
955 PUSH_DATA (push, screen->eng3d->oclass);
956
957 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
958 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
959
960 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
961 /* kill shaders after about 1 second (at 100 MHz) */
962 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
963 PUSH_DATA (push, 0x17);
964 }
965
966 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
967 screen->base.drm->version >= 0x01000101);
968 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
969 for (i = 0; i < 8; ++i)
970 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
971
972 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
973 PUSH_DATA (push, 1);
974
975 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
976 PUSH_DATA (push, 0);
977 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
978 PUSH_DATA (push, 0);
979 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
980 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
981 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
982 PUSH_DATA (push, 0);
983 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
984 PUSH_DATA (push, 1);
985 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
986 PUSH_DATA (push, 1);
987 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
988 PUSH_DATA (push, 1);
989 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
990 PUSH_DATA (push, 0);
991 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
992 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
993 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
994 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
995 } else {
996 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
997 PUSH_DATA (push, 15);
998 }
999 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1000 PUSH_DATA (push, 8); /* 128 */
1001 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1002 PUSH_DATA (push, 1);
1003 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1004 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1005 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1006 }
1007
1008 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1009
1010 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1011 if (ret)
1012 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1013
1014 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1015 &screen->uniform_bo);
1016 if (ret)
1017 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1018
1019 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1020
1021 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1022 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1023 PUSH_DATA (push, 256);
1024 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1025 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1026 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1027 PUSH_DATA (push, 0);
1028 PUSH_DATAf(push, 0.0f);
1029 PUSH_DATAf(push, 0.0f);
1030 PUSH_DATAf(push, 0.0f);
1031 PUSH_DATAf(push, 0.0f);
1032 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1033 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1034 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1035
1036 if (screen->base.drm->version >= 0x01000101) {
1037 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1038 if (ret)
1039 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1040 } else {
1041 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1042 value = (8 << 8) | 4;
1043 else
1044 value = (16 << 8) | 4;
1045 }
1046 screen->gpc_count = value & 0x000000ff;
1047 screen->mp_count = value >> 8;
1048 screen->mp_count_compute = screen->mp_count;
1049
1050 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1051 if (ret)
1052 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1053
1054 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1055 PUSH_DATAh(push, screen->tls->offset);
1056 PUSH_DATA (push, screen->tls->offset);
1057 PUSH_DATA (push, screen->tls->size >> 32);
1058 PUSH_DATA (push, screen->tls->size);
1059 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1060 PUSH_DATA (push, 0);
1061 /* Reduce likelihood of collision with real buffers by placing the hole at
1062 * the top of the 4G area. This will have to be dealt with for real
1063 * eventually by blocking off that area from the VM.
1064 */
1065 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1066 PUSH_DATA (push, 0xff << 24);
1067
1068 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1069 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1070 &screen->poly_cache);
1071 if (ret)
1072 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1073
1074 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1075 PUSH_DATAh(push, screen->poly_cache->offset);
1076 PUSH_DATA (push, screen->poly_cache->offset);
1077 PUSH_DATA (push, 3);
1078 }
1079
1080 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1081 &screen->txc);
1082 if (ret)
1083 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1084
1085 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1086 PUSH_DATAh(push, screen->txc->offset);
1087 PUSH_DATA (push, screen->txc->offset);
1088 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1089 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1090 screen->tic.maxwell = true;
1091 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1092 screen->tic.maxwell =
1093 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1094 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1095 }
1096 }
1097
1098 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1099 PUSH_DATAh(push, screen->txc->offset + 65536);
1100 PUSH_DATA (push, screen->txc->offset + 65536);
1101 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1102
1103 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1104 PUSH_DATA (push, 0);
1105 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1106 PUSH_DATA (push, 0);
1107 PUSH_DATA (push, 0);
1108 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1109 PUSH_DATA (push, 0x3f);
1110
1111 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1112 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1113 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1114 for (i = 0; i < 8 * 2; ++i)
1115 PUSH_DATA(push, 0);
1116 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1117 PUSH_DATA (push, 0);
1118 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1119 PUSH_DATA (push, 0);
1120
1121 /* neither scissors, viewport nor stencil mask should affect clears */
1122 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1123 PUSH_DATA (push, 0);
1124
1125 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1126 PUSH_DATA (push, 1);
1127 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1128 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1129 PUSH_DATAf(push, 0.0f);
1130 PUSH_DATAf(push, 1.0f);
1131 }
1132 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1133 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1134
1135 /* We use scissors instead of exact view volume clipping,
1136 * so they're always enabled.
1137 */
1138 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1139 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1140 PUSH_DATA (push, 1);
1141 PUSH_DATA (push, 8192 << 16);
1142 PUSH_DATA (push, 8192 << 16);
1143 }
1144
1145 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1146
1147 i = 0;
1148 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1149 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1150 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1151 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1152 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1153 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1154 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1155 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1156 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1157 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1158 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1159 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1160 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1161
1162 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1163 PUSH_DATA (push, 1);
1164 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1165 PUSH_DATA (push, 1);
1166 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1167 PUSH_DATA (push, 0x40);
1168 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1169 PUSH_DATA (push, 0);
1170 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1171 PUSH_DATA (push, 0x30);
1172 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1173 PUSH_DATA (push, 3);
1174 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1175 PUSH_DATA (push, 0x20);
1176 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1177 PUSH_DATA (push, 0x00);
1178 screen->save_state.patch_vertices = 3;
1179
1180 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1181 PUSH_DATA (push, 0);
1182 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1183 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1184
1185 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1186
1187 if (nvc0_screen_init_compute(screen))
1188 goto fail;
1189
1190 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1191 for (i = 0; i < 5; ++i) {
1192 /* TIC and TSC entries for each unit (nve4+ only) */
1193 /* auxiliary constants (6 user clip planes, base instance id) */
1194 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1195 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1196 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1197 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1198 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1199 PUSH_DATA (push, (15 << 4) | 1);
1200 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1201 unsigned j;
1202 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1203 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1204 for (j = 0; j < 8; ++j)
1205 PUSH_DATA(push, j);
1206 } else {
1207 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1208 PUSH_DATA (push, 0x54);
1209 }
1210
1211 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1212 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1213 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1214 PUSH_DATA (push, 0); /* 0 */
1215 PUSH_DATA (push, 0);
1216 PUSH_DATA (push, 1); /* 1 */
1217 PUSH_DATA (push, 0);
1218 PUSH_DATA (push, 0); /* 2 */
1219 PUSH_DATA (push, 1);
1220 PUSH_DATA (push, 1); /* 3 */
1221 PUSH_DATA (push, 1);
1222 PUSH_DATA (push, 2); /* 4 */
1223 PUSH_DATA (push, 0);
1224 PUSH_DATA (push, 3); /* 5 */
1225 PUSH_DATA (push, 0);
1226 PUSH_DATA (push, 2); /* 6 */
1227 PUSH_DATA (push, 1);
1228 PUSH_DATA (push, 3); /* 7 */
1229 PUSH_DATA (push, 1);
1230 }
1231 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1232 PUSH_DATA (push, 0);
1233
1234 PUSH_KICK (push);
1235
1236 screen->tic.entries = CALLOC(4096, sizeof(void *));
1237 screen->tsc.entries = screen->tic.entries + 2048;
1238
1239 if (!nvc0_blitter_create(screen))
1240 goto fail;
1241
1242 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1243 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1244
1245 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1246
1247 return &screen->base;
1248
1249 fail:
1250 screen->base.base.context_create = NULL;
1251 return &screen->base;
1252 }
1253
1254 int
1255 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1256 {
1257 int i = screen->tic.next;
1258
1259 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1260 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1261
1262 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1263
1264 if (screen->tic.entries[i])
1265 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1266
1267 screen->tic.entries[i] = entry;
1268 return i;
1269 }
1270
1271 int
1272 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1273 {
1274 int i = screen->tsc.next;
1275
1276 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1277 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1278
1279 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1280
1281 if (screen->tsc.entries[i])
1282 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1283
1284 screen->tsc.entries[i] = entry;
1285 return i;
1286 }