src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/mme/com9097.mme.h"
  36 #include "nvc0/mme/com90c0.mme.h"
  37
  38 #include "nv50/g80_texture.xml.h"
  39
  40 static boolean
  41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  42                                 enum pipe_format format,
  43                                 enum pipe_texture_target target,
  44                                 unsigned sample_count,
  45                                 unsigned bindings)
  46 {
  47    const struct util_format_description *desc = util_format_description(format);
  48
  49    if (sample_count > 8)
  50       return false;
  51    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  52       return false;
  53
  54    /* Short-circuit the rest of the logic -- this is used by the state tracker
  55     * to determine valid MS levels in a no-attachments scenario.
  56     */
  57    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  58       return true;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return false;
  62
  63    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  64       if (util_format_get_blocksizebits(format) == 3 * 32)
  65          return false;
  66
  67    if (bindings & PIPE_BIND_LINEAR)
  68       if (util_format_is_depth_or_stencil(format) ||
  69           (target != PIPE_TEXTURE_1D &&
  70            target != PIPE_TEXTURE_2D &&
  71            target != PIPE_TEXTURE_RECT) ||
  72           sample_count > 1)
  73          return false;
  74
  75    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  76     */
  77    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  78         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  79        /* The claim is that this should work on GM107 but it doesn't. Need to
  80         * test further and figure out if it's a nouveau issue or a HW one.
  81        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  82         */
  83        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  84       return false;
  85
  86    /* shared is always supported */
  87    bindings &= ~(PIPE_BIND_LINEAR |
  88                  PIPE_BIND_SHARED);
  89
  90    if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
  91        nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  92       /* MS images are currently unsupported on Maxwell because they have to
  93        * be handled explicitly. */
  94       return false;
  95    }
  96
  97    return (( nvc0_format_table[format].usage |
  98             nvc0_vertex_format[format].usage) & bindings) == bindings;
  99 }
 100
 101 static int
 102 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 103 {
 104    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 105    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 106
 107    switch (param) {
 108    /* non-boolean caps */
 109    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 110    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 111       return 15;
 112    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 113       return 12;
 114    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 115       return 2048;
 116    case PIPE_CAP_MIN_TEXEL_OFFSET:
 117       return -8;
 118    case PIPE_CAP_MAX_TEXEL_OFFSET:
 119       return 7;
 120    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 121       return -32;
 122    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 123       return 31;
 124    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 125       return 128 * 1024 * 1024;
 126    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 127       return 430;
 128    case PIPE_CAP_MAX_RENDER_TARGETS:
 129       return 8;
 130    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 131       return 1;
 132    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 133       return 4;
 134    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 135    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 136       return 128;
 137    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 138    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 139       return 1024;
 140    case PIPE_CAP_MAX_VERTEX_STREAMS:
 141       return 4;
 142    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 143       return 2048;
 144    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 145       return 256;
 146    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 147       if (class_3d < GM107_3D_CLASS)
 148          return 256; /* IMAGE bindings require alignment to 256 */
 149       return 16;
 150    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 151       return 16;
 152    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 153       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 154    case PIPE_CAP_MAX_VIEWPORTS:
 155       return NVC0_MAX_VIEWPORTS;
 156    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 157       return 4;
 158    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 159       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 160    case PIPE_CAP_ENDIANNESS:
 161       return PIPE_ENDIAN_LITTLE;
 162    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 163       return 30;
 164    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 165       return NVC0_MAX_WINDOW_RECTANGLES;
 166
 167    /* supported caps */
 168    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 169    case PIPE_CAP_TEXTURE_SWIZZLE:
 170    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 171    case PIPE_CAP_NPOT_TEXTURES:
 172    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 173    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 174    case PIPE_CAP_ANISOTROPIC_FILTER:
 175    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 176    case PIPE_CAP_CUBE_MAP_ARRAY:
 177    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 178    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 179    case PIPE_CAP_TWO_SIDED_STENCIL:
 180    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 181    case PIPE_CAP_POINT_SPRITE:
 182    case PIPE_CAP_TGSI_TEXCOORD:
 183    case PIPE_CAP_SM3:
 184    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 185    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 186    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 187    case PIPE_CAP_QUERY_TIMESTAMP:
 188    case PIPE_CAP_QUERY_TIME_ELAPSED:
 189    case PIPE_CAP_OCCLUSION_QUERY:
 190    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 191    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 192    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 193    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 194    case PIPE_CAP_INDEP_BLEND_ENABLE:
 195    case PIPE_CAP_INDEP_BLEND_FUNC:
 196    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 197    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 198    case PIPE_CAP_PRIMITIVE_RESTART:
 199    case PIPE_CAP_TGSI_INSTANCEID:
 200    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 201    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 202    case PIPE_CAP_CONDITIONAL_RENDER:
 203    case PIPE_CAP_TEXTURE_BARRIER:
 204    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 205    case PIPE_CAP_START_INSTANCE:
 206    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 207    case PIPE_CAP_DRAW_INDIRECT:
 208    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 209    case PIPE_CAP_USER_VERTEX_BUFFERS:
 210    case PIPE_CAP_TEXTURE_QUERY_LOD:
 211    case PIPE_CAP_SAMPLE_SHADING:
 212    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 213    case PIPE_CAP_TEXTURE_GATHER_SM5:
 214    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 215    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 216    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 217    case PIPE_CAP_CLIP_HALFZ:
 218    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 219    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 220    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 221    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 222    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 223    case PIPE_CAP_TGSI_TXQS:
 224    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 225    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 226    case PIPE_CAP_SHAREABLE_SHADERS:
 227    case PIPE_CAP_CLEAR_TEXTURE:
 228    case PIPE_CAP_DRAW_PARAMETERS:
 229    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 230    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 231    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 232    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 233    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 234    case PIPE_CAP_INVALIDATE_BUFFER:
 235    case PIPE_CAP_STRING_MARKER:
 236    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 237    case PIPE_CAP_CULL_DISTANCE:
 238    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 239    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 240    case PIPE_CAP_TGSI_VOTE:
 241    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 242    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 243    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 244    case PIPE_CAP_DOUBLES:
 245    case PIPE_CAP_INT64:
 246    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 247    case PIPE_CAP_TGSI_CLOCK:
 248    case PIPE_CAP_COMPUTE:
 249    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 250    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 251       return 1;
 252    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 253       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 254    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 255       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 256    case PIPE_CAP_TGSI_FS_FBFETCH:
 257       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 258    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 259    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 260    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 261       return class_3d >= GM200_3D_CLASS;
 262    case PIPE_CAP_TGSI_BALLOT:
 263       return class_3d >= NVE4_3D_CLASS;
 264
 265    /* unsupported caps */
 266    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 267    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 268    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 269    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 270    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 271    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 272    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 273    case PIPE_CAP_FAKE_SW_MSAA:
 274    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 275    case PIPE_CAP_VERTEXID_NOBASE:
 276    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 277    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 278    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 279    case PIPE_CAP_GENERATE_MIPMAP:
 280    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 281    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 282    case PIPE_CAP_QUERY_MEMORY_INFO:
 283    case PIPE_CAP_PCI_GROUP:
 284    case PIPE_CAP_PCI_BUS:
 285    case PIPE_CAP_PCI_DEVICE:
 286    case PIPE_CAP_PCI_FUNCTION:
 287    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 288    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 289    case PIPE_CAP_NATIVE_FENCE_FD:
 290    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 291    case PIPE_CAP_INT64_DIVMOD:
 292    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 293       return 0;
 294
 295    case PIPE_CAP_VENDOR_ID:
 296       return 0x10de;
 297    case PIPE_CAP_DEVICE_ID: {
 298       uint64_t device_id;
 299       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 300          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 301          return -1;
 302       }
 303       return device_id;
 304    }
 305    case PIPE_CAP_ACCELERATED:
 306       return 1;
 307    case PIPE_CAP_VIDEO_MEMORY:
 308       return dev->vram_size >> 20;
 309    case PIPE_CAP_UMA:
 310       return 0;
 311    }
 312
 313    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 314    return 0;
 315 }
 316
 317 static int
 318 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 319                              enum pipe_shader_type shader,
 320                              enum pipe_shader_cap param)
 321 {
 322    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 323
 324    switch (shader) {
 325    case PIPE_SHADER_VERTEX:
 326    case PIPE_SHADER_GEOMETRY:
 327    case PIPE_SHADER_FRAGMENT:
 328    case PIPE_SHADER_COMPUTE:
 329    case PIPE_SHADER_TESS_CTRL:
 330    case PIPE_SHADER_TESS_EVAL:
 331       break;
 332    default:
 333       return 0;
 334    }
 335
 336    switch (param) {
 337    case PIPE_SHADER_CAP_PREFERRED_IR:
 338       return PIPE_SHADER_IR_TGSI;
 339    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 340       return 1 << PIPE_SHADER_IR_TGSI;
 341    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 342    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 343    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 344    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 345       return 16384;
 346    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 347       return 16;
 348    case PIPE_SHADER_CAP_MAX_INPUTS:
 349       if (shader == PIPE_SHADER_VERTEX)
 350          return 32;
 351       /* NOTE: These only count our slots for GENERIC varyings.
 352        * The address space may be larger, but the actual hard limit seems to be
 353        * less than what the address space layout permits, so don't add TEXCOORD,
 354        * COLOR, etc. here.
 355        */
 356       if (shader == PIPE_SHADER_FRAGMENT)
 357          return 0x1f0 / 16;
 358       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 359        * and excludes 0x60 per-patch inputs.
 360        */
 361       return 0x200 / 16;
 362    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 363       return 32;
 364    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 365       return 65536;
 366    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 367       return NVC0_MAX_PIPE_CONSTBUFS;
 368    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 369       return shader != PIPE_SHADER_FRAGMENT;
 370    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 371    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 372    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 373       return 1;
 374    case PIPE_SHADER_CAP_MAX_TEMPS:
 375       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 376    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 377       return 1;
 378    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 379       return 1;
 380    case PIPE_SHADER_CAP_SUBROUTINES:
 381       return 1;
 382    case PIPE_SHADER_CAP_INTEGERS:
 383       return 1;
 384    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 385       return 1;
 386    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 387       return 1;
 388    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 389       return 1;
 390    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 391    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 392    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 393       return 0;
 394    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 395       return NVC0_MAX_BUFFERS;
 396    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 397       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 398    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 399       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 400    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 401       return 32;
 402    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 403       if (class_3d >= NVE4_3D_CLASS)
 404          return NVC0_MAX_IMAGES;
 405       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 406          return NVC0_MAX_IMAGES;
 407       return 0;
 408    default:
 409       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 410       return 0;
 411    }
 412 }
 413
 414 static float
 415 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 416 {
 417    switch (param) {
 418    case PIPE_CAPF_MAX_LINE_WIDTH:
 419    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 420       return 10.0f;
 421    case PIPE_CAPF_MAX_POINT_WIDTH:
 422       return 63.0f;
 423    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 424       return 63.375f;
 425    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 426       return 16.0f;
 427    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 428       return 15.0f;
 429    case PIPE_CAPF_GUARD_BAND_LEFT:
 430    case PIPE_CAPF_GUARD_BAND_TOP:
 431       return 0.0f;
 432    case PIPE_CAPF_GUARD_BAND_RIGHT:
 433    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 434       return 0.0f; /* that or infinity */
 435    }
 436
 437    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 438    return 0.0f;
 439 }
 440
 441 static int
 442 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 443                               enum pipe_shader_ir ir_type,
 444                               enum pipe_compute_cap param, void *data)
 445 {
 446    struct nvc0_screen *screen = nvc0_screen(pscreen);
 447    const uint16_t obj_class = screen->compute->oclass;
 448
 449 #define RET(x) do {                  \
 450    if (data)                         \
 451       memcpy(data, x, sizeof(x));    \
 452    return sizeof(x);                 \
 453 } while (0)
 454
 455    switch (param) {
 456    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 457       RET((uint64_t []) { 3 });
 458    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 459       if (obj_class >= NVE4_COMPUTE_CLASS) {
 460          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 461       } else {
 462          RET(((uint64_t []) { 65535, 65535, 65535 }));
 463       }
 464    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 465       RET(((uint64_t []) { 1024, 1024, 64 }));
 466    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 467       RET((uint64_t []) { 1024 });
 468    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 469       if (obj_class >= NVE4_COMPUTE_CLASS) {
 470          RET((uint64_t []) { 1024 });
 471       } else {
 472          RET((uint64_t []) { 512 });
 473       }
 474    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 475       RET((uint64_t []) { 1ULL << 40 });
 476    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 477       switch (obj_class) {
 478       case GM200_COMPUTE_CLASS:
 479          RET((uint64_t []) { 96 << 10 });
 480          break;
 481       case GM107_COMPUTE_CLASS:
 482          RET((uint64_t []) { 64 << 10 });
 483          break;
 484       default:
 485          RET((uint64_t []) { 48 << 10 });
 486          break;
 487       }
 488    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 489       RET((uint64_t []) { 512 << 10 });
 490    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 491       RET((uint64_t []) { 4096 });
 492    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 493       RET((uint32_t []) { 32 });
 494    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 495       RET((uint64_t []) { 1ULL << 40 });
 496    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 497       RET((uint32_t []) { 0 });
 498    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 499       RET((uint32_t []) { screen->mp_count_compute });
 500    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 501       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 502    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 503       RET((uint32_t []) { 64 });
 504    default:
 505       return 0;
 506    }
 507
 508 #undef RET
 509 }
 510
 511 static void
 512 nvc0_screen_destroy(struct pipe_screen *pscreen)
 513 {
 514    struct nvc0_screen *screen = nvc0_screen(pscreen);
 515
 516    if (!nouveau_drm_screen_unref(&screen->base))
 517       return;
 518
 519    if (screen->base.fence.current) {
 520       struct nouveau_fence *current = NULL;
 521
 522       /* nouveau_fence_wait will create a new current fence, so wait on the
 523        * _current_ one, and remove both.
 524        */
 525       nouveau_fence_ref(screen->base.fence.current, &current);
 526       nouveau_fence_wait(current, NULL);
 527       nouveau_fence_ref(NULL, &current);
 528       nouveau_fence_ref(NULL, &screen->base.fence.current);
 529    }
 530    if (screen->base.pushbuf)
 531       screen->base.pushbuf->user_priv = NULL;
 532
 533    if (screen->blitter)
 534       nvc0_blitter_destroy(screen);
 535    if (screen->pm.prog) {
 536       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 537       nvc0_program_destroy(NULL, screen->pm.prog);
 538       FREE(screen->pm.prog);
 539    }
 540
 541    nouveau_bo_ref(NULL, &screen->text);
 542    nouveau_bo_ref(NULL, &screen->uniform_bo);
 543    nouveau_bo_ref(NULL, &screen->tls);
 544    nouveau_bo_ref(NULL, &screen->txc);
 545    nouveau_bo_ref(NULL, &screen->fence.bo);
 546    nouveau_bo_ref(NULL, &screen->poly_cache);
 547
 548    nouveau_heap_destroy(&screen->lib_code);
 549    nouveau_heap_destroy(&screen->text_heap);
 550
 551    FREE(screen->default_tsc);
 552    FREE(screen->tic.entries);
 553
 554    nouveau_object_del(&screen->eng3d);
 555    nouveau_object_del(&screen->eng2d);
 556    nouveau_object_del(&screen->m2mf);
 557    nouveau_object_del(&screen->compute);
 558    nouveau_object_del(&screen->nvsw);
 559
 560    nouveau_screen_fini(&screen->base);
 561
 562    FREE(screen);
 563 }
 564
 565 static int
 566 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 567                      unsigned size, const uint32_t *data)
 568 {
 569    struct nouveau_pushbuf *push = screen->base.pushbuf;
 570
 571    size /= 4;
 572
 573    assert((pos + size) <= 0x800);
 574
 575    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 576    PUSH_DATA (push, (m - 0x3800) / 8);
 577    PUSH_DATA (push, pos);
 578    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 579    PUSH_DATA (push, pos);
 580    PUSH_DATAp(push, data, size);
 581
 582    return pos + size;
 583 }
 584
 585 static void
 586 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 587 {
 588    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 589    PUSH_DATA (push, 0xff);
 590    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 591    PUSH_DATA (push, 0xff);
 592    PUSH_DATA (push, 0xff);
 593    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 594    PUSH_DATA (push, 0xff);
 595    PUSH_DATA (push, 0xff);
 596    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 597    PUSH_DATA (push, 0x3f);
 598
 599    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 600    PUSH_DATA (push, (3 << 16) | 3);
 601    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 602    PUSH_DATA (push, (2 << 16) | 2);
 603
 604    if (obj_class < GM107_3D_CLASS) {
 605       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 606       PUSH_DATA (push, 0);
 607    }
 608    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 609    PUSH_DATA (push, 0x10);
 610    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 611    PUSH_DATA (push, 0x10);
 612    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 613    PUSH_DATA (push, 0x10);
 614    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 615    PUSH_DATA (push, 0x10);
 616    PUSH_DATA (push, 0x10);
 617    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 618    PUSH_DATA (push, 0x10);
 619    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 620    PUSH_DATA (push, 0xe);
 621
 622    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 623    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 624    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 625    PUSH_DATA (push, 0);
 626    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 627    PUSH_DATA (push, 3);
 628
 629    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 630    PUSH_DATA (push, 0x3fffff);
 631    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 632    PUSH_DATA (push, 1);
 633    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 634    PUSH_DATA (push, 1);
 635
 636    if (obj_class < GM107_3D_CLASS) {
 637       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 638       PUSH_DATA (push, 3);
 639
 640       if (obj_class >= NVE4_3D_CLASS) {
 641          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 642          PUSH_DATA (push, 1);
 643       }
 644    }
 645
 646    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 647     * are supposed to do */
 648 }
 649
 650 static void
 651 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 652 {
 653    struct nvc0_screen *screen = nvc0_screen(pscreen);
 654    struct nouveau_pushbuf *push = screen->base.pushbuf;
 655
 656    /* we need to do it after possible flush in MARK_RING */
 657    *sequence = ++screen->base.fence.sequence;
 658
 659    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 660    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 661    PUSH_DATAh(push, screen->fence.bo->offset);
 662    PUSH_DATA (push, screen->fence.bo->offset);
 663    PUSH_DATA (push, *sequence);
 664    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 665               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 666 }
 667
 668 static u32
 669 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 670 {
 671    struct nvc0_screen *screen = nvc0_screen(pscreen);
 672    return screen->fence.map[0];
 673 }
 674
 675 static int
 676 nvc0_screen_init_compute(struct nvc0_screen *screen)
 677 {
 678    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 679
 680    switch (screen->base.device->chipset & ~0xf) {
 681    case 0xc0:
 682    case 0xd0:
 683       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 684    case 0xe0:
 685    case 0xf0:
 686    case 0x100:
 687    case 0x110:
 688    case 0x120:
 689    case 0x130:
 690       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 691    default:
 692       return -1;
 693    }
 694 }
 695
 696 static int
 697 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 698                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 699 {
 700    struct nouveau_bo *bo = NULL;
 701    int ret;
 702    uint64_t size = (lpos + lneg) * 32 + cstack;
 703
 704    if (size >= (1 << 20)) {
 705       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 706       return -1;
 707    }
 708
 709    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 710    size  = align(size, 0x8000);
 711    size *= screen->mp_count;
 712
 713    size = align(size, 1 << 17);
 714
 715    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 716                         NULL, &bo);
 717    if (ret)
 718       return ret;
 719    nouveau_bo_ref(NULL, &screen->tls);
 720    screen->tls = bo;
 721    return 0;
 722 }
 723
 724 int
 725 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 726 {
 727    struct nouveau_pushbuf *push = screen->base.pushbuf;
 728    struct nouveau_bo *bo;
 729    int ret;
 730
 731    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 732                         1 << 17, size, NULL, &bo);
 733    if (ret)
 734       return ret;
 735
 736    nouveau_bo_ref(NULL, &screen->text);
 737    screen->text = bo;
 738
 739    nouveau_heap_destroy(&screen->lib_code);
 740    nouveau_heap_destroy(&screen->text_heap);
 741
 742    /* XXX: getting a page fault at the end of the code buffer every few
 743     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 744     */
 745    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 746
 747    /* update the code segment setup */
 748    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 749    PUSH_DATAh(push, screen->text->offset);
 750    PUSH_DATA (push, screen->text->offset);
 751    if (screen->compute) {
 752       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 753       PUSH_DATAh(push, screen->text->offset);
 754       PUSH_DATA (push, screen->text->offset);
 755    }
 756
 757    return 0;
 758 }
 759
 760 #define FAIL_SCREEN_INIT(str, err)                    \
 761    do {                                               \
 762       NOUVEAU_ERR(str, err);                          \
 763       goto fail;                                      \
 764    } while(0)
 765
 766 struct nouveau_screen *
 767 nvc0_screen_create(struct nouveau_device *dev)
 768 {
 769    struct nvc0_screen *screen;
 770    struct pipe_screen *pscreen;
 771    struct nouveau_object *chan;
 772    struct nouveau_pushbuf *push;
 773    uint64_t value;
 774    uint32_t obj_class;
 775    uint32_t flags;
 776    int ret;
 777    unsigned i;
 778
 779    switch (dev->chipset & ~0xf) {
 780    case 0xc0:
 781    case 0xd0:
 782    case 0xe0:
 783    case 0xf0:
 784    case 0x100:
 785    case 0x110:
 786    case 0x120:
 787    case 0x130:
 788       break;
 789    default:
 790       return NULL;
 791    }
 792
 793    screen = CALLOC_STRUCT(nvc0_screen);
 794    if (!screen)
 795       return NULL;
 796    pscreen = &screen->base.base;
 797    pscreen->destroy = nvc0_screen_destroy;
 798
 799    ret = nouveau_screen_init(&screen->base, dev);
 800    if (ret)
 801       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 802    chan = screen->base.channel;
 803    push = screen->base.pushbuf;
 804    push->user_priv = screen;
 805    push->rsvd_kick = 5;
 806
 807    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 808       PIPE_BIND_SHADER_BUFFER |
 809       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 810       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 811    screen->base.sysmem_bindings |=
 812       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 813
 814    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 815       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 816       screen->base.vidmem_bindings = 0;
 817    }
 818
 819    pscreen->context_create = nvc0_create;
 820    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 821    pscreen->get_param = nvc0_screen_get_param;
 822    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 823    pscreen->get_paramf = nvc0_screen_get_paramf;
 824    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 825    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 826
 827    nvc0_screen_init_resource_functions(pscreen);
 828
 829    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 830    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 831
 832    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 833    if (screen->base.drm->version >= 0x01000202)
 834       flags |= NOUVEAU_BO_COHERENT;
 835
 836    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 837    if (ret)
 838       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 839    nouveau_bo_map(screen->fence.bo, 0, NULL);
 840    screen->fence.map = screen->fence.bo->map;
 841    screen->base.fence.emit = nvc0_screen_fence_emit;
 842    screen->base.fence.update = nvc0_screen_fence_update;
 843
 844
 845    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 846                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 847    if (ret)
 848       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 849
 850    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 851    PUSH_DATA (push, screen->nvsw->handle);
 852
 853    switch (dev->chipset & ~0xf) {
 854    case 0x130:
 855    case 0x120:
 856    case 0x110:
 857    case 0x100:
 858    case 0xf0:
 859       obj_class = NVF0_P2MF_CLASS;
 860       break;
 861    case 0xe0:
 862       obj_class = NVE4_P2MF_CLASS;
 863       break;
 864    default:
 865       obj_class = NVC0_M2MF_CLASS;
 866       break;
 867    }
 868    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 869                             &screen->m2mf);
 870    if (ret)
 871       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 872
 873    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 874    PUSH_DATA (push, screen->m2mf->oclass);
 875    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 876       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 877       PUSH_DATA (push, 0xa0b5);
 878    }
 879
 880    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 881                             &screen->eng2d);
 882    if (ret)
 883       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 884
 885    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 886    PUSH_DATA (push, screen->eng2d->oclass);
 887    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 888    PUSH_DATA (push, 0);
 889    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 890    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 891    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 892    PUSH_DATA (push, 0);
 893    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 894    PUSH_DATA (push, 0);
 895    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 896    PUSH_DATA (push, 0x3f);
 897    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 898    PUSH_DATA (push, 1);
 899    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 900    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 901
 902    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 903    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 904    PUSH_DATA (push, screen->fence.bo->offset + 16);
 905
 906    switch (dev->chipset & ~0xf) {
 907    case 0x130:
 908       switch (dev->chipset) {
 909       case 0x130:
 910       case 0x13b:
 911          obj_class = GP100_3D_CLASS;
 912          break;
 913       default:
 914          obj_class = GP102_3D_CLASS;
 915          break;
 916       }
 917       break;
 918    case 0x120:
 919       obj_class = GM200_3D_CLASS;
 920       break;
 921    case 0x110:
 922       obj_class = GM107_3D_CLASS;
 923       break;
 924    case 0x100:
 925    case 0xf0:
 926       obj_class = NVF0_3D_CLASS;
 927       break;
 928    case 0xe0:
 929       switch (dev->chipset) {
 930       case 0xea:
 931          obj_class = NVEA_3D_CLASS;
 932          break;
 933       default:
 934          obj_class = NVE4_3D_CLASS;
 935          break;
 936       }
 937       break;
 938    case 0xd0:
 939       obj_class = NVC8_3D_CLASS;
 940       break;
 941    case 0xc0:
 942    default:
 943       switch (dev->chipset) {
 944       case 0xc8:
 945          obj_class = NVC8_3D_CLASS;
 946          break;
 947       case 0xc1:
 948          obj_class = NVC1_3D_CLASS;
 949          break;
 950       default:
 951          obj_class = NVC0_3D_CLASS;
 952          break;
 953       }
 954       break;
 955    }
 956    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 957                             &screen->eng3d);
 958    if (ret)
 959       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 960    screen->base.class_3d = obj_class;
 961
 962    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 963    PUSH_DATA (push, screen->eng3d->oclass);
 964
 965    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 966    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 967
 968    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 969       /* kill shaders after about 1 second (at 100 MHz) */
 970       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 971       PUSH_DATA (push, 0x17);
 972    }
 973
 974    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 975                     screen->base.drm->version >= 0x01000101);
 976    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 977    for (i = 0; i < 8; ++i)
 978       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 979
 980    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 981    PUSH_DATA (push, 1);
 982
 983    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 984    PUSH_DATA (push, 0);
 985    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 986    PUSH_DATA (push, 0);
 987    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 988    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 989    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 990    PUSH_DATA (push, 0);
 991    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 992    PUSH_DATA (push, 1);
 993    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 994    PUSH_DATA (push, 1);
 995    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 996    PUSH_DATA (push, 1);
 997    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 998    PUSH_DATA (push, 0);
 999    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1000    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1001    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1002       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1003    } else {
1004       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1005       PUSH_DATA (push, 15);
1006    }
1007    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1008    PUSH_DATA (push, 8); /* 128 */
1009    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1010    PUSH_DATA (push, 1);
1011    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1012       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1013       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1014    }
1015
1016    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1017
1018    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1019    if (ret)
1020       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1021
1022    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1023                         &screen->uniform_bo);
1024    if (ret)
1025       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1026
1027    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1028
1029    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1030    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1031    PUSH_DATA (push, 256);
1032    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1033    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1034    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1035    PUSH_DATA (push, 0);
1036    PUSH_DATAf(push, 0.0f);
1037    PUSH_DATAf(push, 0.0f);
1038    PUSH_DATAf(push, 0.0f);
1039    PUSH_DATAf(push, 0.0f);
1040    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1041    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1042    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1043
1044    if (screen->base.drm->version >= 0x01000101) {
1045       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1046       if (ret)
1047          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1048    } else {
1049       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1050          value = (8 << 8) | 4;
1051       else
1052          value = (16 << 8) | 4;
1053    }
1054    screen->gpc_count = value & 0x000000ff;
1055    screen->mp_count = value >> 8;
1056    screen->mp_count_compute = screen->mp_count;
1057
1058    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1059    if (ret)
1060       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1061
1062    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1063    PUSH_DATAh(push, screen->tls->offset);
1064    PUSH_DATA (push, screen->tls->offset);
1065    PUSH_DATA (push, screen->tls->size >> 32);
1066    PUSH_DATA (push, screen->tls->size);
1067    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1068    PUSH_DATA (push, 0);
1069    /* Reduce likelihood of collision with real buffers by placing the hole at
1070     * the top of the 4G area. This will have to be dealt with for real
1071     * eventually by blocking off that area from the VM.
1072     */
1073    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1074    PUSH_DATA (push, 0xff << 24);
1075
1076    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1077       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1078                            &screen->poly_cache);
1079       if (ret)
1080          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1081
1082       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1083       PUSH_DATAh(push, screen->poly_cache->offset);
1084       PUSH_DATA (push, screen->poly_cache->offset);
1085       PUSH_DATA (push, 3);
1086    }
1087
1088    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1089                         &screen->txc);
1090    if (ret)
1091       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1092
1093    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1094    PUSH_DATAh(push, screen->txc->offset);
1095    PUSH_DATA (push, screen->txc->offset);
1096    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1097    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1098       screen->tic.maxwell = true;
1099       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1100          screen->tic.maxwell =
1101             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1102          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1103       }
1104    }
1105
1106    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1107    PUSH_DATAh(push, screen->txc->offset + 65536);
1108    PUSH_DATA (push, screen->txc->offset + 65536);
1109    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1110
1111    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1112    PUSH_DATA (push, 0);
1113    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1114    PUSH_DATA (push, 0);
1115    PUSH_DATA (push, 0);
1116    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1117    PUSH_DATA (push, 0x3f);
1118
1119    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1120    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1121    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1122    for (i = 0; i < 8 * 2; ++i)
1123       PUSH_DATA(push, 0);
1124    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1125    PUSH_DATA (push, 0);
1126    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1127    PUSH_DATA (push, 0);
1128
1129    /* neither scissors, viewport nor stencil mask should affect clears */
1130    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1131    PUSH_DATA (push, 0);
1132
1133    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1134    PUSH_DATA (push, 1);
1135    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1136       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1137       PUSH_DATAf(push, 0.0f);
1138       PUSH_DATAf(push, 1.0f);
1139    }
1140    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1141    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1142
1143    /* We use scissors instead of exact view volume clipping,
1144     * so they're always enabled.
1145     */
1146    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1147       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1148       PUSH_DATA (push, 1);
1149       PUSH_DATA (push, 8192 << 16);
1150       PUSH_DATA (push, 8192 << 16);
1151    }
1152
1153 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1154
1155    i = 0;
1156    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1157    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1158    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1159    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1160    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1161    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1162    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1163    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1164    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1165    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1166    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1167    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1168    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1169
1170    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1171    PUSH_DATA (push, 1);
1172    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1173    PUSH_DATA (push, 1);
1174    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1175    PUSH_DATA (push, 0x40);
1176    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1177    PUSH_DATA (push, 0);
1178    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1179    PUSH_DATA (push, 0x30);
1180    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1181    PUSH_DATA (push, 3);
1182    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1183    PUSH_DATA (push, 0x20);
1184    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1185    PUSH_DATA (push, 0x00);
1186    screen->save_state.patch_vertices = 3;
1187
1188    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1189    PUSH_DATA (push, 0);
1190    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1191    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1192
1193    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1194
1195    if (nvc0_screen_init_compute(screen))
1196       goto fail;
1197
1198    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1199    for (i = 0; i < 5; ++i) {
1200       /* TIC and TSC entries for each unit (nve4+ only) */
1201       /* auxiliary constants (6 user clip planes, base instance id) */
1202       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1203       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1204       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1205       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1206       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1207       PUSH_DATA (push, (15 << 4) | 1);
1208       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1209          unsigned j;
1210          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1211          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1212          for (j = 0; j < 8; ++j)
1213             PUSH_DATA(push, j);
1214       } else {
1215          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1216          PUSH_DATA (push, 0x54);
1217       }
1218
1219       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1220       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1221       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1222       PUSH_DATA (push, 0); /* 0 */
1223       PUSH_DATA (push, 0);
1224       PUSH_DATA (push, 1); /* 1 */
1225       PUSH_DATA (push, 0);
1226       PUSH_DATA (push, 0); /* 2 */
1227       PUSH_DATA (push, 1);
1228       PUSH_DATA (push, 1); /* 3 */
1229       PUSH_DATA (push, 1);
1230       PUSH_DATA (push, 2); /* 4 */
1231       PUSH_DATA (push, 0);
1232       PUSH_DATA (push, 3); /* 5 */
1233       PUSH_DATA (push, 0);
1234       PUSH_DATA (push, 2); /* 6 */
1235       PUSH_DATA (push, 1);
1236       PUSH_DATA (push, 3); /* 7 */
1237       PUSH_DATA (push, 1);
1238    }
1239    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1240    PUSH_DATA (push, 0);
1241
1242    PUSH_KICK (push);
1243
1244    screen->tic.entries = CALLOC(4096, sizeof(void *));
1245    screen->tsc.entries = screen->tic.entries + 2048;
1246
1247    if (!nvc0_blitter_create(screen))
1248       goto fail;
1249
1250    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1251    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1252
1253    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1254
1255    return &screen->base;
1256
1257 fail:
1258    screen->base.base.context_create = NULL;
1259    return &screen->base;
1260 }
1261
1262 int
1263 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1264 {
1265    int i = screen->tic.next;
1266
1267    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1268       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1269
1270    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1271
1272    if (screen->tic.entries[i])
1273       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1274
1275    screen->tic.entries[i] = entry;
1276    return i;
1277 }
1278
1279 int
1280 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1281 {
1282    int i = screen->tsc.next;
1283
1284    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1285       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1286
1287    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1288
1289    if (screen->tsc.entries[i])
1290       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1291
1292    screen->tsc.entries[i] = entry;
1293    return i;
1294 }