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gallium: replace DRM_CONF_THROTTLE with PIPE_CAP_MAX_FRAMES_IN_FLIGHT
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "util/u_screen.h"
29 #include "pipe/p_screen.h"
30 #include "compiler/nir/nir.h"
31
32 #include "nouveau_vp3_video.h"
33
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_screen.h"
36
37 #include "nvc0/mme/com9097.mme.h"
38 #include "nvc0/mme/com90c0.mme.h"
39
40 #include "nv50/g80_texture.xml.h"
41
42 static boolean
43 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
44 enum pipe_format format,
45 enum pipe_texture_target target,
46 unsigned sample_count,
47 unsigned storage_sample_count,
48 unsigned bindings)
49 {
50 const struct util_format_description *desc = util_format_description(format);
51
52 if (sample_count > 8)
53 return false;
54 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
55 return false;
56
57 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
58 return false;
59
60 /* Short-circuit the rest of the logic -- this is used by the state tracker
61 * to determine valid MS levels in a no-attachments scenario.
62 */
63 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
64 return true;
65
66 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
67 if (util_format_get_blocksizebits(format) == 3 * 32)
68 return false;
69
70 if (bindings & PIPE_BIND_LINEAR)
71 if (util_format_is_depth_or_stencil(format) ||
72 (target != PIPE_TEXTURE_1D &&
73 target != PIPE_TEXTURE_2D &&
74 target != PIPE_TEXTURE_RECT) ||
75 sample_count > 1)
76 return false;
77
78 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
79 */
80 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
81 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
82 /* The claim is that this should work on GM107 but it doesn't. Need to
83 * test further and figure out if it's a nouveau issue or a HW one.
84 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
85 */
86 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
87 return false;
88
89 /* shared is always supported */
90 bindings &= ~(PIPE_BIND_LINEAR |
91 PIPE_BIND_SHARED);
92
93 if (bindings & PIPE_BIND_SHADER_IMAGE) {
94 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
95 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
96 /* This should work on Fermi, but for currently unknown reasons it
97 * does not and results in breaking reads from pbos. */
98 return false;
99 }
100 }
101
102 return (( nvc0_format_table[format].usage |
103 nvc0_vertex_format[format].usage) & bindings) == bindings;
104 }
105
106 static int
107 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
108 {
109 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
110 const struct nouveau_screen *screen = nouveau_screen(pscreen);
111 struct nouveau_device *dev = screen->device;
112
113 switch (param) {
114 /* non-boolean caps */
115 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
116 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
117 return 15;
118 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
119 return 12;
120 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
121 return 2048;
122 case PIPE_CAP_MIN_TEXEL_OFFSET:
123 return -8;
124 case PIPE_CAP_MAX_TEXEL_OFFSET:
125 return 7;
126 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
127 return -32;
128 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
129 return 31;
130 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
131 return 128 * 1024 * 1024;
132 case PIPE_CAP_GLSL_FEATURE_LEVEL:
133 return 430;
134 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
135 return 430;
136 case PIPE_CAP_MAX_RENDER_TARGETS:
137 return 8;
138 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
139 return 1;
140 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
141 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
142 return 8;
143 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
144 return 4;
145 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
146 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
147 return 128;
148 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
149 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
150 return 1024;
151 case PIPE_CAP_MAX_VERTEX_STREAMS:
152 return 4;
153 case PIPE_CAP_MAX_GS_INVOCATIONS:
154 return 32;
155 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
156 return 1 << 27;
157 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
158 return 2048;
159 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
160 return 2047;
161 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
162 return 256;
163 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
164 if (class_3d < GM107_3D_CLASS)
165 return 256; /* IMAGE bindings require alignment to 256 */
166 return 16;
167 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
168 return 16;
169 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
170 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
171 case PIPE_CAP_MAX_VIEWPORTS:
172 return NVC0_MAX_VIEWPORTS;
173 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
174 return 4;
175 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
176 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
177 case PIPE_CAP_ENDIANNESS:
178 return PIPE_ENDIAN_LITTLE;
179 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
180 return 30;
181 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
182 return NVC0_MAX_WINDOW_RECTANGLES;
183 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
184 return class_3d >= GM200_3D_CLASS ? 8 : 0;
185 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
186 return 64 * 1024 * 1024;
187 case PIPE_CAP_MAX_VARYINGS:
188 /* NOTE: These only count our slots for GENERIC varyings.
189 * The address space may be larger, but the actual hard limit seems to be
190 * less than what the address space layout permits, so don't add TEXCOORD,
191 * COLOR, etc. here.
192 */
193 return 0x1f0 / 16;
194
195 /* supported caps */
196 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
197 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
198 case PIPE_CAP_TEXTURE_SWIZZLE:
199 case PIPE_CAP_NPOT_TEXTURES:
200 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
201 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
202 case PIPE_CAP_ANISOTROPIC_FILTER:
203 case PIPE_CAP_SEAMLESS_CUBE_MAP:
204 case PIPE_CAP_CUBE_MAP_ARRAY:
205 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
206 case PIPE_CAP_TEXTURE_MULTISAMPLE:
207 case PIPE_CAP_DEPTH_CLIP_DISABLE:
208 case PIPE_CAP_POINT_SPRITE:
209 case PIPE_CAP_TGSI_TEXCOORD:
210 case PIPE_CAP_SM3:
211 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
212 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
213 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
214 case PIPE_CAP_QUERY_TIMESTAMP:
215 case PIPE_CAP_QUERY_TIME_ELAPSED:
216 case PIPE_CAP_OCCLUSION_QUERY:
217 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
218 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
219 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
220 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
221 case PIPE_CAP_INDEP_BLEND_ENABLE:
222 case PIPE_CAP_INDEP_BLEND_FUNC:
223 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
224 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
225 case PIPE_CAP_PRIMITIVE_RESTART:
226 case PIPE_CAP_TGSI_INSTANCEID:
227 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
228 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
229 case PIPE_CAP_CONDITIONAL_RENDER:
230 case PIPE_CAP_TEXTURE_BARRIER:
231 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
232 case PIPE_CAP_START_INSTANCE:
233 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
234 case PIPE_CAP_DRAW_INDIRECT:
235 case PIPE_CAP_USER_VERTEX_BUFFERS:
236 case PIPE_CAP_TEXTURE_QUERY_LOD:
237 case PIPE_CAP_SAMPLE_SHADING:
238 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
239 case PIPE_CAP_TEXTURE_GATHER_SM5:
240 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
241 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
242 case PIPE_CAP_SAMPLER_VIEW_TARGET:
243 case PIPE_CAP_CLIP_HALFZ:
244 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
245 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
246 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
247 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
248 case PIPE_CAP_DEPTH_BOUNDS_TEST:
249 case PIPE_CAP_TGSI_TXQS:
250 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
251 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
252 case PIPE_CAP_SHAREABLE_SHADERS:
253 case PIPE_CAP_CLEAR_TEXTURE:
254 case PIPE_CAP_DRAW_PARAMETERS:
255 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
256 case PIPE_CAP_MULTI_DRAW_INDIRECT:
257 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
258 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
259 case PIPE_CAP_QUERY_BUFFER_OBJECT:
260 case PIPE_CAP_INVALIDATE_BUFFER:
261 case PIPE_CAP_STRING_MARKER:
262 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
263 case PIPE_CAP_CULL_DISTANCE:
264 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
265 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
266 case PIPE_CAP_TGSI_VOTE:
267 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
268 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
269 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
270 case PIPE_CAP_DOUBLES:
271 case PIPE_CAP_INT64:
272 case PIPE_CAP_TGSI_TEX_TXF_LZ:
273 case PIPE_CAP_TGSI_CLOCK:
274 case PIPE_CAP_COMPUTE:
275 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
276 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
277 case PIPE_CAP_QUERY_SO_OVERFLOW:
278 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
279 return 1;
280 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
281 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
282 case PIPE_CAP_TGSI_FS_FBFETCH:
283 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
284 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
285 case PIPE_CAP_TGSI_BALLOT:
286 return class_3d >= NVE4_3D_CLASS;
287 case PIPE_CAP_BINDLESS_TEXTURE:
288 return class_3d >= NVE4_3D_CLASS;
289 case PIPE_CAP_TGSI_ATOMFADD:
290 return class_3d < GM107_3D_CLASS; /* needs additional lowering */
291 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
292 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
293 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
294 case PIPE_CAP_POST_DEPTH_COVERAGE:
295 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
296 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
297 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
298 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
299 return class_3d >= GM200_3D_CLASS;
300 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
301 return class_3d >= GP100_3D_CLASS;
302
303 /* caps has to be turned on with nir */
304 case PIPE_CAP_INT64_DIVMOD:
305 return screen->prefer_nir ? 1 : 0;
306
307 /* unsupported caps */
308 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
309 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
310 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
311 case PIPE_CAP_SHADER_STENCIL_EXPORT:
312 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
313 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
314 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
315 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
316 case PIPE_CAP_FAKE_SW_MSAA:
317 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
318 case PIPE_CAP_VERTEXID_NOBASE:
319 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
320 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
321 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
322 case PIPE_CAP_GENERATE_MIPMAP:
323 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
324 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
325 case PIPE_CAP_QUERY_MEMORY_INFO:
326 case PIPE_CAP_PCI_GROUP:
327 case PIPE_CAP_PCI_BUS:
328 case PIPE_CAP_PCI_DEVICE:
329 case PIPE_CAP_PCI_FUNCTION:
330 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
331 case PIPE_CAP_NATIVE_FENCE_FD:
332 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
333 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
334 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
335 case PIPE_CAP_MEMOBJ:
336 case PIPE_CAP_LOAD_CONSTBUF:
337 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
338 case PIPE_CAP_TILE_RASTER_ORDER:
339 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
340 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
341 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
342 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
343 case PIPE_CAP_FENCE_SIGNAL:
344 case PIPE_CAP_CONSTBUF0_FLAGS:
345 case PIPE_CAP_PACKED_UNIFORMS:
346 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
347 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
348 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
349 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
350 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
351 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
352 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
353 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
354 case PIPE_CAP_NIR_COMPACT_ARRAYS:
355 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
356 return 0;
357
358 case PIPE_CAP_MAX_FRAMES_IN_FLIGHT:
359 return 2;
360
361 case PIPE_CAP_VENDOR_ID:
362 return 0x10de;
363 case PIPE_CAP_DEVICE_ID: {
364 uint64_t device_id;
365 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
366 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
367 return -1;
368 }
369 return device_id;
370 }
371 case PIPE_CAP_ACCELERATED:
372 return 1;
373 case PIPE_CAP_VIDEO_MEMORY:
374 return dev->vram_size >> 20;
375 case PIPE_CAP_UMA:
376 return 0;
377 default:
378 debug_printf("%s: unhandled cap %d\n", __func__, param);
379 return u_pipe_screen_get_param_defaults(pscreen, param);
380 }
381 }
382
383 static int
384 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
385 enum pipe_shader_type shader,
386 enum pipe_shader_cap param)
387 {
388 const struct nouveau_screen *screen = nouveau_screen(pscreen);
389 const uint16_t class_3d = screen->class_3d;
390
391 switch (shader) {
392 case PIPE_SHADER_VERTEX:
393 case PIPE_SHADER_GEOMETRY:
394 case PIPE_SHADER_FRAGMENT:
395 case PIPE_SHADER_COMPUTE:
396 case PIPE_SHADER_TESS_CTRL:
397 case PIPE_SHADER_TESS_EVAL:
398 break;
399 default:
400 return 0;
401 }
402
403 switch (param) {
404 case PIPE_SHADER_CAP_PREFERRED_IR:
405 return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
406 case PIPE_SHADER_CAP_SUPPORTED_IRS:
407 return 1 << PIPE_SHADER_IR_TGSI |
408 1 << PIPE_SHADER_IR_NIR;
409 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
410 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
411 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
412 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
413 return 16384;
414 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
415 return 16;
416 case PIPE_SHADER_CAP_MAX_INPUTS:
417 return 0x200 / 16;
418 case PIPE_SHADER_CAP_MAX_OUTPUTS:
419 return 32;
420 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
421 return NVC0_MAX_CONSTBUF_SIZE;
422 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
423 return NVC0_MAX_PIPE_CONSTBUFS;
424 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
425 return shader != PIPE_SHADER_FRAGMENT;
426 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
427 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
428 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
429 return 1;
430 case PIPE_SHADER_CAP_MAX_TEMPS:
431 return NVC0_CAP_MAX_PROGRAM_TEMPS;
432 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
433 return 1;
434 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
435 return 1;
436 case PIPE_SHADER_CAP_SUBROUTINES:
437 return 1;
438 case PIPE_SHADER_CAP_INTEGERS:
439 return 1;
440 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
441 return 1;
442 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
443 return 1;
444 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
445 return 1;
446 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
447 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
448 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
449 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
450 case PIPE_SHADER_CAP_INT64_ATOMICS:
451 case PIPE_SHADER_CAP_FP16:
452 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
453 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
454 return 0;
455 case PIPE_SHADER_CAP_SCALAR_ISA:
456 return 1;
457 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
458 return NVC0_MAX_BUFFERS;
459 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
460 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
461 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
462 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
463 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
464 return 32;
465 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
466 if (class_3d >= NVE4_3D_CLASS)
467 return NVC0_MAX_IMAGES;
468 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
469 return NVC0_MAX_IMAGES;
470 return 0;
471 default:
472 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
473 return 0;
474 }
475 }
476
477 static float
478 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
479 {
480 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
481
482 switch (param) {
483 case PIPE_CAPF_MAX_LINE_WIDTH:
484 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
485 return 10.0f;
486 case PIPE_CAPF_MAX_POINT_WIDTH:
487 return 63.0f;
488 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
489 return 63.375f;
490 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
491 return 16.0f;
492 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
493 return 15.0f;
494 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
495 return 0.0f;
496 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
497 return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
498 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
499 return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
500 }
501
502 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
503 return 0.0f;
504 }
505
506 static int
507 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
508 enum pipe_shader_ir ir_type,
509 enum pipe_compute_cap param, void *data)
510 {
511 struct nvc0_screen *screen = nvc0_screen(pscreen);
512 const uint16_t obj_class = screen->compute->oclass;
513
514 #define RET(x) do { \
515 if (data) \
516 memcpy(data, x, sizeof(x)); \
517 return sizeof(x); \
518 } while (0)
519
520 switch (param) {
521 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
522 RET((uint64_t []) { 3 });
523 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
524 if (obj_class >= NVE4_COMPUTE_CLASS) {
525 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
526 } else {
527 RET(((uint64_t []) { 65535, 65535, 65535 }));
528 }
529 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
530 RET(((uint64_t []) { 1024, 1024, 64 }));
531 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
532 RET((uint64_t []) { 1024 });
533 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
534 if (obj_class >= NVE4_COMPUTE_CLASS) {
535 RET((uint64_t []) { 1024 });
536 } else {
537 RET((uint64_t []) { 512 });
538 }
539 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
540 RET((uint64_t []) { 1ULL << 40 });
541 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
542 switch (obj_class) {
543 case GM200_COMPUTE_CLASS:
544 RET((uint64_t []) { 96 << 10 });
545 break;
546 case GM107_COMPUTE_CLASS:
547 RET((uint64_t []) { 64 << 10 });
548 break;
549 default:
550 RET((uint64_t []) { 48 << 10 });
551 break;
552 }
553 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
554 RET((uint64_t []) { 512 << 10 });
555 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
556 RET((uint64_t []) { 4096 });
557 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
558 RET((uint32_t []) { 32 });
559 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
560 RET((uint64_t []) { 1ULL << 40 });
561 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
562 RET((uint32_t []) { 0 });
563 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
564 RET((uint32_t []) { screen->mp_count_compute });
565 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
566 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
567 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
568 RET((uint32_t []) { 64 });
569 default:
570 return 0;
571 }
572
573 #undef RET
574 }
575
576 static void
577 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
578 unsigned sample_count,
579 unsigned *width, unsigned *height)
580 {
581 switch (sample_count) {
582 case 0:
583 case 1:
584 /* this could be 4x4, but the GL state tracker makes it difficult to
585 * create a 1x MSAA texture and smaller grids save CB space */
586 *width = 2;
587 *height = 4;
588 break;
589 case 2:
590 *width = 2;
591 *height = 4;
592 break;
593 case 4:
594 *width = 2;
595 *height = 2;
596 break;
597 case 8:
598 *width = 1;
599 *height = 2;
600 break;
601 default:
602 assert(0);
603 }
604 }
605
606 static void
607 nvc0_screen_destroy(struct pipe_screen *pscreen)
608 {
609 struct nvc0_screen *screen = nvc0_screen(pscreen);
610
611 if (!nouveau_drm_screen_unref(&screen->base))
612 return;
613
614 if (screen->base.fence.current) {
615 struct nouveau_fence *current = NULL;
616
617 /* nouveau_fence_wait will create a new current fence, so wait on the
618 * _current_ one, and remove both.
619 */
620 nouveau_fence_ref(screen->base.fence.current, &current);
621 nouveau_fence_wait(current, NULL);
622 nouveau_fence_ref(NULL, &current);
623 nouveau_fence_ref(NULL, &screen->base.fence.current);
624 }
625 if (screen->base.pushbuf)
626 screen->base.pushbuf->user_priv = NULL;
627
628 if (screen->blitter)
629 nvc0_blitter_destroy(screen);
630 if (screen->pm.prog) {
631 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
632 nvc0_program_destroy(NULL, screen->pm.prog);
633 FREE(screen->pm.prog);
634 }
635
636 nouveau_bo_ref(NULL, &screen->text);
637 nouveau_bo_ref(NULL, &screen->uniform_bo);
638 nouveau_bo_ref(NULL, &screen->tls);
639 nouveau_bo_ref(NULL, &screen->txc);
640 nouveau_bo_ref(NULL, &screen->fence.bo);
641 nouveau_bo_ref(NULL, &screen->poly_cache);
642
643 nouveau_heap_destroy(&screen->lib_code);
644 nouveau_heap_destroy(&screen->text_heap);
645
646 FREE(screen->tic.entries);
647
648 nouveau_object_del(&screen->eng3d);
649 nouveau_object_del(&screen->eng2d);
650 nouveau_object_del(&screen->m2mf);
651 nouveau_object_del(&screen->compute);
652 nouveau_object_del(&screen->nvsw);
653
654 nouveau_screen_fini(&screen->base);
655
656 FREE(screen);
657 }
658
659 static int
660 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
661 unsigned size, const uint32_t *data)
662 {
663 struct nouveau_pushbuf *push = screen->base.pushbuf;
664
665 size /= 4;
666
667 assert((pos + size) <= 0x800);
668
669 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
670 PUSH_DATA (push, (m - 0x3800) / 8);
671 PUSH_DATA (push, pos);
672 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
673 PUSH_DATA (push, pos);
674 PUSH_DATAp(push, data, size);
675
676 return pos + size;
677 }
678
679 static void
680 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
681 {
682 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
683 PUSH_DATA (push, 0xff);
684 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
685 PUSH_DATA (push, 0xff);
686 PUSH_DATA (push, 0xff);
687 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
688 PUSH_DATA (push, 0xff);
689 PUSH_DATA (push, 0xff);
690 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
691 PUSH_DATA (push, 0x3f);
692
693 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
694 PUSH_DATA (push, (3 << 16) | 3);
695 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
696 PUSH_DATA (push, (2 << 16) | 2);
697
698 if (obj_class < GM107_3D_CLASS) {
699 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
700 PUSH_DATA (push, 0);
701 }
702 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
703 PUSH_DATA (push, 0x10);
704 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
705 PUSH_DATA (push, 0x10);
706 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
707 PUSH_DATA (push, 0x10);
708 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
709 PUSH_DATA (push, 0x10);
710 PUSH_DATA (push, 0x10);
711 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
712 PUSH_DATA (push, 0x10);
713 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
714 PUSH_DATA (push, 0xe);
715
716 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
717 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
718 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
719 PUSH_DATA (push, 0);
720 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
721 PUSH_DATA (push, 3);
722
723 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
724 PUSH_DATA (push, 0x3fffff);
725 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
726 PUSH_DATA (push, 1);
727 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
728 PUSH_DATA (push, 1);
729
730 if (obj_class < GM107_3D_CLASS) {
731 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
732 PUSH_DATA (push, 3);
733
734 if (obj_class >= NVE4_3D_CLASS) {
735 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
736 PUSH_DATA (push, 1);
737 }
738 }
739
740 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
741 * are supposed to do */
742 }
743
744 static void
745 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
746 {
747 struct nvc0_screen *screen = nvc0_screen(pscreen);
748 struct nouveau_pushbuf *push = screen->base.pushbuf;
749
750 /* we need to do it after possible flush in MARK_RING */
751 *sequence = ++screen->base.fence.sequence;
752
753 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
754 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
755 PUSH_DATAh(push, screen->fence.bo->offset);
756 PUSH_DATA (push, screen->fence.bo->offset);
757 PUSH_DATA (push, *sequence);
758 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
759 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
760 }
761
762 static u32
763 nvc0_screen_fence_update(struct pipe_screen *pscreen)
764 {
765 struct nvc0_screen *screen = nvc0_screen(pscreen);
766 return screen->fence.map[0];
767 }
768
769 static int
770 nvc0_screen_init_compute(struct nvc0_screen *screen)
771 {
772 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
773
774 switch (screen->base.device->chipset & ~0xf) {
775 case 0xc0:
776 case 0xd0:
777 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
778 case 0xe0:
779 case 0xf0:
780 case 0x100:
781 case 0x110:
782 case 0x120:
783 case 0x130:
784 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
785 default:
786 return -1;
787 }
788 }
789
790 static int
791 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
792 uint32_t lpos, uint32_t lneg, uint32_t cstack)
793 {
794 struct nouveau_bo *bo = NULL;
795 int ret;
796 uint64_t size = (lpos + lneg) * 32 + cstack;
797
798 if (size >= (1 << 20)) {
799 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
800 return -1;
801 }
802
803 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
804 size = align(size, 0x8000);
805 size *= screen->mp_count;
806
807 size = align(size, 1 << 17);
808
809 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
810 NULL, &bo);
811 if (ret)
812 return ret;
813
814 /* Make sure that the pushbuf has acquired a reference to the old tls
815 * segment, as it may have commands that will reference it.
816 */
817 if (screen->tls)
818 PUSH_REFN(screen->base.pushbuf, screen->tls,
819 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
820 nouveau_bo_ref(NULL, &screen->tls);
821 screen->tls = bo;
822 return 0;
823 }
824
825 int
826 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
827 {
828 struct nouveau_pushbuf *push = screen->base.pushbuf;
829 struct nouveau_bo *bo;
830 int ret;
831
832 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
833 1 << 17, size, NULL, &bo);
834 if (ret)
835 return ret;
836
837 /* Make sure that the pushbuf has acquired a reference to the old text
838 * segment, as it may have commands that will reference it.
839 */
840 if (screen->text)
841 PUSH_REFN(push, screen->text,
842 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
843 nouveau_bo_ref(NULL, &screen->text);
844 screen->text = bo;
845
846 nouveau_heap_destroy(&screen->lib_code);
847 nouveau_heap_destroy(&screen->text_heap);
848
849 /* XXX: getting a page fault at the end of the code buffer every few
850 * launches, don't use the last 256 bytes to work around them - prefetch ?
851 */
852 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
853
854 /* update the code segment setup */
855 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
856 PUSH_DATAh(push, screen->text->offset);
857 PUSH_DATA (push, screen->text->offset);
858 if (screen->compute) {
859 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
860 PUSH_DATAh(push, screen->text->offset);
861 PUSH_DATA (push, screen->text->offset);
862 }
863
864 return 0;
865 }
866
867 void
868 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
869 int stage, int index, int size, uint64_t addr)
870 {
871 assert(stage != 5);
872
873 struct nouveau_pushbuf *push = screen->base.pushbuf;
874
875 if (screen->base.class_3d >= GM107_3D_CLASS) {
876 struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
877
878 // TODO: Better figure out the conditions in which this is needed
879 bool serialize = binding->addr == addr && binding->size != size;
880 if (can_serialize)
881 serialize = serialize && *can_serialize;
882 if (serialize) {
883 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
884 if (can_serialize)
885 *can_serialize = false;
886 }
887
888 binding->addr = addr;
889 binding->size = size;
890 }
891
892 if (size >= 0) {
893 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
894 PUSH_DATA (push, size);
895 PUSH_DATAh(push, addr);
896 PUSH_DATA (push, addr);
897 }
898 IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
899 }
900
901 static const nir_shader_compiler_options nir_options = {
902 .lower_fdiv = false,
903 .lower_ffma = false,
904 .fuse_ffma = false, /* nir doesn't track mad vs fma */
905 .lower_flrp32 = true,
906 .lower_flrp64 = true,
907 .lower_fpow = false,
908 .lower_fsat = false,
909 .lower_fsqrt = false, // TODO: only before gm200
910 .lower_fmod32 = true,
911 .lower_fmod64 = true,
912 .lower_bitfield_extract = false,
913 .lower_bitfield_extract_to_shifts = false,
914 .lower_bitfield_insert = false,
915 .lower_bitfield_insert_to_shifts = false,
916 .lower_bitfield_reverse = false,
917 .lower_bit_count = false,
918 .lower_bfm = false,
919 .lower_ifind_msb = false,
920 .lower_find_lsb = false,
921 .lower_uadd_carry = true, // TODO
922 .lower_usub_borrow = true, // TODO
923 .lower_mul_high = false,
924 .lower_negate = false,
925 .lower_sub = false, // TODO
926 .lower_scmp = true, // TODO: not implemented yet
927 .lower_idiv = true,
928 .lower_isign = false, // TODO
929 .fdot_replicates = false, // TODO
930 .lower_ffloor = false, // TODO
931 .lower_ffract = true,
932 .lower_fceil = false, // TODO
933 .lower_ldexp = true,
934 .lower_pack_half_2x16 = true,
935 .lower_pack_unorm_2x16 = true,
936 .lower_pack_snorm_2x16 = true,
937 .lower_pack_unorm_4x8 = true,
938 .lower_pack_snorm_4x8 = true,
939 .lower_unpack_half_2x16 = true,
940 .lower_unpack_unorm_2x16 = true,
941 .lower_unpack_snorm_2x16 = true,
942 .lower_unpack_unorm_4x8 = true,
943 .lower_unpack_snorm_4x8 = true,
944 .lower_extract_byte = true,
945 .lower_extract_word = true,
946 .lower_all_io_to_temps = false,
947 .native_integers = true,
948 .vertex_id_zero_based = false,
949 .lower_base_vertex = false,
950 .lower_helper_invocation = false,
951 .lower_cs_local_index_from_id = true,
952 .lower_cs_local_id_from_index = false,
953 .lower_device_index_to_zero = false, // TODO
954 .lower_wpos_pntc = false, // TODO
955 .lower_hadd = true, // TODO
956 .lower_add_sat = true, // TODO
957 .use_interpolated_input_intrinsics = true,
958 .lower_mul_2x32_64 = true, // TODO
959 .max_unroll_iterations = 32,
960 .lower_int64_options = nir_lower_divmod64, // TODO
961 .lower_doubles_options = 0, // TODO
962 };
963
964 static const void *
965 nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
966 enum pipe_shader_ir ir,
967 enum pipe_shader_type shader)
968 {
969 if (ir == PIPE_SHADER_IR_NIR)
970 return &nir_options;
971 return NULL;
972 }
973
974 #define FAIL_SCREEN_INIT(str, err) \
975 do { \
976 NOUVEAU_ERR(str, err); \
977 goto fail; \
978 } while(0)
979
980 struct nouveau_screen *
981 nvc0_screen_create(struct nouveau_device *dev)
982 {
983 struct nvc0_screen *screen;
984 struct pipe_screen *pscreen;
985 struct nouveau_object *chan;
986 struct nouveau_pushbuf *push;
987 uint64_t value;
988 uint32_t obj_class;
989 uint32_t flags;
990 int ret;
991 unsigned i;
992
993 switch (dev->chipset & ~0xf) {
994 case 0xc0:
995 case 0xd0:
996 case 0xe0:
997 case 0xf0:
998 case 0x100:
999 case 0x110:
1000 case 0x120:
1001 case 0x130:
1002 break;
1003 default:
1004 return NULL;
1005 }
1006
1007 screen = CALLOC_STRUCT(nvc0_screen);
1008 if (!screen)
1009 return NULL;
1010 pscreen = &screen->base.base;
1011 pscreen->destroy = nvc0_screen_destroy;
1012
1013 ret = nouveau_screen_init(&screen->base, dev);
1014 if (ret)
1015 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
1016 chan = screen->base.channel;
1017 push = screen->base.pushbuf;
1018 push->user_priv = screen;
1019 push->rsvd_kick = 5;
1020
1021 /* TODO: could this be higher on Kepler+? how does reclocking vs no
1022 * reclocking affect performance?
1023 * TODO: could this be higher on Fermi?
1024 */
1025 if (dev->chipset >= 0xe0)
1026 screen->base.transfer_pushbuf_threshold = 1024;
1027
1028 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1029 PIPE_BIND_SHADER_BUFFER |
1030 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
1031 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
1032 screen->base.sysmem_bindings |=
1033 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1034
1035 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
1036 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
1037 screen->base.vidmem_bindings = 0;
1038 }
1039
1040 pscreen->context_create = nvc0_create;
1041 pscreen->is_format_supported = nvc0_screen_is_format_supported;
1042 pscreen->get_param = nvc0_screen_get_param;
1043 pscreen->get_shader_param = nvc0_screen_get_shader_param;
1044 pscreen->get_paramf = nvc0_screen_get_paramf;
1045 pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
1046 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
1047 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
1048 /* nir stuff */
1049 pscreen->get_compiler_options = nvc0_screen_get_compiler_options;
1050
1051 nvc0_screen_init_resource_functions(pscreen);
1052
1053 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1054 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1055
1056 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
1057 if (screen->base.drm->version >= 0x01000202)
1058 flags |= NOUVEAU_BO_COHERENT;
1059
1060 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
1061 if (ret)
1062 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
1063 nouveau_bo_map(screen->fence.bo, 0, NULL);
1064 screen->fence.map = screen->fence.bo->map;
1065 screen->base.fence.emit = nvc0_screen_fence_emit;
1066 screen->base.fence.update = nvc0_screen_fence_update;
1067
1068
1069 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
1070 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
1071 if (ret)
1072 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
1073
1074 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
1075 PUSH_DATA (push, screen->nvsw->handle);
1076
1077 switch (dev->chipset & ~0xf) {
1078 case 0x130:
1079 case 0x120:
1080 case 0x110:
1081 case 0x100:
1082 case 0xf0:
1083 obj_class = NVF0_P2MF_CLASS;
1084 break;
1085 case 0xe0:
1086 obj_class = NVE4_P2MF_CLASS;
1087 break;
1088 default:
1089 obj_class = NVC0_M2MF_CLASS;
1090 break;
1091 }
1092 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1093 &screen->m2mf);
1094 if (ret)
1095 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1096
1097 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1098 PUSH_DATA (push, screen->m2mf->oclass);
1099 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1100 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1101 PUSH_DATA (push, 0xa0b5);
1102 }
1103
1104 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1105 &screen->eng2d);
1106 if (ret)
1107 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1108
1109 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1110 PUSH_DATA (push, screen->eng2d->oclass);
1111 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1112 PUSH_DATA (push, 0);
1113 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1114 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1115 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1116 PUSH_DATA (push, 0);
1117 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1118 PUSH_DATA (push, 0);
1119 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1120 PUSH_DATA (push, 0x3f);
1121 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1122 PUSH_DATA (push, 1);
1123 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1124 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1125
1126 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1127 PUSH_DATAh(push, screen->fence.bo->offset + 16);
1128 PUSH_DATA (push, screen->fence.bo->offset + 16);
1129
1130 switch (dev->chipset & ~0xf) {
1131 case 0x130:
1132 switch (dev->chipset) {
1133 case 0x130:
1134 case 0x13b:
1135 obj_class = GP100_3D_CLASS;
1136 break;
1137 default:
1138 obj_class = GP102_3D_CLASS;
1139 break;
1140 }
1141 break;
1142 case 0x120:
1143 obj_class = GM200_3D_CLASS;
1144 break;
1145 case 0x110:
1146 obj_class = GM107_3D_CLASS;
1147 break;
1148 case 0x100:
1149 case 0xf0:
1150 obj_class = NVF0_3D_CLASS;
1151 break;
1152 case 0xe0:
1153 switch (dev->chipset) {
1154 case 0xea:
1155 obj_class = NVEA_3D_CLASS;
1156 break;
1157 default:
1158 obj_class = NVE4_3D_CLASS;
1159 break;
1160 }
1161 break;
1162 case 0xd0:
1163 obj_class = NVC8_3D_CLASS;
1164 break;
1165 case 0xc0:
1166 default:
1167 switch (dev->chipset) {
1168 case 0xc8:
1169 obj_class = NVC8_3D_CLASS;
1170 break;
1171 case 0xc1:
1172 obj_class = NVC1_3D_CLASS;
1173 break;
1174 default:
1175 obj_class = NVC0_3D_CLASS;
1176 break;
1177 }
1178 break;
1179 }
1180 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1181 &screen->eng3d);
1182 if (ret)
1183 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1184 screen->base.class_3d = obj_class;
1185
1186 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1187 PUSH_DATA (push, screen->eng3d->oclass);
1188
1189 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1190 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1191
1192 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1193 /* kill shaders after about 1 second (at 100 MHz) */
1194 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1195 PUSH_DATA (push, 0x17);
1196 }
1197
1198 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1199 screen->base.drm->version >= 0x01000101);
1200 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1201 for (i = 0; i < 8; ++i)
1202 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1203
1204 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1205 PUSH_DATA (push, 1);
1206
1207 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1208 PUSH_DATA (push, 0);
1209 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1210 PUSH_DATA (push, 0);
1211 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1212 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1213 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1214 PUSH_DATA (push, 0);
1215 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1216 PUSH_DATA (push, 1);
1217 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1218 PUSH_DATA (push, 1);
1219 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1220 PUSH_DATA (push, 1);
1221 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1222 PUSH_DATA (push, 0);
1223 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1224 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1225 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1226 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1227 } else {
1228 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1229 PUSH_DATA (push, 15);
1230 }
1231 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1232 PUSH_DATA (push, 8); /* 128 */
1233 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1234 PUSH_DATA (push, 1);
1235 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1236 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1237 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1238 }
1239
1240 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1241
1242 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1243 if (ret)
1244 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1245
1246 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1247 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1248 &screen->uniform_bo);
1249 if (ret)
1250 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1251
1252 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1253
1254 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1255 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1256 PUSH_DATA (push, 256);
1257 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1258 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1259 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1260 PUSH_DATA (push, 0);
1261 PUSH_DATAf(push, 0.0f);
1262 PUSH_DATAf(push, 0.0f);
1263 PUSH_DATAf(push, 0.0f);
1264 PUSH_DATAf(push, 0.0f);
1265 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1266 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1267 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1268
1269 if (screen->base.drm->version >= 0x01000101) {
1270 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1271 if (ret)
1272 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1273 } else {
1274 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1275 value = (8 << 8) | 4;
1276 else
1277 value = (16 << 8) | 4;
1278 }
1279 screen->gpc_count = value & 0x000000ff;
1280 screen->mp_count = value >> 8;
1281 screen->mp_count_compute = screen->mp_count;
1282
1283 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1284 if (ret)
1285 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1286
1287 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1288 PUSH_DATAh(push, screen->tls->offset);
1289 PUSH_DATA (push, screen->tls->offset);
1290 PUSH_DATA (push, screen->tls->size >> 32);
1291 PUSH_DATA (push, screen->tls->size);
1292 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1293 PUSH_DATA (push, 0);
1294 /* Reduce likelihood of collision with real buffers by placing the hole at
1295 * the top of the 4G area. This will have to be dealt with for real
1296 * eventually by blocking off that area from the VM.
1297 */
1298 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1299 PUSH_DATA (push, 0xff << 24);
1300
1301 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1302 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1303 &screen->poly_cache);
1304 if (ret)
1305 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1306
1307 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1308 PUSH_DATAh(push, screen->poly_cache->offset);
1309 PUSH_DATA (push, screen->poly_cache->offset);
1310 PUSH_DATA (push, 3);
1311 }
1312
1313 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1314 &screen->txc);
1315 if (ret)
1316 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1317
1318 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1319 PUSH_DATAh(push, screen->txc->offset);
1320 PUSH_DATA (push, screen->txc->offset);
1321 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1322 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1323 screen->tic.maxwell = true;
1324 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1325 screen->tic.maxwell =
1326 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1327 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1328 }
1329 }
1330
1331 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1332 PUSH_DATAh(push, screen->txc->offset + 65536);
1333 PUSH_DATA (push, screen->txc->offset + 65536);
1334 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1335
1336 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1337 PUSH_DATA (push, 0);
1338 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1339 PUSH_DATA (push, 0);
1340 PUSH_DATA (push, 0);
1341 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1342 PUSH_DATA (push, 0x3f);
1343
1344 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1345 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1346 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1347 for (i = 0; i < 8 * 2; ++i)
1348 PUSH_DATA(push, 0);
1349 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1350 PUSH_DATA (push, 0);
1351 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1352 PUSH_DATA (push, 0);
1353
1354 /* neither scissors, viewport nor stencil mask should affect clears */
1355 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1356 PUSH_DATA (push, 0);
1357
1358 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1359 PUSH_DATA (push, 1);
1360 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1361 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1362 PUSH_DATAf(push, 0.0f);
1363 PUSH_DATAf(push, 1.0f);
1364 }
1365 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1366 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1367
1368 /* We use scissors instead of exact view volume clipping,
1369 * so they're always enabled.
1370 */
1371 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1372 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1373 PUSH_DATA (push, 1);
1374 PUSH_DATA (push, 16384 << 16);
1375 PUSH_DATA (push, 16384 << 16);
1376 }
1377
1378 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1379
1380 i = 0;
1381 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1382 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1383 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1384 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1385 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1386 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1387 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1388 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1389 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1390 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1391 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1392 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1393 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1394 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1395 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1396 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1397
1398 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1399 PUSH_DATA (push, 1);
1400 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1401 PUSH_DATA (push, 1);
1402 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1403 PUSH_DATA (push, 0x40);
1404 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1405 PUSH_DATA (push, 0);
1406 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1407 PUSH_DATA (push, 0x30);
1408 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1409 PUSH_DATA (push, 3);
1410 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1411 PUSH_DATA (push, 0x20);
1412 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1413 PUSH_DATA (push, 0x00);
1414 screen->save_state.patch_vertices = 3;
1415
1416 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1417 PUSH_DATA (push, 0);
1418 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1419 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1420
1421 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1422
1423 if (nvc0_screen_init_compute(screen))
1424 goto fail;
1425
1426 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1427 for (i = 0; i < 5; ++i) {
1428 unsigned j = 0;
1429 for (j = 0; j < 16; j++)
1430 screen->cb_bindings[i][j].size = -1;
1431
1432 /* TIC and TSC entries for each unit (nve4+ only) */
1433 /* auxiliary constants (6 user clip planes, base instance id) */
1434 nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1435 screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1436 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1437 unsigned j;
1438 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1439 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1440 for (j = 0; j < 8; ++j)
1441 PUSH_DATA(push, j);
1442 } else {
1443 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1444 PUSH_DATA (push, 0x54);
1445 }
1446
1447 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1448 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1449 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1450 PUSH_DATA (push, 0); /* 0 */
1451 PUSH_DATA (push, 0);
1452 PUSH_DATA (push, 1); /* 1 */
1453 PUSH_DATA (push, 0);
1454 PUSH_DATA (push, 0); /* 2 */
1455 PUSH_DATA (push, 1);
1456 PUSH_DATA (push, 1); /* 3 */
1457 PUSH_DATA (push, 1);
1458 PUSH_DATA (push, 2); /* 4 */
1459 PUSH_DATA (push, 0);
1460 PUSH_DATA (push, 3); /* 5 */
1461 PUSH_DATA (push, 0);
1462 PUSH_DATA (push, 2); /* 6 */
1463 PUSH_DATA (push, 1);
1464 PUSH_DATA (push, 3); /* 7 */
1465 PUSH_DATA (push, 1);
1466 }
1467 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1468 PUSH_DATA (push, 0);
1469
1470 PUSH_KICK (push);
1471
1472 screen->tic.entries = CALLOC(
1473 NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1474 sizeof(void *));
1475 screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1476 screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1477
1478 if (!nvc0_blitter_create(screen))
1479 goto fail;
1480
1481 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1482
1483 return &screen->base;
1484
1485 fail:
1486 screen->base.base.context_create = NULL;
1487 return &screen->base;
1488 }
1489
1490 int
1491 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1492 {
1493 int i = screen->tic.next;
1494
1495 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1496 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1497
1498 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1499
1500 if (screen->tic.entries[i])
1501 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1502
1503 screen->tic.entries[i] = entry;
1504 return i;
1505 }
1506
1507 int
1508 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1509 {
1510 int i = screen->tsc.next;
1511
1512 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1513 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1514
1515 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1516
1517 if (screen->tsc.entries[i])
1518 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1519
1520 screen->tsc.entries[i] = entry;
1521 return i;
1522 }