src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 #include "nv50/g80_texture.xml.h"
  42
  43 static boolean
  44 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  45                                 enum pipe_format format,
  46                                 enum pipe_texture_target target,
  47                                 unsigned sample_count,
  48                                 unsigned bindings)
  49 {
  50    const struct util_format_description *desc = util_format_description(format);
  51
  52    if (sample_count > 8)
  53       return false;
  54    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  55       return false;
  56
  57    /* Short-circuit the rest of the logic -- this is used by the state tracker
  58     * to determine valid MS levels in a no-attachments scenario.
  59     */
  60    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  61       return true;
  62
  63    if (!util_format_is_supported(format, bindings))
  64       return false;
  65
  66    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  67       if (util_format_get_blocksizebits(format) == 3 * 32)
  68          return false;
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  79     */
  80    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  81         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  82        /* The claim is that this should work on GM107 but it doesn't. Need to
  83         * test further and figure out if it's a nouveau issue or a HW one.
  84        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  85         */
  86        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  87       return false;
  88
  89    /* shared is always supported */
  90    bindings &= ~(PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
  94        nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  95       /* MS images are currently unsupported on Maxwell because they have to
  96        * be handled explicitly. */
  97       return false;
  98    }
  99
 100    return (( nvc0_format_table[format].usage |
 101             nvc0_vertex_format[format].usage) & bindings) == bindings;
 102 }
 103
 104 static int
 105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 108    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 109
 110    switch (param) {
 111    /* non-boolean caps */
 112    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 113    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 114       return 15;
 115    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 116       return 12;
 117    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 118       return 2048;
 119    case PIPE_CAP_MIN_TEXEL_OFFSET:
 120       return -8;
 121    case PIPE_CAP_MAX_TEXEL_OFFSET:
 122       return 7;
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124       return -32;
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126       return 31;
 127    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 128       return 128 * 1024 * 1024;
 129    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 130       return 430;
 131    case PIPE_CAP_MAX_RENDER_TARGETS:
 132       return 8;
 133    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 134       return 1;
 135    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 136       return 4;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 138    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 139       return 128;
 140    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 141    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 142       return 1024;
 143    case PIPE_CAP_MAX_VERTEX_STREAMS:
 144       return 4;
 145    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 146       return 2048;
 147    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 148       return 256;
 149    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 150       if (class_3d < NVE4_3D_CLASS)
 151          return 256; /* IMAGE bindings require alignment to 256 */
 152       return 16;
 153    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 154       return 16;
 155    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 156       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 157    case PIPE_CAP_MAX_VIEWPORTS:
 158       return NVC0_MAX_VIEWPORTS;
 159    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 160       return 4;
 161    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 162       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 163    case PIPE_CAP_ENDIANNESS:
 164       return PIPE_ENDIAN_LITTLE;
 165    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 166       return 30;
 167    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 168       return NVC0_MAX_WINDOW_RECTANGLES;
 169
 170    /* supported caps */
 171    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 172    case PIPE_CAP_TEXTURE_SWIZZLE:
 173    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 174    case PIPE_CAP_NPOT_TEXTURES:
 175    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 176    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 177    case PIPE_CAP_ANISOTROPIC_FILTER:
 178    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 179    case PIPE_CAP_CUBE_MAP_ARRAY:
 180    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 181    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 182    case PIPE_CAP_TWO_SIDED_STENCIL:
 183    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 184    case PIPE_CAP_POINT_SPRITE:
 185    case PIPE_CAP_TGSI_TEXCOORD:
 186    case PIPE_CAP_SM3:
 187    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 188    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 189    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 190    case PIPE_CAP_QUERY_TIMESTAMP:
 191    case PIPE_CAP_QUERY_TIME_ELAPSED:
 192    case PIPE_CAP_OCCLUSION_QUERY:
 193    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 194    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 195    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 196    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 197    case PIPE_CAP_INDEP_BLEND_ENABLE:
 198    case PIPE_CAP_INDEP_BLEND_FUNC:
 199    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 200    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 201    case PIPE_CAP_PRIMITIVE_RESTART:
 202    case PIPE_CAP_TGSI_INSTANCEID:
 203    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 204    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 205    case PIPE_CAP_CONDITIONAL_RENDER:
 206    case PIPE_CAP_TEXTURE_BARRIER:
 207    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 208    case PIPE_CAP_START_INSTANCE:
 209    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 210    case PIPE_CAP_DRAW_INDIRECT:
 211    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 212    case PIPE_CAP_USER_VERTEX_BUFFERS:
 213    case PIPE_CAP_TEXTURE_QUERY_LOD:
 214    case PIPE_CAP_SAMPLE_SHADING:
 215    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 216    case PIPE_CAP_TEXTURE_GATHER_SM5:
 217    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 218    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 219    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 220    case PIPE_CAP_CLIP_HALFZ:
 221    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 222    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 223    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 224    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 225    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 226    case PIPE_CAP_TGSI_TXQS:
 227    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 228    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 229    case PIPE_CAP_SHAREABLE_SHADERS:
 230    case PIPE_CAP_CLEAR_TEXTURE:
 231    case PIPE_CAP_DRAW_PARAMETERS:
 232    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 233    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 235    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 236    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 237    case PIPE_CAP_INVALIDATE_BUFFER:
 238    case PIPE_CAP_STRING_MARKER:
 239    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 240    case PIPE_CAP_CULL_DISTANCE:
 241    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 242    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 243    case PIPE_CAP_TGSI_VOTE:
 244    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 245    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 246    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 247    case PIPE_CAP_DOUBLES:
 248    case PIPE_CAP_INT64:
 249    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 250       return 1;
 251    case PIPE_CAP_COMPUTE:
 252       return (class_3d < GP100_3D_CLASS);
 253    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 254       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 255    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 256       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 257    case PIPE_CAP_TGSI_FS_FBFETCH:
 258       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 259
 260    /* unsupported caps */
 261    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 262    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 263    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 264    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 265    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 266    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 267    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 268    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 269    case PIPE_CAP_FAKE_SW_MSAA:
 270    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 271    case PIPE_CAP_VERTEXID_NOBASE:
 272    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 273    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 274    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 275    case PIPE_CAP_GENERATE_MIPMAP:
 276    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 277    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 278    case PIPE_CAP_QUERY_MEMORY_INFO:
 279    case PIPE_CAP_PCI_GROUP:
 280    case PIPE_CAP_PCI_BUS:
 281    case PIPE_CAP_PCI_DEVICE:
 282    case PIPE_CAP_PCI_FUNCTION:
 283    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 284    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 285    case PIPE_CAP_NATIVE_FENCE_FD:
 286    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 287    case PIPE_CAP_INT64_DIVMOD:
 288    case PIPE_CAP_TGSI_CLOCK:
 289    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 290       return 0;
 291
 292    case PIPE_CAP_VENDOR_ID:
 293       return 0x10de;
 294    case PIPE_CAP_DEVICE_ID: {
 295       uint64_t device_id;
 296       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 297          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 298          return -1;
 299       }
 300       return device_id;
 301    }
 302    case PIPE_CAP_ACCELERATED:
 303       return 1;
 304    case PIPE_CAP_VIDEO_MEMORY:
 305       return dev->vram_size >> 20;
 306    case PIPE_CAP_UMA:
 307       return 0;
 308    }
 309
 310    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 311    return 0;
 312 }
 313
 314 static int
 315 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 316                              enum pipe_shader_type shader,
 317                              enum pipe_shader_cap param)
 318 {
 319    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 320
 321    switch (shader) {
 322    case PIPE_SHADER_VERTEX:
 323    case PIPE_SHADER_GEOMETRY:
 324    case PIPE_SHADER_FRAGMENT:
 325    case PIPE_SHADER_COMPUTE:
 326    case PIPE_SHADER_TESS_CTRL:
 327    case PIPE_SHADER_TESS_EVAL:
 328       break;
 329    default:
 330       return 0;
 331    }
 332
 333    switch (param) {
 334    case PIPE_SHADER_CAP_PREFERRED_IR:
 335       return PIPE_SHADER_IR_TGSI;
 336    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 337       return 1 << PIPE_SHADER_IR_TGSI;
 338    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 339    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 340    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 341    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 342       return 16384;
 343    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 344       return 16;
 345    case PIPE_SHADER_CAP_MAX_INPUTS:
 346       if (shader == PIPE_SHADER_VERTEX)
 347          return 32;
 348       /* NOTE: These only count our slots for GENERIC varyings.
 349        * The address space may be larger, but the actual hard limit seems to be
 350        * less than what the address space layout permits, so don't add TEXCOORD,
 351        * COLOR, etc. here.
 352        */
 353       if (shader == PIPE_SHADER_FRAGMENT)
 354          return 0x1f0 / 16;
 355       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 356        * and excludes 0x60 per-patch inputs.
 357        */
 358       return 0x200 / 16;
 359    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 360       return 32;
 361    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 362       return 65536;
 363    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 364       return NVC0_MAX_PIPE_CONSTBUFS;
 365    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 366       return shader != PIPE_SHADER_FRAGMENT;
 367    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 368    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 369    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 370       return 1;
 371    case PIPE_SHADER_CAP_MAX_TEMPS:
 372       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 373    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 374       return 1;
 375    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 376       return 1;
 377    case PIPE_SHADER_CAP_SUBROUTINES:
 378       return 1;
 379    case PIPE_SHADER_CAP_INTEGERS:
 380       return 1;
 381    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 382       return 1;
 383    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 384       return 1;
 385    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 386    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 387    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 388       return 0;
 389    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 390       return NVC0_MAX_BUFFERS;
 391    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 392       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 393    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 394       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 395    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 396       return 32;
 397    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 398       if (class_3d >= NVE4_3D_CLASS)
 399          return NVC0_MAX_IMAGES;
 400       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 401          return NVC0_MAX_IMAGES;
 402       return 0;
 403    default:
 404       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 405       return 0;
 406    }
 407 }
 408
 409 static float
 410 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 411 {
 412    switch (param) {
 413    case PIPE_CAPF_MAX_LINE_WIDTH:
 414    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 415       return 10.0f;
 416    case PIPE_CAPF_MAX_POINT_WIDTH:
 417       return 63.0f;
 418    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 419       return 63.375f;
 420    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 421       return 16.0f;
 422    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 423       return 15.0f;
 424    case PIPE_CAPF_GUARD_BAND_LEFT:
 425    case PIPE_CAPF_GUARD_BAND_TOP:
 426       return 0.0f;
 427    case PIPE_CAPF_GUARD_BAND_RIGHT:
 428    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 429       return 0.0f; /* that or infinity */
 430    }
 431
 432    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 433    return 0.0f;
 434 }
 435
 436 static int
 437 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 438                               enum pipe_shader_ir ir_type,
 439                               enum pipe_compute_cap param, void *data)
 440 {
 441    struct nvc0_screen *screen = nvc0_screen(pscreen);
 442    const uint16_t obj_class = screen->compute->oclass;
 443
 444 #define RET(x) do {                  \
 445    if (data)                         \
 446       memcpy(data, x, sizeof(x));    \
 447    return sizeof(x);                 \
 448 } while (0)
 449
 450    switch (param) {
 451    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 452       RET((uint64_t []) { 3 });
 453    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 454       if (obj_class >= NVE4_COMPUTE_CLASS) {
 455          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 456       } else {
 457          RET(((uint64_t []) { 65535, 65535, 65535 }));
 458       }
 459    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 460       RET(((uint64_t []) { 1024, 1024, 64 }));
 461    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 462       RET((uint64_t []) { 1024 });
 463    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 464       if (obj_class >= NVE4_COMPUTE_CLASS) {
 465          RET((uint64_t []) { 1024 });
 466       } else {
 467          RET((uint64_t []) { 512 });
 468       }
 469    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 470       RET((uint64_t []) { 1ULL << 40 });
 471    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 472       switch (obj_class) {
 473       case GM200_COMPUTE_CLASS:
 474          RET((uint64_t []) { 96 << 10 });
 475          break;
 476       case GM107_COMPUTE_CLASS:
 477          RET((uint64_t []) { 64 << 10 });
 478          break;
 479       default:
 480          RET((uint64_t []) { 48 << 10 });
 481          break;
 482       }
 483    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 484       RET((uint64_t []) { 512 << 10 });
 485    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 486       RET((uint64_t []) { 4096 });
 487    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 488       RET((uint32_t []) { 32 });
 489    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 490       RET((uint64_t []) { 1ULL << 40 });
 491    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 492       RET((uint32_t []) { 0 });
 493    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 494       RET((uint32_t []) { screen->mp_count_compute });
 495    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 496       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 497    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 498       RET((uint32_t []) { 64 });
 499    default:
 500       return 0;
 501    }
 502
 503 #undef RET
 504 }
 505
 506 static void
 507 nvc0_screen_destroy(struct pipe_screen *pscreen)
 508 {
 509    struct nvc0_screen *screen = nvc0_screen(pscreen);
 510
 511    if (!nouveau_drm_screen_unref(&screen->base))
 512       return;
 513
 514    if (screen->base.fence.current) {
 515       struct nouveau_fence *current = NULL;
 516
 517       /* nouveau_fence_wait will create a new current fence, so wait on the
 518        * _current_ one, and remove both.
 519        */
 520       nouveau_fence_ref(screen->base.fence.current, &current);
 521       nouveau_fence_wait(current, NULL);
 522       nouveau_fence_ref(NULL, &current);
 523       nouveau_fence_ref(NULL, &screen->base.fence.current);
 524    }
 525    if (screen->base.pushbuf)
 526       screen->base.pushbuf->user_priv = NULL;
 527
 528    if (screen->blitter)
 529       nvc0_blitter_destroy(screen);
 530    if (screen->pm.prog) {
 531       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 532       nvc0_program_destroy(NULL, screen->pm.prog);
 533       FREE(screen->pm.prog);
 534    }
 535
 536    nouveau_bo_ref(NULL, &screen->text);
 537    nouveau_bo_ref(NULL, &screen->uniform_bo);
 538    nouveau_bo_ref(NULL, &screen->tls);
 539    nouveau_bo_ref(NULL, &screen->txc);
 540    nouveau_bo_ref(NULL, &screen->fence.bo);
 541    nouveau_bo_ref(NULL, &screen->poly_cache);
 542
 543    nouveau_heap_destroy(&screen->lib_code);
 544    nouveau_heap_destroy(&screen->text_heap);
 545
 546    FREE(screen->default_tsc);
 547    FREE(screen->tic.entries);
 548
 549    nouveau_object_del(&screen->eng3d);
 550    nouveau_object_del(&screen->eng2d);
 551    nouveau_object_del(&screen->m2mf);
 552    nouveau_object_del(&screen->compute);
 553    nouveau_object_del(&screen->nvsw);
 554
 555    nouveau_screen_fini(&screen->base);
 556
 557    FREE(screen);
 558 }
 559
 560 static int
 561 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 562                      unsigned size, const uint32_t *data)
 563 {
 564    struct nouveau_pushbuf *push = screen->base.pushbuf;
 565
 566    size /= 4;
 567
 568    assert((pos + size) <= 0x800);
 569
 570    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 571    PUSH_DATA (push, (m - 0x3800) / 8);
 572    PUSH_DATA (push, pos);
 573    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 574    PUSH_DATA (push, pos);
 575    PUSH_DATAp(push, data, size);
 576
 577    return pos + size;
 578 }
 579
 580 static void
 581 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 582 {
 583    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 584    PUSH_DATA (push, 0xff);
 585    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 586    PUSH_DATA (push, 0xff);
 587    PUSH_DATA (push, 0xff);
 588    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 589    PUSH_DATA (push, 0xff);
 590    PUSH_DATA (push, 0xff);
 591    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 592    PUSH_DATA (push, 0x3f);
 593
 594    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 595    PUSH_DATA (push, (3 << 16) | 3);
 596    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 597    PUSH_DATA (push, (2 << 16) | 2);
 598
 599    if (obj_class < GM107_3D_CLASS) {
 600       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 601       PUSH_DATA (push, 0);
 602    }
 603    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 604    PUSH_DATA (push, 0x10);
 605    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 606    PUSH_DATA (push, 0x10);
 607    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 608    PUSH_DATA (push, 0x10);
 609    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 610    PUSH_DATA (push, 0x10);
 611    PUSH_DATA (push, 0x10);
 612    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 613    PUSH_DATA (push, 0x10);
 614    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 615    PUSH_DATA (push, 0xe);
 616
 617    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 618    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 619    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 620    PUSH_DATA (push, 0);
 621    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 622    PUSH_DATA (push, 3);
 623
 624    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 625    PUSH_DATA (push, 0x3fffff);
 626    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 627    PUSH_DATA (push, 1);
 628    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 629    PUSH_DATA (push, 1);
 630
 631    if (obj_class < GM107_3D_CLASS) {
 632       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 633       PUSH_DATA (push, 3);
 634
 635       if (obj_class >= NVE4_3D_CLASS) {
 636          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 637          PUSH_DATA (push, 1);
 638       }
 639    }
 640
 641    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 642     * are supposed to do */
 643 }
 644
 645 static void
 646 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 647 {
 648    struct nvc0_screen *screen = nvc0_screen(pscreen);
 649    struct nouveau_pushbuf *push = screen->base.pushbuf;
 650
 651    /* we need to do it after possible flush in MARK_RING */
 652    *sequence = ++screen->base.fence.sequence;
 653
 654    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 655    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 656    PUSH_DATAh(push, screen->fence.bo->offset);
 657    PUSH_DATA (push, screen->fence.bo->offset);
 658    PUSH_DATA (push, *sequence);
 659    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 660               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 661 }
 662
 663 static u32
 664 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 665 {
 666    struct nvc0_screen *screen = nvc0_screen(pscreen);
 667    return screen->fence.map[0];
 668 }
 669
 670 static int
 671 nvc0_screen_init_compute(struct nvc0_screen *screen)
 672 {
 673    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 674
 675    switch (screen->base.device->chipset & ~0xf) {
 676    case 0xc0:
 677    case 0xd0:
 678       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 679    case 0xe0:
 680    case 0xf0:
 681    case 0x100:
 682    case 0x110:
 683    case 0x120:
 684       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 685    case 0x130:
 686       return 0;
 687    default:
 688       return -1;
 689    }
 690 }
 691
 692 static int
 693 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 694                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 695 {
 696    struct nouveau_bo *bo = NULL;
 697    int ret;
 698    uint64_t size = (lpos + lneg) * 32 + cstack;
 699
 700    if (size >= (1 << 20)) {
 701       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 702       return -1;
 703    }
 704
 705    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 706    size  = align(size, 0x8000);
 707    size *= screen->mp_count;
 708
 709    size = align(size, 1 << 17);
 710
 711    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 712                         NULL, &bo);
 713    if (ret)
 714       return ret;
 715    nouveau_bo_ref(NULL, &screen->tls);
 716    screen->tls = bo;
 717    return 0;
 718 }
 719
 720 int
 721 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 722 {
 723    struct nouveau_pushbuf *push = screen->base.pushbuf;
 724    struct nouveau_bo *bo;
 725    int ret;
 726
 727    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 728                         1 << 17, size, NULL, &bo);
 729    if (ret)
 730       return ret;
 731
 732    nouveau_bo_ref(NULL, &screen->text);
 733    screen->text = bo;
 734
 735    nouveau_heap_destroy(&screen->lib_code);
 736    nouveau_heap_destroy(&screen->text_heap);
 737
 738    /* XXX: getting a page fault at the end of the code buffer every few
 739     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 740     */
 741    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 742
 743    /* update the code segment setup */
 744    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 745    PUSH_DATAh(push, screen->text->offset);
 746    PUSH_DATA (push, screen->text->offset);
 747    if (screen->compute) {
 748       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 749       PUSH_DATAh(push, screen->text->offset);
 750       PUSH_DATA (push, screen->text->offset);
 751    }
 752
 753    return 0;
 754 }
 755
 756 #define FAIL_SCREEN_INIT(str, err)                    \
 757    do {                                               \
 758       NOUVEAU_ERR(str, err);                          \
 759       goto fail;                                      \
 760    } while(0)
 761
 762 struct nouveau_screen *
 763 nvc0_screen_create(struct nouveau_device *dev)
 764 {
 765    struct nvc0_screen *screen;
 766    struct pipe_screen *pscreen;
 767    struct nouveau_object *chan;
 768    struct nouveau_pushbuf *push;
 769    uint64_t value;
 770    uint32_t obj_class;
 771    uint32_t flags;
 772    int ret;
 773    unsigned i;
 774
 775    switch (dev->chipset & ~0xf) {
 776    case 0xc0:
 777    case 0xd0:
 778    case 0xe0:
 779    case 0xf0:
 780    case 0x100:
 781    case 0x110:
 782    case 0x120:
 783    case 0x130:
 784       break;
 785    default:
 786       return NULL;
 787    }
 788
 789    screen = CALLOC_STRUCT(nvc0_screen);
 790    if (!screen)
 791       return NULL;
 792    pscreen = &screen->base.base;
 793    pscreen->destroy = nvc0_screen_destroy;
 794
 795    ret = nouveau_screen_init(&screen->base, dev);
 796    if (ret)
 797       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 798    chan = screen->base.channel;
 799    push = screen->base.pushbuf;
 800    push->user_priv = screen;
 801    push->rsvd_kick = 5;
 802
 803    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 804       PIPE_BIND_SHADER_BUFFER |
 805       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 806       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 807    screen->base.sysmem_bindings |=
 808       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 809
 810    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 811       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 812       screen->base.vidmem_bindings = 0;
 813    }
 814
 815    pscreen->context_create = nvc0_create;
 816    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 817    pscreen->get_param = nvc0_screen_get_param;
 818    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 819    pscreen->get_paramf = nvc0_screen_get_paramf;
 820    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 821    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 822
 823    nvc0_screen_init_resource_functions(pscreen);
 824
 825    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 826    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 827
 828    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 829    if (screen->base.drm->version >= 0x01000202)
 830       flags |= NOUVEAU_BO_COHERENT;
 831
 832    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 833    if (ret)
 834       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 835    nouveau_bo_map(screen->fence.bo, 0, NULL);
 836    screen->fence.map = screen->fence.bo->map;
 837    screen->base.fence.emit = nvc0_screen_fence_emit;
 838    screen->base.fence.update = nvc0_screen_fence_update;
 839
 840
 841    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 842                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 843    if (ret)
 844       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 845
 846    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 847    PUSH_DATA (push, screen->nvsw->handle);
 848
 849    switch (dev->chipset & ~0xf) {
 850    case 0x130:
 851    case 0x120:
 852    case 0x110:
 853    case 0x100:
 854    case 0xf0:
 855       obj_class = NVF0_P2MF_CLASS;
 856       break;
 857    case 0xe0:
 858       obj_class = NVE4_P2MF_CLASS;
 859       break;
 860    default:
 861       obj_class = NVC0_M2MF_CLASS;
 862       break;
 863    }
 864    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 865                             &screen->m2mf);
 866    if (ret)
 867       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 868
 869    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 870    PUSH_DATA (push, screen->m2mf->oclass);
 871    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 872       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 873       PUSH_DATA (push, 0xa0b5);
 874    }
 875
 876    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 877                             &screen->eng2d);
 878    if (ret)
 879       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 880
 881    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 882    PUSH_DATA (push, screen->eng2d->oclass);
 883    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 884    PUSH_DATA (push, 0);
 885    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 886    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 887    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 888    PUSH_DATA (push, 0);
 889    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 890    PUSH_DATA (push, 0);
 891    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 892    PUSH_DATA (push, 0x3f);
 893    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 894    PUSH_DATA (push, 1);
 895    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 896    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 897
 898    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 899    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 900    PUSH_DATA (push, screen->fence.bo->offset + 16);
 901
 902    switch (dev->chipset & ~0xf) {
 903    case 0x130:
 904       switch (dev->chipset) {
 905       case 0x130:
 906          obj_class = GP100_3D_CLASS;
 907          break;
 908       default:
 909          obj_class = GP102_3D_CLASS;
 910          break;
 911       }
 912       break;
 913    case 0x120:
 914       obj_class = GM200_3D_CLASS;
 915       break;
 916    case 0x110:
 917       obj_class = GM107_3D_CLASS;
 918       break;
 919    case 0x100:
 920    case 0xf0:
 921       obj_class = NVF0_3D_CLASS;
 922       break;
 923    case 0xe0:
 924       switch (dev->chipset) {
 925       case 0xea:
 926          obj_class = NVEA_3D_CLASS;
 927          break;
 928       default:
 929          obj_class = NVE4_3D_CLASS;
 930          break;
 931       }
 932       break;
 933    case 0xd0:
 934       obj_class = NVC8_3D_CLASS;
 935       break;
 936    case 0xc0:
 937    default:
 938       switch (dev->chipset) {
 939       case 0xc8:
 940          obj_class = NVC8_3D_CLASS;
 941          break;
 942       case 0xc1:
 943          obj_class = NVC1_3D_CLASS;
 944          break;
 945       default:
 946          obj_class = NVC0_3D_CLASS;
 947          break;
 948       }
 949       break;
 950    }
 951    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 952                             &screen->eng3d);
 953    if (ret)
 954       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 955    screen->base.class_3d = obj_class;
 956
 957    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 958    PUSH_DATA (push, screen->eng3d->oclass);
 959
 960    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 961    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 962
 963    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 964       /* kill shaders after about 1 second (at 100 MHz) */
 965       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 966       PUSH_DATA (push, 0x17);
 967    }
 968
 969    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 970                     screen->base.drm->version >= 0x01000101);
 971    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 972    for (i = 0; i < 8; ++i)
 973       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 974
 975    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 976    PUSH_DATA (push, 1);
 977
 978    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 979    PUSH_DATA (push, 0);
 980    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 981    PUSH_DATA (push, 0);
 982    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 983    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 984    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 985    PUSH_DATA (push, 0);
 986    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 987    PUSH_DATA (push, 1);
 988    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 989    PUSH_DATA (push, 1);
 990    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 991    PUSH_DATA (push, 1);
 992    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 993    PUSH_DATA (push, 0);
 994    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 995    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 996    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 997       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 998    } else {
 999       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1000       PUSH_DATA (push, 15);
1001    }
1002    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1003    PUSH_DATA (push, 8); /* 128 */
1004    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1005    PUSH_DATA (push, 1);
1006    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1007       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1008       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1009    }
1010
1011    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1012
1013    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1014    if (ret)
1015       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1016
1017    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1018                         &screen->uniform_bo);
1019    if (ret)
1020       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1021
1022    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1023
1024    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1025    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1026    PUSH_DATA (push, 256);
1027    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1028    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1029    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1030    PUSH_DATA (push, 0);
1031    PUSH_DATAf(push, 0.0f);
1032    PUSH_DATAf(push, 0.0f);
1033    PUSH_DATAf(push, 0.0f);
1034    PUSH_DATAf(push, 0.0f);
1035    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1036    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1037    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1038
1039    if (screen->base.drm->version >= 0x01000101) {
1040       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1041       if (ret)
1042          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1043    } else {
1044       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1045          value = (8 << 8) | 4;
1046       else
1047          value = (16 << 8) | 4;
1048    }
1049    screen->gpc_count = value & 0x000000ff;
1050    screen->mp_count = value >> 8;
1051    screen->mp_count_compute = screen->mp_count;
1052
1053    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1054    if (ret)
1055       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1056
1057    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1058    PUSH_DATAh(push, screen->tls->offset);
1059    PUSH_DATA (push, screen->tls->offset);
1060    PUSH_DATA (push, screen->tls->size >> 32);
1061    PUSH_DATA (push, screen->tls->size);
1062    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1063    PUSH_DATA (push, 0);
1064    /* Reduce likelihood of collision with real buffers by placing the hole at
1065     * the top of the 4G area. This will have to be dealt with for real
1066     * eventually by blocking off that area from the VM.
1067     */
1068    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1069    PUSH_DATA (push, 0xff << 24);
1070
1071    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1072       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1073                            &screen->poly_cache);
1074       if (ret)
1075          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1076
1077       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1078       PUSH_DATAh(push, screen->poly_cache->offset);
1079       PUSH_DATA (push, screen->poly_cache->offset);
1080       PUSH_DATA (push, 3);
1081    }
1082
1083    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1084                         &screen->txc);
1085    if (ret)
1086       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1087
1088    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1089    PUSH_DATAh(push, screen->txc->offset);
1090    PUSH_DATA (push, screen->txc->offset);
1091    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1092    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1093       screen->tic.maxwell = true;
1094       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1095          screen->tic.maxwell =
1096             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1097          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1098       }
1099    }
1100
1101    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1102    PUSH_DATAh(push, screen->txc->offset + 65536);
1103    PUSH_DATA (push, screen->txc->offset + 65536);
1104    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1105
1106    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1107    PUSH_DATA (push, 0);
1108    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1109    PUSH_DATA (push, 0);
1110    PUSH_DATA (push, 0);
1111    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1112    PUSH_DATA (push, 0x3f);
1113
1114    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1115    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1116    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1117    for (i = 0; i < 8 * 2; ++i)
1118       PUSH_DATA(push, 0);
1119    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1120    PUSH_DATA (push, 0);
1121    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1122    PUSH_DATA (push, 0);
1123
1124    /* neither scissors, viewport nor stencil mask should affect clears */
1125    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1126    PUSH_DATA (push, 0);
1127
1128    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1129    PUSH_DATA (push, 1);
1130    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1131       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1132       PUSH_DATAf(push, 0.0f);
1133       PUSH_DATAf(push, 1.0f);
1134    }
1135    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1136    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1137
1138    /* We use scissors instead of exact view volume clipping,
1139     * so they're always enabled.
1140     */
1141    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1142       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1143       PUSH_DATA (push, 1);
1144       PUSH_DATA (push, 8192 << 16);
1145       PUSH_DATA (push, 8192 << 16);
1146    }
1147
1148 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1149
1150    i = 0;
1151    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1152    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1153    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1154    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1155    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1156    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1157    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1158    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1159    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1160    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1161    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1162    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1163    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1164
1165    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1166    PUSH_DATA (push, 1);
1167    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1168    PUSH_DATA (push, 1);
1169    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1170    PUSH_DATA (push, 0x40);
1171    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1172    PUSH_DATA (push, 0);
1173    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1174    PUSH_DATA (push, 0x30);
1175    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1176    PUSH_DATA (push, 3);
1177    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1178    PUSH_DATA (push, 0x20);
1179    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1180    PUSH_DATA (push, 0x00);
1181    screen->save_state.patch_vertices = 3;
1182
1183    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1184    PUSH_DATA (push, 0);
1185    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1186    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1187
1188    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1189
1190    if (nvc0_screen_init_compute(screen))
1191       goto fail;
1192
1193    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1194    for (i = 0; i < 5; ++i) {
1195       /* TIC and TSC entries for each unit (nve4+ only) */
1196       /* auxiliary constants (6 user clip planes, base instance id) */
1197       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1198       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1199       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1200       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1201       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1202       PUSH_DATA (push, (15 << 4) | 1);
1203       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1204          unsigned j;
1205          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1206          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1207          for (j = 0; j < 8; ++j)
1208             PUSH_DATA(push, j);
1209       } else {
1210          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1211          PUSH_DATA (push, 0x54);
1212       }
1213
1214       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1215       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1216       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1217       PUSH_DATA (push, 0); /* 0 */
1218       PUSH_DATA (push, 0);
1219       PUSH_DATA (push, 1); /* 1 */
1220       PUSH_DATA (push, 0);
1221       PUSH_DATA (push, 0); /* 2 */
1222       PUSH_DATA (push, 1);
1223       PUSH_DATA (push, 1); /* 3 */
1224       PUSH_DATA (push, 1);
1225       PUSH_DATA (push, 2); /* 4 */
1226       PUSH_DATA (push, 0);
1227       PUSH_DATA (push, 3); /* 5 */
1228       PUSH_DATA (push, 0);
1229       PUSH_DATA (push, 2); /* 6 */
1230       PUSH_DATA (push, 1);
1231       PUSH_DATA (push, 3); /* 7 */
1232       PUSH_DATA (push, 1);
1233    }
1234    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1235    PUSH_DATA (push, 0);
1236
1237    PUSH_KICK (push);
1238
1239    screen->tic.entries = CALLOC(4096, sizeof(void *));
1240    screen->tsc.entries = screen->tic.entries + 2048;
1241
1242    if (!nvc0_blitter_create(screen))
1243       goto fail;
1244
1245    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1246    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1247
1248    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1249
1250    return &screen->base;
1251
1252 fail:
1253    screen->base.base.context_create = NULL;
1254    return &screen->base;
1255 }
1256
1257 int
1258 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1259 {
1260    int i = screen->tic.next;
1261
1262    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1263       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1264
1265    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1266
1267    if (screen->tic.entries[i])
1268       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1269
1270    screen->tic.entries[i] = entry;
1271    return i;
1272 }
1273
1274 int
1275 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1276 {
1277    int i = screen->tsc.next;
1278
1279    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1280       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1281
1282    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1283
1284    if (screen->tsc.entries[i])
1285       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1286
1287    screen->tsc.entries[i] = entry;
1288    return i;
1289 }