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gallium: remove pipe_index_buffer and set_index_buffer
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "tgsi/tgsi_parse.h"
30
31 #include "nvc0/nvc0_stateobj.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
34
35 #include "nvc0/nvc0_3d.xml.h"
36
37 #include "nouveau_gldefs.h"
38
39 static inline uint32_t
40 nvc0_colormask(unsigned mask)
41 {
42 uint32_t ret = 0;
43
44 if (mask & PIPE_MASK_R)
45 ret |= 0x0001;
46 if (mask & PIPE_MASK_G)
47 ret |= 0x0010;
48 if (mask & PIPE_MASK_B)
49 ret |= 0x0100;
50 if (mask & PIPE_MASK_A)
51 ret |= 0x1000;
52
53 return ret;
54 }
55
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
58
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor)
61 {
62 switch (factor) {
63 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
82 default:
83 return NV50_BLEND_FACTOR_ZERO;
84 }
85 }
86
87 static void *
88 nvc0_blend_state_create(struct pipe_context *pipe,
89 const struct pipe_blend_state *cso)
90 {
91 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
92 int i;
93 int r; /* reference */
94 uint32_t ms;
95 uint8_t blend_en = 0;
96 bool indep_masks = false;
97 bool indep_funcs = false;
98
99 so->pipe = *cso;
100
101 /* check which states actually have differing values */
102 if (cso->independent_blend_enable) {
103 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
104 blend_en |= 1 << r;
105 for (i = r + 1; i < 8; ++i) {
106 if (!cso->rt[i].blend_enable)
107 continue;
108 blend_en |= 1 << i;
109 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
110 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
111 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
112 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
113 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
114 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
115 indep_funcs = true;
116 break;
117 }
118 }
119 for (; i < 8; ++i)
120 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
121
122 for (i = 1; i < 8; ++i) {
123 if (cso->rt[i].colormask != cso->rt[0].colormask) {
124 indep_masks = true;
125 break;
126 }
127 }
128 } else {
129 r = 0;
130 if (cso->rt[0].blend_enable)
131 blend_en = 0xff;
132 }
133
134 if (cso->logicop_enable) {
135 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
136 SB_DATA (so, 1);
137 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
138
139 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
140 } else {
141 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
142
143 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
144 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
145 if (indep_funcs) {
146 for (i = 0; i < 8; ++i) {
147 if (cso->rt[i].blend_enable) {
148 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
149 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
151 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
152 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
154 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
155 }
156 }
157 } else
158 if (blend_en) {
159 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
160 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
162 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
163 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
164 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
165 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
166 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
167 }
168
169 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
170 if (indep_masks) {
171 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
172 for (i = 0; i < 8; ++i)
173 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
174 } else {
175 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
176 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
177 }
178 }
179
180 ms = 0;
181 if (cso->alpha_to_coverage)
182 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
183 if (cso->alpha_to_one)
184 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
185
186 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
187 SB_DATA (so, ms);
188
189 assert(so->size <= ARRAY_SIZE(so->state));
190 return so;
191 }
192
193 static void
194 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
195 {
196 struct nvc0_context *nvc0 = nvc0_context(pipe);
197
198 nvc0->blend = hwcso;
199 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
200 }
201
202 static void
203 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
204 {
205 FREE(hwcso);
206 }
207
208 /* NOTE: ignoring line_last_pixel */
209 static void *
210 nvc0_rasterizer_state_create(struct pipe_context *pipe,
211 const struct pipe_rasterizer_state *cso)
212 {
213 struct nvc0_rasterizer_stateobj *so;
214 uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
215 uint32_t reg;
216
217 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
218 if (!so)
219 return NULL;
220 so->pipe = *cso;
221
222 /* Scissor enables are handled in scissor state, we will not want to
223 * always emit 16 commands, one for each scissor rectangle, here.
224 */
225
226 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
227 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
228
229 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
230 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
231 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
232
233 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
234
235 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
236 if (cso->line_smooth || cso->multisample)
237 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
238 else
239 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
240 SB_DATA (so, fui(cso->line_width));
241
242 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
243 if (cso->line_stipple_enable) {
244 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
245 SB_DATA (so, (cso->line_stipple_pattern << 8) |
246 cso->line_stipple_factor);
247
248 }
249
250 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
251 if (!cso->point_size_per_vertex) {
252 SB_BEGIN_3D(so, POINT_SIZE, 1);
253 SB_DATA (so, fui(cso->point_size));
254 }
255
256 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
257 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
258 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
259
260 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
261 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
262 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
263 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
264
265 if (class_3d >= GM200_3D_CLASS) {
266 SB_IMMED_3D(so, FILL_RECTANGLE,
267 cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
268 NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
269 }
270
271 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
272 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
273 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
274 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
275 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
276
277 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
278 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
279 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
280 NVC0_3D_FRONT_FACE_CW);
281 switch (cso->cull_face) {
282 case PIPE_FACE_FRONT_AND_BACK:
283 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
284 break;
285 case PIPE_FACE_FRONT:
286 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
287 break;
288 case PIPE_FACE_BACK:
289 default:
290 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
291 break;
292 }
293
294 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
295 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
296 SB_DATA (so, cso->offset_point);
297 SB_DATA (so, cso->offset_line);
298 SB_DATA (so, cso->offset_tri);
299
300 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
301 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
302 SB_DATA (so, fui(cso->offset_scale));
303 if (!cso->offset_units_unscaled) {
304 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
305 SB_DATA (so, fui(cso->offset_units * 2.0f));
306 }
307 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
308 SB_DATA (so, fui(cso->offset_clamp));
309 }
310
311 if (cso->depth_clip)
312 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
313 else
314 reg =
315 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
316 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
317 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
318 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
319
320 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
321 SB_DATA (so, reg);
322
323 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
324
325 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
326
327 assert(so->size <= ARRAY_SIZE(so->state));
328 return (void *)so;
329 }
330
331 static void
332 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
333 {
334 struct nvc0_context *nvc0 = nvc0_context(pipe);
335
336 nvc0->rast = hwcso;
337 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
338 }
339
340 static void
341 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
342 {
343 FREE(hwcso);
344 }
345
346 static void *
347 nvc0_zsa_state_create(struct pipe_context *pipe,
348 const struct pipe_depth_stencil_alpha_state *cso)
349 {
350 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
351
352 so->pipe = *cso;
353
354 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
355 if (cso->depth.enabled) {
356 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
357 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
358 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
359 }
360
361 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
362 if (cso->depth.bounds_test) {
363 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
364 SB_DATA (so, fui(cso->depth.bounds_min));
365 SB_DATA (so, fui(cso->depth.bounds_max));
366 }
367
368 if (cso->stencil[0].enabled) {
369 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
370 SB_DATA (so, 1);
371 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
372 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
373 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
374 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
375 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
376 SB_DATA (so, cso->stencil[0].valuemask);
377 SB_DATA (so, cso->stencil[0].writemask);
378 } else {
379 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
380 }
381
382 if (cso->stencil[1].enabled) {
383 assert(cso->stencil[0].enabled);
384 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
385 SB_DATA (so, 1);
386 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
387 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
388 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
389 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
390 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
391 SB_DATA (so, cso->stencil[1].writemask);
392 SB_DATA (so, cso->stencil[1].valuemask);
393 } else
394 if (cso->stencil[0].enabled) {
395 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
396 }
397
398 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
399 if (cso->alpha.enabled) {
400 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
401 SB_DATA (so, fui(cso->alpha.ref_value));
402 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
403 }
404
405 assert(so->size <= ARRAY_SIZE(so->state));
406 return (void *)so;
407 }
408
409 static void
410 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
411 {
412 struct nvc0_context *nvc0 = nvc0_context(pipe);
413
414 nvc0->zsa = hwcso;
415 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
416 }
417
418 static void
419 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
420 {
421 FREE(hwcso);
422 }
423
424 /* ====================== SAMPLERS AND TEXTURES ================================
425 */
426
427 #define NV50_TSC_WRAP_CASE(n) \
428 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
429
430 static void
431 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
432 {
433 unsigned s, i;
434
435 for (s = 0; s < 6; ++s)
436 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
437 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
438 nvc0_context(pipe)->samplers[s][i] = NULL;
439
440 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
441
442 FREE(hwcso);
443 }
444
445 static inline void
446 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
447 unsigned s,
448 unsigned nr, void **hwcso)
449 {
450 unsigned i;
451
452 for (i = 0; i < nr; ++i) {
453 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
454
455 if (hwcso[i] == old)
456 continue;
457 nvc0->samplers_dirty[s] |= 1 << i;
458
459 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
460 if (old)
461 nvc0_screen_tsc_unlock(nvc0->screen, old);
462 }
463 for (; i < nvc0->num_samplers[s]; ++i) {
464 if (nvc0->samplers[s][i]) {
465 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
466 nvc0->samplers[s][i] = NULL;
467 }
468 }
469
470 nvc0->num_samplers[s] = nr;
471 }
472
473 static void
474 nvc0_bind_sampler_states(struct pipe_context *pipe,
475 enum pipe_shader_type shader,
476 unsigned start, unsigned nr, void **samplers)
477 {
478 const unsigned s = nvc0_shader_stage(shader);
479
480 assert(start == 0);
481 nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
482
483 if (s == 5)
484 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
485 else
486 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
487 }
488
489
490 /* NOTE: only called when not referenced anywhere, won't be bound */
491 static void
492 nvc0_sampler_view_destroy(struct pipe_context *pipe,
493 struct pipe_sampler_view *view)
494 {
495 pipe_resource_reference(&view->texture, NULL);
496
497 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
498
499 FREE(nv50_tic_entry(view));
500 }
501
502 static inline void
503 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
504 unsigned nr,
505 struct pipe_sampler_view **views)
506 {
507 unsigned i;
508
509 for (i = 0; i < nr; ++i) {
510 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
511
512 if (views[i] == nvc0->textures[s][i])
513 continue;
514 nvc0->textures_dirty[s] |= 1 << i;
515
516 if (views[i] && views[i]->texture) {
517 struct pipe_resource *res = views[i]->texture;
518 if (res->target == PIPE_BUFFER &&
519 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
520 nvc0->textures_coherent[s] |= 1 << i;
521 else
522 nvc0->textures_coherent[s] &= ~(1 << i);
523 } else {
524 nvc0->textures_coherent[s] &= ~(1 << i);
525 }
526
527 if (old) {
528 if (s == 5)
529 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
530 else
531 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
532 nvc0_screen_tic_unlock(nvc0->screen, old);
533 }
534
535 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
536 }
537
538 for (i = nr; i < nvc0->num_textures[s]; ++i) {
539 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
540 if (old) {
541 if (s == 5)
542 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
543 else
544 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
545 nvc0_screen_tic_unlock(nvc0->screen, old);
546 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
547 }
548 }
549
550 nvc0->num_textures[s] = nr;
551 }
552
553 static void
554 nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
555 unsigned start, unsigned nr,
556 struct pipe_sampler_view **views)
557 {
558 const unsigned s = nvc0_shader_stage(shader);
559
560 assert(start == 0);
561 nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, views);
562
563 if (s == 5)
564 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
565 else
566 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
567 }
568
569 /* ============================= SHADERS =======================================
570 */
571
572 static void *
573 nvc0_sp_state_create(struct pipe_context *pipe,
574 const struct pipe_shader_state *cso, unsigned type)
575 {
576 struct nvc0_program *prog;
577
578 prog = CALLOC_STRUCT(nvc0_program);
579 if (!prog)
580 return NULL;
581
582 prog->type = type;
583
584 if (cso->tokens)
585 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
586
587 if (cso->stream_output.num_outputs)
588 prog->pipe.stream_output = cso->stream_output;
589
590 prog->translated = nvc0_program_translate(
591 prog, nvc0_context(pipe)->screen->base.device->chipset,
592 &nouveau_context(pipe)->debug);
593
594 return (void *)prog;
595 }
596
597 static void
598 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
599 {
600 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
601
602 nvc0_program_destroy(nvc0_context(pipe), prog);
603
604 FREE((void *)prog->pipe.tokens);
605 FREE(prog);
606 }
607
608 static void *
609 nvc0_vp_state_create(struct pipe_context *pipe,
610 const struct pipe_shader_state *cso)
611 {
612 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
613 }
614
615 static void
616 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
617 {
618 struct nvc0_context *nvc0 = nvc0_context(pipe);
619
620 nvc0->vertprog = hwcso;
621 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
622 }
623
624 static void *
625 nvc0_fp_state_create(struct pipe_context *pipe,
626 const struct pipe_shader_state *cso)
627 {
628 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
629 }
630
631 static void
632 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
633 {
634 struct nvc0_context *nvc0 = nvc0_context(pipe);
635
636 nvc0->fragprog = hwcso;
637 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
638 }
639
640 static void *
641 nvc0_gp_state_create(struct pipe_context *pipe,
642 const struct pipe_shader_state *cso)
643 {
644 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
645 }
646
647 static void
648 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
649 {
650 struct nvc0_context *nvc0 = nvc0_context(pipe);
651
652 nvc0->gmtyprog = hwcso;
653 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
654 }
655
656 static void *
657 nvc0_tcp_state_create(struct pipe_context *pipe,
658 const struct pipe_shader_state *cso)
659 {
660 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
661 }
662
663 static void
664 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
665 {
666 struct nvc0_context *nvc0 = nvc0_context(pipe);
667
668 nvc0->tctlprog = hwcso;
669 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
670 }
671
672 static void *
673 nvc0_tep_state_create(struct pipe_context *pipe,
674 const struct pipe_shader_state *cso)
675 {
676 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
677 }
678
679 static void
680 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
681 {
682 struct nvc0_context *nvc0 = nvc0_context(pipe);
683
684 nvc0->tevlprog = hwcso;
685 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
686 }
687
688 static void *
689 nvc0_cp_state_create(struct pipe_context *pipe,
690 const struct pipe_compute_state *cso)
691 {
692 struct nvc0_program *prog;
693
694 prog = CALLOC_STRUCT(nvc0_program);
695 if (!prog)
696 return NULL;
697 prog->type = PIPE_SHADER_COMPUTE;
698
699 prog->cp.smem_size = cso->req_local_mem;
700 prog->cp.lmem_size = cso->req_private_mem;
701 prog->parm_size = cso->req_input_mem;
702
703 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
704
705 prog->translated = nvc0_program_translate(
706 prog, nvc0_context(pipe)->screen->base.device->chipset,
707 &nouveau_context(pipe)->debug);
708
709 return (void *)prog;
710 }
711
712 static void
713 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
714 {
715 struct nvc0_context *nvc0 = nvc0_context(pipe);
716
717 nvc0->compprog = hwcso;
718 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
719 }
720
721 static void
722 nvc0_set_constant_buffer(struct pipe_context *pipe,
723 enum pipe_shader_type shader, uint index,
724 const struct pipe_constant_buffer *cb)
725 {
726 struct nvc0_context *nvc0 = nvc0_context(pipe);
727 struct pipe_resource *res = cb ? cb->buffer : NULL;
728 const unsigned s = nvc0_shader_stage(shader);
729 const unsigned i = index;
730
731 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
732 if (nvc0->constbuf[s][i].user)
733 nvc0->constbuf[s][i].u.buf = NULL;
734 else
735 if (nvc0->constbuf[s][i].u.buf)
736 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
737
738 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
739 } else {
740 if (nvc0->constbuf[s][i].user)
741 nvc0->constbuf[s][i].u.buf = NULL;
742 else
743 if (nvc0->constbuf[s][i].u.buf)
744 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
745
746 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
747 }
748 nvc0->constbuf_dirty[s] |= 1 << i;
749
750 if (nvc0->constbuf[s][i].u.buf)
751 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
752 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
753
754 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
755 if (nvc0->constbuf[s][i].user) {
756 nvc0->constbuf[s][i].u.data = cb->user_buffer;
757 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
758 nvc0->constbuf_valid[s] |= 1 << i;
759 nvc0->constbuf_coherent[s] &= ~(1 << i);
760 } else
761 if (cb) {
762 nvc0->constbuf[s][i].offset = cb->buffer_offset;
763 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
764 nvc0->constbuf_valid[s] |= 1 << i;
765 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
766 nvc0->constbuf_coherent[s] |= 1 << i;
767 else
768 nvc0->constbuf_coherent[s] &= ~(1 << i);
769 }
770 else {
771 nvc0->constbuf_valid[s] &= ~(1 << i);
772 nvc0->constbuf_coherent[s] &= ~(1 << i);
773 }
774 }
775
776 /* =============================================================================
777 */
778
779 static void
780 nvc0_set_blend_color(struct pipe_context *pipe,
781 const struct pipe_blend_color *bcol)
782 {
783 struct nvc0_context *nvc0 = nvc0_context(pipe);
784
785 nvc0->blend_colour = *bcol;
786 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
787 }
788
789 static void
790 nvc0_set_stencil_ref(struct pipe_context *pipe,
791 const struct pipe_stencil_ref *sr)
792 {
793 struct nvc0_context *nvc0 = nvc0_context(pipe);
794
795 nvc0->stencil_ref = *sr;
796 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
797 }
798
799 static void
800 nvc0_set_clip_state(struct pipe_context *pipe,
801 const struct pipe_clip_state *clip)
802 {
803 struct nvc0_context *nvc0 = nvc0_context(pipe);
804
805 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
806
807 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
808 }
809
810 static void
811 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
812 {
813 struct nvc0_context *nvc0 = nvc0_context(pipe);
814
815 nvc0->sample_mask = sample_mask;
816 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
817 }
818
819 static void
820 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
821 {
822 struct nvc0_context *nvc0 = nvc0_context(pipe);
823
824 if (nvc0->min_samples != min_samples) {
825 nvc0->min_samples = min_samples;
826 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
827 }
828 }
829
830 static void
831 nvc0_set_framebuffer_state(struct pipe_context *pipe,
832 const struct pipe_framebuffer_state *fb)
833 {
834 struct nvc0_context *nvc0 = nvc0_context(pipe);
835
836 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
837
838 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
839
840 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
841 }
842
843 static void
844 nvc0_set_polygon_stipple(struct pipe_context *pipe,
845 const struct pipe_poly_stipple *stipple)
846 {
847 struct nvc0_context *nvc0 = nvc0_context(pipe);
848
849 nvc0->stipple = *stipple;
850 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
851 }
852
853 static void
854 nvc0_set_scissor_states(struct pipe_context *pipe,
855 unsigned start_slot,
856 unsigned num_scissors,
857 const struct pipe_scissor_state *scissor)
858 {
859 struct nvc0_context *nvc0 = nvc0_context(pipe);
860 int i;
861
862 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
863 for (i = 0; i < num_scissors; i++) {
864 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
865 continue;
866 nvc0->scissors[start_slot + i] = scissor[i];
867 nvc0->scissors_dirty |= 1 << (start_slot + i);
868 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
869 }
870 }
871
872 static void
873 nvc0_set_viewport_states(struct pipe_context *pipe,
874 unsigned start_slot,
875 unsigned num_viewports,
876 const struct pipe_viewport_state *vpt)
877 {
878 struct nvc0_context *nvc0 = nvc0_context(pipe);
879 int i;
880
881 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
882 for (i = 0; i < num_viewports; i++) {
883 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
884 continue;
885 nvc0->viewports[start_slot + i] = vpt[i];
886 nvc0->viewports_dirty |= 1 << (start_slot + i);
887 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
888 }
889
890 }
891
892 static void
893 nvc0_set_window_rectangles(struct pipe_context *pipe,
894 boolean include,
895 unsigned num_rectangles,
896 const struct pipe_scissor_state *rectangles)
897 {
898 struct nvc0_context *nvc0 = nvc0_context(pipe);
899
900 nvc0->window_rect.inclusive = include;
901 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
902 memcpy(nvc0->window_rect.rect, rectangles,
903 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
904
905 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
906 }
907
908 static void
909 nvc0_set_tess_state(struct pipe_context *pipe,
910 const float default_tess_outer[4],
911 const float default_tess_inner[2])
912 {
913 struct nvc0_context *nvc0 = nvc0_context(pipe);
914
915 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
916 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
917 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
918 }
919
920 static void
921 nvc0_set_vertex_buffers(struct pipe_context *pipe,
922 unsigned start_slot, unsigned count,
923 const struct pipe_vertex_buffer *vb)
924 {
925 struct nvc0_context *nvc0 = nvc0_context(pipe);
926 unsigned i;
927
928 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
929 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
930
931 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
932 start_slot, count);
933
934 if (!vb) {
935 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
936 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
937 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
938 return;
939 }
940
941 for (i = 0; i < count; ++i) {
942 unsigned dst_index = start_slot + i;
943
944 if (vb[i].is_user_buffer) {
945 nvc0->vbo_user |= 1 << dst_index;
946 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
947 nvc0->constant_vbos |= 1 << dst_index;
948 else
949 nvc0->constant_vbos &= ~(1 << dst_index);
950 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
951 } else {
952 nvc0->vbo_user &= ~(1 << dst_index);
953 nvc0->constant_vbos &= ~(1 << dst_index);
954
955 if (vb[i].buffer.resource &&
956 vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
957 nvc0->vtxbufs_coherent |= (1 << dst_index);
958 else
959 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
960 }
961 }
962 }
963
964 static void
965 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
966 {
967 struct nvc0_context *nvc0 = nvc0_context(pipe);
968
969 nvc0->vertex = hwcso;
970 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
971 }
972
973 static struct pipe_stream_output_target *
974 nvc0_so_target_create(struct pipe_context *pipe,
975 struct pipe_resource *res,
976 unsigned offset, unsigned size)
977 {
978 struct nv04_resource *buf = (struct nv04_resource *)res;
979 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
980 if (!targ)
981 return NULL;
982
983 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
984 if (!targ->pq) {
985 FREE(targ);
986 return NULL;
987 }
988 targ->clean = true;
989
990 targ->pipe.buffer_size = size;
991 targ->pipe.buffer_offset = offset;
992 targ->pipe.context = pipe;
993 targ->pipe.buffer = NULL;
994 pipe_resource_reference(&targ->pipe.buffer, res);
995 pipe_reference_init(&targ->pipe.reference, 1);
996
997 assert(buf->base.target == PIPE_BUFFER);
998 util_range_add(&buf->valid_buffer_range, offset, offset + size);
999
1000 return &targ->pipe;
1001 }
1002
1003 static void
1004 nvc0_so_target_save_offset(struct pipe_context *pipe,
1005 struct pipe_stream_output_target *ptarg,
1006 unsigned index, bool *serialize)
1007 {
1008 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1009
1010 if (*serialize) {
1011 *serialize = false;
1012 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1013 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1014
1015 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1016 }
1017
1018 nvc0_query(targ->pq)->index = index;
1019 pipe->end_query(pipe, targ->pq);
1020 }
1021
1022 static void
1023 nvc0_so_target_destroy(struct pipe_context *pipe,
1024 struct pipe_stream_output_target *ptarg)
1025 {
1026 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1027 pipe->destroy_query(pipe, targ->pq);
1028 pipe_resource_reference(&targ->pipe.buffer, NULL);
1029 FREE(targ);
1030 }
1031
1032 static void
1033 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1034 unsigned num_targets,
1035 struct pipe_stream_output_target **targets,
1036 const unsigned *offsets)
1037 {
1038 struct nvc0_context *nvc0 = nvc0_context(pipe);
1039 unsigned i;
1040 bool serialize = true;
1041
1042 assert(num_targets <= 4);
1043
1044 for (i = 0; i < num_targets; ++i) {
1045 const bool changed = nvc0->tfbbuf[i] != targets[i];
1046 const bool append = (offsets[i] == ((unsigned)-1));
1047 if (!changed && append)
1048 continue;
1049 nvc0->tfbbuf_dirty |= 1 << i;
1050
1051 if (nvc0->tfbbuf[i] && changed)
1052 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1053
1054 if (targets[i] && !append)
1055 nvc0_so_target(targets[i])->clean = true;
1056
1057 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1058 }
1059 for (; i < nvc0->num_tfbbufs; ++i) {
1060 if (nvc0->tfbbuf[i]) {
1061 nvc0->tfbbuf_dirty |= 1 << i;
1062 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1063 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1064 }
1065 }
1066 nvc0->num_tfbbufs = num_targets;
1067
1068 if (nvc0->tfbbuf_dirty) {
1069 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1070 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1071 }
1072 }
1073
1074 static void
1075 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1076 unsigned start, unsigned nr,
1077 struct pipe_surface **psurfaces)
1078 {
1079 const unsigned end = start + nr;
1080 const unsigned mask = ((1 << nr) - 1) << start;
1081 unsigned i;
1082
1083 if (psurfaces) {
1084 for (i = start; i < end; ++i) {
1085 const unsigned p = i - start;
1086 if (psurfaces[p])
1087 nvc0->surfaces_valid[t] |= (1 << i);
1088 else
1089 nvc0->surfaces_valid[t] &= ~(1 << i);
1090 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1091 }
1092 } else {
1093 for (i = start; i < end; ++i)
1094 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1095 nvc0->surfaces_valid[t] &= ~mask;
1096 }
1097 nvc0->surfaces_dirty[t] |= mask;
1098
1099 if (t == 0)
1100 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1101 else
1102 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1103 }
1104
1105 static void
1106 nvc0_set_compute_resources(struct pipe_context *pipe,
1107 unsigned start, unsigned nr,
1108 struct pipe_surface **resources)
1109 {
1110 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1111
1112 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1113 }
1114
1115 static bool
1116 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1117 unsigned start, unsigned nr,
1118 const struct pipe_image_view *pimages)
1119 {
1120 const unsigned end = start + nr;
1121 unsigned mask = 0;
1122 unsigned i;
1123
1124 assert(s < 6);
1125
1126 if (pimages) {
1127 for (i = start; i < end; ++i) {
1128 struct pipe_image_view *img = &nvc0->images[s][i];
1129 const unsigned p = i - start;
1130
1131 if (img->resource == pimages[p].resource &&
1132 img->format == pimages[p].format &&
1133 img->access == pimages[p].access) {
1134 if (img->resource == NULL)
1135 continue;
1136 if (img->resource->target == PIPE_BUFFER &&
1137 img->u.buf.offset == pimages[p].u.buf.offset &&
1138 img->u.buf.size == pimages[p].u.buf.size)
1139 continue;
1140 if (img->resource->target != PIPE_BUFFER &&
1141 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1142 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1143 img->u.tex.level == pimages[p].u.tex.level)
1144 continue;
1145 }
1146
1147 mask |= (1 << i);
1148 if (pimages[p].resource)
1149 nvc0->images_valid[s] |= (1 << i);
1150 else
1151 nvc0->images_valid[s] &= ~(1 << i);
1152
1153 img->format = pimages[p].format;
1154 img->access = pimages[p].access;
1155 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1156 img->u.buf = pimages[p].u.buf;
1157 else
1158 img->u.tex = pimages[p].u.tex;
1159
1160 pipe_resource_reference(
1161 &img->resource, pimages[p].resource);
1162
1163 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1164 if (nvc0->images_tic[s][i]) {
1165 struct nv50_tic_entry *old =
1166 nv50_tic_entry(nvc0->images_tic[s][i]);
1167 nvc0_screen_tic_unlock(nvc0->screen, old);
1168 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1169 }
1170
1171 nvc0->images_tic[s][i] =
1172 gm107_create_texture_view_from_image(&nvc0->base.pipe,
1173 &pimages[p]);
1174 }
1175 }
1176 if (!mask)
1177 return false;
1178 } else {
1179 mask = ((1 << nr) - 1) << start;
1180 if (!(nvc0->images_valid[s] & mask))
1181 return false;
1182 for (i = start; i < end; ++i) {
1183 pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1184 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1185 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1186 if (old) {
1187 nvc0_screen_tic_unlock(nvc0->screen, old);
1188 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1189 }
1190 }
1191 }
1192 nvc0->images_valid[s] &= ~mask;
1193 }
1194 nvc0->images_dirty[s] |= mask;
1195
1196 if (s == 5)
1197 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1198 else
1199 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1200
1201 return true;
1202 }
1203
1204 static void
1205 nvc0_set_shader_images(struct pipe_context *pipe,
1206 enum pipe_shader_type shader,
1207 unsigned start, unsigned nr,
1208 const struct pipe_image_view *images)
1209 {
1210 const unsigned s = nvc0_shader_stage(shader);
1211 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1212 return;
1213
1214 if (s == 5)
1215 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1216 else
1217 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1218 }
1219
1220 static bool
1221 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1222 unsigned start, unsigned nr,
1223 const struct pipe_shader_buffer *pbuffers)
1224 {
1225 const unsigned end = start + nr;
1226 unsigned mask = 0;
1227 unsigned i;
1228
1229 assert(t < 6);
1230
1231 if (pbuffers) {
1232 for (i = start; i < end; ++i) {
1233 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1234 const unsigned p = i - start;
1235 if (buf->buffer == pbuffers[p].buffer &&
1236 buf->buffer_offset == pbuffers[p].buffer_offset &&
1237 buf->buffer_size == pbuffers[p].buffer_size)
1238 continue;
1239
1240 mask |= (1 << i);
1241 if (pbuffers[p].buffer)
1242 nvc0->buffers_valid[t] |= (1 << i);
1243 else
1244 nvc0->buffers_valid[t] &= ~(1 << i);
1245 buf->buffer_offset = pbuffers[p].buffer_offset;
1246 buf->buffer_size = pbuffers[p].buffer_size;
1247 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1248 }
1249 if (!mask)
1250 return false;
1251 } else {
1252 mask = ((1 << nr) - 1) << start;
1253 if (!(nvc0->buffers_valid[t] & mask))
1254 return false;
1255 for (i = start; i < end; ++i)
1256 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1257 nvc0->buffers_valid[t] &= ~mask;
1258 }
1259 nvc0->buffers_dirty[t] |= mask;
1260
1261 if (t == 5)
1262 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1263 else
1264 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1265
1266 return true;
1267 }
1268
1269 static void
1270 nvc0_set_shader_buffers(struct pipe_context *pipe,
1271 enum pipe_shader_type shader,
1272 unsigned start, unsigned nr,
1273 const struct pipe_shader_buffer *buffers)
1274 {
1275 const unsigned s = nvc0_shader_stage(shader);
1276 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1277 return;
1278
1279 if (s == 5)
1280 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1281 else
1282 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1283 }
1284
1285 static inline void
1286 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1287 {
1288 struct nv04_resource *buf = nv04_resource(res);
1289 if (buf) {
1290 uint64_t limit = (buf->address + buf->base.width0) - 1;
1291 if (limit < (1ULL << 32)) {
1292 *phandle = (uint32_t)buf->address;
1293 } else {
1294 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1295 "resource not contained within 32-bit address space !\n");
1296 *phandle = 0;
1297 }
1298 } else {
1299 *phandle = 0;
1300 }
1301 }
1302
1303 static void
1304 nvc0_set_global_bindings(struct pipe_context *pipe,
1305 unsigned start, unsigned nr,
1306 struct pipe_resource **resources,
1307 uint32_t **handles)
1308 {
1309 struct nvc0_context *nvc0 = nvc0_context(pipe);
1310 struct pipe_resource **ptr;
1311 unsigned i;
1312 const unsigned end = start + nr;
1313
1314 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1315 const unsigned old_size = nvc0->global_residents.size;
1316 const unsigned req_size = end * sizeof(struct pipe_resource *);
1317 util_dynarray_resize(&nvc0->global_residents, req_size);
1318 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1319 req_size - old_size);
1320 }
1321
1322 if (resources) {
1323 ptr = util_dynarray_element(
1324 &nvc0->global_residents, struct pipe_resource *, start);
1325 for (i = 0; i < nr; ++i) {
1326 pipe_resource_reference(&ptr[i], resources[i]);
1327 nvc0_set_global_handle(handles[i], resources[i]);
1328 }
1329 } else {
1330 ptr = util_dynarray_element(
1331 &nvc0->global_residents, struct pipe_resource *, start);
1332 for (i = 0; i < nr; ++i)
1333 pipe_resource_reference(&ptr[i], NULL);
1334 }
1335
1336 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1337
1338 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1339 }
1340
1341 void
1342 nvc0_init_state_functions(struct nvc0_context *nvc0)
1343 {
1344 struct pipe_context *pipe = &nvc0->base.pipe;
1345
1346 pipe->create_blend_state = nvc0_blend_state_create;
1347 pipe->bind_blend_state = nvc0_blend_state_bind;
1348 pipe->delete_blend_state = nvc0_blend_state_delete;
1349
1350 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1351 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1352 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1353
1354 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1355 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1356 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1357
1358 pipe->create_sampler_state = nv50_sampler_state_create;
1359 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1360 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1361
1362 pipe->create_sampler_view = nvc0_create_sampler_view;
1363 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1364 pipe->set_sampler_views = nvc0_set_sampler_views;
1365
1366 pipe->create_vs_state = nvc0_vp_state_create;
1367 pipe->create_fs_state = nvc0_fp_state_create;
1368 pipe->create_gs_state = nvc0_gp_state_create;
1369 pipe->create_tcs_state = nvc0_tcp_state_create;
1370 pipe->create_tes_state = nvc0_tep_state_create;
1371 pipe->bind_vs_state = nvc0_vp_state_bind;
1372 pipe->bind_fs_state = nvc0_fp_state_bind;
1373 pipe->bind_gs_state = nvc0_gp_state_bind;
1374 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1375 pipe->bind_tes_state = nvc0_tep_state_bind;
1376 pipe->delete_vs_state = nvc0_sp_state_delete;
1377 pipe->delete_fs_state = nvc0_sp_state_delete;
1378 pipe->delete_gs_state = nvc0_sp_state_delete;
1379 pipe->delete_tcs_state = nvc0_sp_state_delete;
1380 pipe->delete_tes_state = nvc0_sp_state_delete;
1381
1382 pipe->create_compute_state = nvc0_cp_state_create;
1383 pipe->bind_compute_state = nvc0_cp_state_bind;
1384 pipe->delete_compute_state = nvc0_sp_state_delete;
1385
1386 pipe->set_blend_color = nvc0_set_blend_color;
1387 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1388 pipe->set_clip_state = nvc0_set_clip_state;
1389 pipe->set_sample_mask = nvc0_set_sample_mask;
1390 pipe->set_min_samples = nvc0_set_min_samples;
1391 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1392 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1393 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1394 pipe->set_scissor_states = nvc0_set_scissor_states;
1395 pipe->set_viewport_states = nvc0_set_viewport_states;
1396 pipe->set_window_rectangles = nvc0_set_window_rectangles;
1397 pipe->set_tess_state = nvc0_set_tess_state;
1398
1399 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1400 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1401 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1402
1403 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1404
1405 pipe->create_stream_output_target = nvc0_so_target_create;
1406 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1407 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1408
1409 pipe->set_global_binding = nvc0_set_global_bindings;
1410 pipe->set_compute_resources = nvc0_set_compute_resources;
1411 pipe->set_shader_images = nvc0_set_shader_images;
1412 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1413
1414 nvc0->sample_mask = ~0;
1415 nvc0->min_samples = 1;
1416 nvc0->default_tess_outer[0] =
1417 nvc0->default_tess_outer[1] =
1418 nvc0->default_tess_outer[2] =
1419 nvc0->default_tess_outer[3] = 1.0;
1420 nvc0->default_tess_inner[0] =
1421 nvc0->default_tess_inner[1] = 1.0;
1422 }