2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
29 #include "tgsi/tgsi_parse.h"
31 #include "nvc0/nvc0_stateobj.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
35 #include "nvc0/nvc0_3d.xml.h"
37 #include "nouveau_gldefs.h"
39 static inline uint32_t
40 nvc0_colormask(unsigned mask
)
44 if (mask
& PIPE_MASK_R
)
46 if (mask
& PIPE_MASK_G
)
48 if (mask
& PIPE_MASK_B
)
50 if (mask
& PIPE_MASK_A
)
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor
)
63 NVC0_BLEND_FACTOR_CASE(ONE
, ONE
);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR
, SRC_COLOR
);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA
, SRC_ALPHA
);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA
, DST_ALPHA
);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR
, DST_COLOR
);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE
, SRC_ALPHA_SATURATE
);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR
, CONSTANT_COLOR
);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA
, CONSTANT_ALPHA
);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR
, SRC1_COLOR
);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA
, SRC1_ALPHA
);
73 NVC0_BLEND_FACTOR_CASE(ZERO
, ZERO
);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR
, ONE_MINUS_SRC_COLOR
);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA
, ONE_MINUS_SRC_ALPHA
);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA
, ONE_MINUS_DST_ALPHA
);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR
, ONE_MINUS_DST_COLOR
);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR
, ONE_MINUS_CONSTANT_COLOR
);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA
, ONE_MINUS_CONSTANT_ALPHA
);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR
, ONE_MINUS_SRC1_COLOR
);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA
, ONE_MINUS_SRC1_ALPHA
);
83 return NV50_BLEND_FACTOR_ZERO
;
88 nvc0_blend_state_create(struct pipe_context
*pipe
,
89 const struct pipe_blend_state
*cso
)
91 struct nvc0_blend_stateobj
*so
= CALLOC_STRUCT(nvc0_blend_stateobj
);
93 int r
; /* reference */
96 bool indep_masks
= false;
97 bool indep_funcs
= false;
101 /* check which states actually have differing values */
102 if (cso
->independent_blend_enable
) {
103 for (r
= 0; r
< 8 && !cso
->rt
[r
].blend_enable
; ++r
);
105 for (i
= r
+ 1; i
< 8; ++i
) {
106 if (!cso
->rt
[i
].blend_enable
)
109 if (cso
->rt
[i
].rgb_func
!= cso
->rt
[r
].rgb_func
||
110 cso
->rt
[i
].rgb_src_factor
!= cso
->rt
[r
].rgb_src_factor
||
111 cso
->rt
[i
].rgb_dst_factor
!= cso
->rt
[r
].rgb_dst_factor
||
112 cso
->rt
[i
].alpha_func
!= cso
->rt
[r
].alpha_func
||
113 cso
->rt
[i
].alpha_src_factor
!= cso
->rt
[r
].alpha_src_factor
||
114 cso
->rt
[i
].alpha_dst_factor
!= cso
->rt
[r
].alpha_dst_factor
) {
120 blend_en
|= (cso
->rt
[i
].blend_enable
? 1 : 0) << i
;
122 for (i
= 1; i
< 8; ++i
) {
123 if (cso
->rt
[i
].colormask
!= cso
->rt
[0].colormask
) {
130 if (cso
->rt
[0].blend_enable
)
134 if (cso
->logicop_enable
) {
135 SB_BEGIN_3D(so
, LOGIC_OP_ENABLE
, 2);
137 SB_DATA (so
, nvgl_logicop_func(cso
->logicop_func
));
139 SB_IMMED_3D(so
, MACRO_BLEND_ENABLES
, 0);
141 SB_IMMED_3D(so
, LOGIC_OP_ENABLE
, 0);
143 SB_IMMED_3D(so
, BLEND_INDEPENDENT
, indep_funcs
);
144 SB_IMMED_3D(so
, MACRO_BLEND_ENABLES
, blend_en
);
146 for (i
= 0; i
< 8; ++i
) {
147 if (cso
->rt
[i
].blend_enable
) {
148 SB_BEGIN_3D(so
, IBLEND_EQUATION_RGB(i
), 6);
149 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[i
].rgb_func
));
150 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].rgb_src_factor
));
151 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].rgb_dst_factor
));
152 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[i
].alpha_func
));
153 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].alpha_src_factor
));
154 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].alpha_dst_factor
));
159 SB_BEGIN_3D(so
, BLEND_EQUATION_RGB
, 5);
160 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[r
].rgb_func
));
161 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].rgb_src_factor
));
162 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].rgb_dst_factor
));
163 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[r
].alpha_func
));
164 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].alpha_src_factor
));
165 SB_BEGIN_3D(so
, BLEND_FUNC_DST_ALPHA
, 1);
166 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].alpha_dst_factor
));
169 SB_IMMED_3D(so
, COLOR_MASK_COMMON
, !indep_masks
);
171 SB_BEGIN_3D(so
, COLOR_MASK(0), 8);
172 for (i
= 0; i
< 8; ++i
)
173 SB_DATA(so
, nvc0_colormask(cso
->rt
[i
].colormask
));
175 SB_BEGIN_3D(so
, COLOR_MASK(0), 1);
176 SB_DATA (so
, nvc0_colormask(cso
->rt
[0].colormask
));
181 if (cso
->alpha_to_coverage
)
182 ms
|= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE
;
183 if (cso
->alpha_to_one
)
184 ms
|= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE
;
186 SB_BEGIN_3D(so
, MULTISAMPLE_CTRL
, 1);
189 assert(so
->size
<= ARRAY_SIZE(so
->state
));
194 nvc0_blend_state_bind(struct pipe_context
*pipe
, void *hwcso
)
196 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
199 nvc0
->dirty_3d
|= NVC0_NEW_3D_BLEND
;
203 nvc0_blend_state_delete(struct pipe_context
*pipe
, void *hwcso
)
208 /* NOTE: ignoring line_last_pixel */
210 nvc0_rasterizer_state_create(struct pipe_context
*pipe
,
211 const struct pipe_rasterizer_state
*cso
)
213 struct nvc0_rasterizer_stateobj
*so
;
214 uint16_t class_3d
= nouveau_screen(pipe
->screen
)->class_3d
;
217 so
= CALLOC_STRUCT(nvc0_rasterizer_stateobj
);
222 /* Scissor enables are handled in scissor state, we will not want to
223 * always emit 16 commands, one for each scissor rectangle, here.
226 SB_IMMED_3D(so
, PROVOKING_VERTEX_LAST
, !cso
->flatshade_first
);
227 SB_IMMED_3D(so
, VERTEX_TWO_SIDE_ENABLE
, cso
->light_twoside
);
229 SB_IMMED_3D(so
, VERT_COLOR_CLAMP_EN
, cso
->clamp_vertex_color
);
230 SB_BEGIN_3D(so
, FRAG_COLOR_CLAMP_EN
, 1);
231 SB_DATA (so
, cso
->clamp_fragment_color
? 0x11111111 : 0x00000000);
233 SB_IMMED_3D(so
, MULTISAMPLE_ENABLE
, cso
->multisample
);
235 SB_IMMED_3D(so
, LINE_SMOOTH_ENABLE
, cso
->line_smooth
);
236 /* On GM20x+, LINE_WIDTH_SMOOTH controls both aliased and smooth
237 * rendering and LINE_WIDTH_ALIASED seems to be ignored
239 if (cso
->line_smooth
|| cso
->multisample
|| class_3d
>= GM200_3D_CLASS
)
240 SB_BEGIN_3D(so
, LINE_WIDTH_SMOOTH
, 1);
242 SB_BEGIN_3D(so
, LINE_WIDTH_ALIASED
, 1);
243 SB_DATA (so
, fui(cso
->line_width
));
245 SB_IMMED_3D(so
, LINE_STIPPLE_ENABLE
, cso
->line_stipple_enable
);
246 if (cso
->line_stipple_enable
) {
247 SB_BEGIN_3D(so
, LINE_STIPPLE_PATTERN
, 1);
248 SB_DATA (so
, (cso
->line_stipple_pattern
<< 8) |
249 cso
->line_stipple_factor
);
253 SB_IMMED_3D(so
, VP_POINT_SIZE
, cso
->point_size_per_vertex
);
254 if (!cso
->point_size_per_vertex
) {
255 SB_BEGIN_3D(so
, POINT_SIZE
, 1);
256 SB_DATA (so
, fui(cso
->point_size
));
259 reg
= (cso
->sprite_coord_mode
== PIPE_SPRITE_COORD_UPPER_LEFT
) ?
260 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT
:
261 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT
;
263 SB_BEGIN_3D(so
, POINT_COORD_REPLACE
, 1);
264 SB_DATA (so
, ((cso
->sprite_coord_enable
& 0xff) << 3) | reg
);
265 SB_IMMED_3D(so
, POINT_SPRITE_ENABLE
, cso
->point_quad_rasterization
);
266 SB_IMMED_3D(so
, POINT_SMOOTH_ENABLE
, cso
->point_smooth
);
268 if (class_3d
>= GM200_3D_CLASS
) {
269 SB_IMMED_3D(so
, FILL_RECTANGLE
,
270 cso
->fill_front
== PIPE_POLYGON_MODE_FILL_RECTANGLE
?
271 NVC0_3D_FILL_RECTANGLE_ENABLE
: 0);
274 SB_BEGIN_3D(so
, MACRO_POLYGON_MODE_FRONT
, 1);
275 SB_DATA (so
, nvgl_polygon_mode(cso
->fill_front
));
276 SB_BEGIN_3D(so
, MACRO_POLYGON_MODE_BACK
, 1);
277 SB_DATA (so
, nvgl_polygon_mode(cso
->fill_back
));
278 SB_IMMED_3D(so
, POLYGON_SMOOTH_ENABLE
, cso
->poly_smooth
);
280 SB_BEGIN_3D(so
, CULL_FACE_ENABLE
, 3);
281 SB_DATA (so
, cso
->cull_face
!= PIPE_FACE_NONE
);
282 SB_DATA (so
, cso
->front_ccw
? NVC0_3D_FRONT_FACE_CCW
:
283 NVC0_3D_FRONT_FACE_CW
);
284 switch (cso
->cull_face
) {
285 case PIPE_FACE_FRONT_AND_BACK
:
286 SB_DATA(so
, NVC0_3D_CULL_FACE_FRONT_AND_BACK
);
288 case PIPE_FACE_FRONT
:
289 SB_DATA(so
, NVC0_3D_CULL_FACE_FRONT
);
293 SB_DATA(so
, NVC0_3D_CULL_FACE_BACK
);
297 SB_IMMED_3D(so
, POLYGON_STIPPLE_ENABLE
, cso
->poly_stipple_enable
);
298 SB_BEGIN_3D(so
, POLYGON_OFFSET_POINT_ENABLE
, 3);
299 SB_DATA (so
, cso
->offset_point
);
300 SB_DATA (so
, cso
->offset_line
);
301 SB_DATA (so
, cso
->offset_tri
);
303 if (cso
->offset_point
|| cso
->offset_line
|| cso
->offset_tri
) {
304 SB_BEGIN_3D(so
, POLYGON_OFFSET_FACTOR
, 1);
305 SB_DATA (so
, fui(cso
->offset_scale
));
306 if (!cso
->offset_units_unscaled
) {
307 SB_BEGIN_3D(so
, POLYGON_OFFSET_UNITS
, 1);
308 SB_DATA (so
, fui(cso
->offset_units
* 2.0f
));
310 SB_BEGIN_3D(so
, POLYGON_OFFSET_CLAMP
, 1);
311 SB_DATA (so
, fui(cso
->offset_clamp
));
315 reg
= NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
;
318 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
|
319 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR
|
320 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR
|
321 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2
;
323 SB_BEGIN_3D(so
, VIEW_VOLUME_CLIP_CTRL
, 1);
326 SB_IMMED_3D(so
, DEPTH_CLIP_NEGATIVE_Z
, cso
->clip_halfz
);
328 SB_IMMED_3D(so
, PIXEL_CENTER_INTEGER
, !cso
->half_pixel_center
);
330 if (class_3d
>= GM200_3D_CLASS
) {
331 if (cso
->conservative_raster_mode
!= PIPE_CONSERVATIVE_RASTER_OFF
) {
332 bool post_snap
= cso
->conservative_raster_mode
==
333 PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
334 uint32_t state
= cso
->subpixel_precision_x
;
335 state
|= cso
->subpixel_precision_y
<< 4;
336 state
|= (uint32_t)(cso
->conservative_raster_dilate
* 4) << 8;
337 state
|= (post_snap
|| class_3d
< GP100_3D_CLASS
) ? 1 << 10 : 0;
338 SB_IMMED_3D(so
, MACRO_CONSERVATIVE_RASTER_STATE
, state
);
340 SB_IMMED_3D(so
, CONSERVATIVE_RASTER
, 0);
344 assert(so
->size
<= ARRAY_SIZE(so
->state
));
349 nvc0_rasterizer_state_bind(struct pipe_context
*pipe
, void *hwcso
)
351 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
354 nvc0
->dirty_3d
|= NVC0_NEW_3D_RASTERIZER
;
358 nvc0_rasterizer_state_delete(struct pipe_context
*pipe
, void *hwcso
)
364 nvc0_zsa_state_create(struct pipe_context
*pipe
,
365 const struct pipe_depth_stencil_alpha_state
*cso
)
367 struct nvc0_zsa_stateobj
*so
= CALLOC_STRUCT(nvc0_zsa_stateobj
);
371 SB_IMMED_3D(so
, DEPTH_TEST_ENABLE
, cso
->depth
.enabled
);
372 if (cso
->depth
.enabled
) {
373 SB_IMMED_3D(so
, DEPTH_WRITE_ENABLE
, cso
->depth
.writemask
);
374 SB_BEGIN_3D(so
, DEPTH_TEST_FUNC
, 1);
375 SB_DATA (so
, nvgl_comparison_op(cso
->depth
.func
));
378 SB_IMMED_3D(so
, DEPTH_BOUNDS_EN
, cso
->depth
.bounds_test
);
379 if (cso
->depth
.bounds_test
) {
380 SB_BEGIN_3D(so
, DEPTH_BOUNDS(0), 2);
381 SB_DATA (so
, fui(cso
->depth
.bounds_min
));
382 SB_DATA (so
, fui(cso
->depth
.bounds_max
));
385 if (cso
->stencil
[0].enabled
) {
386 SB_BEGIN_3D(so
, STENCIL_ENABLE
, 5);
388 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[0].fail_op
));
389 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[0].zfail_op
));
390 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[0].zpass_op
));
391 SB_DATA (so
, nvgl_comparison_op(cso
->stencil
[0].func
));
392 SB_BEGIN_3D(so
, STENCIL_FRONT_FUNC_MASK
, 2);
393 SB_DATA (so
, cso
->stencil
[0].valuemask
);
394 SB_DATA (so
, cso
->stencil
[0].writemask
);
396 SB_IMMED_3D(so
, STENCIL_ENABLE
, 0);
399 if (cso
->stencil
[1].enabled
) {
400 assert(cso
->stencil
[0].enabled
);
401 SB_BEGIN_3D(so
, STENCIL_TWO_SIDE_ENABLE
, 5);
403 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[1].fail_op
));
404 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[1].zfail_op
));
405 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[1].zpass_op
));
406 SB_DATA (so
, nvgl_comparison_op(cso
->stencil
[1].func
));
407 SB_BEGIN_3D(so
, STENCIL_BACK_MASK
, 2);
408 SB_DATA (so
, cso
->stencil
[1].writemask
);
409 SB_DATA (so
, cso
->stencil
[1].valuemask
);
411 if (cso
->stencil
[0].enabled
) {
412 SB_IMMED_3D(so
, STENCIL_TWO_SIDE_ENABLE
, 0);
415 SB_IMMED_3D(so
, ALPHA_TEST_ENABLE
, cso
->alpha
.enabled
);
416 if (cso
->alpha
.enabled
) {
417 SB_BEGIN_3D(so
, ALPHA_TEST_REF
, 2);
418 SB_DATA (so
, fui(cso
->alpha
.ref_value
));
419 SB_DATA (so
, nvgl_comparison_op(cso
->alpha
.func
));
422 assert(so
->size
<= ARRAY_SIZE(so
->state
));
427 nvc0_zsa_state_bind(struct pipe_context
*pipe
, void *hwcso
)
429 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
432 nvc0
->dirty_3d
|= NVC0_NEW_3D_ZSA
;
436 nvc0_zsa_state_delete(struct pipe_context
*pipe
, void *hwcso
)
441 /* ====================== SAMPLERS AND TEXTURES ================================
444 #define NV50_TSC_WRAP_CASE(n) \
445 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
448 nvc0_sampler_state_delete(struct pipe_context
*pipe
, void *hwcso
)
452 for (s
= 0; s
< 6; ++s
)
453 for (i
= 0; i
< nvc0_context(pipe
)->num_samplers
[s
]; ++i
)
454 if (nvc0_context(pipe
)->samplers
[s
][i
] == hwcso
)
455 nvc0_context(pipe
)->samplers
[s
][i
] = NULL
;
457 nvc0_screen_tsc_free(nvc0_context(pipe
)->screen
, nv50_tsc_entry(hwcso
));
463 nvc0_stage_sampler_states_bind(struct nvc0_context
*nvc0
,
465 unsigned nr
, void **hwcso
)
469 for (i
= 0; i
< nr
; ++i
) {
470 struct nv50_tsc_entry
*old
= nvc0
->samplers
[s
][i
];
474 nvc0
->samplers_dirty
[s
] |= 1 << i
;
476 nvc0
->samplers
[s
][i
] = nv50_tsc_entry(hwcso
[i
]);
478 nvc0_screen_tsc_unlock(nvc0
->screen
, old
);
480 for (; i
< nvc0
->num_samplers
[s
]; ++i
) {
481 if (nvc0
->samplers
[s
][i
]) {
482 nvc0_screen_tsc_unlock(nvc0
->screen
, nvc0
->samplers
[s
][i
]);
483 nvc0
->samplers
[s
][i
] = NULL
;
487 nvc0
->num_samplers
[s
] = nr
;
491 nvc0_bind_sampler_states(struct pipe_context
*pipe
,
492 enum pipe_shader_type shader
,
493 unsigned start
, unsigned nr
, void **samplers
)
495 const unsigned s
= nvc0_shader_stage(shader
);
498 nvc0_stage_sampler_states_bind(nvc0_context(pipe
), s
, nr
, samplers
);
501 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_SAMPLERS
;
503 nvc0_context(pipe
)->dirty_3d
|= NVC0_NEW_3D_SAMPLERS
;
507 /* NOTE: only called when not referenced anywhere, won't be bound */
509 nvc0_sampler_view_destroy(struct pipe_context
*pipe
,
510 struct pipe_sampler_view
*view
)
512 pipe_resource_reference(&view
->texture
, NULL
);
514 nvc0_screen_tic_free(nvc0_context(pipe
)->screen
, nv50_tic_entry(view
));
516 FREE(nv50_tic_entry(view
));
520 nvc0_stage_set_sampler_views(struct nvc0_context
*nvc0
, int s
,
522 struct pipe_sampler_view
**views
)
526 for (i
= 0; i
< nr
; ++i
) {
527 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
529 if (views
[i
] == nvc0
->textures
[s
][i
])
531 nvc0
->textures_dirty
[s
] |= 1 << i
;
533 if (views
[i
] && views
[i
]->texture
) {
534 struct pipe_resource
*res
= views
[i
]->texture
;
535 if (res
->target
== PIPE_BUFFER
&&
536 (res
->flags
& PIPE_RESOURCE_FLAG_MAP_COHERENT
))
537 nvc0
->textures_coherent
[s
] |= 1 << i
;
539 nvc0
->textures_coherent
[s
] &= ~(1 << i
);
541 nvc0
->textures_coherent
[s
] &= ~(1 << i
);
546 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_TEX(i
));
548 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_TEX(s
, i
));
549 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
552 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], views
[i
]);
555 for (i
= nr
; i
< nvc0
->num_textures
[s
]; ++i
) {
556 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
559 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_TEX(i
));
561 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_TEX(s
, i
));
562 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
563 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], NULL
);
567 nvc0
->num_textures
[s
] = nr
;
571 nvc0_set_sampler_views(struct pipe_context
*pipe
, enum pipe_shader_type shader
,
572 unsigned start
, unsigned nr
,
573 struct pipe_sampler_view
**views
)
575 const unsigned s
= nvc0_shader_stage(shader
);
578 nvc0_stage_set_sampler_views(nvc0_context(pipe
), s
, nr
, views
);
581 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_TEXTURES
;
583 nvc0_context(pipe
)->dirty_3d
|= NVC0_NEW_3D_TEXTURES
;
586 /* ============================= SHADERS =======================================
590 nvc0_sp_state_create(struct pipe_context
*pipe
,
591 const struct pipe_shader_state
*cso
, unsigned type
)
593 struct nvc0_program
*prog
;
595 prog
= CALLOC_STRUCT(nvc0_program
);
602 prog
->pipe
.tokens
= tgsi_dup_tokens(cso
->tokens
);
604 if (cso
->stream_output
.num_outputs
)
605 prog
->pipe
.stream_output
= cso
->stream_output
;
607 prog
->translated
= nvc0_program_translate(
608 prog
, nvc0_context(pipe
)->screen
->base
.device
->chipset
,
609 &nouveau_context(pipe
)->debug
);
615 nvc0_sp_state_delete(struct pipe_context
*pipe
, void *hwcso
)
617 struct nvc0_program
*prog
= (struct nvc0_program
*)hwcso
;
619 nvc0_program_destroy(nvc0_context(pipe
), prog
);
621 FREE((void *)prog
->pipe
.tokens
);
626 nvc0_vp_state_create(struct pipe_context
*pipe
,
627 const struct pipe_shader_state
*cso
)
629 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_VERTEX
);
633 nvc0_vp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
635 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
637 nvc0
->vertprog
= hwcso
;
638 nvc0
->dirty_3d
|= NVC0_NEW_3D_VERTPROG
;
642 nvc0_fp_state_create(struct pipe_context
*pipe
,
643 const struct pipe_shader_state
*cso
)
645 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_FRAGMENT
);
649 nvc0_fp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
651 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
653 nvc0
->fragprog
= hwcso
;
654 nvc0
->dirty_3d
|= NVC0_NEW_3D_FRAGPROG
;
658 nvc0_gp_state_create(struct pipe_context
*pipe
,
659 const struct pipe_shader_state
*cso
)
661 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_GEOMETRY
);
665 nvc0_gp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
667 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
669 nvc0
->gmtyprog
= hwcso
;
670 nvc0
->dirty_3d
|= NVC0_NEW_3D_GMTYPROG
;
674 nvc0_tcp_state_create(struct pipe_context
*pipe
,
675 const struct pipe_shader_state
*cso
)
677 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_TESS_CTRL
);
681 nvc0_tcp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
683 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
685 nvc0
->tctlprog
= hwcso
;
686 nvc0
->dirty_3d
|= NVC0_NEW_3D_TCTLPROG
;
690 nvc0_tep_state_create(struct pipe_context
*pipe
,
691 const struct pipe_shader_state
*cso
)
693 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_TESS_EVAL
);
697 nvc0_tep_state_bind(struct pipe_context
*pipe
, void *hwcso
)
699 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
701 nvc0
->tevlprog
= hwcso
;
702 nvc0
->dirty_3d
|= NVC0_NEW_3D_TEVLPROG
;
706 nvc0_cp_state_create(struct pipe_context
*pipe
,
707 const struct pipe_compute_state
*cso
)
709 struct nvc0_program
*prog
;
711 prog
= CALLOC_STRUCT(nvc0_program
);
714 prog
->type
= PIPE_SHADER_COMPUTE
;
716 prog
->cp
.smem_size
= cso
->req_local_mem
;
717 prog
->cp
.lmem_size
= cso
->req_private_mem
;
718 prog
->parm_size
= cso
->req_input_mem
;
720 prog
->pipe
.tokens
= tgsi_dup_tokens((const struct tgsi_token
*)cso
->prog
);
722 prog
->translated
= nvc0_program_translate(
723 prog
, nvc0_context(pipe
)->screen
->base
.device
->chipset
,
724 &nouveau_context(pipe
)->debug
);
730 nvc0_cp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
732 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
734 nvc0
->compprog
= hwcso
;
735 nvc0
->dirty_cp
|= NVC0_NEW_CP_PROGRAM
;
739 nvc0_set_constant_buffer(struct pipe_context
*pipe
,
740 enum pipe_shader_type shader
, uint index
,
741 const struct pipe_constant_buffer
*cb
)
743 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
744 struct pipe_resource
*res
= cb
? cb
->buffer
: NULL
;
745 const unsigned s
= nvc0_shader_stage(shader
);
746 const unsigned i
= index
;
748 if (unlikely(shader
== PIPE_SHADER_COMPUTE
)) {
749 if (nvc0
->constbuf
[s
][i
].user
)
750 nvc0
->constbuf
[s
][i
].u
.buf
= NULL
;
752 if (nvc0
->constbuf
[s
][i
].u
.buf
)
753 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_CB(i
));
755 nvc0
->dirty_cp
|= NVC0_NEW_CP_CONSTBUF
;
757 if (nvc0
->constbuf
[s
][i
].user
)
758 nvc0
->constbuf
[s
][i
].u
.buf
= NULL
;
760 if (nvc0
->constbuf
[s
][i
].u
.buf
)
761 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_CB(s
, i
));
763 nvc0
->dirty_3d
|= NVC0_NEW_3D_CONSTBUF
;
765 nvc0
->constbuf_dirty
[s
] |= 1 << i
;
767 if (nvc0
->constbuf
[s
][i
].u
.buf
)
768 nv04_resource(nvc0
->constbuf
[s
][i
].u
.buf
)->cb_bindings
[s
] &= ~(1 << i
);
769 pipe_resource_reference(&nvc0
->constbuf
[s
][i
].u
.buf
, res
);
771 nvc0
->constbuf
[s
][i
].user
= (cb
&& cb
->user_buffer
) ? true : false;
772 if (nvc0
->constbuf
[s
][i
].user
) {
773 nvc0
->constbuf
[s
][i
].u
.data
= cb
->user_buffer
;
774 nvc0
->constbuf
[s
][i
].size
= MIN2(cb
->buffer_size
, 0x10000);
775 nvc0
->constbuf_valid
[s
] |= 1 << i
;
776 nvc0
->constbuf_coherent
[s
] &= ~(1 << i
);
779 nvc0
->constbuf
[s
][i
].offset
= cb
->buffer_offset
;
780 nvc0
->constbuf
[s
][i
].size
= MIN2(align(cb
->buffer_size
, 0x100), 0x10000);
781 nvc0
->constbuf_valid
[s
] |= 1 << i
;
782 if (res
&& res
->flags
& PIPE_RESOURCE_FLAG_MAP_COHERENT
)
783 nvc0
->constbuf_coherent
[s
] |= 1 << i
;
785 nvc0
->constbuf_coherent
[s
] &= ~(1 << i
);
788 nvc0
->constbuf_valid
[s
] &= ~(1 << i
);
789 nvc0
->constbuf_coherent
[s
] &= ~(1 << i
);
793 /* =============================================================================
797 nvc0_set_blend_color(struct pipe_context
*pipe
,
798 const struct pipe_blend_color
*bcol
)
800 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
802 nvc0
->blend_colour
= *bcol
;
803 nvc0
->dirty_3d
|= NVC0_NEW_3D_BLEND_COLOUR
;
807 nvc0_set_stencil_ref(struct pipe_context
*pipe
,
808 const struct pipe_stencil_ref
*sr
)
810 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
812 nvc0
->stencil_ref
= *sr
;
813 nvc0
->dirty_3d
|= NVC0_NEW_3D_STENCIL_REF
;
817 nvc0_set_clip_state(struct pipe_context
*pipe
,
818 const struct pipe_clip_state
*clip
)
820 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
822 memcpy(nvc0
->clip
.ucp
, clip
->ucp
, sizeof(clip
->ucp
));
824 nvc0
->dirty_3d
|= NVC0_NEW_3D_CLIP
;
828 nvc0_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
830 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
832 nvc0
->sample_mask
= sample_mask
;
833 nvc0
->dirty_3d
|= NVC0_NEW_3D_SAMPLE_MASK
;
837 nvc0_set_min_samples(struct pipe_context
*pipe
, unsigned min_samples
)
839 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
841 if (nvc0
->min_samples
!= min_samples
) {
842 nvc0
->min_samples
= min_samples
;
843 nvc0
->dirty_3d
|= NVC0_NEW_3D_MIN_SAMPLES
;
848 nvc0_set_framebuffer_state(struct pipe_context
*pipe
,
849 const struct pipe_framebuffer_state
*fb
)
851 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
853 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_FB
);
855 util_copy_framebuffer_state(&nvc0
->framebuffer
, fb
);
857 nvc0
->dirty_3d
|= NVC0_NEW_3D_FRAMEBUFFER
;
861 nvc0_set_polygon_stipple(struct pipe_context
*pipe
,
862 const struct pipe_poly_stipple
*stipple
)
864 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
866 nvc0
->stipple
= *stipple
;
867 nvc0
->dirty_3d
|= NVC0_NEW_3D_STIPPLE
;
871 nvc0_set_scissor_states(struct pipe_context
*pipe
,
873 unsigned num_scissors
,
874 const struct pipe_scissor_state
*scissor
)
876 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
879 assert(start_slot
+ num_scissors
<= NVC0_MAX_VIEWPORTS
);
880 for (i
= 0; i
< num_scissors
; i
++) {
881 if (!memcmp(&nvc0
->scissors
[start_slot
+ i
], &scissor
[i
], sizeof(*scissor
)))
883 nvc0
->scissors
[start_slot
+ i
] = scissor
[i
];
884 nvc0
->scissors_dirty
|= 1 << (start_slot
+ i
);
885 nvc0
->dirty_3d
|= NVC0_NEW_3D_SCISSOR
;
890 nvc0_set_viewport_states(struct pipe_context
*pipe
,
892 unsigned num_viewports
,
893 const struct pipe_viewport_state
*vpt
)
895 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
898 assert(start_slot
+ num_viewports
<= NVC0_MAX_VIEWPORTS
);
899 for (i
= 0; i
< num_viewports
; i
++) {
900 if (!memcmp(&nvc0
->viewports
[start_slot
+ i
], &vpt
[i
], sizeof(*vpt
)))
902 nvc0
->viewports
[start_slot
+ i
] = vpt
[i
];
903 nvc0
->viewports_dirty
|= 1 << (start_slot
+ i
);
904 nvc0
->dirty_3d
|= NVC0_NEW_3D_VIEWPORT
;
910 nvc0_set_window_rectangles(struct pipe_context
*pipe
,
912 unsigned num_rectangles
,
913 const struct pipe_scissor_state
*rectangles
)
915 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
917 nvc0
->window_rect
.inclusive
= include
;
918 nvc0
->window_rect
.rects
= MIN2(num_rectangles
, NVC0_MAX_WINDOW_RECTANGLES
);
919 memcpy(nvc0
->window_rect
.rect
, rectangles
,
920 sizeof(struct pipe_scissor_state
) * nvc0
->window_rect
.rects
);
922 nvc0
->dirty_3d
|= NVC0_NEW_3D_WINDOW_RECTS
;
926 nvc0_set_tess_state(struct pipe_context
*pipe
,
927 const float default_tess_outer
[4],
928 const float default_tess_inner
[2])
930 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
932 memcpy(nvc0
->default_tess_outer
, default_tess_outer
, 4 * sizeof(float));
933 memcpy(nvc0
->default_tess_inner
, default_tess_inner
, 2 * sizeof(float));
934 nvc0
->dirty_3d
|= NVC0_NEW_3D_TESSFACTOR
;
938 nvc0_set_vertex_buffers(struct pipe_context
*pipe
,
939 unsigned start_slot
, unsigned count
,
940 const struct pipe_vertex_buffer
*vb
)
942 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
945 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_VTX
);
946 nvc0
->dirty_3d
|= NVC0_NEW_3D_ARRAYS
;
948 util_set_vertex_buffers_count(nvc0
->vtxbuf
, &nvc0
->num_vtxbufs
, vb
,
952 nvc0
->vbo_user
&= ~(((1ull << count
) - 1) << start_slot
);
953 nvc0
->constant_vbos
&= ~(((1ull << count
) - 1) << start_slot
);
954 nvc0
->vtxbufs_coherent
&= ~(((1ull << count
) - 1) << start_slot
);
958 for (i
= 0; i
< count
; ++i
) {
959 unsigned dst_index
= start_slot
+ i
;
961 if (vb
[i
].is_user_buffer
) {
962 nvc0
->vbo_user
|= 1 << dst_index
;
963 if (!vb
[i
].stride
&& nvc0
->screen
->eng3d
->oclass
< GM107_3D_CLASS
)
964 nvc0
->constant_vbos
|= 1 << dst_index
;
966 nvc0
->constant_vbos
&= ~(1 << dst_index
);
967 nvc0
->vtxbufs_coherent
&= ~(1 << dst_index
);
969 nvc0
->vbo_user
&= ~(1 << dst_index
);
970 nvc0
->constant_vbos
&= ~(1 << dst_index
);
972 if (vb
[i
].buffer
.resource
&&
973 vb
[i
].buffer
.resource
->flags
& PIPE_RESOURCE_FLAG_MAP_COHERENT
)
974 nvc0
->vtxbufs_coherent
|= (1 << dst_index
);
976 nvc0
->vtxbufs_coherent
&= ~(1 << dst_index
);
982 nvc0_vertex_state_bind(struct pipe_context
*pipe
, void *hwcso
)
984 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
986 nvc0
->vertex
= hwcso
;
987 nvc0
->dirty_3d
|= NVC0_NEW_3D_VERTEX
;
990 static struct pipe_stream_output_target
*
991 nvc0_so_target_create(struct pipe_context
*pipe
,
992 struct pipe_resource
*res
,
993 unsigned offset
, unsigned size
)
995 struct nv04_resource
*buf
= (struct nv04_resource
*)res
;
996 struct nvc0_so_target
*targ
= MALLOC_STRUCT(nvc0_so_target
);
1000 targ
->pq
= pipe
->create_query(pipe
, NVC0_HW_QUERY_TFB_BUFFER_OFFSET
, 0);
1007 targ
->pipe
.buffer_size
= size
;
1008 targ
->pipe
.buffer_offset
= offset
;
1009 targ
->pipe
.context
= pipe
;
1010 targ
->pipe
.buffer
= NULL
;
1011 pipe_resource_reference(&targ
->pipe
.buffer
, res
);
1012 pipe_reference_init(&targ
->pipe
.reference
, 1);
1014 assert(buf
->base
.target
== PIPE_BUFFER
);
1015 util_range_add(&buf
->valid_buffer_range
, offset
, offset
+ size
);
1021 nvc0_so_target_save_offset(struct pipe_context
*pipe
,
1022 struct pipe_stream_output_target
*ptarg
,
1023 unsigned index
, bool *serialize
)
1025 struct nvc0_so_target
*targ
= nvc0_so_target(ptarg
);
1029 PUSH_SPACE(nvc0_context(pipe
)->base
.pushbuf
, 1);
1030 IMMED_NVC0(nvc0_context(pipe
)->base
.pushbuf
, NVC0_3D(SERIALIZE
), 0);
1032 NOUVEAU_DRV_STAT(nouveau_screen(pipe
->screen
), gpu_serialize_count
, 1);
1035 nvc0_query(targ
->pq
)->index
= index
;
1036 pipe
->end_query(pipe
, targ
->pq
);
1040 nvc0_so_target_destroy(struct pipe_context
*pipe
,
1041 struct pipe_stream_output_target
*ptarg
)
1043 struct nvc0_so_target
*targ
= nvc0_so_target(ptarg
);
1044 pipe
->destroy_query(pipe
, targ
->pq
);
1045 pipe_resource_reference(&targ
->pipe
.buffer
, NULL
);
1050 nvc0_set_transform_feedback_targets(struct pipe_context
*pipe
,
1051 unsigned num_targets
,
1052 struct pipe_stream_output_target
**targets
,
1053 const unsigned *offsets
)
1055 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
1057 bool serialize
= true;
1059 assert(num_targets
<= 4);
1061 for (i
= 0; i
< num_targets
; ++i
) {
1062 const bool changed
= nvc0
->tfbbuf
[i
] != targets
[i
];
1063 const bool append
= (offsets
[i
] == ((unsigned)-1));
1064 if (!changed
&& append
)
1066 nvc0
->tfbbuf_dirty
|= 1 << i
;
1068 if (nvc0
->tfbbuf
[i
] && changed
)
1069 nvc0_so_target_save_offset(pipe
, nvc0
->tfbbuf
[i
], i
, &serialize
);
1071 if (targets
[i
] && !append
)
1072 nvc0_so_target(targets
[i
])->clean
= true;
1074 pipe_so_target_reference(&nvc0
->tfbbuf
[i
], targets
[i
]);
1076 for (; i
< nvc0
->num_tfbbufs
; ++i
) {
1077 if (nvc0
->tfbbuf
[i
]) {
1078 nvc0
->tfbbuf_dirty
|= 1 << i
;
1079 nvc0_so_target_save_offset(pipe
, nvc0
->tfbbuf
[i
], i
, &serialize
);
1080 pipe_so_target_reference(&nvc0
->tfbbuf
[i
], NULL
);
1083 nvc0
->num_tfbbufs
= num_targets
;
1085 if (nvc0
->tfbbuf_dirty
) {
1086 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_TFB
);
1087 nvc0
->dirty_3d
|= NVC0_NEW_3D_TFB_TARGETS
;
1092 nvc0_bind_surfaces_range(struct nvc0_context
*nvc0
, const unsigned t
,
1093 unsigned start
, unsigned nr
,
1094 struct pipe_surface
**psurfaces
)
1096 const unsigned end
= start
+ nr
;
1097 const unsigned mask
= ((1 << nr
) - 1) << start
;
1101 for (i
= start
; i
< end
; ++i
) {
1102 const unsigned p
= i
- start
;
1104 nvc0
->surfaces_valid
[t
] |= (1 << i
);
1106 nvc0
->surfaces_valid
[t
] &= ~(1 << i
);
1107 pipe_surface_reference(&nvc0
->surfaces
[t
][i
], psurfaces
[p
]);
1110 for (i
= start
; i
< end
; ++i
)
1111 pipe_surface_reference(&nvc0
->surfaces
[t
][i
], NULL
);
1112 nvc0
->surfaces_valid
[t
] &= ~mask
;
1114 nvc0
->surfaces_dirty
[t
] |= mask
;
1117 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_SUF
);
1119 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_SUF
);
1123 nvc0_set_compute_resources(struct pipe_context
*pipe
,
1124 unsigned start
, unsigned nr
,
1125 struct pipe_surface
**resources
)
1127 nvc0_bind_surfaces_range(nvc0_context(pipe
), 1, start
, nr
, resources
);
1129 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_SURFACES
;
1133 nvc0_bind_images_range(struct nvc0_context
*nvc0
, const unsigned s
,
1134 unsigned start
, unsigned nr
,
1135 const struct pipe_image_view
*pimages
)
1137 const unsigned end
= start
+ nr
;
1144 for (i
= start
; i
< end
; ++i
) {
1145 struct pipe_image_view
*img
= &nvc0
->images
[s
][i
];
1146 const unsigned p
= i
- start
;
1148 if (img
->resource
== pimages
[p
].resource
&&
1149 img
->format
== pimages
[p
].format
&&
1150 img
->access
== pimages
[p
].access
) {
1151 if (img
->resource
== NULL
)
1153 if (img
->resource
->target
== PIPE_BUFFER
&&
1154 img
->u
.buf
.offset
== pimages
[p
].u
.buf
.offset
&&
1155 img
->u
.buf
.size
== pimages
[p
].u
.buf
.size
)
1157 if (img
->resource
->target
!= PIPE_BUFFER
&&
1158 img
->u
.tex
.first_layer
== pimages
[p
].u
.tex
.first_layer
&&
1159 img
->u
.tex
.last_layer
== pimages
[p
].u
.tex
.last_layer
&&
1160 img
->u
.tex
.level
== pimages
[p
].u
.tex
.level
)
1165 if (pimages
[p
].resource
)
1166 nvc0
->images_valid
[s
] |= (1 << i
);
1168 nvc0
->images_valid
[s
] &= ~(1 << i
);
1170 img
->format
= pimages
[p
].format
;
1171 img
->access
= pimages
[p
].access
;
1172 if (pimages
[p
].resource
&& pimages
[p
].resource
->target
== PIPE_BUFFER
)
1173 img
->u
.buf
= pimages
[p
].u
.buf
;
1175 img
->u
.tex
= pimages
[p
].u
.tex
;
1177 pipe_resource_reference(
1178 &img
->resource
, pimages
[p
].resource
);
1180 if (nvc0
->screen
->base
.class_3d
>= GM107_3D_CLASS
) {
1181 if (nvc0
->images_tic
[s
][i
]) {
1182 struct nv50_tic_entry
*old
=
1183 nv50_tic_entry(nvc0
->images_tic
[s
][i
]);
1184 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
1185 pipe_sampler_view_reference(&nvc0
->images_tic
[s
][i
], NULL
);
1188 nvc0
->images_tic
[s
][i
] =
1189 gm107_create_texture_view_from_image(&nvc0
->base
.pipe
,
1196 mask
= ((1 << nr
) - 1) << start
;
1197 if (!(nvc0
->images_valid
[s
] & mask
))
1199 for (i
= start
; i
< end
; ++i
) {
1200 pipe_resource_reference(&nvc0
->images
[s
][i
].resource
, NULL
);
1201 if (nvc0
->screen
->base
.class_3d
>= GM107_3D_CLASS
) {
1202 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->images_tic
[s
][i
]);
1204 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
1205 pipe_sampler_view_reference(&nvc0
->images_tic
[s
][i
], NULL
);
1209 nvc0
->images_valid
[s
] &= ~mask
;
1211 nvc0
->images_dirty
[s
] |= mask
;
1214 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_SUF
);
1216 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_SUF
);
1222 nvc0_set_shader_images(struct pipe_context
*pipe
,
1223 enum pipe_shader_type shader
,
1224 unsigned start
, unsigned nr
,
1225 const struct pipe_image_view
*images
)
1227 const unsigned s
= nvc0_shader_stage(shader
);
1228 if (!nvc0_bind_images_range(nvc0_context(pipe
), s
, start
, nr
, images
))
1232 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_SURFACES
;
1234 nvc0_context(pipe
)->dirty_3d
|= NVC0_NEW_3D_SURFACES
;
1238 nvc0_bind_buffers_range(struct nvc0_context
*nvc0
, const unsigned t
,
1239 unsigned start
, unsigned nr
,
1240 const struct pipe_shader_buffer
*pbuffers
)
1242 const unsigned end
= start
+ nr
;
1249 for (i
= start
; i
< end
; ++i
) {
1250 struct pipe_shader_buffer
*buf
= &nvc0
->buffers
[t
][i
];
1251 const unsigned p
= i
- start
;
1252 if (buf
->buffer
== pbuffers
[p
].buffer
&&
1253 buf
->buffer_offset
== pbuffers
[p
].buffer_offset
&&
1254 buf
->buffer_size
== pbuffers
[p
].buffer_size
)
1258 if (pbuffers
[p
].buffer
)
1259 nvc0
->buffers_valid
[t
] |= (1 << i
);
1261 nvc0
->buffers_valid
[t
] &= ~(1 << i
);
1262 buf
->buffer_offset
= pbuffers
[p
].buffer_offset
;
1263 buf
->buffer_size
= pbuffers
[p
].buffer_size
;
1264 pipe_resource_reference(&buf
->buffer
, pbuffers
[p
].buffer
);
1269 mask
= ((1 << nr
) - 1) << start
;
1270 if (!(nvc0
->buffers_valid
[t
] & mask
))
1272 for (i
= start
; i
< end
; ++i
)
1273 pipe_resource_reference(&nvc0
->buffers
[t
][i
].buffer
, NULL
);
1274 nvc0
->buffers_valid
[t
] &= ~mask
;
1276 nvc0
->buffers_dirty
[t
] |= mask
;
1279 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_BUF
);
1281 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_3D_BUF
);
1287 nvc0_set_shader_buffers(struct pipe_context
*pipe
,
1288 enum pipe_shader_type shader
,
1289 unsigned start
, unsigned nr
,
1290 const struct pipe_shader_buffer
*buffers
)
1292 const unsigned s
= nvc0_shader_stage(shader
);
1293 if (!nvc0_bind_buffers_range(nvc0_context(pipe
), s
, start
, nr
, buffers
))
1297 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_BUFFERS
;
1299 nvc0_context(pipe
)->dirty_3d
|= NVC0_NEW_3D_BUFFERS
;
1303 nvc0_set_global_handle(uint32_t *phandle
, struct pipe_resource
*res
)
1305 struct nv04_resource
*buf
= nv04_resource(res
);
1307 uint64_t limit
= (buf
->address
+ buf
->base
.width0
) - 1;
1308 if (limit
< (1ULL << 32)) {
1309 *phandle
= (uint32_t)buf
->address
;
1311 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1312 "resource not contained within 32-bit address space !\n");
1321 nvc0_set_global_bindings(struct pipe_context
*pipe
,
1322 unsigned start
, unsigned nr
,
1323 struct pipe_resource
**resources
,
1326 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
1327 struct pipe_resource
**ptr
;
1329 const unsigned end
= start
+ nr
;
1331 if (nvc0
->global_residents
.size
<= (end
* sizeof(struct pipe_resource
*))) {
1332 const unsigned old_size
= nvc0
->global_residents
.size
;
1333 const unsigned req_size
= end
* sizeof(struct pipe_resource
*);
1334 util_dynarray_resize(&nvc0
->global_residents
, req_size
);
1335 memset((uint8_t *)nvc0
->global_residents
.data
+ old_size
, 0,
1336 req_size
- old_size
);
1340 ptr
= util_dynarray_element(
1341 &nvc0
->global_residents
, struct pipe_resource
*, start
);
1342 for (i
= 0; i
< nr
; ++i
) {
1343 pipe_resource_reference(&ptr
[i
], resources
[i
]);
1344 nvc0_set_global_handle(handles
[i
], resources
[i
]);
1347 ptr
= util_dynarray_element(
1348 &nvc0
->global_residents
, struct pipe_resource
*, start
);
1349 for (i
= 0; i
< nr
; ++i
)
1350 pipe_resource_reference(&ptr
[i
], NULL
);
1353 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_GLOBAL
);
1355 nvc0
->dirty_cp
|= NVC0_NEW_CP_GLOBALS
;
1359 nvc0_init_state_functions(struct nvc0_context
*nvc0
)
1361 struct pipe_context
*pipe
= &nvc0
->base
.pipe
;
1363 pipe
->create_blend_state
= nvc0_blend_state_create
;
1364 pipe
->bind_blend_state
= nvc0_blend_state_bind
;
1365 pipe
->delete_blend_state
= nvc0_blend_state_delete
;
1367 pipe
->create_rasterizer_state
= nvc0_rasterizer_state_create
;
1368 pipe
->bind_rasterizer_state
= nvc0_rasterizer_state_bind
;
1369 pipe
->delete_rasterizer_state
= nvc0_rasterizer_state_delete
;
1371 pipe
->create_depth_stencil_alpha_state
= nvc0_zsa_state_create
;
1372 pipe
->bind_depth_stencil_alpha_state
= nvc0_zsa_state_bind
;
1373 pipe
->delete_depth_stencil_alpha_state
= nvc0_zsa_state_delete
;
1375 pipe
->create_sampler_state
= nv50_sampler_state_create
;
1376 pipe
->delete_sampler_state
= nvc0_sampler_state_delete
;
1377 pipe
->bind_sampler_states
= nvc0_bind_sampler_states
;
1379 pipe
->create_sampler_view
= nvc0_create_sampler_view
;
1380 pipe
->sampler_view_destroy
= nvc0_sampler_view_destroy
;
1381 pipe
->set_sampler_views
= nvc0_set_sampler_views
;
1383 pipe
->create_vs_state
= nvc0_vp_state_create
;
1384 pipe
->create_fs_state
= nvc0_fp_state_create
;
1385 pipe
->create_gs_state
= nvc0_gp_state_create
;
1386 pipe
->create_tcs_state
= nvc0_tcp_state_create
;
1387 pipe
->create_tes_state
= nvc0_tep_state_create
;
1388 pipe
->bind_vs_state
= nvc0_vp_state_bind
;
1389 pipe
->bind_fs_state
= nvc0_fp_state_bind
;
1390 pipe
->bind_gs_state
= nvc0_gp_state_bind
;
1391 pipe
->bind_tcs_state
= nvc0_tcp_state_bind
;
1392 pipe
->bind_tes_state
= nvc0_tep_state_bind
;
1393 pipe
->delete_vs_state
= nvc0_sp_state_delete
;
1394 pipe
->delete_fs_state
= nvc0_sp_state_delete
;
1395 pipe
->delete_gs_state
= nvc0_sp_state_delete
;
1396 pipe
->delete_tcs_state
= nvc0_sp_state_delete
;
1397 pipe
->delete_tes_state
= nvc0_sp_state_delete
;
1399 pipe
->create_compute_state
= nvc0_cp_state_create
;
1400 pipe
->bind_compute_state
= nvc0_cp_state_bind
;
1401 pipe
->delete_compute_state
= nvc0_sp_state_delete
;
1403 pipe
->set_blend_color
= nvc0_set_blend_color
;
1404 pipe
->set_stencil_ref
= nvc0_set_stencil_ref
;
1405 pipe
->set_clip_state
= nvc0_set_clip_state
;
1406 pipe
->set_sample_mask
= nvc0_set_sample_mask
;
1407 pipe
->set_min_samples
= nvc0_set_min_samples
;
1408 pipe
->set_constant_buffer
= nvc0_set_constant_buffer
;
1409 pipe
->set_framebuffer_state
= nvc0_set_framebuffer_state
;
1410 pipe
->set_polygon_stipple
= nvc0_set_polygon_stipple
;
1411 pipe
->set_scissor_states
= nvc0_set_scissor_states
;
1412 pipe
->set_viewport_states
= nvc0_set_viewport_states
;
1413 pipe
->set_window_rectangles
= nvc0_set_window_rectangles
;
1414 pipe
->set_tess_state
= nvc0_set_tess_state
;
1416 pipe
->create_vertex_elements_state
= nvc0_vertex_state_create
;
1417 pipe
->delete_vertex_elements_state
= nvc0_vertex_state_delete
;
1418 pipe
->bind_vertex_elements_state
= nvc0_vertex_state_bind
;
1420 pipe
->set_vertex_buffers
= nvc0_set_vertex_buffers
;
1422 pipe
->create_stream_output_target
= nvc0_so_target_create
;
1423 pipe
->stream_output_target_destroy
= nvc0_so_target_destroy
;
1424 pipe
->set_stream_output_targets
= nvc0_set_transform_feedback_targets
;
1426 pipe
->set_global_binding
= nvc0_set_global_bindings
;
1427 pipe
->set_compute_resources
= nvc0_set_compute_resources
;
1428 pipe
->set_shader_images
= nvc0_set_shader_images
;
1429 pipe
->set_shader_buffers
= nvc0_set_shader_buffers
;
1431 nvc0
->sample_mask
= ~0;
1432 nvc0
->min_samples
= 1;
1433 nvc0
->default_tess_outer
[0] =
1434 nvc0
->default_tess_outer
[1] =
1435 nvc0
->default_tess_outer
[2] =
1436 nvc0
->default_tess_outer
[3] = 1.0;
1437 nvc0
->default_tess_inner
[0] =
1438 nvc0
->default_tess_inner
[1] = 1.0;