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Revert "gallium: make handles of set_global_binding 64 bit"
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "tgsi/tgsi_parse.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_serialize.h"
32
33 #include "nvc0/nvc0_stateobj.h"
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_query_hw.h"
36
37 #include "nvc0/nvc0_3d.xml.h"
38
39 #include "nouveau_gldefs.h"
40
41 static inline uint32_t
42 nvc0_colormask(unsigned mask)
43 {
44 uint32_t ret = 0;
45
46 if (mask & PIPE_MASK_R)
47 ret |= 0x0001;
48 if (mask & PIPE_MASK_G)
49 ret |= 0x0010;
50 if (mask & PIPE_MASK_B)
51 ret |= 0x0100;
52 if (mask & PIPE_MASK_A)
53 ret |= 0x1000;
54
55 return ret;
56 }
57
58 #define NVC0_BLEND_FACTOR_CASE(a, b) \
59 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
60
61 static inline uint32_t
62 nvc0_blend_fac(unsigned factor)
63 {
64 switch (factor) {
65 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
66 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
67 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
68 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
69 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
70 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
71 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
72 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
74 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
75 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
76 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
77 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
78 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
79 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
80 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
82 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
83 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
84 default:
85 return NV50_BLEND_FACTOR_ZERO;
86 }
87 }
88
89 static void *
90 nvc0_blend_state_create(struct pipe_context *pipe,
91 const struct pipe_blend_state *cso)
92 {
93 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
94 int i;
95 int r; /* reference */
96 uint32_t ms;
97 uint8_t blend_en = 0;
98 bool indep_masks = false;
99 bool indep_funcs = false;
100
101 so->pipe = *cso;
102
103 /* check which states actually have differing values */
104 if (cso->independent_blend_enable) {
105 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
106 blend_en |= 1 << r;
107 for (i = r + 1; i < 8; ++i) {
108 if (!cso->rt[i].blend_enable)
109 continue;
110 blend_en |= 1 << i;
111 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
112 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
113 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
114 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
115 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
116 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
117 indep_funcs = true;
118 break;
119 }
120 }
121 for (; i < 8; ++i)
122 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
123
124 for (i = 1; i < 8; ++i) {
125 if (cso->rt[i].colormask != cso->rt[0].colormask) {
126 indep_masks = true;
127 break;
128 }
129 }
130 } else {
131 r = 0;
132 if (cso->rt[0].blend_enable)
133 blend_en = 0xff;
134 }
135
136 if (cso->logicop_enable) {
137 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
138 SB_DATA (so, 1);
139 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
140
141 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
142 } else {
143 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
144
145 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
146 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
147 if (indep_funcs) {
148 for (i = 0; i < 8; ++i) {
149 if (cso->rt[i].blend_enable) {
150 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
154 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
155 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
156 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
157 }
158 }
159 } else
160 if (blend_en) {
161 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
164 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
165 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
166 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
167 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
168 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
169 }
170
171 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
172 if (indep_masks) {
173 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
174 for (i = 0; i < 8; ++i)
175 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
176 } else {
177 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
178 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
179 }
180 }
181
182 ms = 0;
183 if (cso->alpha_to_coverage)
184 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
185 if (cso->alpha_to_one)
186 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
187
188 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
189 SB_DATA (so, ms);
190
191 assert(so->size <= ARRAY_SIZE(so->state));
192 return so;
193 }
194
195 static void
196 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
197 {
198 struct nvc0_context *nvc0 = nvc0_context(pipe);
199
200 nvc0->blend = hwcso;
201 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
202 }
203
204 static void
205 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
206 {
207 FREE(hwcso);
208 }
209
210 /* NOTE: ignoring line_last_pixel */
211 static void *
212 nvc0_rasterizer_state_create(struct pipe_context *pipe,
213 const struct pipe_rasterizer_state *cso)
214 {
215 struct nvc0_rasterizer_stateobj *so;
216 uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
217 uint32_t reg;
218
219 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
220 if (!so)
221 return NULL;
222 so->pipe = *cso;
223
224 /* Scissor enables are handled in scissor state, we will not want to
225 * always emit 16 commands, one for each scissor rectangle, here.
226 */
227
228 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
229 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
230
231 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
232 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
233 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
234
235 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
236
237 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
238 /* On GM20x+, LINE_WIDTH_SMOOTH controls both aliased and smooth
239 * rendering and LINE_WIDTH_ALIASED seems to be ignored
240 */
241 if (cso->line_smooth || cso->multisample || class_3d >= GM200_3D_CLASS)
242 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
243 else
244 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
245 SB_DATA (so, fui(cso->line_width));
246
247 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
248 if (cso->line_stipple_enable) {
249 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
250 SB_DATA (so, (cso->line_stipple_pattern << 8) |
251 cso->line_stipple_factor);
252
253 }
254
255 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
256 if (!cso->point_size_per_vertex) {
257 SB_BEGIN_3D(so, POINT_SIZE, 1);
258 SB_DATA (so, fui(cso->point_size));
259 }
260
261 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
262 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
263 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
264
265 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
266 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
267 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
268 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
269
270 if (class_3d >= GM200_3D_CLASS) {
271 SB_IMMED_3D(so, FILL_RECTANGLE,
272 cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
273 NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
274 }
275
276 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
277 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
278 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
279 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
280 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
281
282 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
283 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
284 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
285 NVC0_3D_FRONT_FACE_CW);
286 switch (cso->cull_face) {
287 case PIPE_FACE_FRONT_AND_BACK:
288 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
289 break;
290 case PIPE_FACE_FRONT:
291 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
292 break;
293 case PIPE_FACE_BACK:
294 default:
295 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
296 break;
297 }
298
299 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
300 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
301 SB_DATA (so, cso->offset_point);
302 SB_DATA (so, cso->offset_line);
303 SB_DATA (so, cso->offset_tri);
304
305 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
306 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
307 SB_DATA (so, fui(cso->offset_scale));
308 if (!cso->offset_units_unscaled) {
309 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
310 SB_DATA (so, fui(cso->offset_units * 2.0f));
311 }
312 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
313 SB_DATA (so, fui(cso->offset_clamp));
314 }
315
316 if (cso->depth_clip_near)
317 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
318 else
319 reg =
320 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
321 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
322 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
323 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
324
325 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
326 SB_DATA (so, reg);
327
328 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
329
330 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
331
332 if (class_3d >= GM200_3D_CLASS) {
333 if (cso->conservative_raster_mode != PIPE_CONSERVATIVE_RASTER_OFF) {
334 bool post_snap = cso->conservative_raster_mode ==
335 PIPE_CONSERVATIVE_RASTER_POST_SNAP;
336 uint32_t state = cso->subpixel_precision_x;
337 state |= cso->subpixel_precision_y << 4;
338 state |= (uint32_t)(cso->conservative_raster_dilate * 4) << 8;
339 state |= (post_snap || class_3d < GP100_3D_CLASS) ? 1 << 10 : 0;
340 SB_IMMED_3D(so, MACRO_CONSERVATIVE_RASTER_STATE, state);
341 } else {
342 SB_IMMED_3D(so, CONSERVATIVE_RASTER, 0);
343 }
344 }
345
346 assert(so->size <= ARRAY_SIZE(so->state));
347 return (void *)so;
348 }
349
350 static void
351 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
352 {
353 struct nvc0_context *nvc0 = nvc0_context(pipe);
354
355 nvc0->rast = hwcso;
356 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
357 }
358
359 static void
360 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
361 {
362 FREE(hwcso);
363 }
364
365 static void *
366 nvc0_zsa_state_create(struct pipe_context *pipe,
367 const struct pipe_depth_stencil_alpha_state *cso)
368 {
369 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
370
371 so->pipe = *cso;
372
373 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
374 if (cso->depth.enabled) {
375 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
376 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
377 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
378 }
379
380 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
381 if (cso->depth.bounds_test) {
382 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
383 SB_DATA (so, fui(cso->depth.bounds_min));
384 SB_DATA (so, fui(cso->depth.bounds_max));
385 }
386
387 if (cso->stencil[0].enabled) {
388 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
389 SB_DATA (so, 1);
390 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
391 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
392 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
393 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
394 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
395 SB_DATA (so, cso->stencil[0].valuemask);
396 SB_DATA (so, cso->stencil[0].writemask);
397 } else {
398 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
399 }
400
401 if (cso->stencil[1].enabled) {
402 assert(cso->stencil[0].enabled);
403 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
404 SB_DATA (so, 1);
405 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
406 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
407 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
408 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
409 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
410 SB_DATA (so, cso->stencil[1].writemask);
411 SB_DATA (so, cso->stencil[1].valuemask);
412 } else
413 if (cso->stencil[0].enabled) {
414 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
415 }
416
417 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
418 if (cso->alpha.enabled) {
419 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
420 SB_DATA (so, fui(cso->alpha.ref_value));
421 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
422 }
423
424 assert(so->size <= ARRAY_SIZE(so->state));
425 return (void *)so;
426 }
427
428 static void
429 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
430 {
431 struct nvc0_context *nvc0 = nvc0_context(pipe);
432
433 nvc0->zsa = hwcso;
434 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
435 }
436
437 static void
438 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
439 {
440 FREE(hwcso);
441 }
442
443 /* ====================== SAMPLERS AND TEXTURES ================================
444 */
445
446 #define NV50_TSC_WRAP_CASE(n) \
447 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
448
449 static void
450 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
451 {
452 unsigned s, i;
453
454 for (s = 0; s < 6; ++s)
455 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
456 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
457 nvc0_context(pipe)->samplers[s][i] = NULL;
458
459 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
460
461 FREE(hwcso);
462 }
463
464 static inline void
465 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
466 unsigned s,
467 unsigned nr, void **hwcsos)
468 {
469 unsigned highest_found = 0;
470 unsigned i;
471
472 for (i = 0; i < nr; ++i) {
473 struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
474 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
475
476 if (hwcso)
477 highest_found = i;
478
479 if (hwcso == old)
480 continue;
481 nvc0->samplers_dirty[s] |= 1 << i;
482
483 nvc0->samplers[s][i] = hwcso;
484 if (old)
485 nvc0_screen_tsc_unlock(nvc0->screen, old);
486 }
487 if (nr >= nvc0->num_samplers[s])
488 nvc0->num_samplers[s] = highest_found + 1;
489 }
490
491 static void
492 nvc0_bind_sampler_states(struct pipe_context *pipe,
493 enum pipe_shader_type shader,
494 unsigned start, unsigned nr, void **samplers)
495 {
496 const unsigned s = nvc0_shader_stage(shader);
497
498 assert(start == 0);
499 nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
500
501 if (s == 5)
502 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
503 else
504 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
505 }
506
507
508 /* NOTE: only called when not referenced anywhere, won't be bound */
509 static void
510 nvc0_sampler_view_destroy(struct pipe_context *pipe,
511 struct pipe_sampler_view *view)
512 {
513 pipe_resource_reference(&view->texture, NULL);
514
515 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
516
517 FREE(nv50_tic_entry(view));
518 }
519
520 static inline void
521 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
522 unsigned nr,
523 struct pipe_sampler_view **views)
524 {
525 unsigned i;
526
527 for (i = 0; i < nr; ++i) {
528 struct pipe_sampler_view *view = views ? views[i] : NULL;
529 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
530
531 if (view == nvc0->textures[s][i])
532 continue;
533 nvc0->textures_dirty[s] |= 1 << i;
534
535 if (view && view->texture) {
536 struct pipe_resource *res = view->texture;
537 if (res->target == PIPE_BUFFER &&
538 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
539 nvc0->textures_coherent[s] |= 1 << i;
540 else
541 nvc0->textures_coherent[s] &= ~(1 << i);
542 } else {
543 nvc0->textures_coherent[s] &= ~(1 << i);
544 }
545
546 if (old) {
547 if (s == 5)
548 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
549 else
550 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
551 nvc0_screen_tic_unlock(nvc0->screen, old);
552 }
553
554 pipe_sampler_view_reference(&nvc0->textures[s][i], view);
555 }
556
557 for (i = nr; i < nvc0->num_textures[s]; ++i) {
558 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
559 if (old) {
560 if (s == 5)
561 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
562 else
563 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
564 nvc0_screen_tic_unlock(nvc0->screen, old);
565 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
566 }
567 }
568
569 nvc0->num_textures[s] = nr;
570 }
571
572 static void
573 nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
574 unsigned start, unsigned nr,
575 struct pipe_sampler_view **views)
576 {
577 const unsigned s = nvc0_shader_stage(shader);
578
579 assert(start == 0);
580 nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, views);
581
582 if (s == 5)
583 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
584 else
585 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
586 }
587
588 /* ============================= SHADERS =======================================
589 */
590
591 static void *
592 nvc0_sp_state_create(struct pipe_context *pipe,
593 const struct pipe_shader_state *cso, unsigned type)
594 {
595 struct nvc0_program *prog;
596
597 prog = CALLOC_STRUCT(nvc0_program);
598 if (!prog)
599 return NULL;
600
601 prog->type = type;
602 prog->pipe.type = cso->type;
603
604 switch(cso->type) {
605 case PIPE_SHADER_IR_TGSI:
606 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
607 break;
608 case PIPE_SHADER_IR_NIR:
609 prog->pipe.ir.nir = cso->ir.nir;
610 break;
611 default:
612 assert(!"unsupported IR!");
613 free(prog);
614 return NULL;
615 }
616
617 if (cso->stream_output.num_outputs)
618 prog->pipe.stream_output = cso->stream_output;
619
620 prog->translated = nvc0_program_translate(
621 prog, nvc0_context(pipe)->screen->base.device->chipset,
622 &nouveau_context(pipe)->debug);
623
624 return (void *)prog;
625 }
626
627 static void
628 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
629 {
630 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
631
632 nvc0_program_destroy(nvc0_context(pipe), prog);
633
634 if (prog->pipe.type == PIPE_SHADER_IR_TGSI)
635 FREE((void *)prog->pipe.tokens);
636 else if (prog->pipe.type == PIPE_SHADER_IR_NIR)
637 ralloc_free(prog->pipe.ir.nir);
638 FREE(prog);
639 }
640
641 static void *
642 nvc0_vp_state_create(struct pipe_context *pipe,
643 const struct pipe_shader_state *cso)
644 {
645 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
646 }
647
648 static void
649 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
650 {
651 struct nvc0_context *nvc0 = nvc0_context(pipe);
652
653 nvc0->vertprog = hwcso;
654 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
655 }
656
657 static void *
658 nvc0_fp_state_create(struct pipe_context *pipe,
659 const struct pipe_shader_state *cso)
660 {
661 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
662 }
663
664 static void
665 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
666 {
667 struct nvc0_context *nvc0 = nvc0_context(pipe);
668
669 nvc0->fragprog = hwcso;
670 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
671 }
672
673 static void *
674 nvc0_gp_state_create(struct pipe_context *pipe,
675 const struct pipe_shader_state *cso)
676 {
677 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
678 }
679
680 static void
681 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
682 {
683 struct nvc0_context *nvc0 = nvc0_context(pipe);
684
685 nvc0->gmtyprog = hwcso;
686 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
687 }
688
689 static void *
690 nvc0_tcp_state_create(struct pipe_context *pipe,
691 const struct pipe_shader_state *cso)
692 {
693 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
694 }
695
696 static void
697 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
698 {
699 struct nvc0_context *nvc0 = nvc0_context(pipe);
700
701 nvc0->tctlprog = hwcso;
702 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
703 }
704
705 static void *
706 nvc0_tep_state_create(struct pipe_context *pipe,
707 const struct pipe_shader_state *cso)
708 {
709 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
710 }
711
712 static void
713 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
714 {
715 struct nvc0_context *nvc0 = nvc0_context(pipe);
716
717 nvc0->tevlprog = hwcso;
718 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
719 }
720
721 static void *
722 nvc0_cp_state_create(struct pipe_context *pipe,
723 const struct pipe_compute_state *cso)
724 {
725 struct nvc0_program *prog;
726
727 prog = CALLOC_STRUCT(nvc0_program);
728 if (!prog)
729 return NULL;
730 prog->type = PIPE_SHADER_COMPUTE;
731 prog->pipe.type = cso->ir_type;
732
733 prog->cp.smem_size = cso->req_local_mem;
734 prog->cp.lmem_size = cso->req_private_mem;
735 prog->parm_size = cso->req_input_mem;
736
737 switch(cso->ir_type) {
738 case PIPE_SHADER_IR_TGSI:
739 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
740 break;
741 case PIPE_SHADER_IR_NIR:
742 prog->pipe.ir.nir = (nir_shader *)cso->prog;
743 break;
744 case PIPE_SHADER_IR_NIR_SERIALIZED: {
745 struct blob_reader reader;
746 const struct pipe_binary_program_header *hdr = cso->prog;
747
748 blob_reader_init(&reader, hdr->blob, hdr->num_bytes);
749 prog->pipe.ir.nir = nir_deserialize(NULL, pipe->screen->get_compiler_options(pipe->screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE), &reader);
750 prog->pipe.type = PIPE_SHADER_IR_NIR;
751 break;
752 }
753 default:
754 assert(!"unsupported IR!");
755 free(prog);
756 return NULL;
757 }
758
759 prog->translated = nvc0_program_translate(
760 prog, nvc0_context(pipe)->screen->base.device->chipset,
761 &nouveau_context(pipe)->debug);
762
763 return (void *)prog;
764 }
765
766 static void
767 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
768 {
769 struct nvc0_context *nvc0 = nvc0_context(pipe);
770
771 nvc0->compprog = hwcso;
772 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
773 }
774
775 static void
776 nvc0_set_constant_buffer(struct pipe_context *pipe,
777 enum pipe_shader_type shader, uint index,
778 const struct pipe_constant_buffer *cb)
779 {
780 struct nvc0_context *nvc0 = nvc0_context(pipe);
781 struct pipe_resource *res = cb ? cb->buffer : NULL;
782 const unsigned s = nvc0_shader_stage(shader);
783 const unsigned i = index;
784
785 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
786 if (nvc0->constbuf[s][i].user)
787 nvc0->constbuf[s][i].u.buf = NULL;
788 else
789 if (nvc0->constbuf[s][i].u.buf)
790 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
791
792 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
793 } else {
794 if (nvc0->constbuf[s][i].user)
795 nvc0->constbuf[s][i].u.buf = NULL;
796 else
797 if (nvc0->constbuf[s][i].u.buf)
798 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
799
800 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
801 }
802 nvc0->constbuf_dirty[s] |= 1 << i;
803
804 if (nvc0->constbuf[s][i].u.buf)
805 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
806 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
807
808 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
809 if (nvc0->constbuf[s][i].user) {
810 nvc0->constbuf[s][i].u.data = cb->user_buffer;
811 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
812 nvc0->constbuf_valid[s] |= 1 << i;
813 nvc0->constbuf_coherent[s] &= ~(1 << i);
814 } else
815 if (cb) {
816 nvc0->constbuf[s][i].offset = cb->buffer_offset;
817 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
818 nvc0->constbuf_valid[s] |= 1 << i;
819 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
820 nvc0->constbuf_coherent[s] |= 1 << i;
821 else
822 nvc0->constbuf_coherent[s] &= ~(1 << i);
823 }
824 else {
825 nvc0->constbuf_valid[s] &= ~(1 << i);
826 nvc0->constbuf_coherent[s] &= ~(1 << i);
827 }
828 }
829
830 /* =============================================================================
831 */
832
833 static void
834 nvc0_set_blend_color(struct pipe_context *pipe,
835 const struct pipe_blend_color *bcol)
836 {
837 struct nvc0_context *nvc0 = nvc0_context(pipe);
838
839 nvc0->blend_colour = *bcol;
840 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
841 }
842
843 static void
844 nvc0_set_stencil_ref(struct pipe_context *pipe,
845 const struct pipe_stencil_ref *sr)
846 {
847 struct nvc0_context *nvc0 = nvc0_context(pipe);
848
849 nvc0->stencil_ref = *sr;
850 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
851 }
852
853 static void
854 nvc0_set_clip_state(struct pipe_context *pipe,
855 const struct pipe_clip_state *clip)
856 {
857 struct nvc0_context *nvc0 = nvc0_context(pipe);
858
859 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
860
861 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
862 }
863
864 static void
865 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
866 {
867 struct nvc0_context *nvc0 = nvc0_context(pipe);
868
869 nvc0->sample_mask = sample_mask;
870 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
871 }
872
873 static void
874 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
875 {
876 struct nvc0_context *nvc0 = nvc0_context(pipe);
877
878 if (nvc0->min_samples != min_samples) {
879 nvc0->min_samples = min_samples;
880 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
881 }
882 }
883
884 static void
885 nvc0_set_framebuffer_state(struct pipe_context *pipe,
886 const struct pipe_framebuffer_state *fb)
887 {
888 struct nvc0_context *nvc0 = nvc0_context(pipe);
889
890 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
891
892 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
893
894 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SAMPLE_LOCATIONS |
895 NVC0_NEW_3D_TEXTURES;
896 nvc0->dirty_cp |= NVC0_NEW_CP_TEXTURES;
897 }
898
899 static void
900 nvc0_set_sample_locations(struct pipe_context *pipe,
901 size_t size, const uint8_t *locations)
902 {
903 struct nvc0_context *nvc0 = nvc0_context(pipe);
904
905 nvc0->sample_locations_enabled = size && locations;
906 if (size > sizeof(nvc0->sample_locations))
907 size = sizeof(nvc0->sample_locations);
908 memcpy(nvc0->sample_locations, locations, size);
909
910 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_LOCATIONS;
911 }
912
913 static void
914 nvc0_set_polygon_stipple(struct pipe_context *pipe,
915 const struct pipe_poly_stipple *stipple)
916 {
917 struct nvc0_context *nvc0 = nvc0_context(pipe);
918
919 nvc0->stipple = *stipple;
920 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
921 }
922
923 static void
924 nvc0_set_scissor_states(struct pipe_context *pipe,
925 unsigned start_slot,
926 unsigned num_scissors,
927 const struct pipe_scissor_state *scissor)
928 {
929 struct nvc0_context *nvc0 = nvc0_context(pipe);
930 int i;
931
932 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
933 for (i = 0; i < num_scissors; i++) {
934 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
935 continue;
936 nvc0->scissors[start_slot + i] = scissor[i];
937 nvc0->scissors_dirty |= 1 << (start_slot + i);
938 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
939 }
940 }
941
942 static void
943 nvc0_set_viewport_states(struct pipe_context *pipe,
944 unsigned start_slot,
945 unsigned num_viewports,
946 const struct pipe_viewport_state *vpt)
947 {
948 struct nvc0_context *nvc0 = nvc0_context(pipe);
949 int i;
950
951 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
952 for (i = 0; i < num_viewports; i++) {
953 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
954 continue;
955 nvc0->viewports[start_slot + i] = vpt[i];
956 nvc0->viewports_dirty |= 1 << (start_slot + i);
957 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
958 }
959
960 }
961
962 static void
963 nvc0_set_window_rectangles(struct pipe_context *pipe,
964 bool include,
965 unsigned num_rectangles,
966 const struct pipe_scissor_state *rectangles)
967 {
968 struct nvc0_context *nvc0 = nvc0_context(pipe);
969
970 nvc0->window_rect.inclusive = include;
971 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
972 memcpy(nvc0->window_rect.rect, rectangles,
973 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
974
975 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
976 }
977
978 static void
979 nvc0_set_tess_state(struct pipe_context *pipe,
980 const float default_tess_outer[4],
981 const float default_tess_inner[2])
982 {
983 struct nvc0_context *nvc0 = nvc0_context(pipe);
984
985 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
986 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
987 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
988 }
989
990 static void
991 nvc0_set_vertex_buffers(struct pipe_context *pipe,
992 unsigned start_slot, unsigned count,
993 const struct pipe_vertex_buffer *vb)
994 {
995 struct nvc0_context *nvc0 = nvc0_context(pipe);
996 unsigned i;
997
998 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
999 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
1000
1001 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1002 start_slot, count);
1003
1004 if (!vb) {
1005 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1006 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1007 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
1008 return;
1009 }
1010
1011 for (i = 0; i < count; ++i) {
1012 unsigned dst_index = start_slot + i;
1013
1014 if (vb[i].is_user_buffer) {
1015 nvc0->vbo_user |= 1 << dst_index;
1016 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1017 nvc0->constant_vbos |= 1 << dst_index;
1018 else
1019 nvc0->constant_vbos &= ~(1 << dst_index);
1020 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1021 } else {
1022 nvc0->vbo_user &= ~(1 << dst_index);
1023 nvc0->constant_vbos &= ~(1 << dst_index);
1024
1025 if (vb[i].buffer.resource &&
1026 vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1027 nvc0->vtxbufs_coherent |= (1 << dst_index);
1028 else
1029 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1030 }
1031 }
1032 }
1033
1034 static void
1035 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1036 {
1037 struct nvc0_context *nvc0 = nvc0_context(pipe);
1038
1039 nvc0->vertex = hwcso;
1040 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1041 }
1042
1043 static struct pipe_stream_output_target *
1044 nvc0_so_target_create(struct pipe_context *pipe,
1045 struct pipe_resource *res,
1046 unsigned offset, unsigned size)
1047 {
1048 struct nv04_resource *buf = (struct nv04_resource *)res;
1049 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1050 if (!targ)
1051 return NULL;
1052
1053 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1054 if (!targ->pq) {
1055 FREE(targ);
1056 return NULL;
1057 }
1058 targ->clean = true;
1059
1060 targ->pipe.buffer_size = size;
1061 targ->pipe.buffer_offset = offset;
1062 targ->pipe.context = pipe;
1063 targ->pipe.buffer = NULL;
1064 pipe_resource_reference(&targ->pipe.buffer, res);
1065 pipe_reference_init(&targ->pipe.reference, 1);
1066
1067 assert(buf->base.target == PIPE_BUFFER);
1068 util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
1069
1070 return &targ->pipe;
1071 }
1072
1073 static void
1074 nvc0_so_target_save_offset(struct pipe_context *pipe,
1075 struct pipe_stream_output_target *ptarg,
1076 unsigned index, bool *serialize)
1077 {
1078 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1079
1080 if (*serialize) {
1081 *serialize = false;
1082 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1083 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1084
1085 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1086 }
1087
1088 nvc0_query(targ->pq)->index = index;
1089 pipe->end_query(pipe, targ->pq);
1090 }
1091
1092 static void
1093 nvc0_so_target_destroy(struct pipe_context *pipe,
1094 struct pipe_stream_output_target *ptarg)
1095 {
1096 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1097 pipe->destroy_query(pipe, targ->pq);
1098 pipe_resource_reference(&targ->pipe.buffer, NULL);
1099 FREE(targ);
1100 }
1101
1102 static void
1103 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1104 unsigned num_targets,
1105 struct pipe_stream_output_target **targets,
1106 const unsigned *offsets)
1107 {
1108 struct nvc0_context *nvc0 = nvc0_context(pipe);
1109 unsigned i;
1110 bool serialize = true;
1111
1112 assert(num_targets <= 4);
1113
1114 for (i = 0; i < num_targets; ++i) {
1115 const bool changed = nvc0->tfbbuf[i] != targets[i];
1116 const bool append = (offsets[i] == ((unsigned)-1));
1117 if (!changed && append)
1118 continue;
1119 nvc0->tfbbuf_dirty |= 1 << i;
1120
1121 if (nvc0->tfbbuf[i] && changed)
1122 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1123
1124 if (targets[i] && !append)
1125 nvc0_so_target(targets[i])->clean = true;
1126
1127 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1128 }
1129 for (; i < nvc0->num_tfbbufs; ++i) {
1130 if (nvc0->tfbbuf[i]) {
1131 nvc0->tfbbuf_dirty |= 1 << i;
1132 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1133 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1134 }
1135 }
1136 nvc0->num_tfbbufs = num_targets;
1137
1138 if (nvc0->tfbbuf_dirty) {
1139 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1140 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1141 }
1142 }
1143
1144 static void
1145 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1146 unsigned start, unsigned nr,
1147 struct pipe_surface **psurfaces)
1148 {
1149 const unsigned end = start + nr;
1150 const unsigned mask = ((1 << nr) - 1) << start;
1151 unsigned i;
1152
1153 if (psurfaces) {
1154 for (i = start; i < end; ++i) {
1155 const unsigned p = i - start;
1156 if (psurfaces[p])
1157 nvc0->surfaces_valid[t] |= (1 << i);
1158 else
1159 nvc0->surfaces_valid[t] &= ~(1 << i);
1160 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1161 }
1162 } else {
1163 for (i = start; i < end; ++i)
1164 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1165 nvc0->surfaces_valid[t] &= ~mask;
1166 }
1167 nvc0->surfaces_dirty[t] |= mask;
1168
1169 if (t == 0)
1170 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1171 else
1172 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1173 }
1174
1175 static void
1176 nvc0_set_compute_resources(struct pipe_context *pipe,
1177 unsigned start, unsigned nr,
1178 struct pipe_surface **resources)
1179 {
1180 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1181
1182 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1183 }
1184
1185 static bool
1186 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1187 unsigned start, unsigned nr,
1188 const struct pipe_image_view *pimages)
1189 {
1190 const unsigned end = start + nr;
1191 unsigned mask = 0;
1192 unsigned i;
1193
1194 assert(s < 6);
1195
1196 if (pimages) {
1197 for (i = start; i < end; ++i) {
1198 struct pipe_image_view *img = &nvc0->images[s][i];
1199 const unsigned p = i - start;
1200
1201 if (img->resource == pimages[p].resource &&
1202 img->format == pimages[p].format &&
1203 img->access == pimages[p].access) {
1204 if (img->resource == NULL)
1205 continue;
1206 if (img->resource->target == PIPE_BUFFER &&
1207 img->u.buf.offset == pimages[p].u.buf.offset &&
1208 img->u.buf.size == pimages[p].u.buf.size)
1209 continue;
1210 if (img->resource->target != PIPE_BUFFER &&
1211 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1212 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1213 img->u.tex.level == pimages[p].u.tex.level)
1214 continue;
1215 }
1216
1217 mask |= (1 << i);
1218 if (pimages[p].resource)
1219 nvc0->images_valid[s] |= (1 << i);
1220 else
1221 nvc0->images_valid[s] &= ~(1 << i);
1222
1223 img->format = pimages[p].format;
1224 img->access = pimages[p].access;
1225 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1226 img->u.buf = pimages[p].u.buf;
1227 else
1228 img->u.tex = pimages[p].u.tex;
1229
1230 pipe_resource_reference(
1231 &img->resource, pimages[p].resource);
1232
1233 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1234 if (nvc0->images_tic[s][i]) {
1235 struct nv50_tic_entry *old =
1236 nv50_tic_entry(nvc0->images_tic[s][i]);
1237 nvc0_screen_tic_unlock(nvc0->screen, old);
1238 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1239 }
1240
1241 nvc0->images_tic[s][i] =
1242 gm107_create_texture_view_from_image(&nvc0->base.pipe,
1243 &pimages[p]);
1244 }
1245 }
1246 if (!mask)
1247 return false;
1248 } else {
1249 mask = ((1 << nr) - 1) << start;
1250 if (!(nvc0->images_valid[s] & mask))
1251 return false;
1252 for (i = start; i < end; ++i) {
1253 pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1254 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1255 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1256 if (old) {
1257 nvc0_screen_tic_unlock(nvc0->screen, old);
1258 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1259 }
1260 }
1261 }
1262 nvc0->images_valid[s] &= ~mask;
1263 }
1264 nvc0->images_dirty[s] |= mask;
1265
1266 if (s == 5)
1267 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1268 else
1269 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1270
1271 return true;
1272 }
1273
1274 static void
1275 nvc0_set_shader_images(struct pipe_context *pipe,
1276 enum pipe_shader_type shader,
1277 unsigned start, unsigned nr,
1278 const struct pipe_image_view *images)
1279 {
1280 const unsigned s = nvc0_shader_stage(shader);
1281 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1282 return;
1283
1284 if (s == 5)
1285 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1286 else
1287 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1288 }
1289
1290 static bool
1291 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1292 unsigned start, unsigned nr,
1293 const struct pipe_shader_buffer *pbuffers)
1294 {
1295 const unsigned end = start + nr;
1296 unsigned mask = 0;
1297 unsigned i;
1298
1299 assert(t < 6);
1300
1301 if (pbuffers) {
1302 for (i = start; i < end; ++i) {
1303 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1304 const unsigned p = i - start;
1305 if (buf->buffer == pbuffers[p].buffer &&
1306 buf->buffer_offset == pbuffers[p].buffer_offset &&
1307 buf->buffer_size == pbuffers[p].buffer_size)
1308 continue;
1309
1310 mask |= (1 << i);
1311 if (pbuffers[p].buffer)
1312 nvc0->buffers_valid[t] |= (1 << i);
1313 else
1314 nvc0->buffers_valid[t] &= ~(1 << i);
1315 buf->buffer_offset = pbuffers[p].buffer_offset;
1316 buf->buffer_size = pbuffers[p].buffer_size;
1317 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1318 }
1319 if (!mask)
1320 return false;
1321 } else {
1322 mask = ((1 << nr) - 1) << start;
1323 if (!(nvc0->buffers_valid[t] & mask))
1324 return false;
1325 for (i = start; i < end; ++i)
1326 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1327 nvc0->buffers_valid[t] &= ~mask;
1328 }
1329 nvc0->buffers_dirty[t] |= mask;
1330
1331 if (t == 5)
1332 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1333 else
1334 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1335
1336 return true;
1337 }
1338
1339 static void
1340 nvc0_set_shader_buffers(struct pipe_context *pipe,
1341 enum pipe_shader_type shader,
1342 unsigned start, unsigned nr,
1343 const struct pipe_shader_buffer *buffers,
1344 unsigned writable_bitmask)
1345 {
1346 const unsigned s = nvc0_shader_stage(shader);
1347 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1348 return;
1349
1350 if (s == 5)
1351 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1352 else
1353 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1354 }
1355
1356 static inline void
1357 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1358 {
1359 struct nv04_resource *buf = nv04_resource(res);
1360 if (buf) {
1361 uint64_t limit = (buf->address + buf->base.width0) - 1;
1362 if (limit < (1ULL << 32)) {
1363 *phandle = (uint32_t)buf->address;
1364 } else {
1365 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1366 "resource not contained within 32-bit address space !\n");
1367 *phandle = 0;
1368 }
1369 } else {
1370 *phandle = 0;
1371 }
1372 }
1373
1374 static void
1375 nvc0_set_global_bindings(struct pipe_context *pipe,
1376 unsigned start, unsigned nr,
1377 struct pipe_resource **resources,
1378 uint32_t **handles)
1379 {
1380 struct nvc0_context *nvc0 = nvc0_context(pipe);
1381 struct pipe_resource **ptr;
1382 unsigned i;
1383 const unsigned end = start + nr;
1384
1385 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1386 const unsigned old_size = nvc0->global_residents.size;
1387 util_dynarray_resize(&nvc0->global_residents, struct pipe_resource *, end);
1388 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1389 nvc0->global_residents.size - old_size);
1390 }
1391
1392 if (resources) {
1393 ptr = util_dynarray_element(
1394 &nvc0->global_residents, struct pipe_resource *, start);
1395 for (i = 0; i < nr; ++i) {
1396 pipe_resource_reference(&ptr[i], resources[i]);
1397 nvc0_set_global_handle(handles[i], resources[i]);
1398 }
1399 } else {
1400 ptr = util_dynarray_element(
1401 &nvc0->global_residents, struct pipe_resource *, start);
1402 for (i = 0; i < nr; ++i)
1403 pipe_resource_reference(&ptr[i], NULL);
1404 }
1405
1406 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1407
1408 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1409 }
1410
1411 void
1412 nvc0_init_state_functions(struct nvc0_context *nvc0)
1413 {
1414 struct pipe_context *pipe = &nvc0->base.pipe;
1415
1416 pipe->create_blend_state = nvc0_blend_state_create;
1417 pipe->bind_blend_state = nvc0_blend_state_bind;
1418 pipe->delete_blend_state = nvc0_blend_state_delete;
1419
1420 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1421 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1422 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1423
1424 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1425 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1426 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1427
1428 pipe->create_sampler_state = nv50_sampler_state_create;
1429 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1430 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1431
1432 pipe->create_sampler_view = nvc0_create_sampler_view;
1433 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1434 pipe->set_sampler_views = nvc0_set_sampler_views;
1435
1436 pipe->create_vs_state = nvc0_vp_state_create;
1437 pipe->create_fs_state = nvc0_fp_state_create;
1438 pipe->create_gs_state = nvc0_gp_state_create;
1439 pipe->create_tcs_state = nvc0_tcp_state_create;
1440 pipe->create_tes_state = nvc0_tep_state_create;
1441 pipe->bind_vs_state = nvc0_vp_state_bind;
1442 pipe->bind_fs_state = nvc0_fp_state_bind;
1443 pipe->bind_gs_state = nvc0_gp_state_bind;
1444 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1445 pipe->bind_tes_state = nvc0_tep_state_bind;
1446 pipe->delete_vs_state = nvc0_sp_state_delete;
1447 pipe->delete_fs_state = nvc0_sp_state_delete;
1448 pipe->delete_gs_state = nvc0_sp_state_delete;
1449 pipe->delete_tcs_state = nvc0_sp_state_delete;
1450 pipe->delete_tes_state = nvc0_sp_state_delete;
1451
1452 pipe->create_compute_state = nvc0_cp_state_create;
1453 pipe->bind_compute_state = nvc0_cp_state_bind;
1454 pipe->delete_compute_state = nvc0_sp_state_delete;
1455
1456 pipe->set_blend_color = nvc0_set_blend_color;
1457 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1458 pipe->set_clip_state = nvc0_set_clip_state;
1459 pipe->set_sample_mask = nvc0_set_sample_mask;
1460 pipe->set_min_samples = nvc0_set_min_samples;
1461 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1462 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1463 pipe->set_sample_locations = nvc0_set_sample_locations;
1464 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1465 pipe->set_scissor_states = nvc0_set_scissor_states;
1466 pipe->set_viewport_states = nvc0_set_viewport_states;
1467 pipe->set_window_rectangles = nvc0_set_window_rectangles;
1468 pipe->set_tess_state = nvc0_set_tess_state;
1469
1470 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1471 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1472 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1473
1474 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1475
1476 pipe->create_stream_output_target = nvc0_so_target_create;
1477 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1478 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1479
1480 pipe->set_global_binding = nvc0_set_global_bindings;
1481 pipe->set_compute_resources = nvc0_set_compute_resources;
1482 pipe->set_shader_images = nvc0_set_shader_images;
1483 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1484
1485 nvc0->sample_mask = ~0;
1486 nvc0->min_samples = 1;
1487 nvc0->default_tess_outer[0] =
1488 nvc0->default_tess_outer[1] =
1489 nvc0->default_tess_outer[2] =
1490 nvc0->default_tess_outer[3] = 1.0;
1491 nvc0->default_tess_inner[0] =
1492 nvc0->default_tess_inner[1] = 1.0;
1493 }