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nvc0: add depth bounds test support
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_helpers.h"
25 #include "util/u_inlines.h"
26 #include "util/u_transfer.h"
27
28 #include "tgsi/tgsi_parse.h"
29
30 #include "nvc0/nvc0_stateobj.h"
31 #include "nvc0/nvc0_context.h"
32
33 #include "nvc0/nvc0_3d.xml.h"
34 #include "nv50/nv50_texture.xml.h"
35
36 #include "nouveau_gldefs.h"
37
38 static inline uint32_t
39 nvc0_colormask(unsigned mask)
40 {
41 uint32_t ret = 0;
42
43 if (mask & PIPE_MASK_R)
44 ret |= 0x0001;
45 if (mask & PIPE_MASK_G)
46 ret |= 0x0010;
47 if (mask & PIPE_MASK_B)
48 ret |= 0x0100;
49 if (mask & PIPE_MASK_A)
50 ret |= 0x1000;
51
52 return ret;
53 }
54
55 #define NVC0_BLEND_FACTOR_CASE(a, b) \
56 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
57
58 static inline uint32_t
59 nvc0_blend_fac(unsigned factor)
60 {
61 switch (factor) {
62 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
63 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
64 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
65 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
67 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
68 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
69 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
70 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
71 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
72 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
73 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
75 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
77 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
79 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
81 default:
82 return NV50_BLEND_FACTOR_ZERO;
83 }
84 }
85
86 static void *
87 nvc0_blend_state_create(struct pipe_context *pipe,
88 const struct pipe_blend_state *cso)
89 {
90 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
91 int i;
92 int r; /* reference */
93 uint32_t ms;
94 uint8_t blend_en = 0;
95 bool indep_masks = false;
96 bool indep_funcs = false;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = true;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = true;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 ms = 0;
180 if (cso->alpha_to_coverage)
181 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
182 if (cso->alpha_to_one)
183 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
184
185 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
186 SB_DATA (so, ms);
187
188 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
189 return so;
190 }
191
192 static void
193 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
194 {
195 struct nvc0_context *nvc0 = nvc0_context(pipe);
196
197 nvc0->blend = hwcso;
198 nvc0->dirty |= NVC0_NEW_BLEND;
199 }
200
201 static void
202 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
203 {
204 FREE(hwcso);
205 }
206
207 /* NOTE: ignoring line_last_pixel */
208 static void *
209 nvc0_rasterizer_state_create(struct pipe_context *pipe,
210 const struct pipe_rasterizer_state *cso)
211 {
212 struct nvc0_rasterizer_stateobj *so;
213 uint32_t reg;
214
215 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
216 if (!so)
217 return NULL;
218 so->pipe = *cso;
219
220 /* Scissor enables are handled in scissor state, we will not want to
221 * always emit 16 commands, one for each scissor rectangle, here.
222 */
223
224 SB_BEGIN_3D(so, SHADE_MODEL, 1);
225 SB_DATA (so, cso->flatshade ? NVC0_3D_SHADE_MODEL_FLAT :
226 NVC0_3D_SHADE_MODEL_SMOOTH);
227 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
228 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
229
230 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
231 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
232 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
233
234 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
235
236 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
237 if (cso->line_smooth)
238 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
239 else
240 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
241 SB_DATA (so, fui(cso->line_width));
242
243 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
244 if (cso->line_stipple_enable) {
245 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
246 SB_DATA (so, (cso->line_stipple_pattern << 8) |
247 cso->line_stipple_factor);
248
249 }
250
251 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
252 if (!cso->point_size_per_vertex) {
253 SB_BEGIN_3D(so, POINT_SIZE, 1);
254 SB_DATA (so, fui(cso->point_size));
255 }
256
257 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
258 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
259 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
260
261 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
262 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
263 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
264 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
265
266 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
267 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
268 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
269 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
270 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
271
272 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
273 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
274 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
275 NVC0_3D_FRONT_FACE_CW);
276 switch (cso->cull_face) {
277 case PIPE_FACE_FRONT_AND_BACK:
278 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
279 break;
280 case PIPE_FACE_FRONT:
281 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
282 break;
283 case PIPE_FACE_BACK:
284 default:
285 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
286 break;
287 }
288
289 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
290 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
291 SB_DATA (so, cso->offset_point);
292 SB_DATA (so, cso->offset_line);
293 SB_DATA (so, cso->offset_tri);
294
295 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
296 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
297 SB_DATA (so, fui(cso->offset_scale));
298 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
299 SB_DATA (so, fui(cso->offset_units * 2.0f));
300 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
301 SB_DATA (so, fui(cso->offset_clamp));
302 }
303
304 if (cso->depth_clip)
305 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
306 else
307 reg =
308 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
309 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
310 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
311 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
312
313 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
314 SB_DATA (so, reg);
315
316 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
317
318 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
319
320 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
321 return (void *)so;
322 }
323
324 static void
325 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
326 {
327 struct nvc0_context *nvc0 = nvc0_context(pipe);
328
329 nvc0->rast = hwcso;
330 nvc0->dirty |= NVC0_NEW_RASTERIZER;
331 }
332
333 static void
334 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
335 {
336 FREE(hwcso);
337 }
338
339 static void *
340 nvc0_zsa_state_create(struct pipe_context *pipe,
341 const struct pipe_depth_stencil_alpha_state *cso)
342 {
343 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
344
345 so->pipe = *cso;
346
347 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
348 if (cso->depth.enabled) {
349 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
350 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
351 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
352 }
353
354 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
355 if (cso->depth.bounds_test) {
356 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
357 SB_DATA (so, fui(cso->depth.bounds_min));
358 SB_DATA (so, fui(cso->depth.bounds_max));
359 }
360
361 if (cso->stencil[0].enabled) {
362 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
363 SB_DATA (so, 1);
364 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
365 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
366 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
367 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
368 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
369 SB_DATA (so, cso->stencil[0].valuemask);
370 SB_DATA (so, cso->stencil[0].writemask);
371 } else {
372 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
373 }
374
375 if (cso->stencil[1].enabled) {
376 assert(cso->stencil[0].enabled);
377 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
378 SB_DATA (so, 1);
379 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
380 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
381 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
382 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
383 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
384 SB_DATA (so, cso->stencil[1].writemask);
385 SB_DATA (so, cso->stencil[1].valuemask);
386 } else
387 if (cso->stencil[0].enabled) {
388 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
389 }
390
391 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
392 if (cso->alpha.enabled) {
393 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
394 SB_DATA (so, fui(cso->alpha.ref_value));
395 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
396 }
397
398 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
399 return (void *)so;
400 }
401
402 static void
403 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
404 {
405 struct nvc0_context *nvc0 = nvc0_context(pipe);
406
407 nvc0->zsa = hwcso;
408 nvc0->dirty |= NVC0_NEW_ZSA;
409 }
410
411 static void
412 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
413 {
414 FREE(hwcso);
415 }
416
417 /* ====================== SAMPLERS AND TEXTURES ================================
418 */
419
420 #define NV50_TSC_WRAP_CASE(n) \
421 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
422
423 static void
424 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
425 {
426 unsigned s, i;
427
428 for (s = 0; s < 5; ++s)
429 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
430 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
431 nvc0_context(pipe)->samplers[s][i] = NULL;
432
433 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
434
435 FREE(hwcso);
436 }
437
438 static inline void
439 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
440 unsigned nr, void **hwcso)
441 {
442 unsigned i;
443
444 for (i = 0; i < nr; ++i) {
445 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
446
447 if (hwcso[i] == old)
448 continue;
449 nvc0->samplers_dirty[s] |= 1 << i;
450
451 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
452 if (old)
453 nvc0_screen_tsc_unlock(nvc0->screen, old);
454 }
455 for (; i < nvc0->num_samplers[s]; ++i) {
456 if (nvc0->samplers[s][i]) {
457 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
458 nvc0->samplers[s][i] = NULL;
459 }
460 }
461
462 nvc0->num_samplers[s] = nr;
463
464 nvc0->dirty |= NVC0_NEW_SAMPLERS;
465 }
466
467 static void
468 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
469 const unsigned s,
470 unsigned start, unsigned nr, void **cso)
471 {
472 const unsigned end = start + nr;
473 int last_valid = -1;
474 unsigned i;
475
476 if (cso) {
477 for (i = start; i < end; ++i) {
478 const unsigned p = i - start;
479 if (cso[p])
480 last_valid = i;
481 if (cso[p] == nvc0->samplers[s][i])
482 continue;
483 nvc0->samplers_dirty[s] |= 1 << i;
484
485 if (nvc0->samplers[s][i])
486 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
487 nvc0->samplers[s][i] = cso[p];
488 }
489 } else {
490 for (i = start; i < end; ++i) {
491 if (nvc0->samplers[s][i]) {
492 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
493 nvc0->samplers[s][i] = NULL;
494 nvc0->samplers_dirty[s] |= 1 << i;
495 }
496 }
497 }
498
499 if (nvc0->num_samplers[s] <= end) {
500 if (last_valid < 0) {
501 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
502 nvc0->num_samplers[s] = i;
503 } else {
504 nvc0->num_samplers[s] = last_valid + 1;
505 }
506 }
507 }
508
509 static void
510 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
511 unsigned start, unsigned nr, void **s)
512 {
513 switch (shader) {
514 case PIPE_SHADER_VERTEX:
515 assert(start == 0);
516 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
517 break;
518 case PIPE_SHADER_TESS_CTRL:
519 assert(start == 0);
520 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
521 break;
522 case PIPE_SHADER_TESS_EVAL:
523 assert(start == 0);
524 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
525 break;
526 case PIPE_SHADER_GEOMETRY:
527 assert(start == 0);
528 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
529 break;
530 case PIPE_SHADER_FRAGMENT:
531 assert(start == 0);
532 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
533 break;
534 case PIPE_SHADER_COMPUTE:
535 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
536 start, nr, s);
537 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
538 break;
539 }
540 }
541
542
543 /* NOTE: only called when not referenced anywhere, won't be bound */
544 static void
545 nvc0_sampler_view_destroy(struct pipe_context *pipe,
546 struct pipe_sampler_view *view)
547 {
548 pipe_resource_reference(&view->texture, NULL);
549
550 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
551
552 FREE(nv50_tic_entry(view));
553 }
554
555 static inline void
556 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
557 unsigned nr,
558 struct pipe_sampler_view **views)
559 {
560 unsigned i;
561
562 for (i = 0; i < nr; ++i) {
563 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
564
565 if (views[i] == nvc0->textures[s][i])
566 continue;
567 nvc0->textures_dirty[s] |= 1 << i;
568
569 if (old) {
570 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
571 nvc0_screen_tic_unlock(nvc0->screen, old);
572 }
573
574 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
575 }
576
577 for (i = nr; i < nvc0->num_textures[s]; ++i) {
578 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
579 if (old) {
580 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
581 nvc0_screen_tic_unlock(nvc0->screen, old);
582 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
583 }
584 }
585
586 nvc0->num_textures[s] = nr;
587
588 nvc0->dirty |= NVC0_NEW_TEXTURES;
589 }
590
591 static void
592 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
593 unsigned start, unsigned nr,
594 struct pipe_sampler_view **views)
595 {
596 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
597 const unsigned end = start + nr;
598 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s, 0);
599 int last_valid = -1;
600 unsigned i;
601
602 if (views) {
603 for (i = start; i < end; ++i) {
604 const unsigned p = i - start;
605 if (views[p])
606 last_valid = i;
607 if (views[p] == nvc0->textures[s][i])
608 continue;
609 nvc0->textures_dirty[s] |= 1 << i;
610
611 if (nvc0->textures[s][i]) {
612 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
613 nouveau_bufctx_reset(bctx, bin + i);
614 nvc0_screen_tic_unlock(nvc0->screen, old);
615 }
616 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
617 }
618 } else {
619 for (i = start; i < end; ++i) {
620 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
621 if (!old)
622 continue;
623 nvc0->textures_dirty[s] |= 1 << i;
624
625 nvc0_screen_tic_unlock(nvc0->screen, old);
626 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
627 nouveau_bufctx_reset(bctx, bin + i);
628 }
629 }
630
631 if (nvc0->num_textures[s] <= end) {
632 if (last_valid < 0) {
633 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
634 nvc0->num_textures[s] = i;
635 } else {
636 nvc0->num_textures[s] = last_valid + 1;
637 }
638 }
639 }
640
641 static void
642 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
643 unsigned start, unsigned nr,
644 struct pipe_sampler_view **views)
645 {
646 assert(start == 0);
647 switch (shader) {
648 case PIPE_SHADER_VERTEX:
649 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
650 break;
651 case PIPE_SHADER_TESS_CTRL:
652 nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
653 break;
654 case PIPE_SHADER_TESS_EVAL:
655 nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
656 break;
657 case PIPE_SHADER_GEOMETRY:
658 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
659 break;
660 case PIPE_SHADER_FRAGMENT:
661 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
662 break;
663 case PIPE_SHADER_COMPUTE:
664 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
665 start, nr, views);
666 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
667 break;
668 default:
669 ;
670 }
671 }
672
673
674 /* ============================= SHADERS =======================================
675 */
676
677 static void *
678 nvc0_sp_state_create(struct pipe_context *pipe,
679 const struct pipe_shader_state *cso, unsigned type)
680 {
681 struct nvc0_program *prog;
682
683 prog = CALLOC_STRUCT(nvc0_program);
684 if (!prog)
685 return NULL;
686
687 prog->type = type;
688
689 if (cso->tokens)
690 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
691
692 if (cso->stream_output.num_outputs)
693 prog->pipe.stream_output = cso->stream_output;
694
695 return (void *)prog;
696 }
697
698 static void
699 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
700 {
701 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
702
703 nvc0_program_destroy(nvc0_context(pipe), prog);
704
705 FREE((void *)prog->pipe.tokens);
706 FREE(prog);
707 }
708
709 static void *
710 nvc0_vp_state_create(struct pipe_context *pipe,
711 const struct pipe_shader_state *cso)
712 {
713 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
714 }
715
716 static void
717 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
718 {
719 struct nvc0_context *nvc0 = nvc0_context(pipe);
720
721 nvc0->vertprog = hwcso;
722 nvc0->dirty |= NVC0_NEW_VERTPROG;
723 }
724
725 static void *
726 nvc0_fp_state_create(struct pipe_context *pipe,
727 const struct pipe_shader_state *cso)
728 {
729 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
730 }
731
732 static void
733 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
734 {
735 struct nvc0_context *nvc0 = nvc0_context(pipe);
736
737 nvc0->fragprog = hwcso;
738 nvc0->dirty |= NVC0_NEW_FRAGPROG;
739 }
740
741 static void *
742 nvc0_gp_state_create(struct pipe_context *pipe,
743 const struct pipe_shader_state *cso)
744 {
745 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
746 }
747
748 static void
749 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
750 {
751 struct nvc0_context *nvc0 = nvc0_context(pipe);
752
753 nvc0->gmtyprog = hwcso;
754 nvc0->dirty |= NVC0_NEW_GMTYPROG;
755 }
756
757 static void *
758 nvc0_tcp_state_create(struct pipe_context *pipe,
759 const struct pipe_shader_state *cso)
760 {
761 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
762 }
763
764 static void
765 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
766 {
767 struct nvc0_context *nvc0 = nvc0_context(pipe);
768
769 nvc0->tctlprog = hwcso;
770 nvc0->dirty |= NVC0_NEW_TCTLPROG;
771 }
772
773 static void *
774 nvc0_tep_state_create(struct pipe_context *pipe,
775 const struct pipe_shader_state *cso)
776 {
777 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
778 }
779
780 static void
781 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
782 {
783 struct nvc0_context *nvc0 = nvc0_context(pipe);
784
785 nvc0->tevlprog = hwcso;
786 nvc0->dirty |= NVC0_NEW_TEVLPROG;
787 }
788
789 static void *
790 nvc0_cp_state_create(struct pipe_context *pipe,
791 const struct pipe_compute_state *cso)
792 {
793 struct nvc0_program *prog;
794
795 prog = CALLOC_STRUCT(nvc0_program);
796 if (!prog)
797 return NULL;
798 prog->type = PIPE_SHADER_COMPUTE;
799
800 prog->cp.smem_size = cso->req_local_mem;
801 prog->cp.lmem_size = cso->req_private_mem;
802 prog->parm_size = cso->req_input_mem;
803
804 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
805
806 return (void *)prog;
807 }
808
809 static void
810 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
811 {
812 struct nvc0_context *nvc0 = nvc0_context(pipe);
813
814 nvc0->compprog = hwcso;
815 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
816 }
817
818 static void
819 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
820 struct pipe_constant_buffer *cb)
821 {
822 struct nvc0_context *nvc0 = nvc0_context(pipe);
823 struct pipe_resource *res = cb ? cb->buffer : NULL;
824 const unsigned s = nvc0_shader_stage(shader);
825 const unsigned i = index;
826
827 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
828 assert(!cb || !cb->user_buffer);
829 if (nvc0->constbuf[s][i].u.buf)
830 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
831
832 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
833 } else {
834 if (nvc0->constbuf[s][i].user)
835 nvc0->constbuf[s][i].u.buf = NULL;
836 else
837 if (nvc0->constbuf[s][i].u.buf)
838 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CB(s, i));
839
840 nvc0->dirty |= NVC0_NEW_CONSTBUF;
841 }
842 nvc0->constbuf_dirty[s] |= 1 << i;
843
844 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
845
846 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
847 if (nvc0->constbuf[s][i].user) {
848 nvc0->constbuf[s][i].u.data = cb->user_buffer;
849 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
850 nvc0->constbuf_valid[s] |= 1 << i;
851 } else
852 if (cb) {
853 nvc0->constbuf[s][i].offset = cb->buffer_offset;
854 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
855 nvc0->constbuf_valid[s] |= 1 << i;
856 }
857 else {
858 nvc0->constbuf_valid[s] &= ~(1 << i);
859 }
860 }
861
862 /* =============================================================================
863 */
864
865 static void
866 nvc0_set_blend_color(struct pipe_context *pipe,
867 const struct pipe_blend_color *bcol)
868 {
869 struct nvc0_context *nvc0 = nvc0_context(pipe);
870
871 nvc0->blend_colour = *bcol;
872 nvc0->dirty |= NVC0_NEW_BLEND_COLOUR;
873 }
874
875 static void
876 nvc0_set_stencil_ref(struct pipe_context *pipe,
877 const struct pipe_stencil_ref *sr)
878 {
879 struct nvc0_context *nvc0 = nvc0_context(pipe);
880
881 nvc0->stencil_ref = *sr;
882 nvc0->dirty |= NVC0_NEW_STENCIL_REF;
883 }
884
885 static void
886 nvc0_set_clip_state(struct pipe_context *pipe,
887 const struct pipe_clip_state *clip)
888 {
889 struct nvc0_context *nvc0 = nvc0_context(pipe);
890
891 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
892
893 nvc0->dirty |= NVC0_NEW_CLIP;
894 }
895
896 static void
897 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
898 {
899 struct nvc0_context *nvc0 = nvc0_context(pipe);
900
901 nvc0->sample_mask = sample_mask;
902 nvc0->dirty |= NVC0_NEW_SAMPLE_MASK;
903 }
904
905 static void
906 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
907 {
908 struct nvc0_context *nvc0 = nvc0_context(pipe);
909
910 if (nvc0->min_samples != min_samples) {
911 nvc0->min_samples = min_samples;
912 nvc0->dirty |= NVC0_NEW_MIN_SAMPLES;
913 }
914 }
915
916 static void
917 nvc0_set_framebuffer_state(struct pipe_context *pipe,
918 const struct pipe_framebuffer_state *fb)
919 {
920 struct nvc0_context *nvc0 = nvc0_context(pipe);
921 unsigned i;
922
923 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
924
925 for (i = 0; i < fb->nr_cbufs; ++i)
926 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], fb->cbufs[i]);
927 for (; i < nvc0->framebuffer.nr_cbufs; ++i)
928 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], NULL);
929
930 nvc0->framebuffer.nr_cbufs = fb->nr_cbufs;
931
932 nvc0->framebuffer.width = fb->width;
933 nvc0->framebuffer.height = fb->height;
934
935 pipe_surface_reference(&nvc0->framebuffer.zsbuf, fb->zsbuf);
936
937 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
938 }
939
940 static void
941 nvc0_set_polygon_stipple(struct pipe_context *pipe,
942 const struct pipe_poly_stipple *stipple)
943 {
944 struct nvc0_context *nvc0 = nvc0_context(pipe);
945
946 nvc0->stipple = *stipple;
947 nvc0->dirty |= NVC0_NEW_STIPPLE;
948 }
949
950 static void
951 nvc0_set_scissor_states(struct pipe_context *pipe,
952 unsigned start_slot,
953 unsigned num_scissors,
954 const struct pipe_scissor_state *scissor)
955 {
956 struct nvc0_context *nvc0 = nvc0_context(pipe);
957 int i;
958
959 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
960 for (i = 0; i < num_scissors; i++) {
961 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
962 continue;
963 nvc0->scissors[start_slot + i] = scissor[i];
964 nvc0->scissors_dirty |= 1 << (start_slot + i);
965 nvc0->dirty |= NVC0_NEW_SCISSOR;
966 }
967 }
968
969 static void
970 nvc0_set_viewport_states(struct pipe_context *pipe,
971 unsigned start_slot,
972 unsigned num_viewports,
973 const struct pipe_viewport_state *vpt)
974 {
975 struct nvc0_context *nvc0 = nvc0_context(pipe);
976 int i;
977
978 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
979 for (i = 0; i < num_viewports; i++) {
980 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
981 continue;
982 nvc0->viewports[start_slot + i] = vpt[i];
983 nvc0->viewports_dirty |= 1 << (start_slot + i);
984 nvc0->dirty |= NVC0_NEW_VIEWPORT;
985 }
986
987 }
988
989 static void
990 nvc0_set_tess_state(struct pipe_context *pipe,
991 const float default_tess_outer[4],
992 const float default_tess_inner[2])
993 {
994 struct nvc0_context *nvc0 = nvc0_context(pipe);
995
996 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
997 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
998 nvc0->dirty |= NVC0_NEW_TESSFACTOR;
999 }
1000
1001 static void
1002 nvc0_set_vertex_buffers(struct pipe_context *pipe,
1003 unsigned start_slot, unsigned count,
1004 const struct pipe_vertex_buffer *vb)
1005 {
1006 struct nvc0_context *nvc0 = nvc0_context(pipe);
1007 unsigned i;
1008
1009 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1010 start_slot, count);
1011
1012 if (!vb) {
1013 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1014 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1015 return;
1016 }
1017
1018 for (i = 0; i < count; ++i) {
1019 unsigned dst_index = start_slot + i;
1020
1021 if (vb[i].user_buffer) {
1022 nvc0->vbo_user |= 1 << dst_index;
1023 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1024 nvc0->constant_vbos |= 1 << dst_index;
1025 else
1026 nvc0->constant_vbos &= ~(1 << dst_index);
1027 } else {
1028 nvc0->vbo_user &= ~(1 << dst_index);
1029 nvc0->constant_vbos &= ~(1 << dst_index);
1030 }
1031 }
1032
1033 nvc0->dirty |= NVC0_NEW_ARRAYS;
1034 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
1035 }
1036
1037 static void
1038 nvc0_set_index_buffer(struct pipe_context *pipe,
1039 const struct pipe_index_buffer *ib)
1040 {
1041 struct nvc0_context *nvc0 = nvc0_context(pipe);
1042
1043 if (nvc0->idxbuf.buffer)
1044 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
1045
1046 if (ib) {
1047 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1048 nvc0->idxbuf.index_size = ib->index_size;
1049 if (ib->buffer) {
1050 nvc0->idxbuf.offset = ib->offset;
1051 nvc0->dirty |= NVC0_NEW_IDXBUF;
1052 } else {
1053 nvc0->idxbuf.user_buffer = ib->user_buffer;
1054 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1055 }
1056 } else {
1057 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1058 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1059 }
1060 }
1061
1062 static void
1063 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1064 {
1065 struct nvc0_context *nvc0 = nvc0_context(pipe);
1066
1067 nvc0->vertex = hwcso;
1068 nvc0->dirty |= NVC0_NEW_VERTEX;
1069 }
1070
1071 static struct pipe_stream_output_target *
1072 nvc0_so_target_create(struct pipe_context *pipe,
1073 struct pipe_resource *res,
1074 unsigned offset, unsigned size)
1075 {
1076 struct nv04_resource *buf = (struct nv04_resource *)res;
1077 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1078 if (!targ)
1079 return NULL;
1080
1081 targ->pq = pipe->create_query(pipe, NVC0_QUERY_TFB_BUFFER_OFFSET, 0);
1082 if (!targ->pq) {
1083 FREE(targ);
1084 return NULL;
1085 }
1086 targ->clean = true;
1087
1088 targ->pipe.buffer_size = size;
1089 targ->pipe.buffer_offset = offset;
1090 targ->pipe.context = pipe;
1091 targ->pipe.buffer = NULL;
1092 pipe_resource_reference(&targ->pipe.buffer, res);
1093 pipe_reference_init(&targ->pipe.reference, 1);
1094
1095 assert(buf->base.target == PIPE_BUFFER);
1096 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1097
1098 return &targ->pipe;
1099 }
1100
1101 static void
1102 nvc0_so_target_destroy(struct pipe_context *pipe,
1103 struct pipe_stream_output_target *ptarg)
1104 {
1105 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1106 pipe->destroy_query(pipe, targ->pq);
1107 pipe_resource_reference(&targ->pipe.buffer, NULL);
1108 FREE(targ);
1109 }
1110
1111 static void
1112 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1113 unsigned num_targets,
1114 struct pipe_stream_output_target **targets,
1115 const unsigned *offsets)
1116 {
1117 struct nvc0_context *nvc0 = nvc0_context(pipe);
1118 unsigned i;
1119 bool serialize = true;
1120
1121 assert(num_targets <= 4);
1122
1123 for (i = 0; i < num_targets; ++i) {
1124 const bool changed = nvc0->tfbbuf[i] != targets[i];
1125 const bool append = (offsets[i] == ((unsigned)-1));
1126 if (!changed && append)
1127 continue;
1128 nvc0->tfbbuf_dirty |= 1 << i;
1129
1130 if (nvc0->tfbbuf[i] && changed)
1131 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1132
1133 if (targets[i] && !append)
1134 nvc0_so_target(targets[i])->clean = true;
1135
1136 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1137 }
1138 for (; i < nvc0->num_tfbbufs; ++i) {
1139 if (nvc0->tfbbuf[i]) {
1140 nvc0->tfbbuf_dirty |= 1 << i;
1141 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1142 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1143 }
1144 }
1145 nvc0->num_tfbbufs = num_targets;
1146
1147 if (nvc0->tfbbuf_dirty)
1148 nvc0->dirty |= NVC0_NEW_TFB_TARGETS;
1149 }
1150
1151 static void
1152 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1153 unsigned start, unsigned nr,
1154 struct pipe_surface **psurfaces)
1155 {
1156 const unsigned end = start + nr;
1157 const unsigned mask = ((1 << nr) - 1) << start;
1158 unsigned i;
1159
1160 if (psurfaces) {
1161 for (i = start; i < end; ++i) {
1162 const unsigned p = i - start;
1163 if (psurfaces[p])
1164 nvc0->surfaces_valid[t] |= (1 << i);
1165 else
1166 nvc0->surfaces_valid[t] &= ~(1 << i);
1167 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1168 }
1169 } else {
1170 for (i = start; i < end; ++i)
1171 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1172 nvc0->surfaces_valid[t] &= ~mask;
1173 }
1174 nvc0->surfaces_dirty[t] |= mask;
1175
1176 if (t == 0)
1177 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_SUF);
1178 else
1179 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1180 }
1181
1182 static void
1183 nvc0_set_compute_resources(struct pipe_context *pipe,
1184 unsigned start, unsigned nr,
1185 struct pipe_surface **resources)
1186 {
1187 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1188
1189 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1190 }
1191
1192 static void
1193 nvc0_set_shader_images(struct pipe_context *pipe, unsigned shader,
1194 unsigned start_slot, unsigned count,
1195 struct pipe_image_view **views)
1196 {
1197 #if 0
1198 nvc0_bind_surfaces_range(nvc0_context(pipe), 0, start, nr, views);
1199
1200 nvc0_context(pipe)->dirty |= NVC0_NEW_SURFACES;
1201 #endif
1202 }
1203
1204 static inline void
1205 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1206 {
1207 struct nv04_resource *buf = nv04_resource(res);
1208 if (buf) {
1209 uint64_t limit = (buf->address + buf->base.width0) - 1;
1210 if (limit < (1ULL << 32)) {
1211 *phandle = (uint32_t)buf->address;
1212 } else {
1213 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1214 "resource not contained within 32-bit address space !\n");
1215 *phandle = 0;
1216 }
1217 } else {
1218 *phandle = 0;
1219 }
1220 }
1221
1222 static void
1223 nvc0_set_global_bindings(struct pipe_context *pipe,
1224 unsigned start, unsigned nr,
1225 struct pipe_resource **resources,
1226 uint32_t **handles)
1227 {
1228 struct nvc0_context *nvc0 = nvc0_context(pipe);
1229 struct pipe_resource **ptr;
1230 unsigned i;
1231 const unsigned end = start + nr;
1232
1233 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1234 const unsigned old_size = nvc0->global_residents.size;
1235 const unsigned req_size = end * sizeof(struct pipe_resource *);
1236 util_dynarray_resize(&nvc0->global_residents, req_size);
1237 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1238 req_size - old_size);
1239 }
1240
1241 if (resources) {
1242 ptr = util_dynarray_element(
1243 &nvc0->global_residents, struct pipe_resource *, start);
1244 for (i = 0; i < nr; ++i) {
1245 pipe_resource_reference(&ptr[i], resources[i]);
1246 nvc0_set_global_handle(handles[i], resources[i]);
1247 }
1248 } else {
1249 ptr = util_dynarray_element(
1250 &nvc0->global_residents, struct pipe_resource *, start);
1251 for (i = 0; i < nr; ++i)
1252 pipe_resource_reference(&ptr[i], NULL);
1253 }
1254
1255 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1256
1257 nvc0->dirty_cp = NVC0_NEW_CP_GLOBALS;
1258 }
1259
1260 void
1261 nvc0_init_state_functions(struct nvc0_context *nvc0)
1262 {
1263 struct pipe_context *pipe = &nvc0->base.pipe;
1264
1265 pipe->create_blend_state = nvc0_blend_state_create;
1266 pipe->bind_blend_state = nvc0_blend_state_bind;
1267 pipe->delete_blend_state = nvc0_blend_state_delete;
1268
1269 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1270 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1271 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1272
1273 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1274 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1275 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1276
1277 pipe->create_sampler_state = nv50_sampler_state_create;
1278 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1279 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1280
1281 pipe->create_sampler_view = nvc0_create_sampler_view;
1282 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1283 pipe->set_sampler_views = nvc0_set_sampler_views;
1284
1285 pipe->create_vs_state = nvc0_vp_state_create;
1286 pipe->create_fs_state = nvc0_fp_state_create;
1287 pipe->create_gs_state = nvc0_gp_state_create;
1288 pipe->create_tcs_state = nvc0_tcp_state_create;
1289 pipe->create_tes_state = nvc0_tep_state_create;
1290 pipe->bind_vs_state = nvc0_vp_state_bind;
1291 pipe->bind_fs_state = nvc0_fp_state_bind;
1292 pipe->bind_gs_state = nvc0_gp_state_bind;
1293 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1294 pipe->bind_tes_state = nvc0_tep_state_bind;
1295 pipe->delete_vs_state = nvc0_sp_state_delete;
1296 pipe->delete_fs_state = nvc0_sp_state_delete;
1297 pipe->delete_gs_state = nvc0_sp_state_delete;
1298 pipe->delete_tcs_state = nvc0_sp_state_delete;
1299 pipe->delete_tes_state = nvc0_sp_state_delete;
1300
1301 pipe->create_compute_state = nvc0_cp_state_create;
1302 pipe->bind_compute_state = nvc0_cp_state_bind;
1303 pipe->delete_compute_state = nvc0_sp_state_delete;
1304
1305 pipe->set_blend_color = nvc0_set_blend_color;
1306 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1307 pipe->set_clip_state = nvc0_set_clip_state;
1308 pipe->set_sample_mask = nvc0_set_sample_mask;
1309 pipe->set_min_samples = nvc0_set_min_samples;
1310 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1311 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1312 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1313 pipe->set_scissor_states = nvc0_set_scissor_states;
1314 pipe->set_viewport_states = nvc0_set_viewport_states;
1315 pipe->set_tess_state = nvc0_set_tess_state;
1316
1317 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1318 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1319 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1320
1321 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1322 pipe->set_index_buffer = nvc0_set_index_buffer;
1323
1324 pipe->create_stream_output_target = nvc0_so_target_create;
1325 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1326 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1327
1328 pipe->set_global_binding = nvc0_set_global_bindings;
1329 pipe->set_compute_resources = nvc0_set_compute_resources;
1330 pipe->set_shader_images = nvc0_set_shader_images;
1331
1332 nvc0->sample_mask = ~0;
1333 nvc0->min_samples = 1;
1334 nvc0->default_tess_outer[0] =
1335 nvc0->default_tess_outer[1] =
1336 nvc0->default_tess_outer[2] =
1337 nvc0->default_tess_outer[3] = 1.0;
1338 nvc0->default_tess_inner[0] =
1339 nvc0->default_tess_inner[1] = 1.0;
1340 }