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gallium: add pipe cap for scissored clears and pass scissor state to clear() hook
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/format/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "os/os_thread.h"
33
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_resource.h"
36
37 #include "nv50/g80_defs.xml.h"
38 #include "nv50/g80_texture.xml.h"
39
40 /* these are used in nv50_blit.h */
41 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
42 #define NV50_ENG2D_NOCONVERT_FORMATS 0x009cc02000000000ULL
43 #define NV50_ENG2D_LUMINANCE_FORMATS 0x001cc02000000000ULL
44 #define NV50_ENG2D_INTENSITY_FORMATS 0x0080000000000000ULL
45 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000638000ULL
46
47 #define NOUVEAU_DRIVER 0xc0
48 #include "nv50/nv50_blit.h"
49
50 static inline uint8_t
51 nvc0_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
52 {
53 uint8_t id = nvc0_format_table[format].rt;
54
55 /* A8_UNORM is treated as I8_UNORM as far as the 2D engine is concerned. */
56 if (!dst && unlikely(format == PIPE_FORMAT_I8_UNORM) && !dst_src_equal)
57 return G80_SURFACE_FORMAT_A8_UNORM;
58
59 /* Hardware values for color formats range from 0xc0 to 0xff,
60 * but the 2D engine doesn't support all of them.
61 */
62 if (nv50_2d_format_supported(format))
63 return id;
64 assert(dst_src_equal);
65
66 switch (util_format_get_blocksize(format)) {
67 case 1:
68 return G80_SURFACE_FORMAT_R8_UNORM;
69 case 2:
70 return G80_SURFACE_FORMAT_RG8_UNORM;
71 case 4:
72 return G80_SURFACE_FORMAT_BGRA8_UNORM;
73 case 8:
74 return G80_SURFACE_FORMAT_RGBA16_UNORM;
75 case 16:
76 return G80_SURFACE_FORMAT_RGBA32_FLOAT;
77 default:
78 assert(0);
79 return 0;
80 }
81 }
82
83 static int
84 nvc0_2d_texture_set(struct nouveau_pushbuf *push, bool dst,
85 struct nv50_miptree *mt, unsigned level, unsigned layer,
86 enum pipe_format pformat, bool dst_src_pformat_equal)
87 {
88 struct nouveau_bo *bo = mt->base.bo;
89 uint32_t width, height, depth;
90 uint32_t format;
91 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
92 uint32_t offset = mt->level[level].offset;
93
94 format = nvc0_2d_format(pformat, dst, dst_src_pformat_equal);
95 if (!format) {
96 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
97 util_format_name(pformat));
98 return 1;
99 }
100
101 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
102 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
103 depth = u_minify(mt->base.base.depth0, level);
104
105 /* layer has to be < depth, and depth > tile depth / 2 */
106
107 if (!mt->layout_3d) {
108 offset += mt->layer_stride * layer;
109 layer = 0;
110 depth = 1;
111 } else
112 if (!dst) {
113 offset += nvc0_mt_zslice_offset(mt, level, layer);
114 layer = 0;
115 }
116
117 if (!nouveau_bo_memtype(bo)) {
118 BEGIN_NVC0(push, SUBC_2D(mthd), 2);
119 PUSH_DATA (push, format);
120 PUSH_DATA (push, 1);
121 BEGIN_NVC0(push, SUBC_2D(mthd + 0x14), 5);
122 PUSH_DATA (push, mt->level[level].pitch);
123 PUSH_DATA (push, width);
124 PUSH_DATA (push, height);
125 PUSH_DATAh(push, bo->offset + offset);
126 PUSH_DATA (push, bo->offset + offset);
127 } else {
128 BEGIN_NVC0(push, SUBC_2D(mthd), 5);
129 PUSH_DATA (push, format);
130 PUSH_DATA (push, 0);
131 PUSH_DATA (push, mt->level[level].tile_mode);
132 PUSH_DATA (push, depth);
133 PUSH_DATA (push, layer);
134 BEGIN_NVC0(push, SUBC_2D(mthd + 0x18), 4);
135 PUSH_DATA (push, width);
136 PUSH_DATA (push, height);
137 PUSH_DATAh(push, bo->offset + offset);
138 PUSH_DATA (push, bo->offset + offset);
139 }
140
141 #if 0
142 if (dst) {
143 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_CLIP_X), 4);
144 PUSH_DATA (push, 0);
145 PUSH_DATA (push, 0);
146 PUSH_DATA (push, width);
147 PUSH_DATA (push, height);
148 }
149 #endif
150 return 0;
151 }
152
153 static int
154 nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push,
155 struct nv50_miptree *dst, unsigned dst_level,
156 unsigned dx, unsigned dy, unsigned dz,
157 struct nv50_miptree *src, unsigned src_level,
158 unsigned sx, unsigned sy, unsigned sz,
159 unsigned w, unsigned h)
160 {
161 const enum pipe_format dfmt = dst->base.base.format;
162 const enum pipe_format sfmt = src->base.base.format;
163 int ret;
164 bool eqfmt = dfmt == sfmt;
165
166 if (!PUSH_SPACE(push, 2 * 16 + 32))
167 return PIPE_ERROR;
168
169 ret = nvc0_2d_texture_set(push, true, dst, dst_level, dz, dfmt, eqfmt);
170 if (ret)
171 return ret;
172
173 ret = nvc0_2d_texture_set(push, false, src, src_level, sz, sfmt, eqfmt);
174 if (ret)
175 return ret;
176
177 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), 0x00);
178 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
179 PUSH_DATA (push, dx << dst->ms_x);
180 PUSH_DATA (push, dy << dst->ms_y);
181 PUSH_DATA (push, w << dst->ms_x);
182 PUSH_DATA (push, h << dst->ms_y);
183 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, 1);
186 PUSH_DATA (push, 0);
187 PUSH_DATA (push, 1);
188 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
189 PUSH_DATA (push, 0);
190 PUSH_DATA (push, sx << src->ms_x);
191 PUSH_DATA (push, 0);
192 PUSH_DATA (push, sy << src->ms_y);
193
194 return 0;
195 }
196
197 static void
198 nvc0_resource_copy_region(struct pipe_context *pipe,
199 struct pipe_resource *dst, unsigned dst_level,
200 unsigned dstx, unsigned dsty, unsigned dstz,
201 struct pipe_resource *src, unsigned src_level,
202 const struct pipe_box *src_box)
203 {
204 struct nvc0_context *nvc0 = nvc0_context(pipe);
205 int ret;
206 bool m2mf;
207 unsigned dst_layer = dstz, src_layer = src_box->z;
208
209 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
210 nouveau_copy_buffer(&nvc0->base,
211 nv04_resource(dst), dstx,
212 nv04_resource(src), src_box->x, src_box->width);
213 NOUVEAU_DRV_STAT(&nvc0->screen->base, buf_copy_bytes, src_box->width);
214 return;
215 }
216 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_copy_count, 1);
217
218 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
219 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
220
221 m2mf = (src->format == dst->format) ||
222 (util_format_get_blocksizebits(src->format) ==
223 util_format_get_blocksizebits(dst->format));
224
225 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
226
227 if (m2mf) {
228 struct nv50_miptree *src_mt = nv50_miptree(src);
229 struct nv50_miptree *dst_mt = nv50_miptree(dst);
230 struct nv50_m2mf_rect drect, srect;
231 unsigned i;
232 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
233 << src_mt->ms_x;
234 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
235 << src_mt->ms_y;
236
237 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
238 nv50_m2mf_rect_setup(&srect, src, src_level,
239 src_box->x, src_box->y, src_box->z);
240
241 for (i = 0; i < src_box->depth; ++i) {
242 nvc0->m2mf_copy_rect(nvc0, &drect, &srect, nx, ny);
243
244 if (dst_mt->layout_3d)
245 drect.z++;
246 else
247 drect.base += dst_mt->layer_stride;
248
249 if (src_mt->layout_3d)
250 srect.z++;
251 else
252 srect.base += src_mt->layer_stride;
253 }
254 return;
255 }
256
257 assert(nv50_2d_dst_format_faithful(dst->format));
258 assert(nv50_2d_src_format_faithful(src->format));
259
260 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(src), RD);
261 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(dst), WR);
262 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
263 nouveau_pushbuf_validate(nvc0->base.pushbuf);
264
265 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
266 ret = nvc0_2d_texture_do_copy(nvc0->base.pushbuf,
267 nv50_miptree(dst), dst_level,
268 dstx, dsty, dst_layer,
269 nv50_miptree(src), src_level,
270 src_box->x, src_box->y, src_layer,
271 src_box->width, src_box->height);
272 if (ret)
273 break;
274 }
275 nouveau_bufctx_reset(nvc0->bufctx, 0);
276 }
277
278 static void
279 nvc0_clear_render_target(struct pipe_context *pipe,
280 struct pipe_surface *dst,
281 const union pipe_color_union *color,
282 unsigned dstx, unsigned dsty,
283 unsigned width, unsigned height,
284 bool render_condition_enabled)
285 {
286 struct nvc0_context *nvc0 = nvc0_context(pipe);
287 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
288 struct nv50_surface *sf = nv50_surface(dst);
289 struct nv04_resource *res = nv04_resource(sf->base.texture);
290 unsigned z;
291
292 assert(dst->texture->target != PIPE_BUFFER);
293
294 if (!PUSH_SPACE(push, 32 + sf->depth))
295 return;
296
297 PUSH_REFN (push, res->bo, res->domain | NOUVEAU_BO_WR);
298
299 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
300 PUSH_DATAf(push, color->f[0]);
301 PUSH_DATAf(push, color->f[1]);
302 PUSH_DATAf(push, color->f[2]);
303 PUSH_DATAf(push, color->f[3]);
304
305 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
306 PUSH_DATA (push, ( width << 16) | dstx);
307 PUSH_DATA (push, (height << 16) | dsty);
308
309 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
310 PUSH_DATA (push, 1);
311 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
312 PUSH_DATAh(push, res->address + sf->offset);
313 PUSH_DATA (push, res->address + sf->offset);
314 if (likely(nouveau_bo_memtype(res->bo))) {
315 struct nv50_miptree *mt = nv50_miptree(dst->texture);
316
317 PUSH_DATA(push, sf->width);
318 PUSH_DATA(push, sf->height);
319 PUSH_DATA(push, nvc0_format_table[dst->format].rt);
320 PUSH_DATA(push, (mt->layout_3d << 16) |
321 mt->level[sf->base.u.tex.level].tile_mode);
322 PUSH_DATA(push, dst->u.tex.first_layer + sf->depth);
323 PUSH_DATA(push, mt->layer_stride >> 2);
324 PUSH_DATA(push, dst->u.tex.first_layer);
325 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
326 } else {
327 if (res->base.target == PIPE_BUFFER) {
328 PUSH_DATA(push, 262144);
329 PUSH_DATA(push, 1);
330 } else {
331 PUSH_DATA(push, nv50_miptree(&res->base)->level[0].pitch);
332 PUSH_DATA(push, sf->height);
333 }
334 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
335 PUSH_DATA(push, 1 << 12);
336 PUSH_DATA(push, 1);
337 PUSH_DATA(push, 0);
338 PUSH_DATA(push, 0);
339
340 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
341 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
342
343 /* tiled textures don't have to be fenced, they're not mapped directly */
344 nvc0_resource_fence(res, NOUVEAU_BO_WR);
345 }
346
347 if (!render_condition_enabled)
348 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
349
350 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
351 for (z = 0; z < sf->depth; ++z) {
352 PUSH_DATA (push, 0x3c |
353 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
354 }
355
356 if (!render_condition_enabled)
357 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
358
359 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
360 }
361
362 static void
363 nvc0_clear_buffer_push_nvc0(struct pipe_context *pipe,
364 struct pipe_resource *res,
365 unsigned offset, unsigned size,
366 const void *data, int data_size)
367 {
368 struct nvc0_context *nvc0 = nvc0_context(pipe);
369 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
370 struct nv04_resource *buf = nv04_resource(res);
371 unsigned i;
372
373 nouveau_bufctx_refn(nvc0->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
374 nouveau_pushbuf_bufctx(push, nvc0->bufctx);
375 nouveau_pushbuf_validate(push);
376
377 unsigned count = (size + 3) / 4;
378 unsigned data_words = data_size / 4;
379
380 while (count) {
381 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
382 unsigned nr = nr_data * data_words;
383
384 if (!PUSH_SPACE(push, nr + 9))
385 break;
386
387 BEGIN_NVC0(push, NVC0_M2MF(OFFSET_OUT_HIGH), 2);
388 PUSH_DATAh(push, buf->address + offset);
389 PUSH_DATA (push, buf->address + offset);
390 BEGIN_NVC0(push, NVC0_M2MF(LINE_LENGTH_IN), 2);
391 PUSH_DATA (push, MIN2(size, nr * 4));
392 PUSH_DATA (push, 1);
393 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1);
394 PUSH_DATA (push, 0x100111);
395
396 /* must not be interrupted (trap on QUERY fence, 0x50 works however) */
397 BEGIN_NIC0(push, NVC0_M2MF(DATA), nr);
398 for (i = 0; i < nr_data; i++)
399 PUSH_DATAp(push, data, data_words);
400
401 count -= nr;
402 offset += nr * 4;
403 size -= nr * 4;
404 }
405
406 nvc0_resource_validate(buf, NOUVEAU_BO_WR);
407
408 nouveau_bufctx_reset(nvc0->bufctx, 0);
409 }
410
411 static void
412 nvc0_clear_buffer_push_nve4(struct pipe_context *pipe,
413 struct pipe_resource *res,
414 unsigned offset, unsigned size,
415 const void *data, int data_size)
416 {
417 struct nvc0_context *nvc0 = nvc0_context(pipe);
418 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
419 struct nv04_resource *buf = nv04_resource(res);
420 unsigned i;
421
422 nouveau_bufctx_refn(nvc0->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
423 nouveau_pushbuf_bufctx(push, nvc0->bufctx);
424 nouveau_pushbuf_validate(push);
425
426 unsigned count = (size + 3) / 4;
427 unsigned data_words = data_size / 4;
428
429 while (count) {
430 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
431 unsigned nr = nr_data * data_words;
432
433 if (!PUSH_SPACE(push, nr + 10))
434 break;
435
436 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);
437 PUSH_DATAh(push, buf->address + offset);
438 PUSH_DATA (push, buf->address + offset);
439 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2);
440 PUSH_DATA (push, MIN2(size, nr * 4));
441 PUSH_DATA (push, 1);
442 /* must not be interrupted (trap on QUERY fence, 0x50 works however) */
443 BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), nr + 1);
444 PUSH_DATA (push, 0x1001);
445 for (i = 0; i < nr_data; i++)
446 PUSH_DATAp(push, data, data_words);
447
448 count -= nr;
449 offset += nr * 4;
450 size -= nr * 4;
451 }
452
453 nvc0_resource_validate(buf, NOUVEAU_BO_WR);
454
455 nouveau_bufctx_reset(nvc0->bufctx, 0);
456 }
457
458 static void
459 nvc0_clear_buffer_push(struct pipe_context *pipe,
460 struct pipe_resource *res,
461 unsigned offset, unsigned size,
462 const void *data, int data_size)
463 {
464 struct nvc0_context *nvc0 = nvc0_context(pipe);
465 unsigned tmp;
466
467 if (data_size == 1) {
468 tmp = *(unsigned char *)data;
469 tmp = (tmp << 24) | (tmp << 16) | (tmp << 8) | tmp;
470 data = &tmp;
471 data_size = 4;
472 } else if (data_size == 2) {
473 tmp = *(unsigned short *)data;
474 tmp = (tmp << 16) | tmp;
475 data = &tmp;
476 data_size = 4;
477 }
478
479 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS)
480 nvc0_clear_buffer_push_nvc0(pipe, res, offset, size, data, data_size);
481 else
482 nvc0_clear_buffer_push_nve4(pipe, res, offset, size, data, data_size);
483 }
484
485 static void
486 nvc0_clear_buffer(struct pipe_context *pipe,
487 struct pipe_resource *res,
488 unsigned offset, unsigned size,
489 const void *data, int data_size)
490 {
491 struct nvc0_context *nvc0 = nvc0_context(pipe);
492 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
493 struct nv04_resource *buf = nv04_resource(res);
494 union pipe_color_union color;
495 enum pipe_format dst_fmt;
496 unsigned width, height, elements;
497
498 assert(res->target == PIPE_BUFFER);
499 assert(nouveau_bo_memtype(buf->bo) == 0);
500
501 switch (data_size) {
502 case 16:
503 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
504 memcpy(&color.ui, data, 16);
505 break;
506 case 12:
507 /* RGB32 is not a valid RT format. This will be handled by the pushbuf
508 * uploader.
509 */
510 break;
511 case 8:
512 dst_fmt = PIPE_FORMAT_R32G32_UINT;
513 memcpy(&color.ui, data, 8);
514 memset(&color.ui[2], 0, 8);
515 break;
516 case 4:
517 dst_fmt = PIPE_FORMAT_R32_UINT;
518 memcpy(&color.ui, data, 4);
519 memset(&color.ui[1], 0, 12);
520 break;
521 case 2:
522 dst_fmt = PIPE_FORMAT_R16_UINT;
523 color.ui[0] = util_cpu_to_le32(
524 util_le16_to_cpu(*(unsigned short *)data));
525 memset(&color.ui[1], 0, 12);
526 break;
527 case 1:
528 dst_fmt = PIPE_FORMAT_R8_UINT;
529 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
530 memset(&color.ui[1], 0, 12);
531 break;
532 default:
533 assert(!"Unsupported element size");
534 return;
535 }
536
537 util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
538
539 assert(size % data_size == 0);
540
541 if (data_size == 12) {
542 nvc0_clear_buffer_push(pipe, res, offset, size, data, data_size);
543 return;
544 }
545
546 if (offset & 0xff) {
547 unsigned fixup_size = MIN2(size, align(offset, 0x100) - offset);
548 assert(fixup_size % data_size == 0);
549 nvc0_clear_buffer_push(pipe, res, offset, fixup_size, data, data_size);
550 offset += fixup_size;
551 size -= fixup_size;
552 if (!size)
553 return;
554 }
555
556 elements = size / data_size;
557 height = (elements + 16383) / 16384;
558 width = elements / height;
559 if (height > 1)
560 width &= ~0xff;
561 assert(width > 0);
562
563 if (!PUSH_SPACE(push, 40))
564 return;
565
566 PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
567
568 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
569 PUSH_DATA (push, color.ui[0]);
570 PUSH_DATA (push, color.ui[1]);
571 PUSH_DATA (push, color.ui[2]);
572 PUSH_DATA (push, color.ui[3]);
573 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
574 PUSH_DATA (push, width << 16);
575 PUSH_DATA (push, height << 16);
576
577 IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1);
578
579 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
580 PUSH_DATAh(push, buf->address + offset);
581 PUSH_DATA (push, buf->address + offset);
582 PUSH_DATA (push, align(width * data_size, 0x100));
583 PUSH_DATA (push, height);
584 PUSH_DATA (push, nvc0_format_table[dst_fmt].rt);
585 PUSH_DATA (push, NVC0_3D_RT_TILE_MODE_LINEAR);
586 PUSH_DATA (push, 1);
587 PUSH_DATA (push, 0);
588 PUSH_DATA (push, 0);
589
590 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
591 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
592
593 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
594
595 IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c);
596
597 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
598
599 nvc0_resource_validate(buf, NOUVEAU_BO_WR);
600
601 if (width * height != elements) {
602 offset += width * height * data_size;
603 width = elements - width * height;
604 nvc0_clear_buffer_push(pipe, res, offset, width * data_size,
605 data, data_size);
606 }
607
608 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
609 }
610
611 static void
612 nvc0_clear_depth_stencil(struct pipe_context *pipe,
613 struct pipe_surface *dst,
614 unsigned clear_flags,
615 double depth,
616 unsigned stencil,
617 unsigned dstx, unsigned dsty,
618 unsigned width, unsigned height,
619 bool render_condition_enabled)
620 {
621 struct nvc0_context *nvc0 = nvc0_context(pipe);
622 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
623 struct nv50_miptree *mt = nv50_miptree(dst->texture);
624 struct nv50_surface *sf = nv50_surface(dst);
625 uint32_t mode = 0;
626 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
627 unsigned z;
628
629 assert(dst->texture->target != PIPE_BUFFER);
630
631 if (!PUSH_SPACE(push, 32 + sf->depth))
632 return;
633
634 PUSH_REFN (push, mt->base.bo, mt->base.domain | NOUVEAU_BO_WR);
635
636 if (clear_flags & PIPE_CLEAR_DEPTH) {
637 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
638 PUSH_DATAf(push, depth);
639 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
640 }
641
642 if (clear_flags & PIPE_CLEAR_STENCIL) {
643 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
644 PUSH_DATA (push, stencil & 0xff);
645 mode |= NVC0_3D_CLEAR_BUFFERS_S;
646 }
647
648 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
649 PUSH_DATA (push, ( width << 16) | dstx);
650 PUSH_DATA (push, (height << 16) | dsty);
651
652 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
653 PUSH_DATAh(push, mt->base.address + sf->offset);
654 PUSH_DATA (push, mt->base.address + sf->offset);
655 PUSH_DATA (push, nvc0_format_table[dst->format].rt);
656 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
657 PUSH_DATA (push, mt->layer_stride >> 2);
658 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
659 PUSH_DATA (push, 1);
660 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
661 PUSH_DATA (push, sf->width);
662 PUSH_DATA (push, sf->height);
663 PUSH_DATA (push, (unk << 16) | (dst->u.tex.first_layer + sf->depth));
664 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
665 PUSH_DATA (push, dst->u.tex.first_layer);
666 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
667
668 if (!render_condition_enabled)
669 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
670
671 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
672 for (z = 0; z < sf->depth; ++z) {
673 PUSH_DATA (push, mode |
674 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
675 }
676
677 if (!render_condition_enabled)
678 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
679
680 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
681 }
682
683 void
684 nvc0_clear(struct pipe_context *pipe, unsigned buffers,
685 const struct pipe_scissor_state *scissor_state,
686 const union pipe_color_union *color,
687 double depth, unsigned stencil)
688 {
689 struct nvc0_context *nvc0 = nvc0_context(pipe);
690 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
691 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
692 unsigned i, j, k;
693 uint32_t mode = 0;
694
695 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
696 if (!nvc0_state_validate_3d(nvc0, NVC0_NEW_3D_FRAMEBUFFER))
697 return;
698
699 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
700 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
701 PUSH_DATAf(push, color->f[0]);
702 PUSH_DATAf(push, color->f[1]);
703 PUSH_DATAf(push, color->f[2]);
704 PUSH_DATAf(push, color->f[3]);
705 if (buffers & PIPE_CLEAR_COLOR0)
706 mode =
707 NVC0_3D_CLEAR_BUFFERS_R | NVC0_3D_CLEAR_BUFFERS_G |
708 NVC0_3D_CLEAR_BUFFERS_B | NVC0_3D_CLEAR_BUFFERS_A;
709 }
710
711 if (buffers & PIPE_CLEAR_DEPTH) {
712 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
713 PUSH_DATA (push, fui(depth));
714 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
715 }
716
717 if (buffers & PIPE_CLEAR_STENCIL) {
718 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
719 PUSH_DATA (push, stencil & 0xff);
720 mode |= NVC0_3D_CLEAR_BUFFERS_S;
721 }
722
723 if (mode) {
724 int zs_layers = 0, color0_layers = 0;
725 if (fb->cbufs[0] && (mode & 0x3c))
726 color0_layers = fb->cbufs[0]->u.tex.last_layer -
727 fb->cbufs[0]->u.tex.first_layer + 1;
728 if (fb->zsbuf && (mode & ~0x3c))
729 zs_layers = fb->zsbuf->u.tex.last_layer -
730 fb->zsbuf->u.tex.first_layer + 1;
731
732 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
733 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
734 PUSH_DATA(push, mode | (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
735 }
736 for (k = j; k < zs_layers; k++) {
737 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
738 PUSH_DATA(push, (mode & ~0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
739 }
740 for (k = j; k < color0_layers; k++) {
741 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
742 PUSH_DATA(push, (mode & 0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
743 }
744 }
745
746 for (i = 1; i < fb->nr_cbufs; i++) {
747 struct pipe_surface *sf = fb->cbufs[i];
748 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
749 continue;
750 for (j = 0; j <= sf->u.tex.last_layer - sf->u.tex.first_layer; j++) {
751 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
752 PUSH_DATA (push, (i << 6) | 0x3c |
753 (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
754 }
755 }
756 }
757
758 static void
759 gm200_evaluate_depth_buffer(struct pipe_context *pipe)
760 {
761 struct nvc0_context *nvc0 = nvc0_context(pipe);
762 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
763
764 nvc0_state_validate_3d(nvc0, NVC0_NEW_3D_FRAMEBUFFER);
765 IMMED_NVC0(push, SUBC_3D(0x11fc), 1);
766 }
767
768
769 /* =============================== BLIT CODE ===================================
770 */
771
772 struct nvc0_blitter
773 {
774 struct nvc0_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
775 struct nvc0_program vp;
776
777 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
778
779 mtx_t mutex;
780
781 struct nvc0_screen *screen;
782 };
783
784 struct nvc0_blitctx
785 {
786 struct nvc0_context *nvc0;
787 struct nvc0_program *fp;
788 uint8_t mode;
789 uint16_t color_mask;
790 uint8_t filter;
791 uint8_t render_condition_enable;
792 enum pipe_texture_target target;
793 struct {
794 struct pipe_framebuffer_state fb;
795 struct nvc0_window_rect_stateobj window_rect;
796 struct nvc0_rasterizer_stateobj *rast;
797 struct nvc0_program *vp;
798 struct nvc0_program *tcp;
799 struct nvc0_program *tep;
800 struct nvc0_program *gp;
801 struct nvc0_program *fp;
802 unsigned num_textures[5];
803 unsigned num_samplers[5];
804 struct pipe_sampler_view *texture[2];
805 struct nv50_tsc_entry *sampler[2];
806 unsigned min_samples;
807 uint32_t dirty_3d;
808 } saved;
809 struct nvc0_rasterizer_stateobj rast;
810 };
811
812 static void
813 nvc0_blitter_make_vp(struct nvc0_blitter *blit)
814 {
815 static const uint32_t code_nvc0[] =
816 {
817 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
818 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
819 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
820 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
821 0x00001de7, 0x80000000, /* exit */
822 };
823 static const uint32_t code_nve4[] =
824 {
825 0x00000007, 0x20000000, /* sched */
826 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
827 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
828 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
829 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
830 0x00001de7, 0x80000000, /* exit */
831 };
832 static const uint32_t code_gk110[] =
833 {
834 0x00000000, 0x08000000, /* sched */
835 0x401ffc12, 0x7ec7fc00, /* ld b64 $r4d a[0x80] 0x0 0x0 */
836 0x481ffc02, 0x7ecbfc00, /* ld b96 $r0t a[0x90] 0x0 0x0 */
837 0x381ffc12, 0x7f07fc00, /* st b64 a[0x70] $r4d 0x0 0x0 */
838 0x401ffc02, 0x7f0bfc00, /* st b96 a[0x80] $r0t 0x0 0x0 */
839 0x001c003c, 0x18000000, /* exit */
840 };
841 static const uint32_t code_gm107[] =
842 {
843 0xe4200701, 0x001d0400, /* sched (st 0x1 wr 0x0) (st 0x1 wr 0x1) (st 0x1 wr 0x2) */
844 0x0807ff00, 0xefd87f80, /* ld b32 $r0 a[0x80] 0x0 */
845 0x0847ff01, 0xefd87f80, /* ld b32 $r1 a[0x84] 0x0 */
846 0x0907ff02, 0xefd87f80, /* ld b32 $r2 a[0x90] 0x0 */
847 0xf0200761, 0x003f8400, /* sched (st 0x1 wr 0x3) (st 0x1 wr 0x4) (st 0x1 wt 0x1) */
848 0x0947ff03, 0xefd87f80, /* ld b32 $r3 a[0x94] 0x0 */
849 0x0987ff04, 0xefd87f80, /* ld b32 $r4 a[0x98] 0x0 */
850 0x0707ff00, 0xeff07f80, /* st b32 a[0x70] $r0 0x0 */
851 0xfc2017e1, 0x011f8404, /* sched (st 0x1 wt 0x2) (st 0x1 wt 0x4) (st 0x1 wt 0x8) */
852 0x0747ff01, 0xeff07f80, /* st b32 a[0x74] $r1 0x0 */
853 0x0807ff02, 0xeff07f80, /* st b32 a[0x80] $r2 0x0 */
854 0x0847ff03, 0xeff07f80, /* st b32 a[0x84] $r3 0x0 */
855 0xfde087e1, 0x001f8000, /* sched (st 0x1 wt 0x10) (st 0xf) (st 0x0) */
856 0x0887ff04, 0xeff07f80, /* st b32 a[0x88] $r4 0x0 */
857 0x0007000f, 0xe3000000, /* exit */
858 };
859
860 blit->vp.type = PIPE_SHADER_VERTEX;
861 blit->vp.translated = true;
862 if (blit->screen->base.class_3d >= GM107_3D_CLASS) {
863 blit->vp.code = (uint32_t *)code_gm107; /* const_cast */
864 blit->vp.code_size = sizeof(code_gm107);
865 } else
866 if (blit->screen->base.class_3d >= NVF0_3D_CLASS) {
867 blit->vp.code = (uint32_t *)code_gk110; /* const_cast */
868 blit->vp.code_size = sizeof(code_gk110);
869 } else
870 if (blit->screen->base.class_3d >= NVE4_3D_CLASS) {
871 blit->vp.code = (uint32_t *)code_nve4; /* const_cast */
872 blit->vp.code_size = sizeof(code_nve4);
873 } else {
874 blit->vp.code = (uint32_t *)code_nvc0; /* const_cast */
875 blit->vp.code_size = sizeof(code_nvc0);
876 }
877 blit->vp.num_gprs = 6;
878 blit->vp.vp.edgeflag = PIPE_MAX_ATTRIBS;
879
880 blit->vp.hdr[0] = 0x00020461; /* vertprog magic */
881 blit->vp.hdr[4] = 0x000ff000; /* no outputs read */
882 blit->vp.hdr[6] = 0x00000073; /* a[0x80].xy, a[0x90].xyz */
883 blit->vp.hdr[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
884 }
885
886 static void
887 nvc0_blitter_make_sampler(struct nvc0_blitter *blit)
888 {
889 /* clamp to edge, min/max lod = 0, nearest filtering */
890
891 blit->sampler[0].id = -1;
892
893 blit->sampler[0].tsc[0] = G80_TSC_0_SRGB_CONVERSION |
894 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_U__SHIFT) |
895 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_V__SHIFT) |
896 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_P__SHIFT);
897 blit->sampler[0].tsc[1] =
898 G80_TSC_1_MAG_FILTER_NEAREST |
899 G80_TSC_1_MIN_FILTER_NEAREST |
900 G80_TSC_1_MIP_FILTER_NONE;
901
902 /* clamp to edge, min/max lod = 0, bilinear filtering */
903
904 blit->sampler[1].id = -1;
905
906 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
907 blit->sampler[1].tsc[1] =
908 G80_TSC_1_MAG_FILTER_LINEAR |
909 G80_TSC_1_MIN_FILTER_LINEAR |
910 G80_TSC_1_MIP_FILTER_NONE;
911 }
912
913 static void
914 nvc0_blit_select_fp(struct nvc0_blitctx *ctx, const struct pipe_blit_info *info)
915 {
916 struct nvc0_blitter *blitter = ctx->nvc0->screen->blitter;
917
918 const enum pipe_texture_target ptarg =
919 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
920
921 const unsigned targ = nv50_blit_texture_type(ptarg);
922 const unsigned mode = ctx->mode;
923
924 if (!blitter->fp[targ][mode]) {
925 mtx_lock(&blitter->mutex);
926 if (!blitter->fp[targ][mode])
927 blitter->fp[targ][mode] =
928 nv50_blitter_make_fp(&ctx->nvc0->base.pipe, mode, ptarg);
929 mtx_unlock(&blitter->mutex);
930 }
931 ctx->fp = blitter->fp[targ][mode];
932 }
933
934 static void
935 nvc0_blit_set_dst(struct nvc0_blitctx *ctx,
936 struct pipe_resource *res, unsigned level, unsigned layer,
937 enum pipe_format format)
938 {
939 struct nvc0_context *nvc0 = ctx->nvc0;
940 struct pipe_context *pipe = &nvc0->base.pipe;
941 struct pipe_surface templ;
942
943 if (util_format_is_depth_or_stencil(format))
944 templ.format = nv50_blit_zeta_to_colour_format(format);
945 else
946 templ.format = format;
947
948 templ.u.tex.level = level;
949 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
950
951 if (layer == -1) {
952 templ.u.tex.first_layer = 0;
953 templ.u.tex.last_layer =
954 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
955 }
956
957 nvc0->framebuffer.cbufs[0] = nvc0_miptree_surface_new(pipe, res, &templ);
958 nvc0->framebuffer.nr_cbufs = 1;
959 nvc0->framebuffer.zsbuf = NULL;
960 nvc0->framebuffer.width = nvc0->framebuffer.cbufs[0]->width;
961 nvc0->framebuffer.height = nvc0->framebuffer.cbufs[0]->height;
962 }
963
964 static void
965 nvc0_blit_set_src(struct nvc0_blitctx *ctx,
966 struct pipe_resource *res, unsigned level, unsigned layer,
967 enum pipe_format format, const uint8_t filter)
968 {
969 struct nvc0_context *nvc0 = ctx->nvc0;
970 struct pipe_context *pipe = &nvc0->base.pipe;
971 struct pipe_sampler_view templ;
972 uint32_t flags;
973 unsigned s;
974 enum pipe_texture_target target;
975
976 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
977
978 templ.format = format;
979 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
980 templ.u.tex.first_level = templ.u.tex.last_level = level;
981 templ.swizzle_r = PIPE_SWIZZLE_X;
982 templ.swizzle_g = PIPE_SWIZZLE_Y;
983 templ.swizzle_b = PIPE_SWIZZLE_Z;
984 templ.swizzle_a = PIPE_SWIZZLE_W;
985
986 if (layer == -1) {
987 templ.u.tex.first_layer = 0;
988 templ.u.tex.last_layer =
989 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
990 }
991
992 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
993 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
994 if (filter && res->nr_samples == 8)
995 flags |= NV50_TEXVIEW_FILTER_MSAA8;
996
997 nvc0->textures[4][0] = nvc0_create_texture_view(
998 pipe, res, &templ, flags, target);
999 nvc0->textures[4][1] = NULL;
1000
1001 for (s = 0; s <= 3; ++s)
1002 nvc0->num_textures[s] = 0;
1003 nvc0->num_textures[4] = 1;
1004
1005 templ.format = nv50_zs_to_s_format(format);
1006 if (templ.format != format) {
1007 nvc0->textures[4][1] = nvc0_create_texture_view(
1008 pipe, res, &templ, flags, target);
1009 nvc0->num_textures[4] = 2;
1010 }
1011 }
1012
1013 static void
1014 nvc0_blitctx_prepare_state(struct nvc0_blitctx *blit)
1015 {
1016 struct nouveau_pushbuf *push = blit->nvc0->base.pushbuf;
1017
1018 /* TODO: maybe make this a MACRO (if we need more logic) ? */
1019
1020 if (blit->nvc0->cond_query && !blit->render_condition_enable)
1021 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
1022
1023 /* blend state */
1024 BEGIN_NVC0(push, NVC0_3D(COLOR_MASK(0)), 1);
1025 PUSH_DATA (push, blit->color_mask);
1026 IMMED_NVC0(push, NVC0_3D(BLEND_ENABLE(0)), 0);
1027 IMMED_NVC0(push, NVC0_3D(LOGIC_OP_ENABLE), 0);
1028
1029 /* rasterizer state */
1030 IMMED_NVC0(push, NVC0_3D(FRAG_COLOR_CLAMP_EN), 0);
1031 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 0);
1032 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
1033 PUSH_DATA (push, 0xffff);
1034 PUSH_DATA (push, 0xffff);
1035 PUSH_DATA (push, 0xffff);
1036 PUSH_DATA (push, 0xffff);
1037 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_FRONT), 1);
1038 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_FRONT_FILL);
1039 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_BACK), 1);
1040 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_BACK_FILL);
1041 IMMED_NVC0(push, NVC0_3D(POLYGON_SMOOTH_ENABLE), 0);
1042 IMMED_NVC0(push, NVC0_3D(POLYGON_OFFSET_FILL_ENABLE), 0);
1043 IMMED_NVC0(push, NVC0_3D(POLYGON_STIPPLE_ENABLE), 0);
1044 IMMED_NVC0(push, NVC0_3D(CULL_FACE_ENABLE), 0);
1045
1046 /* zsa state */
1047 IMMED_NVC0(push, NVC0_3D(DEPTH_TEST_ENABLE), 0);
1048 IMMED_NVC0(push, NVC0_3D(DEPTH_BOUNDS_EN), 0);
1049 IMMED_NVC0(push, NVC0_3D(STENCIL_ENABLE), 0);
1050 IMMED_NVC0(push, NVC0_3D(ALPHA_TEST_ENABLE), 0);
1051
1052 /* disable transform feedback */
1053 IMMED_NVC0(push, NVC0_3D(TFB_ENABLE), 0);
1054 }
1055
1056 static void
1057 nvc0_blitctx_pre_blit(struct nvc0_blitctx *ctx,
1058 const struct pipe_blit_info *info)
1059 {
1060 struct nvc0_context *nvc0 = ctx->nvc0;
1061 struct nvc0_blitter *blitter = nvc0->screen->blitter;
1062 int s;
1063
1064 ctx->saved.fb.width = nvc0->framebuffer.width;
1065 ctx->saved.fb.height = nvc0->framebuffer.height;
1066 ctx->saved.fb.samples = nvc0->framebuffer.samples;
1067 ctx->saved.fb.layers = nvc0->framebuffer.layers;
1068 ctx->saved.fb.nr_cbufs = nvc0->framebuffer.nr_cbufs;
1069 ctx->saved.fb.cbufs[0] = nvc0->framebuffer.cbufs[0];
1070 ctx->saved.fb.zsbuf = nvc0->framebuffer.zsbuf;
1071
1072 ctx->saved.rast = nvc0->rast;
1073
1074 ctx->saved.vp = nvc0->vertprog;
1075 ctx->saved.tcp = nvc0->tctlprog;
1076 ctx->saved.tep = nvc0->tevlprog;
1077 ctx->saved.gp = nvc0->gmtyprog;
1078 ctx->saved.fp = nvc0->fragprog;
1079
1080 ctx->saved.min_samples = nvc0->min_samples;
1081 ctx->saved.window_rect = nvc0->window_rect;
1082
1083 nvc0->rast = &ctx->rast;
1084
1085 nvc0->vertprog = &blitter->vp;
1086 nvc0->tctlprog = NULL;
1087 nvc0->tevlprog = NULL;
1088 nvc0->gmtyprog = NULL;
1089 nvc0->fragprog = ctx->fp;
1090
1091 nvc0->window_rect.rects =
1092 MIN2(info->num_window_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
1093 nvc0->window_rect.inclusive = info->window_rectangle_include;
1094 if (nvc0->window_rect.rects)
1095 memcpy(nvc0->window_rect.rect, info->window_rectangles,
1096 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
1097
1098 for (s = 0; s <= 4; ++s) {
1099 ctx->saved.num_textures[s] = nvc0->num_textures[s];
1100 ctx->saved.num_samplers[s] = nvc0->num_samplers[s];
1101 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
1102 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
1103 }
1104 ctx->saved.texture[0] = nvc0->textures[4][0];
1105 ctx->saved.texture[1] = nvc0->textures[4][1];
1106 ctx->saved.sampler[0] = nvc0->samplers[4][0];
1107 ctx->saved.sampler[1] = nvc0->samplers[4][1];
1108
1109 nvc0->samplers[4][0] = &blitter->sampler[ctx->filter];
1110 nvc0->samplers[4][1] = &blitter->sampler[ctx->filter];
1111
1112 for (s = 0; s <= 3; ++s)
1113 nvc0->num_samplers[s] = 0;
1114 nvc0->num_samplers[4] = 2;
1115
1116 nvc0->min_samples = 1;
1117
1118 ctx->saved.dirty_3d = nvc0->dirty_3d;
1119
1120 nvc0->textures_dirty[4] |= 3;
1121 nvc0->samplers_dirty[4] |= 3;
1122
1123 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
1124 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 0));
1125 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 1));
1126
1127 nvc0->dirty_3d = NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_MIN_SAMPLES |
1128 NVC0_NEW_3D_VERTPROG | NVC0_NEW_3D_FRAGPROG |
1129 NVC0_NEW_3D_TCTLPROG | NVC0_NEW_3D_TEVLPROG | NVC0_NEW_3D_GMTYPROG |
1130 NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS | NVC0_NEW_3D_WINDOW_RECTS;
1131 }
1132
1133 static void
1134 nvc0_blitctx_post_blit(struct nvc0_blitctx *blit)
1135 {
1136 struct nvc0_context *nvc0 = blit->nvc0;
1137 int s;
1138
1139 pipe_surface_reference(&nvc0->framebuffer.cbufs[0], NULL);
1140
1141 nvc0->framebuffer.width = blit->saved.fb.width;
1142 nvc0->framebuffer.height = blit->saved.fb.height;
1143 nvc0->framebuffer.samples = blit->saved.fb.samples;
1144 nvc0->framebuffer.layers = blit->saved.fb.layers;
1145 nvc0->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1146 nvc0->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1147 nvc0->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1148
1149 nvc0->rast = blit->saved.rast;
1150
1151 nvc0->vertprog = blit->saved.vp;
1152 nvc0->tctlprog = blit->saved.tcp;
1153 nvc0->tevlprog = blit->saved.tep;
1154 nvc0->gmtyprog = blit->saved.gp;
1155 nvc0->fragprog = blit->saved.fp;
1156
1157 nvc0->min_samples = blit->saved.min_samples;
1158 nvc0->window_rect = blit->saved.window_rect;
1159
1160 pipe_sampler_view_reference(&nvc0->textures[4][0], NULL);
1161 pipe_sampler_view_reference(&nvc0->textures[4][1], NULL);
1162
1163 for (s = 0; s <= 4; ++s) {
1164 nvc0->num_textures[s] = blit->saved.num_textures[s];
1165 nvc0->num_samplers[s] = blit->saved.num_samplers[s];
1166 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
1167 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
1168 }
1169 nvc0->textures[4][0] = blit->saved.texture[0];
1170 nvc0->textures[4][1] = blit->saved.texture[1];
1171 nvc0->samplers[4][0] = blit->saved.sampler[0];
1172 nvc0->samplers[4][1] = blit->saved.sampler[1];
1173
1174 nvc0->textures_dirty[4] |= 3;
1175 nvc0->samplers_dirty[4] |= 3;
1176
1177 if (nvc0->cond_query && !blit->render_condition_enable)
1178 nvc0->base.pipe.render_condition(&nvc0->base.pipe, nvc0->cond_query,
1179 nvc0->cond_cond, nvc0->cond_mode);
1180
1181 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX_TMP);
1182 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
1183 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
1184 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 0));
1185 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 1));
1186 nouveau_scratch_done(&nvc0->base);
1187
1188 nvc0->dirty_3d = blit->saved.dirty_3d |
1189 (NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SCISSOR | NVC0_NEW_3D_SAMPLE_MASK |
1190 NVC0_NEW_3D_RASTERIZER | NVC0_NEW_3D_ZSA | NVC0_NEW_3D_BLEND |
1191 NVC0_NEW_3D_VIEWPORT | NVC0_NEW_3D_WINDOW_RECTS |
1192 NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS |
1193 NVC0_NEW_3D_VERTPROG | NVC0_NEW_3D_FRAGPROG |
1194 NVC0_NEW_3D_TCTLPROG | NVC0_NEW_3D_TEVLPROG | NVC0_NEW_3D_GMTYPROG |
1195 NVC0_NEW_3D_TFB_TARGETS | NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS);
1196 nvc0->scissors_dirty |= 1;
1197 nvc0->viewports_dirty |= 1;
1198
1199 nvc0->base.pipe.set_min_samples(&nvc0->base.pipe, blit->saved.min_samples);
1200 }
1201
1202 static void
1203 nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1204 {
1205 struct nvc0_screen *screen = nvc0->screen;
1206 struct nvc0_blitctx *blit = nvc0->blit;
1207 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1208 struct pipe_resource *src = info->src.resource;
1209 struct pipe_resource *dst = info->dst.resource;
1210 struct nouveau_bo *vtxbuf_bo;
1211 uint32_t stride, length, *vbuf;
1212 uint64_t vtxbuf;
1213 int32_t minx, maxx, miny, maxy;
1214 int32_t i, n;
1215 float x0, x1, y0, y1, z;
1216 float dz;
1217 float x_range, y_range;
1218
1219 blit->mode = nv50_blit_select_mode(info);
1220 blit->color_mask = nv50_blit_derive_color_mask(info);
1221 blit->filter = nv50_blit_get_filter(info);
1222 blit->render_condition_enable = info->render_condition_enable;
1223
1224 nvc0_blit_select_fp(blit, info);
1225 nvc0_blitctx_pre_blit(blit, info);
1226
1227 nvc0_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1228 nvc0_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1229 blit->filter);
1230
1231 nvc0_blitctx_prepare_state(blit);
1232
1233 nvc0_state_validate_3d(nvc0, ~0);
1234
1235 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1236 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1237
1238 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1239 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1240
1241 x1 = x0 + 32768.0f * x_range;
1242 y1 = y0 + 32768.0f * y_range;
1243
1244 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1245 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1246 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1247 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1248
1249 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1250 z = (float)info->src.box.z;
1251 if (nv50_miptree(src)->layout_3d)
1252 z += 0.5f * dz;
1253
1254 if (src->last_level > 0) {
1255 /* If there are mip maps, GPU always assumes normalized coordinates. */
1256 const unsigned l = info->src.level;
1257 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1258 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1259 x0 /= fh;
1260 x1 /= fh;
1261 y0 /= fv;
1262 y1 /= fv;
1263 if (nv50_miptree(src)->layout_3d) {
1264 z /= u_minify(src->depth0, l);
1265 dz /= u_minify(src->depth0, l);
1266 }
1267 }
1268
1269 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
1270 IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 |
1271 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1);
1272 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
1273 PUSH_DATA (push, nvc0->framebuffer.width << 16);
1274 PUSH_DATA (push, nvc0->framebuffer.height << 16);
1275
1276 /* Draw a large triangle in screen coordinates covering the whole
1277 * render target, with scissors defining the destination region.
1278 * The vertex is supplied with non-normalized texture coordinates
1279 * arranged in a way to yield the desired offset and scale.
1280 *
1281 * Note that while the source texture is presented to the sampler as
1282 * non-MSAA (even if it is), the destination texture is treated as MSAA for
1283 * rendering. This means that
1284 * - destination coordinates shouldn't be scaled
1285 * - without per-sample rendering, the target will be a solid-fill for all
1286 * of the samples
1287 *
1288 * The last point implies that this process is very bad for 1:1 blits, as
1289 * well as scaled blits between MSAA surfaces. This works fine for
1290 * upscaling and downscaling though. The 1:1 blits should ideally be
1291 * handled by the 2d engine, which can do it perfectly.
1292 */
1293
1294 minx = info->dst.box.x;
1295 maxx = info->dst.box.x + info->dst.box.width;
1296 miny = info->dst.box.y;
1297 maxy = info->dst.box.y + info->dst.box.height;
1298 if (info->scissor_enable) {
1299 minx = MAX2(minx, info->scissor.minx);
1300 maxx = MIN2(maxx, info->scissor.maxx);
1301 miny = MAX2(miny, info->scissor.miny);
1302 maxy = MIN2(maxy, info->scissor.maxy);
1303 }
1304 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
1305 PUSH_DATA (push, (maxx << 16) | minx);
1306 PUSH_DATA (push, (maxy << 16) | miny);
1307
1308 stride = (3 + 2) * 4;
1309 length = stride * 3 * info->dst.box.depth;
1310
1311 vbuf = nouveau_scratch_get(&nvc0->base, length, &vtxbuf, &vtxbuf_bo);
1312 if (!vbuf) {
1313 assert(vbuf);
1314 return;
1315 }
1316
1317 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP,
1318 NOUVEAU_BO_GART | NOUVEAU_BO_RD, vtxbuf_bo);
1319 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT,
1320 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD, screen->text);
1321 nouveau_pushbuf_validate(push);
1322
1323 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 4);
1324 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | stride <<
1325 NVC0_3D_VERTEX_ARRAY_FETCH_STRIDE__SHIFT);
1326 PUSH_DATAh(push, vtxbuf);
1327 PUSH_DATA (push, vtxbuf);
1328 PUSH_DATA (push, 0);
1329 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(0)), 2);
1330 PUSH_DATAh(push, vtxbuf + length - 1);
1331 PUSH_DATA (push, vtxbuf + length - 1);
1332
1333 n = MAX2(2, nvc0->state.num_vtxelts);
1334
1335 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
1336 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1337 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32 | 0x00 <<
1338 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1339 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1340 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32_32 | 0x08 <<
1341 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1342 for (i = 2; i < n; i++) {
1343 PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1344 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 |
1345 NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
1346 }
1347 for (i = 1; i < n; ++i)
1348 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
1349 if (nvc0->state.instance_elts) {
1350 nvc0->state.instance_elts = 0;
1351 BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
1352 PUSH_DATA (push, n);
1353 PUSH_DATA (push, 0);
1354 }
1355 nvc0->state.num_vtxelts = 2;
1356
1357 if (nvc0->state.prim_restart) {
1358 IMMED_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 0);
1359 nvc0->state.prim_restart = 0;
1360 }
1361
1362 if (nvc0->state.index_bias) {
1363 IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
1364 IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
1365 nvc0->state.index_bias = 0;
1366 }
1367
1368 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1369 if (info->dst.box.z + i) {
1370 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1371 PUSH_DATA (push, info->dst.box.z + i);
1372 }
1373
1374 *(vbuf++) = fui(0.0f);
1375 *(vbuf++) = fui(0.0f);
1376 *(vbuf++) = fui(x0);
1377 *(vbuf++) = fui(y0);
1378 *(vbuf++) = fui(z);
1379
1380 *(vbuf++) = fui(32768.0f);
1381 *(vbuf++) = fui(0.0f);
1382 *(vbuf++) = fui(x1);
1383 *(vbuf++) = fui(y0);
1384 *(vbuf++) = fui(z);
1385
1386 *(vbuf++) = fui(0.0f);
1387 *(vbuf++) = fui(32768.0f);
1388 *(vbuf++) = fui(x0);
1389 *(vbuf++) = fui(y1);
1390 *(vbuf++) = fui(z);
1391
1392 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL),
1393 NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1394 BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
1395 PUSH_DATA (push, i * 3);
1396 PUSH_DATA (push, 3);
1397 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
1398 }
1399 if (info->dst.box.z + info->dst.box.depth - 1)
1400 IMMED_NVC0(push, NVC0_3D(LAYER), 0);
1401
1402 nvc0_blitctx_post_blit(blit);
1403
1404 /* restore viewport transform */
1405 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1406 }
1407
1408 static void
1409 nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1410 {
1411 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1412 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1413 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1414 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1415 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1416 const int dz = info->dst.box.z;
1417 const int sz = info->src.box.z;
1418 uint32_t dstw, dsth;
1419 int32_t dstx, dsty;
1420 int64_t srcx, srcy;
1421 int64_t du_dx, dv_dy;
1422 int i;
1423 uint32_t mode;
1424 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1425 bool b;
1426
1427 mode = nv50_blit_get_filter(info) ?
1428 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1429 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1430 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1431 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1432
1433 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1434 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1435
1436 b = info->dst.format == info->src.format;
1437 nvc0_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1438 nvc0_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1439
1440 if (info->scissor_enable) {
1441 BEGIN_NVC0(push, NVC0_2D(CLIP_X), 5);
1442 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1443 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1444 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1445 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1446 PUSH_DATA (push, 1); /* enable */
1447 }
1448
1449 if (nvc0->cond_query && info->render_condition_enable)
1450 IMMED_NVC0(push, NVC0_2D(COND_MODE), nvc0->cond_condmode);
1451
1452 if (mask != 0xffffffff) {
1453 IMMED_NVC0(push, NVC0_2D(ROP), 0xca); /* DPSDxax */
1454 IMMED_NVC0(push, NVC0_2D(PATTERN_COLOR_FORMAT),
1455 NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1456 BEGIN_NVC0(push, NVC0_2D(PATTERN_BITMAP_COLOR(0)), 4);
1457 PUSH_DATA (push, 0x00000000);
1458 PUSH_DATA (push, mask);
1459 PUSH_DATA (push, 0xffffffff);
1460 PUSH_DATA (push, 0xffffffff);
1461 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_ROP);
1462 } else
1463 if (info->src.format != info->dst.format) {
1464 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1465 info->src.format == PIPE_FORMAT_R8_SNORM ||
1466 info->src.format == PIPE_FORMAT_R16_UNORM ||
1467 info->src.format == PIPE_FORMAT_R16_SNORM ||
1468 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1469 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1470 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1471 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1472 PUSH_DATA (push, mask);
1473 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1474 } else
1475 if (info->src.format == PIPE_FORMAT_A8_UNORM) {
1476 mask = 0xff000000;
1477 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1478 PUSH_DATA (push, mask);
1479 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1480 }
1481 }
1482
1483 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1484 /* ms_x is always >= ms_y */
1485 du_dx <<= src->ms_x - dst->ms_x;
1486 dv_dy <<= src->ms_y - dst->ms_y;
1487 } else {
1488 du_dx >>= dst->ms_x - src->ms_x;
1489 dv_dy >>= dst->ms_y - src->ms_y;
1490 }
1491
1492 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1493 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1494
1495 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1496 /* center src coorinates for proper MS resolve filtering */
1497 srcx += (int64_t)1 << (src->ms_x + 31);
1498 srcy += (int64_t)1 << (src->ms_y + 31);
1499 }
1500
1501 dstx = info->dst.box.x << dst->ms_x;
1502 dsty = info->dst.box.y << dst->ms_y;
1503
1504 dstw = info->dst.box.width << dst->ms_x;
1505 dsth = info->dst.box.height << dst->ms_y;
1506
1507 if (dstx < 0) {
1508 dstw += dstx;
1509 srcx -= du_dx * dstx;
1510 dstx = 0;
1511 }
1512 if (dsty < 0) {
1513 dsth += dsty;
1514 srcy -= dv_dy * dsty;
1515 dsty = 0;
1516 }
1517
1518 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), mode);
1519 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
1520 PUSH_DATA (push, dstx);
1521 PUSH_DATA (push, dsty);
1522 PUSH_DATA (push, dstw);
1523 PUSH_DATA (push, dsth);
1524 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
1525 PUSH_DATA (push, du_dx);
1526 PUSH_DATA (push, du_dx >> 32);
1527 PUSH_DATA (push, dv_dy);
1528 PUSH_DATA (push, dv_dy >> 32);
1529
1530 BCTX_REFN(nvc0->bufctx, 2D, &dst->base, WR);
1531 BCTX_REFN(nvc0->bufctx, 2D, &src->base, RD);
1532 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
1533 if (nouveau_pushbuf_validate(nvc0->base.pushbuf))
1534 return;
1535
1536 for (i = 0; i < info->dst.box.depth; ++i) {
1537 if (i > 0) {
1538 /* no scaling in z-direction possible for eng2d blits */
1539 if (dst->layout_3d) {
1540 BEGIN_NVC0(push, NVC0_2D(DST_LAYER), 1);
1541 PUSH_DATA (push, info->dst.box.z + i);
1542 } else {
1543 const unsigned z = info->dst.box.z + i;
1544 const uint64_t address = dst->base.address +
1545 dst->level[info->dst.level].offset +
1546 z * dst->layer_stride;
1547 BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
1548 PUSH_DATAh(push, address);
1549 PUSH_DATA (push, address);
1550 }
1551 if (src->layout_3d) {
1552 /* not possible because of depth tiling */
1553 assert(0);
1554 } else {
1555 const unsigned z = info->src.box.z + i;
1556 const uint64_t address = src->base.address +
1557 src->level[info->src.level].offset +
1558 z * src->layer_stride;
1559 BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
1560 PUSH_DATAh(push, address);
1561 PUSH_DATA (push, address);
1562 }
1563 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1564 PUSH_DATA (push, srcy >> 32);
1565 } else {
1566 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
1567 PUSH_DATA (push, srcx);
1568 PUSH_DATA (push, srcx >> 32);
1569 PUSH_DATA (push, srcy);
1570 PUSH_DATA (push, srcy >> 32);
1571 }
1572 }
1573 nvc0_resource_validate(&dst->base, NOUVEAU_BO_WR);
1574 nvc0_resource_validate(&src->base, NOUVEAU_BO_RD);
1575
1576 nouveau_bufctx_reset(nvc0->bufctx, NVC0_BIND_2D);
1577
1578 if (info->scissor_enable)
1579 IMMED_NVC0(push, NVC0_2D(CLIP_ENABLE), 0);
1580 if (mask != 0xffffffff)
1581 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_SRCCOPY);
1582 if (nvc0->cond_query && info->render_condition_enable)
1583 IMMED_NVC0(push, NVC0_2D(COND_MODE), NV50_2D_COND_MODE_ALWAYS);
1584 }
1585
1586 static void
1587 nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1588 {
1589 struct nvc0_context *nvc0 = nvc0_context(pipe);
1590 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1591 bool eng3d = false;
1592
1593 if (info->src.box.width == 0 || info->src.box.height == 0 ||
1594 info->dst.box.width == 0 || info->dst.box.height == 0) {
1595 pipe_debug_message(&nvc0->base.debug, ERROR,
1596 "Blit with zero-size src or dst box");
1597 return;
1598 }
1599
1600 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1601 if (!(info->mask & PIPE_MASK_ZS))
1602 return;
1603 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1604 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1605 eng3d = true;
1606 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1607 eng3d = true;
1608 } else {
1609 if (!(info->mask & PIPE_MASK_RGBA))
1610 return;
1611 if (info->mask != PIPE_MASK_RGBA)
1612 eng3d = true;
1613 }
1614
1615 if (nv50_miptree(info->src.resource)->layout_3d) {
1616 eng3d = true;
1617 } else
1618 if (info->src.box.depth != info->dst.box.depth) {
1619 eng3d = true;
1620 debug_printf("blit: cannot filter array or cube textures in z direction");
1621 }
1622
1623 if (!eng3d && info->dst.format != info->src.format) {
1624 if (!nv50_2d_dst_format_faithful(info->dst.format)) {
1625 eng3d = true;
1626 } else
1627 if (!nv50_2d_src_format_faithful(info->src.format)) {
1628 if (!util_format_is_luminance(info->src.format)) {
1629 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1630 eng3d = true;
1631 else
1632 if (util_format_is_intensity(info->src.format))
1633 eng3d = info->src.format != PIPE_FORMAT_I8_UNORM;
1634 else
1635 if (util_format_is_alpha(info->src.format))
1636 eng3d = info->src.format != PIPE_FORMAT_A8_UNORM;
1637 else
1638 if (util_format_is_srgb(info->dst.format) &&
1639 util_format_get_nr_components(info->src.format) == 1)
1640 eng3d = true;
1641 else
1642 eng3d = !nv50_2d_format_supported(info->src.format);
1643 }
1644 } else
1645 if (util_format_is_luminance_alpha(info->src.format))
1646 eng3d = true;
1647 }
1648
1649 if (info->src.resource->nr_samples == 8 &&
1650 info->dst.resource->nr_samples <= 1)
1651 eng3d = true;
1652 #if 0
1653 /* FIXME: can't make this work with eng2d anymore, at least not on nv50 */
1654 if (info->src.resource->nr_samples > 1 ||
1655 info->dst.resource->nr_samples > 1)
1656 eng3d = true;
1657 #endif
1658 /* FIXME: find correct src coordinates adjustments */
1659 if ((info->src.box.width != info->dst.box.width &&
1660 info->src.box.width != -info->dst.box.width) ||
1661 (info->src.box.height != info->dst.box.height &&
1662 info->src.box.height != -info->dst.box.height))
1663 eng3d = true;
1664
1665 if (info->num_window_rectangles > 0 || info->window_rectangle_include)
1666 eng3d = true;
1667
1668 if (nvc0->screen->num_occlusion_queries_active)
1669 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 0);
1670
1671 if (!eng3d)
1672 nvc0_blit_eng2d(nvc0, info);
1673 else
1674 nvc0_blit_3d(nvc0, info);
1675
1676 if (nvc0->screen->num_occlusion_queries_active)
1677 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 1);
1678
1679 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_blit_count, 1);
1680 }
1681
1682 static void
1683 nvc0_flush_resource(struct pipe_context *ctx,
1684 struct pipe_resource *resource)
1685 {
1686 }
1687
1688 bool
1689 nvc0_blitter_create(struct nvc0_screen *screen)
1690 {
1691 screen->blitter = CALLOC_STRUCT(nvc0_blitter);
1692 if (!screen->blitter) {
1693 NOUVEAU_ERR("failed to allocate blitter struct\n");
1694 return false;
1695 }
1696 screen->blitter->screen = screen;
1697
1698 (void) mtx_init(&screen->blitter->mutex, mtx_plain);
1699
1700 nvc0_blitter_make_vp(screen->blitter);
1701 nvc0_blitter_make_sampler(screen->blitter);
1702
1703 return true;
1704 }
1705
1706 void
1707 nvc0_blitter_destroy(struct nvc0_screen *screen)
1708 {
1709 struct nvc0_blitter *blitter = screen->blitter;
1710 unsigned i, m;
1711
1712 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1713 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1714 struct nvc0_program *prog = blitter->fp[i][m];
1715 if (prog) {
1716 nvc0_program_destroy(NULL, prog);
1717 FREE((void *)prog->pipe.tokens);
1718 FREE(prog);
1719 }
1720 }
1721 }
1722
1723 mtx_destroy(&blitter->mutex);
1724 FREE(blitter);
1725 }
1726
1727 bool
1728 nvc0_blitctx_create(struct nvc0_context *nvc0)
1729 {
1730 nvc0->blit = CALLOC_STRUCT(nvc0_blitctx);
1731 if (!nvc0->blit) {
1732 NOUVEAU_ERR("failed to allocate blit context\n");
1733 return false;
1734 }
1735
1736 nvc0->blit->nvc0 = nvc0;
1737
1738 nvc0->blit->rast.pipe.half_pixel_center = 1;
1739
1740 return true;
1741 }
1742
1743 void
1744 nvc0_blitctx_destroy(struct nvc0_context *nvc0)
1745 {
1746 FREE(nvc0->blit);
1747 }
1748
1749 void
1750 nvc0_init_surface_functions(struct nvc0_context *nvc0)
1751 {
1752 struct pipe_context *pipe = &nvc0->base.pipe;
1753
1754 pipe->resource_copy_region = nvc0_resource_copy_region;
1755 pipe->blit = nvc0_blit;
1756 pipe->flush_resource = nvc0_flush_resource;
1757 pipe->clear_render_target = nvc0_clear_render_target;
1758 pipe->clear_depth_stencil = nvc0_clear_depth_stencil;
1759 pipe->clear_texture = nv50_clear_texture;
1760 pipe->clear_buffer = nvc0_clear_buffer;
1761 if (nvc0->screen->base.class_3d >= GM200_3D_CLASS)
1762 pipe->evaluate_depth_buffer = gm200_evaluate_depth_buffer;
1763 }