1 #include "pipe/p_context.h"
2 #include "pipe/p_format.h"
3 #include "util/u_memory.h"
5 #include "nouveau/nouveau_winsys.h"
6 #include "nouveau/nouveau_util.h"
7 #include "nv04_surface_2d.h"
10 nv04_surface_format(enum pipe_format format
)
13 case PIPE_FORMAT_A8_UNORM
:
14 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8
;
15 case PIPE_FORMAT_R16_SNORM
:
16 case PIPE_FORMAT_R5G6B5_UNORM
:
17 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5
;
18 case PIPE_FORMAT_X8R8G8B8_UNORM
:
19 case PIPE_FORMAT_A8R8G8B8_UNORM
:
20 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8
;
21 case PIPE_FORMAT_Z24S8_UNORM
:
22 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32
;
29 nv04_rect_format(enum pipe_format format
)
32 case PIPE_FORMAT_A8_UNORM
:
33 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8
;
34 case PIPE_FORMAT_R5G6B5_UNORM
:
35 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5
;
36 case PIPE_FORMAT_A8R8G8B8_UNORM
:
37 case PIPE_FORMAT_Z24S8_UNORM
:
38 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8
;
45 nv04_scaled_image_format(enum pipe_format format
)
48 case PIPE_FORMAT_A1R5G5B5_UNORM
:
49 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5
;
50 case PIPE_FORMAT_A8R8G8B8_UNORM
:
51 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8
;
52 case PIPE_FORMAT_X8R8G8B8_UNORM
:
53 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8
;
54 case PIPE_FORMAT_R5G6B5_UNORM
:
55 case PIPE_FORMAT_R16_SNORM
:
56 return NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5
;
62 static INLINE
unsigned
63 nv04_swizzle_bits(unsigned x
, unsigned y
)
65 unsigned u
= (x
& 0x001) << 0 |
78 unsigned v
= (y
& 0x001) << 1 |
94 nv04_surface_copy_swizzle(struct nv04_surface_2d
*ctx
,
95 struct pipe_surface
*dst
, int dx
, int dy
,
96 struct pipe_surface
*src
, int sx
, int sy
,
99 struct nouveau_channel
*chan
= ctx
->nvws
->channel
;
100 struct nouveau_grobj
*swzsurf
= ctx
->swzsurf
;
101 struct nouveau_grobj
*sifm
= ctx
->sifm
;
102 struct nouveau_bo
*src_bo
= ctx
->nvws
->get_bo(ctx
->buf(src
));
103 struct nouveau_bo
*dst_bo
= ctx
->nvws
->get_bo(ctx
->buf(dst
));
104 const unsigned max_w
= 1024;
105 const unsigned max_h
= 1024;
106 const unsigned sub_w
= w
> max_w
? max_w
: w
;
107 const unsigned sub_h
= h
> max_h
? max_h
: h
;
112 assert(!(w
& (w
- 1)) && !(h
& (h
- 1)));
114 BEGIN_RING(chan
, swzsurf
, NV04_SWIZZLED_SURFACE_DMA_IMAGE
, 1);
115 OUT_RELOCo(chan
, dst_bo
,
116 NOUVEAU_BO_GART
| NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
118 BEGIN_RING(chan
, swzsurf
, NV04_SWIZZLED_SURFACE_FORMAT
, 1);
119 OUT_RING (chan
, nv04_surface_format(dst
->format
) |
120 log2i(w
) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT
|
121 log2i(h
) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT
);
123 BEGIN_RING(chan
, sifm
, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE
, 1);
124 OUT_RELOCo(chan
, src_bo
,
125 NOUVEAU_BO_GART
| NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
126 BEGIN_RING(chan
, sifm
, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE
, 1);
127 OUT_RING (chan
, swzsurf
->handle
);
129 for (cy
= 0; cy
< h
; cy
+= sub_h
) {
130 for (cx
= 0; cx
< w
; cx
+= sub_w
) {
131 BEGIN_RING(chan
, swzsurf
, NV04_SWIZZLED_SURFACE_OFFSET
, 1);
132 OUT_RELOCl(chan
, dst_bo
, dst
->offset
+ nv04_swizzle_bits(cx
, cy
) *
133 dst
->block
.size
, NOUVEAU_BO_GART
|
134 NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
136 BEGIN_RING(chan
, sifm
, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION
, 9);
137 OUT_RING (chan
, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE
);
138 OUT_RING (chan
, nv04_scaled_image_format(src
->format
));
139 OUT_RING (chan
, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY
);
141 OUT_RING (chan
, sub_h
<< 16 | sub_w
);
143 OUT_RING (chan
, sub_h
<< 16 | sub_w
);
144 OUT_RING (chan
, 1 << 20);
145 OUT_RING (chan
, 1 << 20);
147 BEGIN_RING(chan
, sifm
, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE
, 4);
148 OUT_RING (chan
, sub_h
<< 16 | sub_w
);
149 OUT_RING (chan
, src
->stride
|
150 NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER
|
151 NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE
);
152 OUT_RELOCl(chan
, src_bo
, src
->offset
+ cy
* src
->stride
+
153 cx
* src
->block
.size
, NOUVEAU_BO_GART
|
154 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
163 nv04_surface_copy_m2mf(struct nv04_surface_2d
*ctx
,
164 struct pipe_surface
*dst
, int dx
, int dy
,
165 struct pipe_surface
*src
, int sx
, int sy
, int w
, int h
)
167 struct nouveau_channel
*chan
= ctx
->nvws
->channel
;
168 struct nouveau_grobj
*m2mf
= ctx
->m2mf
;
169 struct nouveau_bo
*src_bo
= ctx
->nvws
->get_bo(ctx
->buf(src
));
170 struct nouveau_bo
*dst_bo
= ctx
->nvws
->get_bo(ctx
->buf(dst
));
171 unsigned dst_offset
, src_offset
;
173 dst_offset
= dst
->offset
+ (dy
* dst
->stride
) + (dx
* dst
->block
.size
);
174 src_offset
= src
->offset
+ (sy
* src
->stride
) + (sx
* src
->block
.size
);
176 WAIT_RING (chan
, 3 + ((h
/ 2047) + 1) * 9);
177 BEGIN_RING(chan
, m2mf
, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN
, 2);
178 OUT_RELOCo(chan
, src_bo
,
179 NOUVEAU_BO_GART
| NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
180 OUT_RELOCo(chan
, dst_bo
,
181 NOUVEAU_BO_GART
| NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
184 int count
= (h
> 2047) ? 2047 : h
;
186 BEGIN_RING(chan
, m2mf
, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN
, 8);
187 OUT_RELOCl(chan
, src_bo
, src_offset
,
188 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
);
189 OUT_RELOCl(chan
, dst_bo
, dst_offset
,
190 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_WR
);
191 OUT_RING (chan
, src
->stride
);
192 OUT_RING (chan
, dst
->stride
);
193 OUT_RING (chan
, w
* src
->block
.size
);
194 OUT_RING (chan
, count
);
195 OUT_RING (chan
, 0x0101);
199 src_offset
+= src
->stride
* count
;
200 dst_offset
+= dst
->stride
* count
;
207 nv04_surface_copy_blit(struct nv04_surface_2d
*ctx
, struct pipe_surface
*dst
,
208 int dx
, int dy
, struct pipe_surface
*src
, int sx
, int sy
,
211 struct nouveau_channel
*chan
= ctx
->nvws
->channel
;
212 struct nouveau_grobj
*surf2d
= ctx
->surf2d
;
213 struct nouveau_grobj
*blit
= ctx
->blit
;
214 struct nouveau_bo
*src_bo
= ctx
->nvws
->get_bo(ctx
->buf(src
));
215 struct nouveau_bo
*dst_bo
= ctx
->nvws
->get_bo(ctx
->buf(dst
));
218 format
= nv04_surface_format(dst
->format
);
222 WAIT_RING (chan
, 12);
223 BEGIN_RING(chan
, surf2d
, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE
, 2);
224 OUT_RELOCo(chan
, src_bo
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
225 OUT_RELOCo(chan
, dst_bo
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
226 BEGIN_RING(chan
, surf2d
, NV04_CONTEXT_SURFACES_2D_FORMAT
, 4);
227 OUT_RING (chan
, format
);
228 OUT_RING (chan
, (dst
->stride
<< 16) | src
->stride
);
229 OUT_RELOCl(chan
, src_bo
, src
->offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
230 OUT_RELOCl(chan
, dst_bo
, dst
->offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
232 BEGIN_RING(chan
, blit
, 0x0300, 3);
233 OUT_RING (chan
, (sy
<< 16) | sx
);
234 OUT_RING (chan
, (dy
<< 16) | dx
);
235 OUT_RING (chan
, ( h
<< 16) | w
);
241 nv04_surface_copy(struct nv04_surface_2d
*ctx
, struct pipe_surface
*dst
,
242 int dx
, int dy
, struct pipe_surface
*src
, int sx
, int sy
,
245 int src_linear
= src
->texture
->tex_usage
& NOUVEAU_TEXTURE_USAGE_LINEAR
;
246 int dst_linear
= dst
->texture
->tex_usage
& NOUVEAU_TEXTURE_USAGE_LINEAR
;
248 assert(src
->format
== dst
->format
);
250 /* Setup transfer to swizzle the texture to vram if needed */
251 if (src_linear
&& !dst_linear
&& w
> 1 && h
> 1) {
252 nv04_surface_copy_swizzle(ctx
, dst
, dx
, dy
, src
, sx
, sy
, w
, h
);
256 /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
257 * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
259 if ((src
->offset
& 63) || (dst
->offset
& 63) ||
260 (src
->stride
& 63) || (dst
->stride
& 63)) {
261 nv04_surface_copy_m2mf(ctx
, dst
, dx
, dy
, src
, sx
, sy
, w
, h
);
265 nv04_surface_copy_blit(ctx
, dst
, dx
, dy
, src
, sx
, sy
, w
, h
);
269 nv04_surface_fill(struct nv04_surface_2d
*ctx
, struct pipe_surface
*dst
,
270 int dx
, int dy
, int w
, int h
, unsigned value
)
272 struct nouveau_channel
*chan
= ctx
->nvws
->channel
;
273 struct nouveau_grobj
*surf2d
= ctx
->surf2d
;
274 struct nouveau_grobj
*rect
= ctx
->rect
;
275 struct nouveau_bo
*dst_bo
= ctx
->nvws
->get_bo(ctx
->buf(dst
));
276 int cs2d_format
, gdirect_format
;
278 cs2d_format
= nv04_surface_format(dst
->format
);
279 assert(cs2d_format
>= 0);
281 gdirect_format
= nv04_rect_format(dst
->format
);
282 assert(gdirect_format
>= 0);
284 WAIT_RING (chan
, 16);
285 BEGIN_RING(chan
, surf2d
, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE
, 2);
286 OUT_RELOCo(chan
, dst_bo
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
287 OUT_RELOCo(chan
, dst_bo
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
288 BEGIN_RING(chan
, surf2d
, NV04_CONTEXT_SURFACES_2D_FORMAT
, 4);
289 OUT_RING (chan
, cs2d_format
);
290 OUT_RING (chan
, (dst
->stride
<< 16) | dst
->stride
);
291 OUT_RELOCl(chan
, dst_bo
, dst
->offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
292 OUT_RELOCl(chan
, dst_bo
, dst
->offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
294 BEGIN_RING(chan
, rect
, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT
, 1);
295 OUT_RING (chan
, gdirect_format
);
296 BEGIN_RING(chan
, rect
, NV04_GDI_RECTANGLE_TEXT_COLOR1_A
, 1);
297 OUT_RING (chan
, value
);
298 BEGIN_RING(chan
, rect
,
299 NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
300 OUT_RING (chan
, (dx
<< 16) | dy
);
301 OUT_RING (chan
, ( w
<< 16) | h
);
305 nv04_surface_2d_takedown(struct nv04_surface_2d
**pctx
)
307 struct nv04_surface_2d
*ctx
;
314 nouveau_notifier_free(&ctx
->ntfy
);
315 nouveau_grobj_free(&ctx
->m2mf
);
316 nouveau_grobj_free(&ctx
->surf2d
);
317 nouveau_grobj_free(&ctx
->swzsurf
);
318 nouveau_grobj_free(&ctx
->rect
);
319 nouveau_grobj_free(&ctx
->blit
);
320 nouveau_grobj_free(&ctx
->sifm
);
325 struct nv04_surface_2d
*
326 nv04_surface_2d_init(struct nouveau_winsys
*nvws
)
328 struct nv04_surface_2d
*ctx
= CALLOC_STRUCT(nv04_surface_2d
);
329 struct nouveau_channel
*chan
= nvws
->channel
;
330 unsigned handle
= 0x88000000, class;
336 ret
= nouveau_notifier_alloc(chan
, handle
++, 1, &ctx
->ntfy
);
338 nv04_surface_2d_takedown(&ctx
);
342 ret
= nouveau_grobj_alloc(chan
, handle
++, 0x0039, &ctx
->m2mf
);
344 nv04_surface_2d_takedown(&ctx
);
348 BEGIN_RING(chan
, ctx
->m2mf
, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY
, 1);
349 OUT_RING (chan
, ctx
->ntfy
->handle
);
351 if (chan
->device
->chipset
< 0x10)
352 class = NV04_CONTEXT_SURFACES_2D
;
354 class = NV10_CONTEXT_SURFACES_2D
;
356 ret
= nouveau_grobj_alloc(chan
, handle
++, class, &ctx
->surf2d
);
358 nv04_surface_2d_takedown(&ctx
);
362 BEGIN_RING(chan
, ctx
->surf2d
,
363 NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE
, 2);
364 OUT_RING (chan
, chan
->vram
->handle
);
365 OUT_RING (chan
, chan
->vram
->handle
);
367 if (chan
->device
->chipset
< 0x10)
368 class = NV04_IMAGE_BLIT
;
370 class = NV12_IMAGE_BLIT
;
372 ret
= nouveau_grobj_alloc(chan
, handle
++, class, &ctx
->blit
);
374 nv04_surface_2d_takedown(&ctx
);
378 BEGIN_RING(chan
, ctx
->blit
, NV04_IMAGE_BLIT_DMA_NOTIFY
, 1);
379 OUT_RING (chan
, ctx
->ntfy
->handle
);
380 BEGIN_RING(chan
, ctx
->blit
, NV04_IMAGE_BLIT_SURFACE
, 1);
381 OUT_RING (chan
, ctx
->surf2d
->handle
);
382 BEGIN_RING(chan
, ctx
->blit
, NV04_IMAGE_BLIT_OPERATION
, 1);
383 OUT_RING (chan
, NV04_IMAGE_BLIT_OPERATION_SRCCOPY
);
385 ret
= nouveau_grobj_alloc(chan
, handle
++, NV04_GDI_RECTANGLE_TEXT
,
388 nv04_surface_2d_takedown(&ctx
);
392 BEGIN_RING(chan
, ctx
->rect
, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY
, 1);
393 OUT_RING (chan
, ctx
->ntfy
->handle
);
394 BEGIN_RING(chan
, ctx
->rect
, NV04_GDI_RECTANGLE_TEXT_SURFACE
, 1);
395 OUT_RING (chan
, ctx
->surf2d
->handle
);
396 BEGIN_RING(chan
, ctx
->rect
, NV04_GDI_RECTANGLE_TEXT_OPERATION
, 1);
397 OUT_RING (chan
, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY
);
398 BEGIN_RING(chan
, ctx
->rect
,
399 NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT
, 1);
400 OUT_RING (chan
, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE
);
402 switch (chan
->device
->chipset
& 0xf0) {
405 class = NV04_SWIZZLED_SURFACE
;
408 class = NV20_SWIZZLED_SURFACE
;
411 class = NV30_SWIZZLED_SURFACE
;
415 class = NV40_SWIZZLED_SURFACE
;
418 /* Famous last words: this really can't happen.. */
423 ret
= nouveau_grobj_alloc(chan
, handle
++, class, &ctx
->swzsurf
);
425 nv04_surface_2d_takedown(&ctx
);
429 if (chan
->device
->chipset
< 0x10) {
430 class = NV04_SCALED_IMAGE_FROM_MEMORY
;
432 if (chan
->device
->chipset
< 0x40) {
433 class = NV10_SCALED_IMAGE_FROM_MEMORY
;
435 class = NV40_SCALED_IMAGE_FROM_MEMORY
;
438 ret
= nouveau_grobj_alloc(chan
, handle
++, class, &ctx
->sifm
);
440 nv04_surface_2d_takedown(&ctx
);
445 ctx
->copy
= nv04_surface_copy
;
446 ctx
->fill
= nv04_surface_fill
;