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Merge commit 'origin/gallium-master-merge'
[mesa.git] / src / gallium / drivers / nv30 / nv30_fragprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4
5 #include "pipe/p_shader_tokens.h"
6 #include "tgsi/tgsi_parse.h"
7 #include "tgsi/tgsi_util.h"
8
9 #include "nv30_context.h"
10
11 #define SWZ_X 0
12 #define SWZ_Y 1
13 #define SWZ_Z 2
14 #define SWZ_W 3
15 #define MASK_X 1
16 #define MASK_Y 2
17 #define MASK_Z 4
18 #define MASK_W 8
19 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
20 #define DEF_SCALE NV30_FP_OP_DST_SCALE_1X
21 #define DEF_CTEST NV30_FP_OP_COND_TR
22 #include "nv30_shader.h"
23
24 #define swz(s,x,y,z,w) nv30_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
25 #define neg(s) nv30_sr_neg((s))
26 #define abs(s) nv30_sr_abs((s))
27 #define scale(s,v) nv30_sr_scale((s), NV30_FP_OP_DST_SCALE_##v)
28
29 #define MAX_CONSTS 128
30 #define MAX_IMM 32
31 struct nv30_fpc {
32 struct nv30_fragment_program *fp;
33
34 uint attrib_map[PIPE_MAX_SHADER_INPUTS];
35
36 int high_temp;
37 int temp_temp_count;
38 int num_regs;
39
40 uint depth_id;
41 uint colour_id;
42
43 unsigned inst_offset;
44
45 struct {
46 int pipe;
47 float vals[4];
48 } consts[MAX_CONSTS];
49 int nr_consts;
50
51 struct nv30_sreg imm[MAX_IMM];
52 unsigned nr_imm;
53 };
54
55 static INLINE struct nv30_sreg
56 temp(struct nv30_fpc *fpc)
57 {
58 int idx;
59
60 idx = fpc->temp_temp_count++;
61 idx += fpc->high_temp + 1;
62 return nv30_sr(NV30SR_TEMP, idx);
63 }
64
65 static INLINE struct nv30_sreg
66 constant(struct nv30_fpc *fpc, int pipe, float vals[4])
67 {
68 int idx;
69
70 if (fpc->nr_consts == MAX_CONSTS)
71 assert(0);
72 idx = fpc->nr_consts++;
73
74 fpc->consts[idx].pipe = pipe;
75 if (pipe == -1)
76 memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
77 return nv30_sr(NV30SR_CONST, idx);
78 }
79
80 #define arith(cc,s,o,d,m,s0,s1,s2) \
81 nv30_fp_arith((cc), (s), NV30_FP_OP_OPCODE_##o, \
82 (d), (m), (s0), (s1), (s2))
83 #define tex(cc,s,o,u,d,m,s0,s1,s2) \
84 nv30_fp_tex((cc), (s), NV30_FP_OP_OPCODE_##o, (u), \
85 (d), (m), (s0), none, none)
86
87 static void
88 grow_insns(struct nv30_fpc *fpc, int size)
89 {
90 struct nv30_fragment_program *fp = fpc->fp;
91
92 fp->insn_len += size;
93 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
94 }
95
96 static void
97 emit_src(struct nv30_fpc *fpc, int pos, struct nv30_sreg src)
98 {
99 struct nv30_fragment_program *fp = fpc->fp;
100 uint32_t *hw = &fp->insn[fpc->inst_offset];
101 uint32_t sr = 0;
102
103 switch (src.type) {
104 case NV30SR_INPUT:
105 sr |= (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT);
106 hw[0] |= (src.index << NV30_FP_OP_INPUT_SRC_SHIFT);
107 break;
108 case NV30SR_OUTPUT:
109 sr |= NV30_FP_REG_SRC_HALF;
110 /* fall-through */
111 case NV30SR_TEMP:
112 sr |= (NV30_FP_REG_TYPE_TEMP << NV30_FP_REG_TYPE_SHIFT);
113 sr |= (src.index << NV30_FP_REG_SRC_SHIFT);
114 break;
115 case NV30SR_CONST:
116 grow_insns(fpc, 4);
117 hw = &fp->insn[fpc->inst_offset];
118 if (fpc->consts[src.index].pipe >= 0) {
119 struct nv30_fragment_program_data *fpd;
120
121 fp->consts = realloc(fp->consts, ++fp->nr_consts *
122 sizeof(*fpd));
123 fpd = &fp->consts[fp->nr_consts - 1];
124 fpd->offset = fpc->inst_offset + 4;
125 fpd->index = fpc->consts[src.index].pipe;
126 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
127 } else {
128 memcpy(&fp->insn[fpc->inst_offset + 4],
129 fpc->consts[src.index].vals,
130 sizeof(uint32_t) * 4);
131 }
132
133 sr |= (NV30_FP_REG_TYPE_CONST << NV30_FP_REG_TYPE_SHIFT);
134 break;
135 case NV30SR_NONE:
136 sr |= (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT);
137 break;
138 default:
139 assert(0);
140 }
141
142 if (src.negate)
143 sr |= NV30_FP_REG_NEGATE;
144
145 if (src.abs)
146 hw[1] |= (1 << (29 + pos));
147
148 sr |= ((src.swz[0] << NV30_FP_REG_SWZ_X_SHIFT) |
149 (src.swz[1] << NV30_FP_REG_SWZ_Y_SHIFT) |
150 (src.swz[2] << NV30_FP_REG_SWZ_Z_SHIFT) |
151 (src.swz[3] << NV30_FP_REG_SWZ_W_SHIFT));
152
153 hw[pos + 1] |= sr;
154 }
155
156 static void
157 emit_dst(struct nv30_fpc *fpc, struct nv30_sreg dst)
158 {
159 struct nv30_fragment_program *fp = fpc->fp;
160 uint32_t *hw = &fp->insn[fpc->inst_offset];
161
162 switch (dst.type) {
163 case NV30SR_TEMP:
164 if (fpc->num_regs < (dst.index + 1))
165 fpc->num_regs = dst.index + 1;
166 break;
167 case NV30SR_OUTPUT:
168 if (dst.index == 1) {
169 fp->fp_control |= 0xe;
170 } else {
171 hw[0] |= NV30_FP_OP_OUT_REG_HALF;
172 }
173 break;
174 case NV30SR_NONE:
175 hw[0] |= (1 << 30);
176 break;
177 default:
178 assert(0);
179 }
180
181 hw[0] |= (dst.index << NV30_FP_OP_OUT_REG_SHIFT);
182 }
183
184 static void
185 nv30_fp_arith(struct nv30_fpc *fpc, int sat, int op,
186 struct nv30_sreg dst, int mask,
187 struct nv30_sreg s0, struct nv30_sreg s1, struct nv30_sreg s2)
188 {
189 struct nv30_fragment_program *fp = fpc->fp;
190 uint32_t *hw;
191
192 fpc->inst_offset = fp->insn_len;
193 grow_insns(fpc, 4);
194 hw = &fp->insn[fpc->inst_offset];
195 memset(hw, 0, sizeof(uint32_t) * 4);
196
197 if (op == NV30_FP_OP_OPCODE_KIL)
198 fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL;
199 hw[0] |= (op << NV30_FP_OP_OPCODE_SHIFT);
200 hw[0] |= (mask << NV30_FP_OP_OUTMASK_SHIFT);
201 hw[2] |= (dst.dst_scale << NV30_FP_OP_DST_SCALE_SHIFT);
202
203 if (sat)
204 hw[0] |= NV30_FP_OP_OUT_SAT;
205
206 if (dst.cc_update)
207 hw[0] |= NV30_FP_OP_COND_WRITE_ENABLE;
208 hw[1] |= (dst.cc_test << NV30_FP_OP_COND_SHIFT);
209 hw[1] |= ((dst.cc_swz[0] << NV30_FP_OP_COND_SWZ_X_SHIFT) |
210 (dst.cc_swz[1] << NV30_FP_OP_COND_SWZ_Y_SHIFT) |
211 (dst.cc_swz[2] << NV30_FP_OP_COND_SWZ_Z_SHIFT) |
212 (dst.cc_swz[3] << NV30_FP_OP_COND_SWZ_W_SHIFT));
213
214 emit_dst(fpc, dst);
215 emit_src(fpc, 0, s0);
216 emit_src(fpc, 1, s1);
217 emit_src(fpc, 2, s2);
218 }
219
220 static void
221 nv30_fp_tex(struct nv30_fpc *fpc, int sat, int op, int unit,
222 struct nv30_sreg dst, int mask,
223 struct nv30_sreg s0, struct nv30_sreg s1, struct nv30_sreg s2)
224 {
225 struct nv30_fragment_program *fp = fpc->fp;
226
227 nv30_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2);
228
229 fp->insn[fpc->inst_offset] |= (unit << NV30_FP_OP_TEX_UNIT_SHIFT);
230 fp->samplers |= (1 << unit);
231 }
232
233 static INLINE struct nv30_sreg
234 tgsi_src(struct nv30_fpc *fpc, const struct tgsi_full_src_register *fsrc)
235 {
236 struct nv30_sreg src;
237
238 switch (fsrc->SrcRegister.File) {
239 case TGSI_FILE_INPUT:
240 src = nv30_sr(NV30SR_INPUT,
241 fpc->attrib_map[fsrc->SrcRegister.Index]);
242 break;
243 case TGSI_FILE_CONSTANT:
244 src = constant(fpc, fsrc->SrcRegister.Index, NULL);
245 break;
246 case TGSI_FILE_IMMEDIATE:
247 assert(fsrc->SrcRegister.Index < fpc->nr_imm);
248 src = fpc->imm[fsrc->SrcRegister.Index];
249 break;
250 case TGSI_FILE_TEMPORARY:
251 src = nv30_sr(NV30SR_TEMP, fsrc->SrcRegister.Index + 1);
252 if (fpc->high_temp < src.index)
253 fpc->high_temp = src.index;
254 break;
255 /* This is clearly insane, but gallium hands us shaders like this.
256 * Luckily fragprog results are just temp regs..
257 */
258 case TGSI_FILE_OUTPUT:
259 if (fsrc->SrcRegister.Index == fpc->colour_id)
260 return nv30_sr(NV30SR_OUTPUT, 0);
261 else
262 return nv30_sr(NV30SR_OUTPUT, 1);
263 break;
264 default:
265 NOUVEAU_ERR("bad src file\n");
266 break;
267 }
268
269 src.abs = fsrc->SrcRegisterExtMod.Absolute;
270 src.negate = fsrc->SrcRegister.Negate;
271 src.swz[0] = fsrc->SrcRegister.SwizzleX;
272 src.swz[1] = fsrc->SrcRegister.SwizzleY;
273 src.swz[2] = fsrc->SrcRegister.SwizzleZ;
274 src.swz[3] = fsrc->SrcRegister.SwizzleW;
275 return src;
276 }
277
278 static INLINE struct nv30_sreg
279 tgsi_dst(struct nv30_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
280 int idx;
281
282 switch (fdst->DstRegister.File) {
283 case TGSI_FILE_OUTPUT:
284 if (fdst->DstRegister.Index == fpc->colour_id)
285 return nv30_sr(NV30SR_OUTPUT, 0);
286 else
287 return nv30_sr(NV30SR_OUTPUT, 1);
288 break;
289 case TGSI_FILE_TEMPORARY:
290 idx = fdst->DstRegister.Index + 1;
291 if (fpc->high_temp < idx)
292 fpc->high_temp = idx;
293 return nv30_sr(NV30SR_TEMP, idx);
294 case TGSI_FILE_NULL:
295 return nv30_sr(NV30SR_NONE, 0);
296 default:
297 NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File);
298 return nv30_sr(NV30SR_NONE, 0);
299 }
300 }
301
302 static INLINE int
303 tgsi_mask(uint tgsi)
304 {
305 int mask = 0;
306
307 if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
308 if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
309 if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
310 if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
311 return mask;
312 }
313
314 static boolean
315 src_native_swz(struct nv30_fpc *fpc, const struct tgsi_full_src_register *fsrc,
316 struct nv30_sreg *src)
317 {
318 const struct nv30_sreg none = nv30_sr(NV30SR_NONE, 0);
319 struct nv30_sreg tgsi = tgsi_src(fpc, fsrc);
320 uint mask = 0, zero_mask = 0, one_mask = 0, neg_mask = 0;
321 uint neg[4] = { fsrc->SrcRegisterExtSwz.NegateX,
322 fsrc->SrcRegisterExtSwz.NegateY,
323 fsrc->SrcRegisterExtSwz.NegateZ,
324 fsrc->SrcRegisterExtSwz.NegateW };
325 uint c;
326
327 for (c = 0; c < 4; c++) {
328 switch (tgsi_util_get_full_src_register_extswizzle(fsrc, c)) {
329 case TGSI_EXTSWIZZLE_X:
330 case TGSI_EXTSWIZZLE_Y:
331 case TGSI_EXTSWIZZLE_Z:
332 case TGSI_EXTSWIZZLE_W:
333 mask |= (1 << c);
334 break;
335 case TGSI_EXTSWIZZLE_ZERO:
336 zero_mask |= (1 << c);
337 tgsi.swz[c] = SWZ_X;
338 break;
339 case TGSI_EXTSWIZZLE_ONE:
340 one_mask |= (1 << c);
341 tgsi.swz[c] = SWZ_X;
342 break;
343 default:
344 assert(0);
345 }
346
347 if (!tgsi.negate && neg[c])
348 neg_mask |= (1 << c);
349 }
350
351 if (mask == MASK_ALL && !neg_mask)
352 return TRUE;
353
354 *src = temp(fpc);
355
356 if (mask)
357 arith(fpc, 0, MOV, *src, mask, tgsi, none, none);
358
359 if (zero_mask)
360 arith(fpc, 0, SFL, *src, zero_mask, *src, none, none);
361
362 if (one_mask)
363 arith(fpc, 0, STR, *src, one_mask, *src, none, none);
364
365 if (neg_mask) {
366 struct nv30_sreg one = temp(fpc);
367 arith(fpc, 0, STR, one, neg_mask, one, none, none);
368 arith(fpc, 0, MUL, *src, neg_mask, *src, neg(one), none);
369 }
370
371 return FALSE;
372 }
373
374 static boolean
375 nv30_fragprog_parse_instruction(struct nv30_fpc *fpc,
376 const struct tgsi_full_instruction *finst)
377 {
378 const struct nv30_sreg none = nv30_sr(NV30SR_NONE, 0);
379 struct nv30_sreg src[3], dst, tmp;
380 int mask, sat, unit = 0;
381 int ai = -1, ci = -1;
382 int i;
383
384 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
385 return TRUE;
386
387 fpc->temp_temp_count = 0;
388 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
389 const struct tgsi_full_src_register *fsrc;
390
391 fsrc = &finst->FullSrcRegisters[i];
392 if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
393 src[i] = tgsi_src(fpc, fsrc);
394 }
395 }
396
397 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
398 const struct tgsi_full_src_register *fsrc;
399
400 fsrc = &finst->FullSrcRegisters[i];
401
402 switch (fsrc->SrcRegister.File) {
403 case TGSI_FILE_INPUT:
404 case TGSI_FILE_CONSTANT:
405 case TGSI_FILE_TEMPORARY:
406 if (!src_native_swz(fpc, fsrc, &src[i]))
407 continue;
408 break;
409 default:
410 break;
411 }
412
413 switch (fsrc->SrcRegister.File) {
414 case TGSI_FILE_INPUT:
415 if (ai == -1 || ai == fsrc->SrcRegister.Index) {
416 ai = fsrc->SrcRegister.Index;
417 src[i] = tgsi_src(fpc, fsrc);
418 } else {
419 NOUVEAU_MSG("extra src attr %d\n",
420 fsrc->SrcRegister.Index);
421 src[i] = temp(fpc);
422 arith(fpc, 0, MOV, src[i], MASK_ALL,
423 tgsi_src(fpc, fsrc), none, none);
424 }
425 break;
426 case TGSI_FILE_CONSTANT:
427 case TGSI_FILE_IMMEDIATE:
428 if (ci == -1 || ci == fsrc->SrcRegister.Index) {
429 ci = fsrc->SrcRegister.Index;
430 src[i] = tgsi_src(fpc, fsrc);
431 } else {
432 src[i] = temp(fpc);
433 arith(fpc, 0, MOV, src[i], MASK_ALL,
434 tgsi_src(fpc, fsrc), none, none);
435 }
436 break;
437 case TGSI_FILE_TEMPORARY:
438 /* handled above */
439 break;
440 case TGSI_FILE_SAMPLER:
441 unit = fsrc->SrcRegister.Index;
442 break;
443 case TGSI_FILE_OUTPUT:
444 break;
445 default:
446 NOUVEAU_ERR("bad src file\n");
447 return FALSE;
448 }
449 }
450
451 dst = tgsi_dst(fpc, &finst->FullDstRegisters[0]);
452 mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
453 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
454
455 switch (finst->Instruction.Opcode) {
456 case TGSI_OPCODE_ABS:
457 arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none);
458 break;
459 case TGSI_OPCODE_ADD:
460 arith(fpc, sat, ADD, dst, mask, src[0], src[1], none);
461 break;
462 case TGSI_OPCODE_CMP:
463 tmp = temp(fpc);
464 arith(fpc, sat, MOV, dst, mask, src[2], none, none);
465 tmp.cc_update = 1;
466 arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none);
467 dst.cc_test = NV30_VP_INST_COND_LT;
468 arith(fpc, sat, MOV, dst, mask, src[1], none, none);
469 break;
470 case TGSI_OPCODE_COS:
471 arith(fpc, sat, COS, dst, mask, src[0], none, none);
472 break;
473 case TGSI_OPCODE_DP3:
474 arith(fpc, sat, DP3, dst, mask, src[0], src[1], none);
475 break;
476 case TGSI_OPCODE_DP4:
477 arith(fpc, sat, DP4, dst, mask, src[0], src[1], none);
478 break;
479 case TGSI_OPCODE_DPH:
480 tmp = temp(fpc);
481 arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[1], none);
482 arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X),
483 swz(src[1], W, W, W, W), none);
484 break;
485 case TGSI_OPCODE_DST:
486 arith(fpc, sat, DST, dst, mask, src[0], src[1], none);
487 break;
488 case TGSI_OPCODE_EX2:
489 arith(fpc, sat, EX2, dst, mask, src[0], none, none);
490 break;
491 case TGSI_OPCODE_FLR:
492 arith(fpc, sat, FLR, dst, mask, src[0], none, none);
493 break;
494 case TGSI_OPCODE_FRC:
495 arith(fpc, sat, FRC, dst, mask, src[0], none, none);
496 break;
497 case TGSI_OPCODE_KILP:
498 arith(fpc, 0, KIL, none, 0, none, none, none);
499 break;
500 case TGSI_OPCODE_KIL:
501 dst = nv30_sr(NV30SR_NONE, 0);
502 dst.cc_update = 1;
503 arith(fpc, 0, MOV, dst, MASK_ALL, src[0], none, none);
504 dst.cc_update = 0; dst.cc_test = NV30_FP_OP_COND_LT;
505 arith(fpc, 0, KIL, dst, 0, none, none, none);
506 break;
507 case TGSI_OPCODE_LG2:
508 arith(fpc, sat, LG2, dst, mask, src[0], none, none);
509 break;
510 // case TGSI_OPCODE_LIT:
511 case TGSI_OPCODE_LRP:
512 arith(fpc, sat, LRP, dst, mask, src[0], src[1], src[2]);
513 break;
514 case TGSI_OPCODE_MAD:
515 arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]);
516 break;
517 case TGSI_OPCODE_MAX:
518 arith(fpc, sat, MAX, dst, mask, src[0], src[1], none);
519 break;
520 case TGSI_OPCODE_MIN:
521 arith(fpc, sat, MIN, dst, mask, src[0], src[1], none);
522 break;
523 case TGSI_OPCODE_MOV:
524 arith(fpc, sat, MOV, dst, mask, src[0], none, none);
525 break;
526 case TGSI_OPCODE_MUL:
527 arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
528 break;
529 case TGSI_OPCODE_NOISE1:
530 case TGSI_OPCODE_NOISE2:
531 case TGSI_OPCODE_NOISE3:
532 case TGSI_OPCODE_NOISE4:
533 arith(fpc, sat, SFL, dst, mask, none, none, none);
534 break;
535 case TGSI_OPCODE_POW:
536 arith(fpc, sat, POW, dst, mask, src[0], src[1], none);
537 break;
538 case TGSI_OPCODE_RCP:
539 arith(fpc, sat, RCP, dst, mask, src[0], none, none);
540 break;
541 case TGSI_OPCODE_RET:
542 assert(0);
543 break;
544 case TGSI_OPCODE_RFL:
545 arith(fpc, 0, RFL, dst, mask, src[0], src[1], none);
546 break;
547 case TGSI_OPCODE_RSQ:
548 arith(fpc, sat, RSQ, dst, mask, abs(swz(src[0], X, X, X, X)), none, none);
549 break;
550 case TGSI_OPCODE_SCS:
551 if (mask & MASK_X) {
552 arith(fpc, sat, COS, dst, MASK_X,
553 swz(src[0], X, X, X, X), none, none);
554 }
555 if (mask & MASK_Y) {
556 arith(fpc, sat, SIN, dst, MASK_Y,
557 swz(src[0], X, X, X, X), none, none);
558 }
559 break;
560 case TGSI_OPCODE_SIN:
561 arith(fpc, sat, SIN, dst, mask, src[0], none, none);
562 break;
563 case TGSI_OPCODE_SGE:
564 arith(fpc, sat, SGE, dst, mask, src[0], src[1], none);
565 break;
566 case TGSI_OPCODE_SGT:
567 arith(fpc, sat, SGT, dst, mask, src[0], src[1], none);
568 break;
569 case TGSI_OPCODE_SLT:
570 arith(fpc, sat, SLT, dst, mask, src[0], src[1], none);
571 break;
572 case TGSI_OPCODE_SUB:
573 arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none);
574 break;
575 case TGSI_OPCODE_TEX:
576 tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none);
577 break;
578 case TGSI_OPCODE_TXB:
579 tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none);
580 break;
581 case TGSI_OPCODE_TXP:
582 tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none);
583 break;
584 case TGSI_OPCODE_XPD:
585 tmp = temp(fpc);
586 arith(fpc, 0, MUL, tmp, mask,
587 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
588 arith(fpc, sat, MAD, dst, (mask & ~MASK_W),
589 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
590 neg(tmp));
591 break;
592 default:
593 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
594 return FALSE;
595 }
596
597 return TRUE;
598 }
599
600 static boolean
601 nv30_fragprog_parse_decl_attrib(struct nv30_fpc *fpc,
602 const struct tgsi_full_declaration *fdec)
603 {
604 int hw;
605
606 switch (fdec->Semantic.SemanticName) {
607 case TGSI_SEMANTIC_POSITION:
608 hw = NV30_FP_OP_INPUT_SRC_POSITION;
609 break;
610 case TGSI_SEMANTIC_COLOR:
611 if (fdec->Semantic.SemanticIndex == 0) {
612 hw = NV30_FP_OP_INPUT_SRC_COL0;
613 } else
614 if (fdec->Semantic.SemanticIndex == 1) {
615 hw = NV30_FP_OP_INPUT_SRC_COL1;
616 } else {
617 NOUVEAU_ERR("bad colour semantic index\n");
618 return FALSE;
619 }
620 break;
621 case TGSI_SEMANTIC_FOG:
622 hw = NV30_FP_OP_INPUT_SRC_FOGC;
623 break;
624 case TGSI_SEMANTIC_GENERIC:
625 if (fdec->Semantic.SemanticIndex <= 7) {
626 hw = NV30_FP_OP_INPUT_SRC_TC(fdec->Semantic.
627 SemanticIndex);
628 } else {
629 NOUVEAU_ERR("bad generic semantic index\n");
630 return FALSE;
631 }
632 break;
633 default:
634 NOUVEAU_ERR("bad input semantic\n");
635 return FALSE;
636 }
637
638 fpc->attrib_map[fdec->DeclarationRange.First] = hw;
639 return TRUE;
640 }
641
642 static boolean
643 nv30_fragprog_parse_decl_output(struct nv30_fpc *fpc,
644 const struct tgsi_full_declaration *fdec)
645 {
646 switch (fdec->Semantic.SemanticName) {
647 case TGSI_SEMANTIC_POSITION:
648 fpc->depth_id = fdec->DeclarationRange.First;
649 break;
650 case TGSI_SEMANTIC_COLOR:
651 fpc->colour_id = fdec->DeclarationRange.First;
652 break;
653 default:
654 NOUVEAU_ERR("bad output semantic\n");
655 return FALSE;
656 }
657
658 return TRUE;
659 }
660
661 static boolean
662 nv30_fragprog_prepare(struct nv30_fpc *fpc)
663 {
664 struct tgsi_parse_context p;
665 /*int high_temp = -1, i;*/
666
667 tgsi_parse_init(&p, fpc->fp->pipe.tokens);
668 while (!tgsi_parse_end_of_tokens(&p)) {
669 const union tgsi_full_token *tok = &p.FullToken;
670
671 tgsi_parse_token(&p);
672 switch(tok->Token.Type) {
673 case TGSI_TOKEN_TYPE_DECLARATION:
674 {
675 const struct tgsi_full_declaration *fdec;
676 fdec = &p.FullToken.FullDeclaration;
677 switch (fdec->Declaration.File) {
678 case TGSI_FILE_INPUT:
679 if (!nv30_fragprog_parse_decl_attrib(fpc, fdec))
680 goto out_err;
681 break;
682 case TGSI_FILE_OUTPUT:
683 if (!nv30_fragprog_parse_decl_output(fpc, fdec))
684 goto out_err;
685 break;
686 /*case TGSI_FILE_TEMPORARY:
687 if (fdec->DeclarationRange.Last > high_temp) {
688 high_temp =
689 fdec->DeclarationRange.Last;
690 }
691 break;*/
692 default:
693 break;
694 }
695 }
696 break;
697 case TGSI_TOKEN_TYPE_IMMEDIATE:
698 {
699 struct tgsi_full_immediate *imm;
700 float vals[4];
701
702 imm = &p.FullToken.FullImmediate;
703 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
704 assert(fpc->nr_imm < MAX_IMM);
705
706 vals[0] = imm->u.ImmediateFloat32[0].Float;
707 vals[1] = imm->u.ImmediateFloat32[1].Float;
708 vals[2] = imm->u.ImmediateFloat32[2].Float;
709 vals[3] = imm->u.ImmediateFloat32[3].Float;
710 fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals);
711 }
712 break;
713 default:
714 break;
715 }
716 }
717 tgsi_parse_free(&p);
718
719 /*if (++high_temp) {
720 fpc->r_temp = CALLOC(high_temp, sizeof(struct nv30_sreg));
721 for (i = 0; i < high_temp; i++)
722 fpc->r_temp[i] = temp(fpc);
723 fpc->r_temps_discard = 0;
724 }*/
725
726 return TRUE;
727
728 out_err:
729 /*if (fpc->r_temp)
730 FREE(fpc->r_temp);*/
731 tgsi_parse_free(&p);
732 return FALSE;
733 }
734
735 static void
736 nv30_fragprog_translate(struct nv30_context *nv30,
737 struct nv30_fragment_program *fp)
738 {
739 struct tgsi_parse_context parse;
740 struct nv30_fpc *fpc = NULL;
741
742 tgsi_dump(fp->pipe.tokens,0);
743
744 fpc = CALLOC(1, sizeof(struct nv30_fpc));
745 if (!fpc)
746 return;
747 fpc->fp = fp;
748 fpc->high_temp = -1;
749 fpc->num_regs = 2;
750
751 if (!nv30_fragprog_prepare(fpc)) {
752 FREE(fpc);
753 return;
754 }
755
756 tgsi_parse_init(&parse, fp->pipe.tokens);
757
758 while (!tgsi_parse_end_of_tokens(&parse)) {
759 tgsi_parse_token(&parse);
760
761 switch (parse.FullToken.Token.Type) {
762 case TGSI_TOKEN_TYPE_INSTRUCTION:
763 {
764 const struct tgsi_full_instruction *finst;
765
766 finst = &parse.FullToken.FullInstruction;
767 if (!nv30_fragprog_parse_instruction(fpc, finst))
768 goto out_err;
769 }
770 break;
771 default:
772 break;
773 }
774 }
775
776 fp->fp_control |= (fpc->num_regs-1)/2;
777 fp->fp_reg_control = (1<<16)|0x4;
778
779 /* Terminate final instruction */
780 fp->insn[fpc->inst_offset] |= 0x00000001;
781
782 /* Append NOP + END instruction, may or may not be necessary. */
783 fpc->inst_offset = fp->insn_len;
784 grow_insns(fpc, 4);
785 fp->insn[fpc->inst_offset + 0] = 0x00000001;
786 fp->insn[fpc->inst_offset + 1] = 0x00000000;
787 fp->insn[fpc->inst_offset + 2] = 0x00000000;
788 fp->insn[fpc->inst_offset + 3] = 0x00000000;
789
790 fp->translated = TRUE;
791 fp->on_hw = FALSE;
792 out_err:
793 tgsi_parse_free(&parse);
794 FREE(fpc);
795 }
796
797 static void
798 nv30_fragprog_upload(struct nv30_context *nv30,
799 struct nv30_fragment_program *fp)
800 {
801 struct pipe_winsys *ws = nv30->pipe.winsys;
802 const uint32_t le = 1;
803 uint32_t *map;
804 int i;
805
806 map = ws->buffer_map(ws, fp->buffer, PIPE_BUFFER_USAGE_CPU_WRITE);
807
808 #if 0
809 for (i = 0; i < fp->insn_len; i++) {
810 fflush(stdout); fflush(stderr);
811 NOUVEAU_ERR("%d 0x%08x\n", i, fp->insn[i]);
812 fflush(stdout); fflush(stderr);
813 }
814 #endif
815
816 if ((*(const uint8_t *)&le)) {
817 for (i = 0; i < fp->insn_len; i++) {
818 map[i] = fp->insn[i];
819 }
820 } else {
821 /* Weird swapping for big-endian chips */
822 for (i = 0; i < fp->insn_len; i++) {
823 map[i] = ((fp->insn[i] & 0xffff) << 16) |
824 ((fp->insn[i] >> 16) & 0xffff);
825 }
826 }
827
828 ws->buffer_unmap(ws, fp->buffer);
829 }
830
831 static boolean
832 nv30_fragprog_validate(struct nv30_context *nv30)
833 {
834 struct nv30_fragment_program *fp = nv30->fragprog;
835 struct pipe_buffer *constbuf =
836 nv30->constbuf[PIPE_SHADER_FRAGMENT];
837 struct pipe_winsys *ws = nv30->pipe.winsys;
838 struct nouveau_stateobj *so;
839 boolean new_consts = FALSE;
840 int i;
841
842 if (fp->translated)
843 goto update_constants;
844
845 /*nv30->fallback_swrast &= ~NV30_NEW_FRAGPROG;*/
846 nv30_fragprog_translate(nv30, fp);
847 if (!fp->translated) {
848 /*nv30->fallback_swrast |= NV30_NEW_FRAGPROG;*/
849 return FALSE;
850 }
851
852 fp->buffer = ws->buffer_create(ws, 0x100, 0, fp->insn_len * 4);
853 nv30_fragprog_upload(nv30, fp);
854
855 so = so_new(8, 1);
856 so_method(so, nv30->screen->rankine, NV34TCL_FP_ACTIVE_PROGRAM, 1);
857 so_reloc (so, fp->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
858 NOUVEAU_BO_RD | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
859 NV34TCL_FP_ACTIVE_PROGRAM_DMA0, NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
860 so_method(so, nv30->screen->rankine, NV34TCL_FP_CONTROL, 1);
861 so_data (so, fp->fp_control);
862 so_method(so, nv30->screen->rankine, NV34TCL_FP_REG_CONTROL, 1);
863 so_data (so, fp->fp_reg_control);
864 so_method(so, nv30->screen->rankine, NV34TCL_TX_UNITS_ENABLE, 1);
865 so_data (so, fp->samplers);
866 so_ref(so, &fp->so);
867
868 update_constants:
869 if (fp->nr_consts) {
870 float *map;
871
872 map = ws->buffer_map(ws, constbuf, PIPE_BUFFER_USAGE_CPU_READ);
873 for (i = 0; i < fp->nr_consts; i++) {
874 struct nv30_fragment_program_data *fpd = &fp->consts[i];
875 uint32_t *p = &fp->insn[fpd->offset];
876 uint32_t *cb = (uint32_t *)&map[fpd->index * 4];
877
878 if (!memcmp(p, cb, 4 * sizeof(float)))
879 continue;
880 memcpy(p, cb, 4 * sizeof(float));
881 new_consts = TRUE;
882 }
883 ws->buffer_unmap(ws, constbuf);
884
885 if (new_consts)
886 nv30_fragprog_upload(nv30, fp);
887 }
888
889 if (new_consts || fp->so != nv30->state.hw[NV30_STATE_FRAGPROG]) {
890 so_ref(fp->so, &nv30->state.hw[NV30_STATE_FRAGPROG]);
891 return TRUE;
892 }
893
894 return FALSE;
895 }
896
897 void
898 nv30_fragprog_destroy(struct nv30_context *nv30,
899 struct nv30_fragment_program *fp)
900 {
901 if (fp->insn_len)
902 FREE(fp->insn);
903 }
904
905 struct nv30_state_entry nv30_state_fragprog = {
906 .validate = nv30_fragprog_validate,
907 .dirty = {
908 .pipe = NV30_NEW_FRAGPROG,
909 .hw = NV30_STATE_FRAGPROG
910 }
911 };