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st/mesa: fix incorrect RowStride computation
[mesa.git] / src / gallium / drivers / nv40 / nv40_fragprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_util.h"
9
10 #include "nv40_context.h"
11
12 #define SWZ_X 0
13 #define SWZ_Y 1
14 #define SWZ_Z 2
15 #define SWZ_W 3
16 #define MASK_X 1
17 #define MASK_Y 2
18 #define MASK_Z 4
19 #define MASK_W 8
20 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
21 #define DEF_SCALE NV40_FP_OP_DST_SCALE_1X
22 #define DEF_CTEST NV40_FP_OP_COND_TR
23 #include "nv40_shader.h"
24
25 #define swz(s,x,y,z,w) nv40_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
26 #define neg(s) nv40_sr_neg((s))
27 #define abs(s) nv40_sr_abs((s))
28 #define scale(s,v) nv40_sr_scale((s), NV40_FP_OP_DST_SCALE_##v)
29
30 #define MAX_CONSTS 128
31 #define MAX_IMM 32
32 struct nv40_fpc {
33 struct nv40_fragment_program *fp;
34
35 uint attrib_map[PIPE_MAX_SHADER_INPUTS];
36
37 unsigned r_temps;
38 unsigned r_temps_discard;
39 struct nv40_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
40 struct nv40_sreg *r_temp;
41
42 int num_regs;
43
44 unsigned inst_offset;
45 unsigned have_const;
46
47 struct {
48 int pipe;
49 float vals[4];
50 } consts[MAX_CONSTS];
51 int nr_consts;
52
53 struct nv40_sreg imm[MAX_IMM];
54 unsigned nr_imm;
55 };
56
57 static INLINE struct nv40_sreg
58 temp(struct nv40_fpc *fpc)
59 {
60 int idx = ffs(~fpc->r_temps) - 1;
61
62 if (idx < 0) {
63 NOUVEAU_ERR("out of temps!!\n");
64 assert(0);
65 return nv40_sr(NV40SR_TEMP, 0);
66 }
67
68 fpc->r_temps |= (1 << idx);
69 fpc->r_temps_discard |= (1 << idx);
70 return nv40_sr(NV40SR_TEMP, idx);
71 }
72
73 static INLINE void
74 release_temps(struct nv40_fpc *fpc)
75 {
76 fpc->r_temps &= ~fpc->r_temps_discard;
77 fpc->r_temps_discard = 0;
78 }
79
80 static INLINE struct nv40_sreg
81 constant(struct nv40_fpc *fpc, int pipe, float vals[4])
82 {
83 int idx;
84
85 if (fpc->nr_consts == MAX_CONSTS)
86 assert(0);
87 idx = fpc->nr_consts++;
88
89 fpc->consts[idx].pipe = pipe;
90 if (pipe == -1)
91 memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
92 return nv40_sr(NV40SR_CONST, idx);
93 }
94
95 #define arith(cc,s,o,d,m,s0,s1,s2) \
96 nv40_fp_arith((cc), (s), NV40_FP_OP_OPCODE_##o, \
97 (d), (m), (s0), (s1), (s2))
98 #define tex(cc,s,o,u,d,m,s0,s1,s2) \
99 nv40_fp_tex((cc), (s), NV40_FP_OP_OPCODE_##o, (u), \
100 (d), (m), (s0), none, none)
101
102 static void
103 grow_insns(struct nv40_fpc *fpc, int size)
104 {
105 struct nv40_fragment_program *fp = fpc->fp;
106
107 fp->insn_len += size;
108 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
109 }
110
111 static void
112 emit_src(struct nv40_fpc *fpc, int pos, struct nv40_sreg src)
113 {
114 struct nv40_fragment_program *fp = fpc->fp;
115 uint32_t *hw = &fp->insn[fpc->inst_offset];
116 uint32_t sr = 0;
117
118 switch (src.type) {
119 case NV40SR_INPUT:
120 sr |= (NV40_FP_REG_TYPE_INPUT << NV40_FP_REG_TYPE_SHIFT);
121 hw[0] |= (src.index << NV40_FP_OP_INPUT_SRC_SHIFT);
122 break;
123 case NV40SR_OUTPUT:
124 sr |= NV40_FP_REG_SRC_HALF;
125 /* fall-through */
126 case NV40SR_TEMP:
127 sr |= (NV40_FP_REG_TYPE_TEMP << NV40_FP_REG_TYPE_SHIFT);
128 sr |= (src.index << NV40_FP_REG_SRC_SHIFT);
129 break;
130 case NV40SR_CONST:
131 if (!fpc->have_const) {
132 grow_insns(fpc, 4);
133 fpc->have_const = 1;
134 }
135
136 hw = &fp->insn[fpc->inst_offset];
137 if (fpc->consts[src.index].pipe >= 0) {
138 struct nv40_fragment_program_data *fpd;
139
140 fp->consts = realloc(fp->consts, ++fp->nr_consts *
141 sizeof(*fpd));
142 fpd = &fp->consts[fp->nr_consts - 1];
143 fpd->offset = fpc->inst_offset + 4;
144 fpd->index = fpc->consts[src.index].pipe;
145 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
146 } else {
147 memcpy(&fp->insn[fpc->inst_offset + 4],
148 fpc->consts[src.index].vals,
149 sizeof(uint32_t) * 4);
150 }
151
152 sr |= (NV40_FP_REG_TYPE_CONST << NV40_FP_REG_TYPE_SHIFT);
153 break;
154 case NV40SR_NONE:
155 sr |= (NV40_FP_REG_TYPE_INPUT << NV40_FP_REG_TYPE_SHIFT);
156 break;
157 default:
158 assert(0);
159 }
160
161 if (src.negate)
162 sr |= NV40_FP_REG_NEGATE;
163
164 if (src.abs)
165 hw[1] |= (1 << (29 + pos));
166
167 sr |= ((src.swz[0] << NV40_FP_REG_SWZ_X_SHIFT) |
168 (src.swz[1] << NV40_FP_REG_SWZ_Y_SHIFT) |
169 (src.swz[2] << NV40_FP_REG_SWZ_Z_SHIFT) |
170 (src.swz[3] << NV40_FP_REG_SWZ_W_SHIFT));
171
172 hw[pos + 1] |= sr;
173 }
174
175 static void
176 emit_dst(struct nv40_fpc *fpc, struct nv40_sreg dst)
177 {
178 struct nv40_fragment_program *fp = fpc->fp;
179 uint32_t *hw = &fp->insn[fpc->inst_offset];
180
181 switch (dst.type) {
182 case NV40SR_TEMP:
183 if (fpc->num_regs < (dst.index + 1))
184 fpc->num_regs = dst.index + 1;
185 break;
186 case NV40SR_OUTPUT:
187 if (dst.index == 1) {
188 fp->fp_control |= 0xe;
189 } else {
190 hw[0] |= NV40_FP_OP_OUT_REG_HALF;
191 }
192 break;
193 case NV40SR_NONE:
194 hw[0] |= (1 << 30);
195 break;
196 default:
197 assert(0);
198 }
199
200 hw[0] |= (dst.index << NV40_FP_OP_OUT_REG_SHIFT);
201 }
202
203 static void
204 nv40_fp_arith(struct nv40_fpc *fpc, int sat, int op,
205 struct nv40_sreg dst, int mask,
206 struct nv40_sreg s0, struct nv40_sreg s1, struct nv40_sreg s2)
207 {
208 struct nv40_fragment_program *fp = fpc->fp;
209 uint32_t *hw;
210
211 fpc->inst_offset = fp->insn_len;
212 fpc->have_const = 0;
213 grow_insns(fpc, 4);
214 hw = &fp->insn[fpc->inst_offset];
215 memset(hw, 0, sizeof(uint32_t) * 4);
216
217 if (op == NV40_FP_OP_OPCODE_KIL)
218 fp->fp_control |= NV40TCL_FP_CONTROL_KIL;
219 hw[0] |= (op << NV40_FP_OP_OPCODE_SHIFT);
220 hw[0] |= (mask << NV40_FP_OP_OUTMASK_SHIFT);
221 hw[2] |= (dst.dst_scale << NV40_FP_OP_DST_SCALE_SHIFT);
222
223 if (sat)
224 hw[0] |= NV40_FP_OP_OUT_SAT;
225
226 if (dst.cc_update)
227 hw[0] |= NV40_FP_OP_COND_WRITE_ENABLE;
228 hw[1] |= (dst.cc_test << NV40_FP_OP_COND_SHIFT);
229 hw[1] |= ((dst.cc_swz[0] << NV40_FP_OP_COND_SWZ_X_SHIFT) |
230 (dst.cc_swz[1] << NV40_FP_OP_COND_SWZ_Y_SHIFT) |
231 (dst.cc_swz[2] << NV40_FP_OP_COND_SWZ_Z_SHIFT) |
232 (dst.cc_swz[3] << NV40_FP_OP_COND_SWZ_W_SHIFT));
233
234 emit_dst(fpc, dst);
235 emit_src(fpc, 0, s0);
236 emit_src(fpc, 1, s1);
237 emit_src(fpc, 2, s2);
238 }
239
240 static void
241 nv40_fp_tex(struct nv40_fpc *fpc, int sat, int op, int unit,
242 struct nv40_sreg dst, int mask,
243 struct nv40_sreg s0, struct nv40_sreg s1, struct nv40_sreg s2)
244 {
245 struct nv40_fragment_program *fp = fpc->fp;
246
247 nv40_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2);
248
249 fp->insn[fpc->inst_offset] |= (unit << NV40_FP_OP_TEX_UNIT_SHIFT);
250 fp->samplers |= (1 << unit);
251 }
252
253 static INLINE struct nv40_sreg
254 tgsi_src(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc)
255 {
256 struct nv40_sreg src;
257
258 switch (fsrc->Register.File) {
259 case TGSI_FILE_INPUT:
260 src = nv40_sr(NV40SR_INPUT,
261 fpc->attrib_map[fsrc->Register.Index]);
262 break;
263 case TGSI_FILE_CONSTANT:
264 src = constant(fpc, fsrc->Register.Index, NULL);
265 break;
266 case TGSI_FILE_IMMEDIATE:
267 assert(fsrc->Register.Index < fpc->nr_imm);
268 src = fpc->imm[fsrc->Register.Index];
269 break;
270 case TGSI_FILE_TEMPORARY:
271 src = fpc->r_temp[fsrc->Register.Index];
272 break;
273 /* NV40 fragprog result regs are just temps, so this is simple */
274 case TGSI_FILE_OUTPUT:
275 src = fpc->r_result[fsrc->Register.Index];
276 break;
277 default:
278 NOUVEAU_ERR("bad src file\n");
279 break;
280 }
281
282 src.abs = fsrc->Register.Absolute;
283 src.negate = fsrc->Register.Negate;
284 src.swz[0] = fsrc->Register.SwizzleX;
285 src.swz[1] = fsrc->Register.SwizzleY;
286 src.swz[2] = fsrc->Register.SwizzleZ;
287 src.swz[3] = fsrc->Register.SwizzleW;
288 return src;
289 }
290
291 static INLINE struct nv40_sreg
292 tgsi_dst(struct nv40_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
293 switch (fdst->Register.File) {
294 case TGSI_FILE_OUTPUT:
295 return fpc->r_result[fdst->Register.Index];
296 case TGSI_FILE_TEMPORARY:
297 return fpc->r_temp[fdst->Register.Index];
298 case TGSI_FILE_NULL:
299 return nv40_sr(NV40SR_NONE, 0);
300 default:
301 NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
302 return nv40_sr(NV40SR_NONE, 0);
303 }
304 }
305
306 static INLINE int
307 tgsi_mask(uint tgsi)
308 {
309 int mask = 0;
310
311 if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
312 if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
313 if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
314 if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
315 return mask;
316 }
317
318 static boolean
319 src_native_swz(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc,
320 struct nv40_sreg *src)
321 {
322 const struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
323 struct nv40_sreg tgsi = tgsi_src(fpc, fsrc);
324 uint mask = 0;
325 uint c;
326
327 for (c = 0; c < 4; c++) {
328 switch (tgsi_util_get_full_src_register_swizzle(fsrc, c)) {
329 case TGSI_SWIZZLE_X:
330 case TGSI_SWIZZLE_Y:
331 case TGSI_SWIZZLE_Z:
332 case TGSI_SWIZZLE_W:
333 mask |= (1 << c);
334 break;
335 default:
336 assert(0);
337 }
338 }
339
340 if (mask == MASK_ALL)
341 return TRUE;
342
343 *src = temp(fpc);
344
345 if (mask)
346 arith(fpc, 0, MOV, *src, mask, tgsi, none, none);
347
348 return FALSE;
349 }
350
351 static boolean
352 nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
353 const struct tgsi_full_instruction *finst)
354 {
355 const struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
356 struct nv40_sreg src[3], dst, tmp;
357 int mask, sat, unit;
358 int ai = -1, ci = -1, ii = -1;
359 int i;
360
361 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
362 return TRUE;
363
364 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
365 const struct tgsi_full_src_register *fsrc;
366
367 fsrc = &finst->Src[i];
368 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
369 src[i] = tgsi_src(fpc, fsrc);
370 }
371 }
372
373 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
374 const struct tgsi_full_src_register *fsrc;
375
376 fsrc = &finst->Src[i];
377
378 switch (fsrc->Register.File) {
379 case TGSI_FILE_INPUT:
380 case TGSI_FILE_CONSTANT:
381 case TGSI_FILE_TEMPORARY:
382 if (!src_native_swz(fpc, fsrc, &src[i]))
383 continue;
384 break;
385 default:
386 break;
387 }
388
389 switch (fsrc->Register.File) {
390 case TGSI_FILE_INPUT:
391 if (ai == -1 || ai == fsrc->Register.Index) {
392 ai = fsrc->Register.Index;
393 src[i] = tgsi_src(fpc, fsrc);
394 } else {
395 src[i] = temp(fpc);
396 arith(fpc, 0, MOV, src[i], MASK_ALL,
397 tgsi_src(fpc, fsrc), none, none);
398 }
399 break;
400 case TGSI_FILE_CONSTANT:
401 if ((ci == -1 && ii == -1) ||
402 ci == fsrc->Register.Index) {
403 ci = fsrc->Register.Index;
404 src[i] = tgsi_src(fpc, fsrc);
405 } else {
406 src[i] = temp(fpc);
407 arith(fpc, 0, MOV, src[i], MASK_ALL,
408 tgsi_src(fpc, fsrc), none, none);
409 }
410 break;
411 case TGSI_FILE_IMMEDIATE:
412 if ((ci == -1 && ii == -1) ||
413 ii == fsrc->Register.Index) {
414 ii = fsrc->Register.Index;
415 src[i] = tgsi_src(fpc, fsrc);
416 } else {
417 src[i] = temp(fpc);
418 arith(fpc, 0, MOV, src[i], MASK_ALL,
419 tgsi_src(fpc, fsrc), none, none);
420 }
421 break;
422 case TGSI_FILE_TEMPORARY:
423 /* handled above */
424 break;
425 case TGSI_FILE_SAMPLER:
426 unit = fsrc->Register.Index;
427 break;
428 case TGSI_FILE_OUTPUT:
429 break;
430 default:
431 NOUVEAU_ERR("bad src file\n");
432 return FALSE;
433 }
434 }
435
436 dst = tgsi_dst(fpc, &finst->Dst[0]);
437 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
438 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
439
440 switch (finst->Instruction.Opcode) {
441 case TGSI_OPCODE_ABS:
442 arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none);
443 break;
444 case TGSI_OPCODE_ADD:
445 arith(fpc, sat, ADD, dst, mask, src[0], src[1], none);
446 break;
447 case TGSI_OPCODE_CMP:
448 tmp = nv40_sr(NV40SR_NONE, 0);
449 tmp.cc_update = 1;
450 arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none);
451 dst.cc_test = NV40_VP_INST_COND_GE;
452 arith(fpc, sat, MOV, dst, mask, src[2], none, none);
453 dst.cc_test = NV40_VP_INST_COND_LT;
454 arith(fpc, sat, MOV, dst, mask, src[1], none, none);
455 break;
456 case TGSI_OPCODE_COS:
457 arith(fpc, sat, COS, dst, mask, src[0], none, none);
458 break;
459 case TGSI_OPCODE_DDX:
460 if (mask & (MASK_Z | MASK_W)) {
461 tmp = temp(fpc);
462 arith(fpc, sat, DDX, tmp, MASK_X | MASK_Y,
463 swz(src[0], Z, W, Z, W), none, none);
464 arith(fpc, 0, MOV, tmp, MASK_Z | MASK_W,
465 swz(tmp, X, Y, X, Y), none, none);
466 arith(fpc, sat, DDX, tmp, MASK_X | MASK_Y, src[0],
467 none, none);
468 arith(fpc, 0, MOV, dst, mask, tmp, none, none);
469 } else {
470 arith(fpc, sat, DDX, dst, mask, src[0], none, none);
471 }
472 break;
473 case TGSI_OPCODE_DDY:
474 if (mask & (MASK_Z | MASK_W)) {
475 tmp = temp(fpc);
476 arith(fpc, sat, DDY, tmp, MASK_X | MASK_Y,
477 swz(src[0], Z, W, Z, W), none, none);
478 arith(fpc, 0, MOV, tmp, MASK_Z | MASK_W,
479 swz(tmp, X, Y, X, Y), none, none);
480 arith(fpc, sat, DDY, tmp, MASK_X | MASK_Y, src[0],
481 none, none);
482 arith(fpc, 0, MOV, dst, mask, tmp, none, none);
483 } else {
484 arith(fpc, sat, DDY, dst, mask, src[0], none, none);
485 }
486 break;
487 case TGSI_OPCODE_DP3:
488 arith(fpc, sat, DP3, dst, mask, src[0], src[1], none);
489 break;
490 case TGSI_OPCODE_DP4:
491 arith(fpc, sat, DP4, dst, mask, src[0], src[1], none);
492 break;
493 case TGSI_OPCODE_DPH:
494 tmp = temp(fpc);
495 arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[1], none);
496 arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X),
497 swz(src[1], W, W, W, W), none);
498 break;
499 case TGSI_OPCODE_DST:
500 arith(fpc, sat, DST, dst, mask, src[0], src[1], none);
501 break;
502 case TGSI_OPCODE_EX2:
503 arith(fpc, sat, EX2, dst, mask, src[0], none, none);
504 break;
505 case TGSI_OPCODE_FLR:
506 arith(fpc, sat, FLR, dst, mask, src[0], none, none);
507 break;
508 case TGSI_OPCODE_FRC:
509 arith(fpc, sat, FRC, dst, mask, src[0], none, none);
510 break;
511 case TGSI_OPCODE_KILP:
512 arith(fpc, 0, KIL, none, 0, none, none, none);
513 break;
514 case TGSI_OPCODE_KIL:
515 dst = nv40_sr(NV40SR_NONE, 0);
516 dst.cc_update = 1;
517 arith(fpc, 0, MOV, dst, MASK_ALL, src[0], none, none);
518 dst.cc_update = 0; dst.cc_test = NV40_FP_OP_COND_LT;
519 arith(fpc, 0, KIL, dst, 0, none, none, none);
520 break;
521 case TGSI_OPCODE_LG2:
522 arith(fpc, sat, LG2, dst, mask, src[0], none, none);
523 break;
524 // case TGSI_OPCODE_LIT:
525 case TGSI_OPCODE_LRP:
526 tmp = temp(fpc);
527 arith(fpc, 0, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
528 arith(fpc, sat, MAD, dst, mask, src[0], src[1], tmp);
529 break;
530 case TGSI_OPCODE_MAD:
531 arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]);
532 break;
533 case TGSI_OPCODE_MAX:
534 arith(fpc, sat, MAX, dst, mask, src[0], src[1], none);
535 break;
536 case TGSI_OPCODE_MIN:
537 arith(fpc, sat, MIN, dst, mask, src[0], src[1], none);
538 break;
539 case TGSI_OPCODE_MOV:
540 arith(fpc, sat, MOV, dst, mask, src[0], none, none);
541 break;
542 case TGSI_OPCODE_MUL:
543 arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
544 break;
545 case TGSI_OPCODE_POW:
546 tmp = temp(fpc);
547 arith(fpc, 0, LG2, tmp, MASK_X,
548 swz(src[0], X, X, X, X), none, none);
549 arith(fpc, 0, MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
550 swz(src[1], X, X, X, X), none);
551 arith(fpc, sat, EX2, dst, mask,
552 swz(tmp, X, X, X, X), none, none);
553 break;
554 case TGSI_OPCODE_RCP:
555 arith(fpc, sat, RCP, dst, mask, src[0], none, none);
556 break;
557 case TGSI_OPCODE_RET:
558 assert(0);
559 break;
560 case TGSI_OPCODE_RFL:
561 tmp = temp(fpc);
562 arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[0], none);
563 arith(fpc, 0, DP3, tmp, MASK_Y, src[0], src[1], none);
564 arith(fpc, 0, DIV, scale(tmp, 2X), MASK_Z,
565 swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
566 arith(fpc, sat, MAD, dst, mask,
567 swz(tmp, Z, Z, Z, Z), src[0], neg(src[1]));
568 break;
569 case TGSI_OPCODE_RSQ:
570 tmp = temp(fpc);
571 arith(fpc, 0, LG2, scale(tmp, INV_2X), MASK_X,
572 abs(swz(src[0], X, X, X, X)), none, none);
573 arith(fpc, sat, EX2, dst, mask,
574 neg(swz(tmp, X, X, X, X)), none, none);
575 break;
576 case TGSI_OPCODE_SCS:
577 /* avoid overwriting the source */
578 if(src[0].swz[SWZ_X] != SWZ_X)
579 {
580 if (mask & MASK_X) {
581 arith(fpc, sat, COS, dst, MASK_X,
582 swz(src[0], X, X, X, X), none, none);
583 }
584 if (mask & MASK_Y) {
585 arith(fpc, sat, SIN, dst, MASK_Y,
586 swz(src[0], X, X, X, X), none, none);
587 }
588 }
589 else
590 {
591 if (mask & MASK_Y) {
592 arith(fpc, sat, SIN, dst, MASK_Y,
593 swz(src[0], X, X, X, X), none, none);
594 }
595 if (mask & MASK_X) {
596 arith(fpc, sat, COS, dst, MASK_X,
597 swz(src[0], X, X, X, X), none, none);
598 }
599 }
600 break;
601 case TGSI_OPCODE_SEQ:
602 arith(fpc, sat, SEQ, dst, mask, src[0], src[1], none);
603 break;
604 case TGSI_OPCODE_SFL:
605 arith(fpc, sat, SFL, dst, mask, src[0], src[1], none);
606 break;
607 case TGSI_OPCODE_SGE:
608 arith(fpc, sat, SGE, dst, mask, src[0], src[1], none);
609 break;
610 case TGSI_OPCODE_SGT:
611 arith(fpc, sat, SGT, dst, mask, src[0], src[1], none);
612 break;
613 case TGSI_OPCODE_SIN:
614 arith(fpc, sat, SIN, dst, mask, src[0], none, none);
615 break;
616 case TGSI_OPCODE_SLE:
617 arith(fpc, sat, SLE, dst, mask, src[0], src[1], none);
618 break;
619 case TGSI_OPCODE_SLT:
620 arith(fpc, sat, SLT, dst, mask, src[0], src[1], none);
621 break;
622 case TGSI_OPCODE_SNE:
623 arith(fpc, sat, SNE, dst, mask, src[0], src[1], none);
624 break;
625 case TGSI_OPCODE_STR:
626 arith(fpc, sat, STR, dst, mask, src[0], src[1], none);
627 break;
628 case TGSI_OPCODE_SUB:
629 arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none);
630 break;
631 case TGSI_OPCODE_TEX:
632 tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none);
633 break;
634 case TGSI_OPCODE_TXB:
635 tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none);
636 break;
637 case TGSI_OPCODE_TXP:
638 tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none);
639 break;
640 case TGSI_OPCODE_XPD:
641 tmp = temp(fpc);
642 arith(fpc, 0, MUL, tmp, mask,
643 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
644 arith(fpc, sat, MAD, dst, (mask & ~MASK_W),
645 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
646 neg(tmp));
647 break;
648 default:
649 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
650 return FALSE;
651 }
652
653 release_temps(fpc);
654 return TRUE;
655 }
656
657 static boolean
658 nv40_fragprog_parse_decl_attrib(struct nv40_fpc *fpc,
659 const struct tgsi_full_declaration *fdec)
660 {
661 int hw;
662
663 switch (fdec->Semantic.Name) {
664 case TGSI_SEMANTIC_POSITION:
665 hw = NV40_FP_OP_INPUT_SRC_POSITION;
666 break;
667 case TGSI_SEMANTIC_COLOR:
668 if (fdec->Semantic.Index == 0) {
669 hw = NV40_FP_OP_INPUT_SRC_COL0;
670 } else
671 if (fdec->Semantic.Index == 1) {
672 hw = NV40_FP_OP_INPUT_SRC_COL1;
673 } else {
674 NOUVEAU_ERR("bad colour semantic index\n");
675 return FALSE;
676 }
677 break;
678 case TGSI_SEMANTIC_FOG:
679 hw = NV40_FP_OP_INPUT_SRC_FOGC;
680 break;
681 case TGSI_SEMANTIC_GENERIC:
682 if (fdec->Semantic.Index <= 7) {
683 hw = NV40_FP_OP_INPUT_SRC_TC(fdec->Semantic.
684 Index);
685 } else {
686 NOUVEAU_ERR("bad generic semantic index\n");
687 return FALSE;
688 }
689 break;
690 default:
691 NOUVEAU_ERR("bad input semantic\n");
692 return FALSE;
693 }
694
695 fpc->attrib_map[fdec->Range.First] = hw;
696 return TRUE;
697 }
698
699 static boolean
700 nv40_fragprog_parse_decl_output(struct nv40_fpc *fpc,
701 const struct tgsi_full_declaration *fdec)
702 {
703 unsigned idx = fdec->Range.First;
704 unsigned hw;
705
706 switch (fdec->Semantic.Name) {
707 case TGSI_SEMANTIC_POSITION:
708 hw = 1;
709 break;
710 case TGSI_SEMANTIC_COLOR:
711 switch (fdec->Semantic.Index) {
712 case 0: hw = 0; break;
713 case 1: hw = 2; break;
714 case 2: hw = 3; break;
715 case 3: hw = 4; break;
716 default:
717 NOUVEAU_ERR("bad rcol index\n");
718 return FALSE;
719 }
720 break;
721 default:
722 NOUVEAU_ERR("bad output semantic\n");
723 return FALSE;
724 }
725
726 fpc->r_result[idx] = nv40_sr(NV40SR_OUTPUT, hw);
727 fpc->r_temps |= (1 << hw);
728 return TRUE;
729 }
730
731 static boolean
732 nv40_fragprog_prepare(struct nv40_fpc *fpc)
733 {
734 struct tgsi_parse_context p;
735 int high_temp = -1, i;
736
737 tgsi_parse_init(&p, fpc->fp->pipe.tokens);
738 while (!tgsi_parse_end_of_tokens(&p)) {
739 const union tgsi_full_token *tok = &p.FullToken;
740
741 tgsi_parse_token(&p);
742 switch(tok->Token.Type) {
743 case TGSI_TOKEN_TYPE_DECLARATION:
744 {
745 const struct tgsi_full_declaration *fdec;
746 fdec = &p.FullToken.FullDeclaration;
747 switch (fdec->Declaration.File) {
748 case TGSI_FILE_INPUT:
749 if (!nv40_fragprog_parse_decl_attrib(fpc, fdec))
750 goto out_err;
751 break;
752 case TGSI_FILE_OUTPUT:
753 if (!nv40_fragprog_parse_decl_output(fpc, fdec))
754 goto out_err;
755 break;
756 case TGSI_FILE_TEMPORARY:
757 if (fdec->Range.Last > high_temp) {
758 high_temp =
759 fdec->Range.Last;
760 }
761 break;
762 default:
763 break;
764 }
765 }
766 break;
767 case TGSI_TOKEN_TYPE_IMMEDIATE:
768 {
769 struct tgsi_full_immediate *imm;
770 float vals[4];
771
772 imm = &p.FullToken.FullImmediate;
773 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
774 assert(fpc->nr_imm < MAX_IMM);
775
776 vals[0] = imm->u[0].Float;
777 vals[1] = imm->u[1].Float;
778 vals[2] = imm->u[2].Float;
779 vals[3] = imm->u[3].Float;
780 fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals);
781 }
782 break;
783 default:
784 break;
785 }
786 }
787 tgsi_parse_free(&p);
788
789 if (++high_temp) {
790 fpc->r_temp = CALLOC(high_temp, sizeof(struct nv40_sreg));
791 for (i = 0; i < high_temp; i++)
792 fpc->r_temp[i] = temp(fpc);
793 fpc->r_temps_discard = 0;
794 }
795
796 return TRUE;
797
798 out_err:
799 if (fpc->r_temp)
800 FREE(fpc->r_temp);
801 tgsi_parse_free(&p);
802 return FALSE;
803 }
804
805 static void
806 nv40_fragprog_translate(struct nv40_context *nv40,
807 struct nv40_fragment_program *fp)
808 {
809 struct tgsi_parse_context parse;
810 struct nv40_fpc *fpc = NULL;
811
812 fpc = CALLOC(1, sizeof(struct nv40_fpc));
813 if (!fpc)
814 return;
815 fpc->fp = fp;
816 fpc->num_regs = 2;
817
818 if (!nv40_fragprog_prepare(fpc)) {
819 FREE(fpc);
820 return;
821 }
822
823 tgsi_parse_init(&parse, fp->pipe.tokens);
824
825 while (!tgsi_parse_end_of_tokens(&parse)) {
826 tgsi_parse_token(&parse);
827
828 switch (parse.FullToken.Token.Type) {
829 case TGSI_TOKEN_TYPE_INSTRUCTION:
830 {
831 const struct tgsi_full_instruction *finst;
832
833 finst = &parse.FullToken.FullInstruction;
834 if (!nv40_fragprog_parse_instruction(fpc, finst))
835 goto out_err;
836 }
837 break;
838 default:
839 break;
840 }
841 }
842
843 fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT;
844
845 /* Terminate final instruction */
846 fp->insn[fpc->inst_offset] |= 0x00000001;
847
848 /* Append NOP + END instruction, may or may not be necessary. */
849 fpc->inst_offset = fp->insn_len;
850 grow_insns(fpc, 4);
851 fp->insn[fpc->inst_offset + 0] = 0x00000001;
852 fp->insn[fpc->inst_offset + 1] = 0x00000000;
853 fp->insn[fpc->inst_offset + 2] = 0x00000000;
854 fp->insn[fpc->inst_offset + 3] = 0x00000000;
855
856 fp->translated = TRUE;
857 out_err:
858 tgsi_parse_free(&parse);
859 if (fpc->r_temp)
860 FREE(fpc->r_temp);
861 FREE(fpc);
862 }
863
864 static void
865 nv40_fragprog_upload(struct nv40_context *nv40,
866 struct nv40_fragment_program *fp)
867 {
868 struct pipe_screen *pscreen = nv40->pipe.screen;
869 const uint32_t le = 1;
870 uint32_t *map;
871 int i;
872
873 map = pipe_buffer_map(pscreen, fp->buffer, PIPE_BUFFER_USAGE_CPU_WRITE);
874
875 #if 0
876 for (i = 0; i < fp->insn_len; i++) {
877 fflush(stdout); fflush(stderr);
878 NOUVEAU_ERR("%d 0x%08x\n", i, fp->insn[i]);
879 fflush(stdout); fflush(stderr);
880 }
881 #endif
882
883 if ((*(const uint8_t *)&le)) {
884 for (i = 0; i < fp->insn_len; i++) {
885 map[i] = fp->insn[i];
886 }
887 } else {
888 /* Weird swapping for big-endian chips */
889 for (i = 0; i < fp->insn_len; i++) {
890 map[i] = ((fp->insn[i] & 0xffff) << 16) |
891 ((fp->insn[i] >> 16) & 0xffff);
892 }
893 }
894
895 pipe_buffer_unmap(pscreen, fp->buffer);
896 }
897
898 static boolean
899 nv40_fragprog_validate(struct nv40_context *nv40)
900 {
901 struct nv40_fragment_program *fp = nv40->fragprog;
902 struct pipe_buffer *constbuf =
903 nv40->constbuf[PIPE_SHADER_FRAGMENT];
904 struct pipe_screen *pscreen = nv40->pipe.screen;
905 struct nouveau_stateobj *so;
906 boolean new_consts = FALSE;
907 int i;
908
909 if (fp->translated)
910 goto update_constants;
911
912 nv40->fallback_swrast &= ~NV40_NEW_FRAGPROG;
913 nv40_fragprog_translate(nv40, fp);
914 if (!fp->translated) {
915 nv40->fallback_swrast |= NV40_NEW_FRAGPROG;
916 return FALSE;
917 }
918
919 fp->buffer = pscreen->buffer_create(pscreen, 0x100, 0, fp->insn_len * 4);
920 nv40_fragprog_upload(nv40, fp);
921
922 so = so_new(2, 2, 1);
923 so_method(so, nv40->screen->curie, NV40TCL_FP_ADDRESS, 1);
924 so_reloc (so, nouveau_bo(fp->buffer), 0, NOUVEAU_BO_VRAM |
925 NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
926 NOUVEAU_BO_OR, NV40TCL_FP_ADDRESS_DMA0,
927 NV40TCL_FP_ADDRESS_DMA1);
928 so_method(so, nv40->screen->curie, NV40TCL_FP_CONTROL, 1);
929 so_data (so, fp->fp_control);
930 so_ref(so, &fp->so);
931 so_ref(NULL, &so);
932
933 update_constants:
934 if (fp->nr_consts) {
935 float *map;
936
937 map = pipe_buffer_map(pscreen, constbuf,
938 PIPE_BUFFER_USAGE_CPU_READ);
939 for (i = 0; i < fp->nr_consts; i++) {
940 struct nv40_fragment_program_data *fpd = &fp->consts[i];
941 uint32_t *p = &fp->insn[fpd->offset];
942 uint32_t *cb = (uint32_t *)&map[fpd->index * 4];
943
944 if (!memcmp(p, cb, 4 * sizeof(float)))
945 continue;
946 memcpy(p, cb, 4 * sizeof(float));
947 new_consts = TRUE;
948 }
949 pipe_buffer_unmap(pscreen, constbuf);
950
951 if (new_consts)
952 nv40_fragprog_upload(nv40, fp);
953 }
954
955 if (new_consts || fp->so != nv40->state.hw[NV40_STATE_FRAGPROG]) {
956 so_ref(fp->so, &nv40->state.hw[NV40_STATE_FRAGPROG]);
957 return TRUE;
958 }
959
960 return FALSE;
961 }
962
963 void
964 nv40_fragprog_destroy(struct nv40_context *nv40,
965 struct nv40_fragment_program *fp)
966 {
967 if (fp->buffer)
968 pipe_buffer_reference(&fp->buffer, NULL);
969
970 if (fp->so)
971 so_ref(NULL, &fp->so);
972
973 if (fp->insn_len)
974 FREE(fp->insn);
975 }
976
977 struct nv40_state_entry nv40_state_fragprog = {
978 .validate = nv40_fragprog_validate,
979 .dirty = {
980 .pipe = NV40_NEW_FRAGPROG,
981 .hw = NV40_STATE_FRAGPROG
982 }
983 };
984