src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2
   3 #include "nv40_context.h"
   4 #include "nv40_screen.h"
   5
   6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
   9
  10 static int
  11 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  12 {
  13         struct nv40_screen *screen = nv40_screen(pscreen);
  14
  15         switch (param) {
  16         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  17                 return 16;
  18         case PIPE_CAP_NPOT_TEXTURES:
  19                 return 1;
  20         case PIPE_CAP_TWO_SIDED_STENCIL:
  21                 return 1;
  22         case PIPE_CAP_GLSL:
  23                 return 0;
  24         case PIPE_CAP_ANISOTROPIC_FILTER:
  25                 return 1;
  26         case PIPE_CAP_POINT_SPRITE:
  27                 return 1;
  28         case PIPE_CAP_MAX_RENDER_TARGETS:
  29                 return 4;
  30         case PIPE_CAP_OCCLUSION_QUERY:
  31                 return 1;
  32         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  33                 return 1;
  34         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  35                 return 13;
  36         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  37                 return 10;
  38         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  39                 return 13;
  40         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  41         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  42                 return 1;
  43         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  44                 return 0; /* We have 4 - but unsupported currently */
  45         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  46                 return 0;
  47         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  48                 return 1;
  49         case NOUVEAU_CAP_HW_VTXBUF:
  50                 return 1;
  51         case NOUVEAU_CAP_HW_IDXBUF:
  52                 if (screen->curie->grclass == NV40TCL)
  53                         return 1;
  54                 return 0;
  55         default:
  56                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  57                 return 0;
  58         }
  59 }
  60
  61 static float
  62 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  63 {
  64         switch (param) {
  65         case PIPE_CAP_MAX_LINE_WIDTH:
  66         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  67                 return 10.0;
  68         case PIPE_CAP_MAX_POINT_WIDTH:
  69         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  70                 return 64.0;
  71         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  72                 return 16.0;
  73         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  74                 return 16.0;
  75         default:
  76                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  77                 return 0.0;
  78         }
  79 }
  80
  81 static boolean
  82 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  83                                      enum pipe_format format,
  84                                      enum pipe_texture_target target,
  85                                      unsigned tex_usage, unsigned geom_flags)
  86 {
  87         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
  88                 switch (format) {
  89                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  90                 case PIPE_FORMAT_R5G6B5_UNORM:
  91                         return TRUE;
  92                 default:
  93                         break;
  94                 }
  95         } else
  96         if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
  97                 switch (format) {
  98                 case PIPE_FORMAT_Z24S8_UNORM:
  99                 case PIPE_FORMAT_Z24X8_UNORM:
 100                 case PIPE_FORMAT_Z16_UNORM:
 101                         return TRUE;
 102                 default:
 103                         break;
 104                 }
 105         } else {
 106                 switch (format) {
 107                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 108                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 109                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 110                 case PIPE_FORMAT_R5G6B5_UNORM:
 111                 case PIPE_FORMAT_R16_SNORM:
 112                 case PIPE_FORMAT_L8_UNORM:
 113                 case PIPE_FORMAT_A8_UNORM:
 114                 case PIPE_FORMAT_I8_UNORM:
 115                 case PIPE_FORMAT_A8L8_UNORM:
 116                 case PIPE_FORMAT_Z16_UNORM:
 117                 case PIPE_FORMAT_Z24S8_UNORM:
 118                 case PIPE_FORMAT_DXT1_RGB:
 119                 case PIPE_FORMAT_DXT1_RGBA:
 120                 case PIPE_FORMAT_DXT3_RGBA:
 121                 case PIPE_FORMAT_DXT5_RGBA:
 122                         return TRUE;
 123                 default:
 124                         break;
 125                 }
 126         }
 127
 128         return FALSE;
 129 }
 130
 131 static struct pipe_buffer *
 132 nv40_surface_buffer(struct pipe_surface *surf)
 133 {
 134         struct nv40_miptree *mt = (struct nv40_miptree *)surf->texture;
 135
 136         return mt->buffer;
 137 }
 138
 139 static void
 140 nv40_screen_destroy(struct pipe_screen *pscreen)
 141 {
 142         struct nv40_screen *screen = nv40_screen(pscreen);
 143         unsigned i;
 144
 145         for (i = 0; i < NV40_STATE_MAX; i++) {
 146                 if (screen->state[i])
 147                         so_ref(NULL, &screen->state[i]);
 148         }
 149
 150         nouveau_resource_free(&screen->vp_exec_heap);
 151         nouveau_resource_free(&screen->vp_data_heap);
 152         nouveau_resource_free(&screen->query_heap);
 153         nouveau_notifier_free(&screen->query);
 154         nouveau_notifier_free(&screen->sync);
 155         nouveau_grobj_free(&screen->curie);
 156         nv04_surface_2d_takedown(&screen->eng2d);
 157
 158         nouveau_screen_fini(&screen->base);
 159
 160         FREE(pscreen);
 161 }
 162
 163 struct pipe_screen *
 164 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 165 {
 166         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 167         struct nouveau_channel *chan;
 168         struct pipe_screen *pscreen;
 169         struct nouveau_stateobj *so;
 170         unsigned curie_class = 0;
 171         int ret;
 172
 173         if (!screen)
 174                 return NULL;
 175         pscreen = &screen->base.base;
 176
 177         ret = nouveau_screen_init(&screen->base, dev);
 178         if (ret) {
 179                 nv40_screen_destroy(pscreen);
 180                 return NULL;
 181         }
 182         chan = screen->base.channel;
 183
 184         pscreen->winsys = ws;
 185         pscreen->destroy = nv40_screen_destroy;
 186         pscreen->get_param = nv40_screen_get_param;
 187         pscreen->get_paramf = nv40_screen_get_paramf;
 188         pscreen->is_format_supported = nv40_screen_surface_format_supported;
 189
 190         nv40_screen_init_miptree_functions(pscreen);
 191         nv40_screen_init_transfer_functions(pscreen);
 192
 193         /* 3D object */
 194         switch (dev->chipset & 0xf0) {
 195         case 0x40:
 196                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 197                         curie_class = NV40TCL;
 198                 else
 199                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 200                         curie_class = NV44TCL;
 201                 break;
 202         case 0x60:
 203                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 204                         curie_class = NV44TCL;
 205                 break;
 206         }
 207
 208         if (!curie_class) {
 209                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev->chipset);
 210                 return NULL;
 211         }
 212
 213         ret = nouveau_grobj_alloc(chan, 0xbeef3097, curie_class, &screen->curie);
 214         if (ret) {
 215                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 216                 return FALSE;
 217         }
 218
 219         /* 2D engine setup */
 220         screen->eng2d = nv04_surface_2d_init(&screen->base);
 221         screen->eng2d->buf = nv40_surface_buffer;
 222
 223         /* Notifier for sync purposes */
 224         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 225         if (ret) {
 226                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 227                 nv40_screen_destroy(pscreen);
 228                 return NULL;
 229         }
 230
 231         /* Query objects */
 232         ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
 233         if (ret) {
 234                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 235                 nv40_screen_destroy(pscreen);
 236                 return NULL;
 237         }
 238
 239         nouveau_resource_init(&screen->query_heap, 0, 32);
 240         if (ret) {
 241                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 242                 nv40_screen_destroy(pscreen);
 243                 return NULL;
 244         }
 245
 246         /* Vtxprog resources */
 247         if (nouveau_resource_init(&screen->vp_exec_heap, 0, 512) ||
 248             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 249                 nv40_screen_destroy(pscreen);
 250                 return NULL;
 251         }
 252
 253         /* Static curie initialisation */
 254         so = so_new(16, 25, 0);
 255         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 256         so_data  (so, screen->sync->handle);
 257         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 258         so_data  (so, chan->vram->handle);
 259         so_data  (so, chan->gart->handle);
 260         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 261         so_data  (so, chan->vram->handle);
 262         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 263         so_data  (so, chan->vram->handle);
 264         so_data  (so, chan->vram->handle);
 265         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 266         so_data  (so, chan->vram->handle);
 267         so_data  (so, chan->gart->handle);
 268         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 269         so_data  (so, 0);
 270         so_data  (so, screen->query->handle);
 271         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 272         so_data  (so, chan->vram->handle);
 273         so_data  (so, chan->vram->handle);
 274         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 275         so_data  (so, chan->vram->handle);
 276         so_data  (so, chan->vram->handle);
 277
 278         so_method(so, screen->curie, 0x1ea4, 3);
 279         so_data  (so, 0x00000010);
 280         so_data  (so, 0x01000100);
 281         so_data  (so, 0xff800006);
 282
 283         /* vtxprog output routing */
 284         so_method(so, screen->curie, 0x1fc4, 1);
 285         so_data  (so, 0x06144321);
 286         so_method(so, screen->curie, 0x1fc8, 2);
 287         so_data  (so, 0xedcba987);
 288         so_data  (so, 0x00000021);
 289         so_method(so, screen->curie, 0x1fd0, 1);
 290         so_data  (so, 0x00171615);
 291         so_method(so, screen->curie, 0x1fd4, 1);
 292         so_data  (so, 0x001b1a19);
 293
 294         so_method(so, screen->curie, 0x1ef8, 1);
 295         so_data  (so, 0x0020ffff);
 296         so_method(so, screen->curie, 0x1d64, 1);
 297         so_data  (so, 0x00d30000);
 298         so_method(so, screen->curie, 0x1e94, 1);
 299         so_data  (so, 0x00000001);
 300
 301         so_emit(chan, so);
 302         so_ref(NULL, &so);
 303         nouveau_pushbuf_flush(chan, 0);
 304
 305         return pscreen;
 306 }
 307