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r600: don't enable depth test if there is no depth buffer
[mesa.git] / src / gallium / drivers / nv40 / nv40_shader.h
1 #ifndef __NV40_SHADER_H__
2 #define __NV40_SHADER_H__
3
4 /* Vertex programs instruction set
5 *
6 * The NV40 instruction set is very similar to NV30. Most fields are in
7 * a slightly different position in the instruction however.
8 *
9 * Merged instructions
10 * In some cases it is possible to put two instructions into one opcode
11 * slot. The rules for when this is OK is not entirely clear to me yet.
12 *
13 * There are separate writemasks and dest temp register fields for each
14 * grouping of instructions. There is however only one field with the
15 * ID of a result register. Writing to temp/result regs is selected by
16 * setting VEC_RESULT/SCA_RESULT.
17 *
18 * Temporary registers
19 * The source/dest temp register fields have been extended by 1 bit, to
20 * give a total of 32 temporary registers.
21 *
22 * Relative Addressing
23 * NV40 can use an address register to index into vertex attribute regs.
24 * This is done by putting the offset value into INPUT_SRC and setting
25 * the INDEX_INPUT flag.
26 *
27 * Conditional execution (see NV_vertex_program{2,3} for details)
28 * There is a second condition code register on NV40, it's use is enabled
29 * by setting the COND_REG_SELECT_1 flag.
30 *
31 * Texture lookup
32 * TODO
33 */
34
35 /* ---- OPCODE BITS 127:96 / data DWORD 0 --- */
36 #define NV40_VP_INST_VEC_RESULT (1 << 30)
37 /* uncertain.. */
38 #define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29)
39 /* use address reg as index into attribs */
40 #define NV40_VP_INST_INDEX_INPUT (1 << 27)
41 #define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25)
42 #define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24)
43 #define NV40_VP_INST_SRC2_ABS (1 << 23)
44 #define NV40_VP_INST_SRC1_ABS (1 << 22)
45 #define NV40_VP_INST_SRC0_ABS (1 << 21)
46 #define NV40_VP_INST_VEC_DEST_TEMP_SHIFT 15
47 #define NV40_VP_INST_VEC_DEST_TEMP_MASK (0x1F << 15)
48 #define NV40_VP_INST_COND_TEST_ENABLE (1 << 13)
49 #define NV40_VP_INST_COND_SHIFT 10
50 #define NV40_VP_INST_COND_MASK (0x7 << 10)
51 # define NV40_VP_INST_COND_FL 0
52 # define NV40_VP_INST_COND_LT 1
53 # define NV40_VP_INST_COND_EQ 2
54 # define NV40_VP_INST_COND_LE 3
55 # define NV40_VP_INST_COND_GT 4
56 # define NV40_VP_INST_COND_NE 5
57 # define NV40_VP_INST_COND_GE 6
58 # define NV40_VP_INST_COND_TR 7
59 #define NV40_VP_INST_COND_SWZ_X_SHIFT 8
60 #define NV40_VP_INST_COND_SWZ_X_MASK (3 << 8)
61 #define NV40_VP_INST_COND_SWZ_Y_SHIFT 6
62 #define NV40_VP_INST_COND_SWZ_Y_MASK (3 << 6)
63 #define NV40_VP_INST_COND_SWZ_Z_SHIFT 4
64 #define NV40_VP_INST_COND_SWZ_Z_MASK (3 << 4)
65 #define NV40_VP_INST_COND_SWZ_W_SHIFT 2
66 #define NV40_VP_INST_COND_SWZ_W_MASK (3 << 2)
67 #define NV40_VP_INST_COND_SWZ_ALL_SHIFT 2
68 #define NV40_VP_INST_COND_SWZ_ALL_MASK (0xFF << 2)
69 #define NV40_VP_INST_ADDR_SWZ_SHIFT 0
70 #define NV40_VP_INST_ADDR_SWZ_MASK (0x03 << 0)
71 #define NV40_VP_INST0_KNOWN ( \
72 NV40_VP_INST_INDEX_INPUT | \
73 NV40_VP_INST_COND_REG_SELECT_1 | \
74 NV40_VP_INST_ADDR_REG_SELECT_1 | \
75 NV40_VP_INST_SRC2_ABS | \
76 NV40_VP_INST_SRC1_ABS | \
77 NV40_VP_INST_SRC0_ABS | \
78 NV40_VP_INST_VEC_DEST_TEMP_MASK | \
79 NV40_VP_INST_COND_TEST_ENABLE | \
80 NV40_VP_INST_COND_MASK | \
81 NV40_VP_INST_COND_SWZ_ALL_MASK | \
82 NV40_VP_INST_ADDR_SWZ_MASK)
83
84 /* ---- OPCODE BITS 95:64 / data DWORD 1 --- */
85 #define NV40_VP_INST_VEC_OPCODE_SHIFT 22
86 #define NV40_VP_INST_VEC_OPCODE_MASK (0x1F << 22)
87 # define NV40_VP_INST_OP_NOP 0x00
88 # define NV40_VP_INST_OP_MOV 0x01
89 # define NV40_VP_INST_OP_MUL 0x02
90 # define NV40_VP_INST_OP_ADD 0x03
91 # define NV40_VP_INST_OP_MAD 0x04
92 # define NV40_VP_INST_OP_DP3 0x05
93 # define NV40_VP_INST_OP_DPH 0x06
94 # define NV40_VP_INST_OP_DP4 0x07
95 # define NV40_VP_INST_OP_DST 0x08
96 # define NV40_VP_INST_OP_MIN 0x09
97 # define NV40_VP_INST_OP_MAX 0x0A
98 # define NV40_VP_INST_OP_SLT 0x0B
99 # define NV40_VP_INST_OP_SGE 0x0C
100 # define NV40_VP_INST_OP_ARL 0x0D
101 # define NV40_VP_INST_OP_FRC 0x0E
102 # define NV40_VP_INST_OP_FLR 0x0F
103 # define NV40_VP_INST_OP_SEQ 0x10
104 # define NV40_VP_INST_OP_SFL 0x11
105 # define NV40_VP_INST_OP_SGT 0x12
106 # define NV40_VP_INST_OP_SLE 0x13
107 # define NV40_VP_INST_OP_SNE 0x14
108 # define NV40_VP_INST_OP_STR 0x15
109 # define NV40_VP_INST_OP_SSG 0x16
110 # define NV40_VP_INST_OP_ARR 0x17
111 # define NV40_VP_INST_OP_ARA 0x18
112 # define NV40_VP_INST_OP_TXL 0x19
113 #define NV40_VP_INST_SCA_OPCODE_SHIFT 27
114 #define NV40_VP_INST_SCA_OPCODE_MASK (0x1F << 27)
115 # define NV40_VP_INST_OP_NOP 0x00
116 # define NV40_VP_INST_OP_MOV 0x01
117 # define NV40_VP_INST_OP_RCP 0x02
118 # define NV40_VP_INST_OP_RCC 0x03
119 # define NV40_VP_INST_OP_RSQ 0x04
120 # define NV40_VP_INST_OP_EXP 0x05
121 # define NV40_VP_INST_OP_LOG 0x06
122 # define NV40_VP_INST_OP_LIT 0x07
123 # define NV40_VP_INST_OP_BRA 0x09
124 # define NV40_VP_INST_OP_CAL 0x0B
125 # define NV40_VP_INST_OP_RET 0x0C
126 # define NV40_VP_INST_OP_LG2 0x0D
127 # define NV40_VP_INST_OP_EX2 0x0E
128 # define NV40_VP_INST_OP_SIN 0x0F
129 # define NV40_VP_INST_OP_COS 0x10
130 # define NV40_VP_INST_OP_PUSHA 0x13
131 # define NV40_VP_INST_OP_POPA 0x14
132 #define NV40_VP_INST_CONST_SRC_SHIFT 12
133 #define NV40_VP_INST_CONST_SRC_MASK (0xFF << 12)
134 #define NV40_VP_INST_INPUT_SRC_SHIFT 8
135 #define NV40_VP_INST_INPUT_SRC_MASK (0x0F << 8)
136 # define NV40_VP_INST_IN_POS 0
137 # define NV40_VP_INST_IN_WEIGHT 1
138 # define NV40_VP_INST_IN_NORMAL 2
139 # define NV40_VP_INST_IN_COL0 3
140 # define NV40_VP_INST_IN_COL1 4
141 # define NV40_VP_INST_IN_FOGC 5
142 # define NV40_VP_INST_IN_TC0 8
143 # define NV40_VP_INST_IN_TC(n) (8+n)
144 #define NV40_VP_INST_SRC0H_SHIFT 0
145 #define NV40_VP_INST_SRC0H_MASK (0xFF << 0)
146 #define NV40_VP_INST1_KNOWN ( \
147 NV40_VP_INST_VEC_OPCODE_MASK | \
148 NV40_VP_INST_SCA_OPCODE_MASK | \
149 NV40_VP_INST_CONST_SRC_MASK | \
150 NV40_VP_INST_INPUT_SRC_MASK | \
151 NV40_VP_INST_SRC0H_MASK \
152 )
153
154 /* ---- OPCODE BITS 63:32 / data DWORD 2 --- */
155 #define NV40_VP_INST_SRC0L_SHIFT 23
156 #define NV40_VP_INST_SRC0L_MASK (0x1FF << 23)
157 #define NV40_VP_INST_SRC1_SHIFT 6
158 #define NV40_VP_INST_SRC1_MASK (0x1FFFF << 6)
159 #define NV40_VP_INST_SRC2H_SHIFT 0
160 #define NV40_VP_INST_SRC2H_MASK (0x3F << 0)
161 #define NV40_VP_INST_IADDRH_SHIFT 0
162 #define NV40_VP_INST_IADDRH_MASK (0x1F << 0)
163
164 /* ---- OPCODE BITS 31:0 / data DWORD 3 --- */
165 #define NV40_VP_INST_IADDRL_SHIFT 29
166 #define NV40_VP_INST_IADDRL_MASK (7 << 29)
167 #define NV40_VP_INST_SRC2L_SHIFT 21
168 #define NV40_VP_INST_SRC2L_MASK (0x7FF << 21)
169 #define NV40_VP_INST_SCA_WRITEMASK_SHIFT 17
170 #define NV40_VP_INST_SCA_WRITEMASK_MASK (0xF << 17)
171 # define NV40_VP_INST_SCA_WRITEMASK_X (1 << 20)
172 # define NV40_VP_INST_SCA_WRITEMASK_Y (1 << 19)
173 # define NV40_VP_INST_SCA_WRITEMASK_Z (1 << 18)
174 # define NV40_VP_INST_SCA_WRITEMASK_W (1 << 17)
175 #define NV40_VP_INST_VEC_WRITEMASK_SHIFT 13
176 #define NV40_VP_INST_VEC_WRITEMASK_MASK (0xF << 13)
177 # define NV40_VP_INST_VEC_WRITEMASK_X (1 << 16)
178 # define NV40_VP_INST_VEC_WRITEMASK_Y (1 << 15)
179 # define NV40_VP_INST_VEC_WRITEMASK_Z (1 << 14)
180 # define NV40_VP_INST_VEC_WRITEMASK_W (1 << 13)
181 #define NV40_VP_INST_SCA_RESULT (1 << 12)
182 #define NV40_VP_INST_SCA_DEST_TEMP_SHIFT 7
183 #define NV40_VP_INST_SCA_DEST_TEMP_MASK (0x1F << 7)
184 #define NV40_VP_INST_DEST_SHIFT 2
185 #define NV40_VP_INST_DEST_MASK (31 << 2)
186 # define NV40_VP_INST_DEST_POS 0
187 # define NV40_VP_INST_DEST_COL0 1
188 # define NV40_VP_INST_DEST_COL1 2
189 # define NV40_VP_INST_DEST_BFC0 3
190 # define NV40_VP_INST_DEST_BFC1 4
191 # define NV40_VP_INST_DEST_FOGC 5
192 # define NV40_VP_INST_DEST_PSZ 6
193 # define NV40_VP_INST_DEST_TC0 7
194 # define NV40_VP_INST_DEST_TC(n) (7+n)
195 # define NV40_VP_INST_DEST_TEMP 0x1F
196 #define NV40_VP_INST_INDEX_CONST (1 << 1)
197 #define NV40_VP_INST_LAST (1 << 0)
198 #define NV40_VP_INST3_KNOWN ( \
199 NV40_VP_INST_SRC2L_MASK |\
200 NV40_VP_INST_SCA_WRITEMASK_MASK |\
201 NV40_VP_INST_VEC_WRITEMASK_MASK |\
202 NV40_VP_INST_SCA_DEST_TEMP_MASK |\
203 NV40_VP_INST_DEST_MASK |\
204 NV40_VP_INST_INDEX_CONST)
205
206 /* Useful to split the source selection regs into their pieces */
207 #define NV40_VP_SRC0_HIGH_SHIFT 9
208 #define NV40_VP_SRC0_HIGH_MASK 0x0001FE00
209 #define NV40_VP_SRC0_LOW_MASK 0x000001FF
210 #define NV40_VP_SRC2_HIGH_SHIFT 11
211 #define NV40_VP_SRC2_HIGH_MASK 0x0001F800
212 #define NV40_VP_SRC2_LOW_MASK 0x000007FF
213
214 /* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */
215 #define NV40_VP_SRC_NEGATE (1 << 16)
216 #define NV40_VP_SRC_SWZ_X_SHIFT 14
217 #define NV40_VP_SRC_SWZ_X_MASK (3 << 14)
218 #define NV40_VP_SRC_SWZ_Y_SHIFT 12
219 #define NV40_VP_SRC_SWZ_Y_MASK (3 << 12)
220 #define NV40_VP_SRC_SWZ_Z_SHIFT 10
221 #define NV40_VP_SRC_SWZ_Z_MASK (3 << 10)
222 #define NV40_VP_SRC_SWZ_W_SHIFT 8
223 #define NV40_VP_SRC_SWZ_W_MASK (3 << 8)
224 #define NV40_VP_SRC_SWZ_ALL_SHIFT 8
225 #define NV40_VP_SRC_SWZ_ALL_MASK (0xFF << 8)
226 #define NV40_VP_SRC_TEMP_SRC_SHIFT 2
227 #define NV40_VP_SRC_TEMP_SRC_MASK (0x1F << 2)
228 #define NV40_VP_SRC_REG_TYPE_SHIFT 0
229 #define NV40_VP_SRC_REG_TYPE_MASK (3 << 0)
230 # define NV40_VP_SRC_REG_TYPE_UNK0 0
231 # define NV40_VP_SRC_REG_TYPE_TEMP 1
232 # define NV40_VP_SRC_REG_TYPE_INPUT 2
233 # define NV40_VP_SRC_REG_TYPE_CONST 3
234
235
236 /*
237 * Each fragment program opcode appears to be comprised of 4 32-bit values.
238 *
239 * 0 - Opcode, output reg/mask, ATTRIB source
240 * 1 - Source 0
241 * 2 - Source 1
242 * 3 - Source 2
243 *
244 * There appears to be no special difference between result regs and temp regs.
245 * result.color == R0.xyzw
246 * result.depth == R1.z
247 * When the fragprog contains instructions to write depth,
248 * NV30_TCL_PRIMITIVE_3D_UNK1D78=0 otherwise it is set to 1.
249 *
250 * Constants are inserted directly after the instruction that uses them.
251 *
252 * It appears that it's not possible to use two input registers in one
253 * instruction as the input sourcing is done in the instruction dword
254 * and not the source selection dwords. As such instructions such as:
255 *
256 * ADD result.color, fragment.color, fragment.texcoord[0];
257 *
258 * must be split into two MOV's and then an ADD (nvidia does this) but
259 * I'm not sure why it's not just one MOV and then source the second input
260 * in the ADD instruction..
261 *
262 * Negation of the full source is done with NV30_FP_REG_NEGATE, arbitrary
263 * negation requires multiplication with a const.
264 *
265 * Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO and
266 * SWIZZLE_ONE.
267 *
268 * The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as
269 * SWIZZLE_ZERO is implemented simply by not writing to the relevant components
270 * of the destination.
271 *
272 * Looping
273 * Loops appear to be fairly expensive on NV40 at least, the proprietary
274 * driver goes to a lot of effort to avoid using the native looping
275 * instructions. If the total number of *executed* instructions between
276 * REP/ENDREP or LOOP/ENDLOOP is <=500, the driver will unroll the loop.
277 * The maximum loop count is 255.
278 *
279 * Conditional execution
280 * TODO
281 *
282 * Non-native instructions:
283 * LIT
284 * LRP - MAD+MAD
285 * SUB - ADD, negate second source
286 * RSQ - LG2 + EX2
287 * POW - LG2 + MUL + EX2
288 * SCS - COS + SIN
289 * XPD
290 * DP2 - MUL + ADD
291 * NRM
292 */
293
294 //== Opcode / Destination selection ==
295 #define NV40_FP_OP_PROGRAM_END (1 << 0)
296 #define NV40_FP_OP_OUT_REG_SHIFT 1
297 #define NV40_FP_OP_OUT_REG_MASK (63 << 1)
298 /* Needs to be set when writing outputs to get expected result.. */
299 #define NV40_FP_OP_OUT_REG_HALF (1 << 7)
300 #define NV40_FP_OP_COND_WRITE_ENABLE (1 << 8)
301 #define NV40_FP_OP_OUTMASK_SHIFT 9
302 #define NV40_FP_OP_OUTMASK_MASK (0xF << 9)
303 # define NV40_FP_OP_OUT_X (1 << 9)
304 # define NV40_FP_OP_OUT_Y (1 <<10)
305 # define NV40_FP_OP_OUT_Z (1 <<11)
306 # define NV40_FP_OP_OUT_W (1 <<12)
307 /* Uncertain about these, especially the input_src values.. it's possible that
308 * they can be dynamically changed.
309 */
310 #define NV40_FP_OP_INPUT_SRC_SHIFT 13
311 #define NV40_FP_OP_INPUT_SRC_MASK (15 << 13)
312 # define NV40_FP_OP_INPUT_SRC_POSITION 0x0
313 # define NV40_FP_OP_INPUT_SRC_COL0 0x1
314 # define NV40_FP_OP_INPUT_SRC_COL1 0x2
315 # define NV40_FP_OP_INPUT_SRC_FOGC 0x3
316 # define NV40_FP_OP_INPUT_SRC_TC0 0x4
317 # define NV40_FP_OP_INPUT_SRC_TC(n) (0x4 + n)
318 # define NV40_FP_OP_INPUT_SRC_FACING 0xE
319 #define NV40_FP_OP_TEX_UNIT_SHIFT 17
320 #define NV40_FP_OP_TEX_UNIT_MASK (0xF << 17)
321 #define NV40_FP_OP_PRECISION_SHIFT 22
322 #define NV40_FP_OP_PRECISION_MASK (3 << 22)
323 # define NV40_FP_PRECISION_FP32 0
324 # define NV40_FP_PRECISION_FP16 1
325 # define NV40_FP_PRECISION_FX12 2
326 #define NV40_FP_OP_OPCODE_SHIFT 24
327 #define NV40_FP_OP_OPCODE_MASK (0x3F << 24)
328 # define NV40_FP_OP_OPCODE_NOP 0x00
329 # define NV40_FP_OP_OPCODE_MOV 0x01
330 # define NV40_FP_OP_OPCODE_MUL 0x02
331 # define NV40_FP_OP_OPCODE_ADD 0x03
332 # define NV40_FP_OP_OPCODE_MAD 0x04
333 # define NV40_FP_OP_OPCODE_DP3 0x05
334 # define NV40_FP_OP_OPCODE_DP4 0x06
335 # define NV40_FP_OP_OPCODE_DST 0x07
336 # define NV40_FP_OP_OPCODE_MIN 0x08
337 # define NV40_FP_OP_OPCODE_MAX 0x09
338 # define NV40_FP_OP_OPCODE_SLT 0x0A
339 # define NV40_FP_OP_OPCODE_SGE 0x0B
340 # define NV40_FP_OP_OPCODE_SLE 0x0C
341 # define NV40_FP_OP_OPCODE_SGT 0x0D
342 # define NV40_FP_OP_OPCODE_SNE 0x0E
343 # define NV40_FP_OP_OPCODE_SEQ 0x0F
344 # define NV40_FP_OP_OPCODE_FRC 0x10
345 # define NV40_FP_OP_OPCODE_FLR 0x11
346 # define NV40_FP_OP_OPCODE_KIL 0x12
347 # define NV40_FP_OP_OPCODE_PK4B 0x13
348 # define NV40_FP_OP_OPCODE_UP4B 0x14
349 /* DDX/DDY can only write to XY */
350 # define NV40_FP_OP_OPCODE_DDX 0x15
351 # define NV40_FP_OP_OPCODE_DDY 0x16
352 # define NV40_FP_OP_OPCODE_TEX 0x17
353 # define NV40_FP_OP_OPCODE_TXP 0x18
354 # define NV40_FP_OP_OPCODE_TXD 0x19
355 # define NV40_FP_OP_OPCODE_RCP 0x1A
356 # define NV40_FP_OP_OPCODE_EX2 0x1C
357 # define NV40_FP_OP_OPCODE_LG2 0x1D
358 # define NV40_FP_OP_OPCODE_STR 0x20
359 # define NV40_FP_OP_OPCODE_SFL 0x21
360 # define NV40_FP_OP_OPCODE_COS 0x22
361 # define NV40_FP_OP_OPCODE_SIN 0x23
362 # define NV40_FP_OP_OPCODE_PK2H 0x24
363 # define NV40_FP_OP_OPCODE_UP2H 0x25
364 # define NV40_FP_OP_OPCODE_PK4UB 0x27
365 # define NV40_FP_OP_OPCODE_UP4UB 0x28
366 # define NV40_FP_OP_OPCODE_PK2US 0x29
367 # define NV40_FP_OP_OPCODE_UP2US 0x2A
368 # define NV40_FP_OP_OPCODE_DP2A 0x2E
369 # define NV40_FP_OP_OPCODE_TXL 0x2F
370 # define NV40_FP_OP_OPCODE_TXB 0x31
371 # define NV40_FP_OP_OPCODE_DIV 0x3A
372 # define NV40_FP_OP_OPCODE_UNK_LIT 0x3C
373 /* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/
374 # define NV40_FP_OP_BRA_OPCODE_BRK 0x0
375 # define NV40_FP_OP_BRA_OPCODE_CAL 0x1
376 # define NV40_FP_OP_BRA_OPCODE_IF 0x2
377 # define NV40_FP_OP_BRA_OPCODE_LOOP 0x3
378 # define NV40_FP_OP_BRA_OPCODE_REP 0x4
379 # define NV40_FP_OP_BRA_OPCODE_RET 0x5
380 #define NV40_FP_OP_OUT_SAT (1 << 31)
381
382 /* high order bits of SRC0 */
383 #define NV40_FP_OP_OUT_ABS (1 << 29)
384 #define NV40_FP_OP_COND_SWZ_W_SHIFT 27
385 #define NV40_FP_OP_COND_SWZ_W_MASK (3 << 27)
386 #define NV40_FP_OP_COND_SWZ_Z_SHIFT 25
387 #define NV40_FP_OP_COND_SWZ_Z_MASK (3 << 25)
388 #define NV40_FP_OP_COND_SWZ_Y_SHIFT 23
389 #define NV40_FP_OP_COND_SWZ_Y_MASK (3 << 23)
390 #define NV40_FP_OP_COND_SWZ_X_SHIFT 21
391 #define NV40_FP_OP_COND_SWZ_X_MASK (3 << 21)
392 #define NV40_FP_OP_COND_SWZ_ALL_SHIFT 21
393 #define NV40_FP_OP_COND_SWZ_ALL_MASK (0xFF << 21)
394 #define NV40_FP_OP_COND_SHIFT 18
395 #define NV40_FP_OP_COND_MASK (0x07 << 18)
396 # define NV40_FP_OP_COND_FL 0
397 # define NV40_FP_OP_COND_LT 1
398 # define NV40_FP_OP_COND_EQ 2
399 # define NV40_FP_OP_COND_LE 3
400 # define NV40_FP_OP_COND_GT 4
401 # define NV40_FP_OP_COND_NE 5
402 # define NV40_FP_OP_COND_GE 6
403 # define NV40_FP_OP_COND_TR 7
404
405 /* high order bits of SRC1 */
406 #define NV40_FP_OP_OPCODE_IS_BRANCH (1<<31)
407 #define NV40_FP_OP_DST_SCALE_SHIFT 28
408 #define NV40_FP_OP_DST_SCALE_MASK (3 << 28)
409 #define NV40_FP_OP_DST_SCALE_1X 0
410 #define NV40_FP_OP_DST_SCALE_2X 1
411 #define NV40_FP_OP_DST_SCALE_4X 2
412 #define NV40_FP_OP_DST_SCALE_8X 3
413 #define NV40_FP_OP_DST_SCALE_INV_2X 5
414 #define NV40_FP_OP_DST_SCALE_INV_4X 6
415 #define NV40_FP_OP_DST_SCALE_INV_8X 7
416
417 /* SRC1 LOOP */
418 #define NV40_FP_OP_LOOP_INCR_SHIFT 19
419 #define NV40_FP_OP_LOOP_INCR_MASK (0xFF << 19)
420 #define NV40_FP_OP_LOOP_INDEX_SHIFT 10
421 #define NV40_FP_OP_LOOP_INDEX_MASK (0xFF << 10)
422 #define NV40_FP_OP_LOOP_COUNT_SHIFT 2
423 #define NV40_FP_OP_LOOP_COUNT_MASK (0xFF << 2)
424
425 /* SRC1 IF */
426 #define NV40_FP_OP_ELSE_ID_SHIFT 2
427 #define NV40_FP_OP_ELSE_ID_MASK (0xFF << 2)
428
429 /* SRC1 CAL */
430 #define NV40_FP_OP_IADDR_SHIFT 2
431 #define NV40_FP_OP_IADDR_MASK (0xFF << 2)
432
433 /* SRC1 REP
434 * I have no idea why there are 3 count values here.. but they
435 * have always been filled with the same value in my tests so
436 * far..
437 */
438 #define NV40_FP_OP_REP_COUNT1_SHIFT 2
439 #define NV40_FP_OP_REP_COUNT1_MASK (0xFF << 2)
440 #define NV40_FP_OP_REP_COUNT2_SHIFT 10
441 #define NV40_FP_OP_REP_COUNT2_MASK (0xFF << 10)
442 #define NV40_FP_OP_REP_COUNT3_SHIFT 19
443 #define NV40_FP_OP_REP_COUNT3_MASK (0xFF << 19)
444
445 /* SRC2 REP/IF */
446 #define NV40_FP_OP_END_ID_SHIFT 2
447 #define NV40_FP_OP_END_ID_MASK (0xFF << 2)
448
449 // SRC2 high-order
450 #define NV40_FP_OP_INDEX_INPUT (1 << 30)
451 #define NV40_FP_OP_ADDR_INDEX_SHIFT 19
452 #define NV40_FP_OP_ADDR_INDEX_MASK (0xF << 19)
453
454 //== Register selection ==
455 #define NV40_FP_REG_TYPE_SHIFT 0
456 #define NV40_FP_REG_TYPE_MASK (3 << 0)
457 # define NV40_FP_REG_TYPE_TEMP 0
458 # define NV40_FP_REG_TYPE_INPUT 1
459 # define NV40_FP_REG_TYPE_CONST 2
460 #define NV40_FP_REG_SRC_SHIFT 2
461 #define NV40_FP_REG_SRC_MASK (63 << 2)
462 #define NV40_FP_REG_SRC_HALF (1 << 8)
463 #define NV40_FP_REG_SWZ_ALL_SHIFT 9
464 #define NV40_FP_REG_SWZ_ALL_MASK (255 << 9)
465 #define NV40_FP_REG_SWZ_X_SHIFT 9
466 #define NV40_FP_REG_SWZ_X_MASK (3 << 9)
467 #define NV40_FP_REG_SWZ_Y_SHIFT 11
468 #define NV40_FP_REG_SWZ_Y_MASK (3 << 11)
469 #define NV40_FP_REG_SWZ_Z_SHIFT 13
470 #define NV40_FP_REG_SWZ_Z_MASK (3 << 13)
471 #define NV40_FP_REG_SWZ_W_SHIFT 15
472 #define NV40_FP_REG_SWZ_W_MASK (3 << 15)
473 # define NV40_FP_SWIZZLE_X 0
474 # define NV40_FP_SWIZZLE_Y 1
475 # define NV40_FP_SWIZZLE_Z 2
476 # define NV40_FP_SWIZZLE_W 3
477 #define NV40_FP_REG_NEGATE (1 << 17)
478
479 #ifndef NV40_SHADER_NO_FUCKEDNESS
480 #define NV40SR_NONE 0
481 #define NV40SR_OUTPUT 1
482 #define NV40SR_INPUT 2
483 #define NV40SR_TEMP 3
484 #define NV40SR_CONST 4
485
486 struct nv40_sreg {
487 int type;
488 int index;
489
490 int dst_scale;
491
492 int negate;
493 int abs;
494 int swz[4];
495
496 int cc_update;
497 int cc_update_reg;
498 int cc_test;
499 int cc_test_reg;
500 int cc_swz[4];
501 };
502
503 static INLINE struct nv40_sreg
504 nv40_sr(int type, int index)
505 {
506 struct nv40_sreg temp = {
507 .type = type,
508 .index = index,
509 .dst_scale = DEF_SCALE,
510 .abs = 0,
511 .negate = 0,
512 .swz = { 0, 1, 2, 3 },
513 .cc_update = 0,
514 .cc_update_reg = 0,
515 .cc_test = DEF_CTEST,
516 .cc_test_reg = 0,
517 .cc_swz = { 0, 1, 2, 3 },
518 };
519 return temp;
520 }
521
522 static INLINE struct nv40_sreg
523 nv40_sr_swz(struct nv40_sreg src, int x, int y, int z, int w)
524 {
525 struct nv40_sreg dst = src;
526
527 dst.swz[SWZ_X] = src.swz[x];
528 dst.swz[SWZ_Y] = src.swz[y];
529 dst.swz[SWZ_Z] = src.swz[z];
530 dst.swz[SWZ_W] = src.swz[w];
531 return dst;
532 }
533
534 static INLINE struct nv40_sreg
535 nv40_sr_neg(struct nv40_sreg src)
536 {
537 src.negate = !src.negate;
538 return src;
539 }
540
541 static INLINE struct nv40_sreg
542 nv40_sr_abs(struct nv40_sreg src)
543 {
544 src.abs = 1;
545 return src;
546 }
547
548 static INLINE struct nv40_sreg
549 nv40_sr_scale(struct nv40_sreg src, int scale)
550 {
551 src.dst_scale = scale;
552 return src;
553 }
554 #endif
555
556 #endif