src/gallium/drivers/nv40/nv40_state.c

   1 #include "pipe/p_state.h"
   2 #include "pipe/p_defines.h"
   3 #include "util/u_inlines.h"
   4
   5 #include "draw/draw_context.h"
   6
   7 #include "tgsi/tgsi_parse.h"
   8
   9 #include "nv40_context.h"
  10 #include "nv40_state.h"
  11
  12 static void *
  13 nv40_blend_state_create(struct pipe_context *pipe,
  14                         const struct pipe_blend_state *cso)
  15 {
  16         struct nv40_context *nv40 = nv40_context(pipe);
  17         struct nouveau_grobj *curie = nv40->screen->curie;
  18         struct nv40_blend_state *bso = CALLOC(1, sizeof(*bso));
  19         struct nouveau_stateobj *so = so_new(5, 8, 0);
  20
  21         if (cso->rt[0].blend_enable) {
  22                 so_method(so, curie, NV40TCL_BLEND_ENABLE, 3);
  23                 so_data  (so, 1);
  24                 so_data  (so, (nvgl_blend_func(cso->rt[0].alpha_src_factor) << 16) |
  25                                nvgl_blend_func(cso->rt[0].rgb_src_factor));
  26                 so_data  (so, nvgl_blend_func(cso->rt[0].alpha_dst_factor) << 16 |
  27                               nvgl_blend_func(cso->rt[0].rgb_dst_factor));
  28                 so_method(so, curie, NV40TCL_BLEND_EQUATION, 1);
  29                 so_data  (so, nvgl_blend_eqn(cso->rt[0].alpha_func) << 16 |
  30                               nvgl_blend_eqn(cso->rt[0].rgb_func));
  31         } else {
  32                 so_method(so, curie, NV40TCL_BLEND_ENABLE, 1);
  33                 so_data  (so, 0);
  34         }
  35
  36         so_method(so, curie, NV40TCL_COLOR_MASK, 1);
  37         so_data  (so, (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) |
  38                        ((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) |
  39                        ((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01 <<  8) : 0) |
  40                        ((cso->rt[0].colormask & PIPE_MASK_B) ? (0x01 <<  0) : 0)));
  41
  42         if (cso->logicop_enable) {
  43                 so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2);
  44                 so_data  (so, 1);
  45                 so_data  (so, nvgl_logicop_func(cso->logicop_func));
  46         } else {
  47                 so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 1);
  48                 so_data  (so, 0);
  49         }
  50
  51         so_method(so, curie, NV40TCL_DITHER_ENABLE, 1);
  52         so_data  (so, cso->dither ? 1 : 0);
  53
  54         so_ref(so, &bso->so);
  55         so_ref(NULL, &so);
  56         bso->pipe = *cso;
  57         return (void *)bso;
  58 }
  59
  60 static void
  61 nv40_blend_state_bind(struct pipe_context *pipe, void *hwcso)
  62 {
  63         struct nv40_context *nv40 = nv40_context(pipe);
  64
  65         nv40->blend = hwcso;
  66         nv40->dirty |= NV40_NEW_BLEND;
  67 }
  68
  69 static void
  70 nv40_blend_state_delete(struct pipe_context *pipe, void *hwcso)
  71 {
  72         struct nv40_blend_state *bso = hwcso;
  73
  74         so_ref(NULL, &bso->so);
  75         FREE(bso);
  76 }
  77
  78
  79 static INLINE unsigned
  80 wrap_mode(unsigned wrap) {
  81         unsigned ret;
  82
  83         switch (wrap) {
  84         case PIPE_TEX_WRAP_REPEAT:
  85                 ret = NV40TCL_TEX_WRAP_S_REPEAT;
  86                 break;
  87         case PIPE_TEX_WRAP_MIRROR_REPEAT:
  88                 ret = NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT;
  89                 break;
  90         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
  91                 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE;
  92                 break;
  93         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
  94                 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER;
  95                 break;
  96         case PIPE_TEX_WRAP_CLAMP:
  97                 ret = NV40TCL_TEX_WRAP_S_CLAMP;
  98                 break;
  99         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 100                 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
 101                 break;
 102         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 103                 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
 104                 break;
 105         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 106                 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
 107                 break;
 108         default:
 109                 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
 110                 ret = NV40TCL_TEX_WRAP_S_REPEAT;
 111                 break;
 112         }
 113
 114         return ret >> NV40TCL_TEX_WRAP_S_SHIFT;
 115 }
 116
 117 static void *
 118 nv40_sampler_state_create(struct pipe_context *pipe,
 119                           const struct pipe_sampler_state *cso)
 120 {
 121         struct nv40_sampler_state *ps;
 122         uint32_t filter = 0;
 123
 124         ps = MALLOC(sizeof(struct nv40_sampler_state));
 125
 126         ps->fmt = 0;
 127         if (!cso->normalized_coords)
 128                 ps->fmt |= NV40TCL_TEX_FORMAT_RECT;
 129
 130         ps->wrap = ((wrap_mode(cso->wrap_s) << NV40TCL_TEX_WRAP_S_SHIFT) |
 131                     (wrap_mode(cso->wrap_t) << NV40TCL_TEX_WRAP_T_SHIFT) |
 132                     (wrap_mode(cso->wrap_r) << NV40TCL_TEX_WRAP_R_SHIFT));
 133
 134         ps->en = 0;
 135         if (cso->max_anisotropy >= 2) {
 136                 /* no idea, binary driver sets it, works without it.. meh.. */
 137                 ps->wrap |= (1 << 5);
 138
 139                 if (cso->max_anisotropy >= 16) {
 140                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_16X;
 141                 } else
 142                 if (cso->max_anisotropy >= 12) {
 143                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_12X;
 144                 } else
 145                 if (cso->max_anisotropy >= 10) {
 146                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_10X;
 147                 } else
 148                 if (cso->max_anisotropy >= 8) {
 149                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_8X;
 150                 } else
 151                 if (cso->max_anisotropy >= 6) {
 152                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_6X;
 153                 } else
 154                 if (cso->max_anisotropy >= 4) {
 155                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_4X;
 156                 } else {
 157                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X;
 158                 }
 159         }
 160
 161         switch (cso->mag_img_filter) {
 162         case PIPE_TEX_FILTER_LINEAR:
 163                 filter |= NV40TCL_TEX_FILTER_MAG_LINEAR;
 164                 break;
 165         case PIPE_TEX_FILTER_NEAREST:
 166         default:
 167                 filter |= NV40TCL_TEX_FILTER_MAG_NEAREST;
 168                 break;
 169         }
 170
 171         switch (cso->min_img_filter) {
 172         case PIPE_TEX_FILTER_LINEAR:
 173                 switch (cso->min_mip_filter) {
 174                 case PIPE_TEX_MIPFILTER_NEAREST:
 175                         filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
 176                         break;
 177                 case PIPE_TEX_MIPFILTER_LINEAR:
 178                         filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
 179                         break;
 180                 case PIPE_TEX_MIPFILTER_NONE:
 181                 default:
 182                         filter |= NV40TCL_TEX_FILTER_MIN_LINEAR;
 183                         break;
 184                 }
 185                 break;
 186         case PIPE_TEX_FILTER_NEAREST:
 187         default:
 188                 switch (cso->min_mip_filter) {
 189                 case PIPE_TEX_MIPFILTER_NEAREST:
 190                         filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
 191                 break;
 192                 case PIPE_TEX_MIPFILTER_LINEAR:
 193                         filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
 194                         break;
 195                 case PIPE_TEX_MIPFILTER_NONE:
 196                 default:
 197                         filter |= NV40TCL_TEX_FILTER_MIN_NEAREST;
 198                         break;
 199                 }
 200                 break;
 201         }
 202
 203         ps->filt = filter;
 204
 205         {
 206                 float limit;
 207
 208                 limit = CLAMP(cso->lod_bias, -16.0, 15.0);
 209                 ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
 210
 211                 limit = CLAMP(cso->max_lod, 0.0, 15.0);
 212                 ps->en |= (int)(limit * 256.0) << 7;
 213
 214                 limit = CLAMP(cso->min_lod, 0.0, 15.0);
 215                 ps->en |= (int)(limit * 256.0) << 19;
 216         }
 217
 218
 219         if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
 220                 switch (cso->compare_func) {
 221                 case PIPE_FUNC_NEVER:
 222                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NEVER;
 223                         break;
 224                 case PIPE_FUNC_GREATER:
 225                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GREATER;
 226                         break;
 227                 case PIPE_FUNC_EQUAL:
 228                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_EQUAL;
 229                         break;
 230                 case PIPE_FUNC_GEQUAL:
 231                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GEQUAL;
 232                         break;
 233                 case PIPE_FUNC_LESS:
 234                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LESS;
 235                         break;
 236                 case PIPE_FUNC_NOTEQUAL:
 237                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NOTEQUAL;
 238                         break;
 239                 case PIPE_FUNC_LEQUAL:
 240                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LEQUAL;
 241                         break;
 242                 case PIPE_FUNC_ALWAYS:
 243                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_ALWAYS;
 244                         break;
 245                 default:
 246                         break;
 247                 }
 248         }
 249
 250         ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
 251                     (float_to_ubyte(cso->border_color[0]) << 16) |
 252                     (float_to_ubyte(cso->border_color[1]) <<  8) |
 253                     (float_to_ubyte(cso->border_color[2]) <<  0));
 254
 255         return (void *)ps;
 256 }
 257
 258 static void
 259 nv40_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
 260 {
 261         struct nv40_context *nv40 = nv40_context(pipe);
 262         unsigned unit;
 263
 264         for (unit = 0; unit < nr; unit++) {
 265                 nv40->tex_sampler[unit] = sampler[unit];
 266                 nv40->dirty_samplers |= (1 << unit);
 267         }
 268
 269         for (unit = nr; unit < nv40->nr_samplers; unit++) {
 270                 nv40->tex_sampler[unit] = NULL;
 271                 nv40->dirty_samplers |= (1 << unit);
 272         }
 273
 274         nv40->nr_samplers = nr;
 275         nv40->dirty |= NV40_NEW_SAMPLER;
 276 }
 277
 278 static void
 279 nv40_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
 280 {
 281         FREE(hwcso);
 282 }
 283
 284 static void
 285 nv40_set_sampler_texture(struct pipe_context *pipe, unsigned nr,
 286                          struct pipe_texture **miptree)
 287 {
 288         struct nv40_context *nv40 = nv40_context(pipe);
 289         unsigned unit;
 290
 291         for (unit = 0; unit < nr; unit++) {
 292                 pipe_texture_reference((struct pipe_texture **)
 293                                        &nv40->tex_miptree[unit], miptree[unit]);
 294                 nv40->dirty_samplers |= (1 << unit);
 295         }
 296
 297         for (unit = nr; unit < nv40->nr_textures; unit++) {
 298                 pipe_texture_reference((struct pipe_texture **)
 299                                        &nv40->tex_miptree[unit], NULL);
 300                 nv40->dirty_samplers |= (1 << unit);
 301         }
 302
 303         nv40->nr_textures = nr;
 304         nv40->dirty |= NV40_NEW_SAMPLER;
 305 }
 306
 307 static void *
 308 nv40_rasterizer_state_create(struct pipe_context *pipe,
 309                              const struct pipe_rasterizer_state *cso)
 310 {
 311         struct nv40_context *nv40 = nv40_context(pipe);
 312         struct nv40_rasterizer_state *rsso = CALLOC(1, sizeof(*rsso));
 313         struct nouveau_stateobj *so = so_new(9, 19, 0);
 314         struct nouveau_grobj *curie = nv40->screen->curie;
 315
 316         /*XXX: ignored:
 317          *      light_twoside
 318          *      point_smooth -nohw
 319          *      multisample
 320          */
 321
 322         so_method(so, curie, NV40TCL_SHADE_MODEL, 1);
 323         so_data  (so, cso->flatshade ? NV40TCL_SHADE_MODEL_FLAT :
 324                                        NV40TCL_SHADE_MODEL_SMOOTH);
 325
 326         so_method(so, curie, NV40TCL_LINE_WIDTH, 2);
 327         so_data  (so, (unsigned char)(cso->line_width * 8.0) & 0xff);
 328         so_data  (so, cso->line_smooth ? 1 : 0);
 329         so_method(so, curie, NV40TCL_LINE_STIPPLE_ENABLE, 2);
 330         so_data  (so, cso->line_stipple_enable ? 1 : 0);
 331         so_data  (so, (cso->line_stipple_pattern << 16) |
 332                        cso->line_stipple_factor);
 333
 334         so_method(so, curie, NV40TCL_POINT_SIZE, 1);
 335         so_data  (so, fui(cso->point_size));
 336
 337         so_method(so, curie, NV40TCL_POLYGON_MODE_FRONT, 6);
 338         if (cso->front_winding == PIPE_WINDING_CCW) {
 339                 so_data(so, nvgl_polygon_mode(cso->fill_ccw));
 340                 so_data(so, nvgl_polygon_mode(cso->fill_cw));
 341                 switch (cso->cull_mode) {
 342                 case PIPE_WINDING_CCW:
 343                         so_data(so, NV40TCL_CULL_FACE_FRONT);
 344                         break;
 345                 case PIPE_WINDING_CW:
 346                         so_data(so, NV40TCL_CULL_FACE_BACK);
 347                         break;
 348                 case PIPE_WINDING_BOTH:
 349                         so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK);
 350                         break;
 351                 default:
 352                         so_data(so, NV40TCL_CULL_FACE_BACK);
 353                         break;
 354                 }
 355                 so_data(so, NV40TCL_FRONT_FACE_CCW);
 356         } else {
 357                 so_data(so, nvgl_polygon_mode(cso->fill_cw));
 358                 so_data(so, nvgl_polygon_mode(cso->fill_ccw));
 359                 switch (cso->cull_mode) {
 360                 case PIPE_WINDING_CCW:
 361                         so_data(so, NV40TCL_CULL_FACE_BACK);
 362                         break;
 363                 case PIPE_WINDING_CW:
 364                         so_data(so, NV40TCL_CULL_FACE_FRONT);
 365                         break;
 366                 case PIPE_WINDING_BOTH:
 367                         so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK);
 368                         break;
 369                 default:
 370                         so_data(so, NV40TCL_CULL_FACE_BACK);
 371                         break;
 372                 }
 373                 so_data(so, NV40TCL_FRONT_FACE_CW);
 374         }
 375         so_data(so, cso->poly_smooth ? 1 : 0);
 376         so_data(so, (cso->cull_mode != PIPE_WINDING_NONE) ? 1 : 0);
 377
 378         so_method(so, curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1);
 379         so_data  (so, cso->poly_stipple_enable ? 1 : 0);
 380
 381         so_method(so, curie, NV40TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
 382         if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_POINT) ||
 383             (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_POINT))
 384                 so_data(so, 1);
 385         else
 386                 so_data(so, 0);
 387         if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_LINE) ||
 388             (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_LINE))
 389                 so_data(so, 1);
 390         else
 391                 so_data(so, 0);
 392         if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_FILL) ||
 393             (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_FILL))
 394                 so_data(so, 1);
 395         else
 396                 so_data(so, 0);
 397         if (cso->offset_cw || cso->offset_ccw) {
 398                 so_method(so, curie, NV40TCL_POLYGON_OFFSET_FACTOR, 2);
 399                 so_data  (so, fui(cso->offset_scale));
 400                 so_data  (so, fui(cso->offset_units * 2));
 401         }
 402
 403         so_method(so, curie, NV40TCL_POINT_SPRITE, 1);
 404         if (cso->point_quad_rasterization) {
 405                 unsigned psctl = (1 << 0), i;
 406
 407                 for (i = 0; i < 8; i++) {
 408                         if ((cso->sprite_coord_enable >> i) & 1)
 409                                 psctl |= (1 << (8 + i));
 410                 }
 411
 412                 so_data(so, psctl);
 413         } else {
 414                 so_data(so, 0);
 415         }
 416
 417         so_ref(so, &rsso->so);
 418         so_ref(NULL, &so);
 419         rsso->pipe = *cso;
 420         return (void *)rsso;
 421 }
 422
 423 static void
 424 nv40_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
 425 {
 426         struct nv40_context *nv40 = nv40_context(pipe);
 427
 428         nv40->rasterizer = hwcso;
 429         nv40->dirty |= NV40_NEW_RAST;
 430         nv40->draw_dirty |= NV40_NEW_RAST;
 431 }
 432
 433 static void
 434 nv40_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
 435 {
 436         struct nv40_rasterizer_state *rsso = hwcso;
 437
 438         so_ref(NULL, &rsso->so);
 439         FREE(rsso);
 440 }
 441
 442 static void *
 443 nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe,
 444                         const struct pipe_depth_stencil_alpha_state *cso)
 445 {
 446         struct nv40_context *nv40 = nv40_context(pipe);
 447         struct nv40_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso));
 448         struct nouveau_stateobj *so = so_new(6, 20, 0);
 449         struct nouveau_grobj *curie = nv40->screen->curie;
 450
 451         so_method(so, curie, NV40TCL_DEPTH_FUNC, 3);
 452         so_data  (so, nvgl_comparison_op(cso->depth.func));
 453         so_data  (so, cso->depth.writemask ? 1 : 0);
 454         so_data  (so, cso->depth.enabled ? 1 : 0);
 455
 456         so_method(so, curie, NV40TCL_ALPHA_TEST_ENABLE, 3);
 457         so_data  (so, cso->alpha.enabled ? 1 : 0);
 458         so_data  (so, nvgl_comparison_op(cso->alpha.func));
 459         so_data  (so, float_to_ubyte(cso->alpha.ref_value));
 460
 461         if (cso->stencil[0].enabled) {
 462                 so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 3);
 463                 so_data  (so, cso->stencil[0].enabled ? 1 : 0);
 464                 so_data  (so, cso->stencil[0].writemask);
 465                 so_data  (so, nvgl_comparison_op(cso->stencil[0].func));
 466                 so_method(so, curie, NV40TCL_STENCIL_FRONT_FUNC_MASK, 4);
 467                 so_data  (so, cso->stencil[0].valuemask);
 468                 so_data  (so, nvgl_stencil_op(cso->stencil[0].fail_op));
 469                 so_data  (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
 470                 so_data  (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
 471         } else {
 472                 so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 1);
 473                 so_data  (so, 0);
 474         }
 475
 476         if (cso->stencil[1].enabled) {
 477                 so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 3);
 478                 so_data  (so, cso->stencil[1].enabled ? 1 : 0);
 479                 so_data  (so, cso->stencil[1].writemask);
 480                 so_data  (so, nvgl_comparison_op(cso->stencil[1].func));
 481                 so_method(so, curie, NV40TCL_STENCIL_BACK_FUNC_MASK, 4);
 482                 so_data  (so, cso->stencil[1].valuemask);
 483                 so_data  (so, nvgl_stencil_op(cso->stencil[1].fail_op));
 484                 so_data  (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
 485                 so_data  (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
 486         } else {
 487                 so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 1);
 488                 so_data  (so, 0);
 489         }
 490
 491         so_ref(so, &zsaso->so);
 492         so_ref(NULL, &so);
 493         zsaso->pipe = *cso;
 494         return (void *)zsaso;
 495 }
 496
 497 static void
 498 nv40_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *hwcso)
 499 {
 500         struct nv40_context *nv40 = nv40_context(pipe);
 501
 502         nv40->zsa = hwcso;
 503         nv40->dirty |= NV40_NEW_ZSA;
 504 }
 505
 506 static void
 507 nv40_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
 508 {
 509         struct nv40_zsa_state *zsaso = hwcso;
 510
 511         so_ref(NULL, &zsaso->so);
 512         FREE(zsaso);
 513 }
 514
 515 static void *
 516 nv40_vp_state_create(struct pipe_context *pipe,
 517                      const struct pipe_shader_state *cso)
 518 {
 519         struct nv40_context *nv40 = nv40_context(pipe);
 520         struct nv40_vertex_program *vp;
 521
 522         vp = CALLOC(1, sizeof(struct nv40_vertex_program));
 523         vp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
 524         vp->draw = draw_create_vertex_shader(nv40->draw, &vp->pipe);
 525
 526         return (void *)vp;
 527 }
 528
 529 static void
 530 nv40_vp_state_bind(struct pipe_context *pipe, void *hwcso)
 531 {
 532         struct nv40_context *nv40 = nv40_context(pipe);
 533
 534         nv40->vertprog = hwcso;
 535         nv40->dirty |= NV40_NEW_VERTPROG;
 536         nv40->draw_dirty |= NV40_NEW_VERTPROG;
 537 }
 538
 539 static void
 540 nv40_vp_state_delete(struct pipe_context *pipe, void *hwcso)
 541 {
 542         struct nv40_context *nv40 = nv40_context(pipe);
 543         struct nv40_vertex_program *vp = hwcso;
 544
 545         draw_delete_vertex_shader(nv40->draw, vp->draw);
 546         nv40_vertprog_destroy(nv40, vp);
 547         FREE((void*)vp->pipe.tokens);
 548         FREE(vp);
 549 }
 550
 551 static void *
 552 nv40_fp_state_create(struct pipe_context *pipe,
 553                      const struct pipe_shader_state *cso)
 554 {
 555         struct nv40_fragment_program *fp;
 556
 557         fp = CALLOC(1, sizeof(struct nv40_fragment_program));
 558         fp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
 559
 560         tgsi_scan_shader(fp->pipe.tokens, &fp->info);
 561
 562         return (void *)fp;
 563 }
 564
 565 static void
 566 nv40_fp_state_bind(struct pipe_context *pipe, void *hwcso)
 567 {
 568         struct nv40_context *nv40 = nv40_context(pipe);
 569
 570         nv40->fragprog = hwcso;
 571         nv40->dirty |= NV40_NEW_FRAGPROG;
 572 }
 573
 574 static void
 575 nv40_fp_state_delete(struct pipe_context *pipe, void *hwcso)
 576 {
 577         struct nv40_context *nv40 = nv40_context(pipe);
 578         struct nv40_fragment_program *fp = hwcso;
 579
 580         nv40_fragprog_destroy(nv40, fp);
 581         FREE((void*)fp->pipe.tokens);
 582         FREE(fp);
 583 }
 584
 585 static void
 586 nv40_set_blend_color(struct pipe_context *pipe,
 587                      const struct pipe_blend_color *bcol)
 588 {
 589         struct nv40_context *nv40 = nv40_context(pipe);
 590
 591         nv40->blend_colour = *bcol;
 592         nv40->dirty |= NV40_NEW_BCOL;
 593 }
 594
 595  static void
 596 nv40_set_stencil_ref(struct pipe_context *pipe,
 597                      const struct pipe_stencil_ref *sr)
 598 {
 599         struct nv40_context *nv40 = nv40_context(pipe);
 600
 601         nv40->stencil_ref = *sr;
 602         nv40->dirty |= NV40_NEW_SR;
 603 }
 604
 605 static void
 606 nv40_set_clip_state(struct pipe_context *pipe,
 607                     const struct pipe_clip_state *clip)
 608 {
 609         struct nv40_context *nv40 = nv40_context(pipe);
 610
 611         nv40->clip = *clip;
 612         nv40->dirty |= NV40_NEW_UCP;
 613         nv40->draw_dirty |= NV40_NEW_UCP;
 614 }
 615
 616 static void
 617 nv40_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
 618                          struct pipe_buffer *buf )
 619 {
 620         struct nv40_context *nv40 = nv40_context(pipe);
 621
 622         nv40->constbuf[shader] = buf;
 623         nv40->constbuf_nr[shader] = buf->size / (4 * sizeof(float));
 624
 625         if (shader == PIPE_SHADER_VERTEX) {
 626                 nv40->dirty |= NV40_NEW_VERTPROG;
 627         } else
 628         if (shader == PIPE_SHADER_FRAGMENT) {
 629                 nv40->dirty |= NV40_NEW_FRAGPROG;
 630         }
 631 }
 632
 633 static void
 634 nv40_set_framebuffer_state(struct pipe_context *pipe,
 635                            const struct pipe_framebuffer_state *fb)
 636 {
 637         struct nv40_context *nv40 = nv40_context(pipe);
 638
 639         nv40->framebuffer = *fb;
 640         nv40->dirty |= NV40_NEW_FB;
 641 }
 642
 643 static void
 644 nv40_set_polygon_stipple(struct pipe_context *pipe,
 645                          const struct pipe_poly_stipple *stipple)
 646 {
 647         struct nv40_context *nv40 = nv40_context(pipe);
 648
 649         memcpy(nv40->stipple, stipple->stipple, 4 * 32);
 650         nv40->dirty |= NV40_NEW_STIPPLE;
 651 }
 652
 653 static void
 654 nv40_set_scissor_state(struct pipe_context *pipe,
 655                        const struct pipe_scissor_state *s)
 656 {
 657         struct nv40_context *nv40 = nv40_context(pipe);
 658
 659         nv40->scissor = *s;
 660         nv40->dirty |= NV40_NEW_SCISSOR;
 661 }
 662
 663 static void
 664 nv40_set_viewport_state(struct pipe_context *pipe,
 665                         const struct pipe_viewport_state *vpt)
 666 {
 667         struct nv40_context *nv40 = nv40_context(pipe);
 668
 669         nv40->viewport = *vpt;
 670         nv40->dirty |= NV40_NEW_VIEWPORT;
 671         nv40->draw_dirty |= NV40_NEW_VIEWPORT;
 672 }
 673
 674 static void
 675 nv40_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
 676                         const struct pipe_vertex_buffer *vb)
 677 {
 678         struct nv40_context *nv40 = nv40_context(pipe);
 679
 680         memcpy(nv40->vtxbuf, vb, sizeof(*vb) * count);
 681         nv40->vtxbuf_nr = count;
 682
 683         nv40->dirty |= NV40_NEW_ARRAYS;
 684         nv40->draw_dirty |= NV40_NEW_ARRAYS;
 685 }
 686
 687 static void
 688 nv40_set_vertex_elements(struct pipe_context *pipe, unsigned count,
 689                          const struct pipe_vertex_element *ve)
 690 {
 691         struct nv40_context *nv40 = nv40_context(pipe);
 692
 693         memcpy(nv40->vtxelt, ve, sizeof(*ve) * count);
 694         nv40->vtxelt_nr = count;
 695
 696         nv40->dirty |= NV40_NEW_ARRAYS;
 697         nv40->draw_dirty |= NV40_NEW_ARRAYS;
 698 }
 699
 700 void
 701 nv40_init_state_functions(struct nv40_context *nv40)
 702 {
 703         nv40->pipe.create_blend_state = nv40_blend_state_create;
 704         nv40->pipe.bind_blend_state = nv40_blend_state_bind;
 705         nv40->pipe.delete_blend_state = nv40_blend_state_delete;
 706
 707         nv40->pipe.create_sampler_state = nv40_sampler_state_create;
 708         nv40->pipe.bind_fragment_sampler_states = nv40_sampler_state_bind;
 709         nv40->pipe.delete_sampler_state = nv40_sampler_state_delete;
 710         nv40->pipe.set_fragment_sampler_textures = nv40_set_sampler_texture;
 711
 712         nv40->pipe.create_rasterizer_state = nv40_rasterizer_state_create;
 713         nv40->pipe.bind_rasterizer_state = nv40_rasterizer_state_bind;
 714         nv40->pipe.delete_rasterizer_state = nv40_rasterizer_state_delete;
 715
 716         nv40->pipe.create_depth_stencil_alpha_state =
 717                 nv40_depth_stencil_alpha_state_create;
 718         nv40->pipe.bind_depth_stencil_alpha_state =
 719                 nv40_depth_stencil_alpha_state_bind;
 720         nv40->pipe.delete_depth_stencil_alpha_state =
 721                 nv40_depth_stencil_alpha_state_delete;
 722
 723         nv40->pipe.create_vs_state = nv40_vp_state_create;
 724         nv40->pipe.bind_vs_state = nv40_vp_state_bind;
 725         nv40->pipe.delete_vs_state = nv40_vp_state_delete;
 726
 727         nv40->pipe.create_fs_state = nv40_fp_state_create;
 728         nv40->pipe.bind_fs_state = nv40_fp_state_bind;
 729         nv40->pipe.delete_fs_state = nv40_fp_state_delete;
 730
 731         nv40->pipe.set_blend_color = nv40_set_blend_color;
 732         nv40->pipe.set_stencil_ref = nv40_set_stencil_ref;
 733         nv40->pipe.set_clip_state = nv40_set_clip_state;
 734         nv40->pipe.set_constant_buffer = nv40_set_constant_buffer;
 735         nv40->pipe.set_framebuffer_state = nv40_set_framebuffer_state;
 736         nv40->pipe.set_polygon_stipple = nv40_set_polygon_stipple;
 737         nv40->pipe.set_scissor_state = nv40_set_scissor_state;
 738         nv40->pipe.set_viewport_state = nv40_set_viewport_state;
 739
 740         nv40->pipe.set_vertex_buffers = nv40_set_vertex_buffers;
 741         nv40->pipe.set_vertex_elements = nv40_set_vertex_elements;
 742 }
 743