src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "pipe/p_screen.h"
  24
  25 #include "nv50_context.h"
  26 #include "nv50_screen.h"
  27
  28 #include "nouveau/nouveau_stateobj.h"
  29
  30 static boolean
  31 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  32                                 enum pipe_format format,
  33                                 enum pipe_texture_target target,
  34                                 unsigned tex_usage, unsigned geom_flags)
  35 {
  36         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
  37                 switch (format) {
  38                 case PIPE_FORMAT_B8G8R8X8_UNORM:
  39                 case PIPE_FORMAT_B8G8R8A8_UNORM:
  40                 case PIPE_FORMAT_B5G6R5_UNORM:
  41                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  42                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  43                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  44                 case PIPE_FORMAT_R16G16_SNORM:
  45                 case PIPE_FORMAT_R16G16_UNORM:
  46                         return TRUE;
  47                 default:
  48                         break;
  49                 }
  50         } else
  51         if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
  52                 switch (format) {
  53                 case PIPE_FORMAT_Z32_FLOAT:
  54                 case PIPE_FORMAT_S8Z24_UNORM:
  55                 case PIPE_FORMAT_Z24X8_UNORM:
  56                 case PIPE_FORMAT_Z24S8_UNORM:
  57                         return TRUE;
  58                 default:
  59                         break;
  60                 }
  61         } else {
  62                 switch (format) {
  63                 case PIPE_FORMAT_B8G8R8A8_UNORM:
  64                 case PIPE_FORMAT_B8G8R8X8_UNORM:
  65                 case PIPE_FORMAT_B8G8R8A8_SRGB:
  66                 case PIPE_FORMAT_B8G8R8X8_SRGB:
  67                 case PIPE_FORMAT_B5G5R5A1_UNORM:
  68                 case PIPE_FORMAT_B4G4R4A4_UNORM:
  69                 case PIPE_FORMAT_B5G6R5_UNORM:
  70                 case PIPE_FORMAT_L8_UNORM:
  71                 case PIPE_FORMAT_A8_UNORM:
  72                 case PIPE_FORMAT_I8_UNORM:
  73                 case PIPE_FORMAT_L8A8_UNORM:
  74                 case PIPE_FORMAT_DXT1_RGB:
  75                 case PIPE_FORMAT_DXT1_RGBA:
  76                 case PIPE_FORMAT_DXT3_RGBA:
  77                 case PIPE_FORMAT_DXT5_RGBA:
  78                 case PIPE_FORMAT_S8Z24_UNORM:
  79                 case PIPE_FORMAT_Z24S8_UNORM:
  80                 case PIPE_FORMAT_Z32_FLOAT:
  81                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  82                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  83                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  84                 case PIPE_FORMAT_R16G16_SNORM:
  85                 case PIPE_FORMAT_R16G16_UNORM:
  86                         return TRUE;
  87                 default:
  88                         break;
  89                 }
  90         }
  91
  92         return FALSE;
  93 }
  94
  95 static int
  96 nv50_screen_get_param(struct pipe_screen *pscreen, int param)
  97 {
  98         struct nv50_screen *screen = nv50_screen(pscreen);
  99
 100         switch (param) {
 101         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 102                 return 32;
 103         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 104                 return 32;
 105         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 106                 return 64;
 107         case PIPE_CAP_NPOT_TEXTURES:
 108                 return 1;
 109         case PIPE_CAP_TWO_SIDED_STENCIL:
 110                 return 1;
 111         case PIPE_CAP_GLSL:
 112                 return 1;
 113         case PIPE_CAP_ANISOTROPIC_FILTER:
 114                 return 1;
 115         case PIPE_CAP_POINT_SPRITE:
 116                 return 1;
 117         case PIPE_CAP_MAX_RENDER_TARGETS:
 118                 return 8;
 119         case PIPE_CAP_OCCLUSION_QUERY:
 120                 return 1;
 121         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 122                 return 1;
 123         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 124                 return 13;
 125         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 126                 return 10;
 127         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 128                 return 13;
 129         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 130         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
 131                 return 1;
 132         case PIPE_CAP_TGSI_CONT_SUPPORTED:
 133                 return 1;
 134         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 135                 return 1;
 136         case NOUVEAU_CAP_HW_VTXBUF:
 137                 return screen->force_push ? 0 : 1;
 138         case NOUVEAU_CAP_HW_IDXBUF:
 139                 return screen->force_push ? 0 : 1;
 140         case PIPE_CAP_INDEP_BLEND_ENABLE:
 141                 return 1;
 142         case PIPE_CAP_INDEP_BLEND_FUNC:
 143                 return 0;
 144         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 145         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 146                 return 1;
 147         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 148         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 149                 return 0;
 150         default:
 151                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 152                 return 0;
 153         }
 154 }
 155
 156 static float
 157 nv50_screen_get_paramf(struct pipe_screen *pscreen, int param)
 158 {
 159         switch (param) {
 160         case PIPE_CAP_MAX_LINE_WIDTH:
 161         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 162                 return 10.0;
 163         case PIPE_CAP_MAX_POINT_WIDTH:
 164         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 165                 return 64.0;
 166         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 167                 return 16.0;
 168         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 169                 return 4.0;
 170         default:
 171                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 172                 return 0.0;
 173         }
 174 }
 175
 176 static void
 177 nv50_screen_destroy(struct pipe_screen *pscreen)
 178 {
 179         struct nv50_screen *screen = nv50_screen(pscreen);
 180         unsigned i;
 181
 182         for (i = 0; i < 3; i++) {
 183                 if (screen->constbuf_parm[i])
 184                         nouveau_bo_ref(NULL, &screen->constbuf_parm[i]);
 185         }
 186
 187         if (screen->constbuf_misc[0])
 188                 nouveau_bo_ref(NULL, &screen->constbuf_misc[0]);
 189         if (screen->tic)
 190                 nouveau_bo_ref(NULL, &screen->tic);
 191         if (screen->tsc)
 192                 nouveau_bo_ref(NULL, &screen->tsc);
 193
 194         nouveau_notifier_free(&screen->sync);
 195         nouveau_grobj_free(&screen->tesla);
 196         nouveau_grobj_free(&screen->eng2d);
 197         nouveau_grobj_free(&screen->m2mf);
 198         nouveau_resource_destroy(&screen->immd_heap[0]);
 199         nouveau_resource_destroy(&screen->parm_heap[0]);
 200         nouveau_resource_destroy(&screen->parm_heap[1]);
 201         nouveau_screen_fini(&screen->base);
 202         FREE(screen);
 203 }
 204
 205 #define BGN_RELOC(ch, bo, gr, m, n, fl) \
 206    OUT_RELOC(ch, bo, (n << 18) | (gr->subc << 13) | m, fl, 0, 0)
 207
 208 void
 209 nv50_screen_relocs(struct nv50_screen *screen)
 210 {
 211         struct nouveau_channel *chan = screen->base.channel;
 212         struct nouveau_grobj *tesla = screen->tesla;
 213         unsigned i;
 214         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
 215
 216         MARK_RING (chan, 28, 26);
 217
 218         /* cause grobj autobind */
 219         BEGIN_RING(chan, tesla, 0x0100, 1);
 220         OUT_RING  (chan, 0);
 221
 222         BGN_RELOC (chan, screen->tic, tesla, NV50TCL_TIC_ADDRESS_HIGH, 2, rl);
 223         OUT_RELOCh(chan, screen->tic, 0, rl);
 224         OUT_RELOCl(chan, screen->tic, 0, rl);
 225
 226         BGN_RELOC (chan, screen->tsc, tesla, NV50TCL_TSC_ADDRESS_HIGH, 2, rl);
 227         OUT_RELOCh(chan, screen->tsc, 0, rl);
 228         OUT_RELOCl(chan, screen->tsc, 0, rl);
 229
 230         BGN_RELOC (chan, screen->constbuf_misc[0],
 231                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 232         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 233         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 234         OUT_RELOC (chan, screen->constbuf_misc[0],
 235                    (NV50_CB_PMISC << 16) | 0x0200, rl, 0, 0);
 236
 237         BGN_RELOC (chan, screen->constbuf_misc[0],
 238                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 239         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 240         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 241         OUT_RELOC (chan, screen->constbuf_misc[0],
 242                    (NV50_CB_AUX << 16) | 0x0200, rl, 0, 0);
 243
 244         for (i = 0; i < 3; ++i) {
 245                 BGN_RELOC (chan, screen->constbuf_parm[i],
 246                            tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 247                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 248                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 249                 OUT_RELOC (chan, screen->constbuf_parm[i],
 250                            ((NV50_CB_PVP + i) << 16) | 0x0800, rl, 0, 0);
 251         }
 252 }
 253
 254 struct pipe_screen *
 255 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 256 {
 257         struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen);
 258         struct nouveau_channel *chan;
 259         struct pipe_screen *pscreen;
 260         unsigned chipset = dev->chipset;
 261         unsigned tesla_class = 0;
 262         int ret, i;
 263         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 264
 265         if (!screen)
 266                 return NULL;
 267         pscreen = &screen->base.base;
 268
 269         ret = nouveau_screen_init(&screen->base, dev);
 270         if (ret) {
 271                 nv50_screen_destroy(pscreen);
 272                 return NULL;
 273         }
 274         chan = screen->base.channel;
 275
 276         pscreen->winsys = ws;
 277         pscreen->destroy = nv50_screen_destroy;
 278         pscreen->get_param = nv50_screen_get_param;
 279         pscreen->get_paramf = nv50_screen_get_paramf;
 280         pscreen->is_format_supported = nv50_screen_is_format_supported;
 281         pscreen->context_create = nv50_create;
 282
 283         nv50_screen_init_miptree_functions(pscreen);
 284
 285         /* DMA engine object */
 286         ret = nouveau_grobj_alloc(chan, 0xbeef5039,
 287                 NV50_MEMORY_TO_MEMORY_FORMAT, &screen->m2mf);
 288         if (ret) {
 289                 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret);
 290                 nv50_screen_destroy(pscreen);
 291                 return NULL;
 292         }
 293
 294         /* 2D object */
 295         ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 296         if (ret) {
 297                 NOUVEAU_ERR("Error creating 2D object: %d\n", ret);
 298                 nv50_screen_destroy(pscreen);
 299                 return NULL;
 300         }
 301
 302         /* 3D object */
 303         switch (chipset & 0xf0) {
 304         case 0x50:
 305                 tesla_class = NV50TCL;
 306                 break;
 307         case 0x80:
 308         case 0x90:
 309                 tesla_class = NV84TCL;
 310                 break;
 311         case 0xa0:
 312                 switch (chipset) {
 313                 case 0xa0:
 314                 case 0xaa:
 315                 case 0xac:
 316                         tesla_class = NVA0TCL;
 317                         break;
 318                 default:
 319                         tesla_class = NVA8TCL;
 320                         break;
 321                 }
 322                 break;
 323         default:
 324                 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset);
 325                 nv50_screen_destroy(pscreen);
 326                 return NULL;
 327         }
 328
 329         ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class,
 330                 &screen->tesla);
 331         if (ret) {
 332                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 333                 nv50_screen_destroy(pscreen);
 334                 return NULL;
 335         }
 336
 337         /* Sync notifier */
 338         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 339         if (ret) {
 340                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 341                 nv50_screen_destroy(pscreen);
 342                 return NULL;
 343         }
 344
 345         /* Static M2MF init */
 346         BEGIN_RING(chan, screen->m2mf,
 347                    NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 348         OUT_RING  (chan, screen->sync->handle);
 349         OUT_RING  (chan, chan->vram->handle);
 350         OUT_RING  (chan, chan->vram->handle);
 351
 352         /* Static 2D init */
 353         BEGIN_RING(chan, screen->eng2d, NV50_2D_DMA_NOTIFY, 4);
 354         OUT_RING  (chan, screen->sync->handle);
 355         OUT_RING  (chan, chan->vram->handle);
 356         OUT_RING  (chan, chan->vram->handle);
 357         OUT_RING  (chan, chan->vram->handle);
 358         BEGIN_RING(chan, screen->eng2d, NV50_2D_OPERATION, 1);
 359         OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 360         BEGIN_RING(chan, screen->eng2d, NV50_2D_CLIP_ENABLE, 1);
 361         OUT_RING  (chan, 0);
 362         BEGIN_RING(chan, screen->eng2d, 0x0888, 1);
 363         OUT_RING  (chan, 1);
 364
 365         /* Static tesla init */
 366         BEGIN_RING(chan, screen->tesla, NV50TCL_COND_MODE, 1);
 367         OUT_RING  (chan, NV50TCL_COND_MODE_ALWAYS);
 368         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
 369         OUT_RING  (chan, screen->sync->handle);
 370         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_ZETA, 11);
 371         for (i = 0; i < 11; i++)
 372                 OUT_RING  (chan, chan->vram->handle);
 373         BEGIN_RING(chan, screen->tesla,
 374                    NV50TCL_DMA_COLOR(0), NV50TCL_DMA_COLOR__SIZE);
 375         for (i = 0; i < NV50TCL_DMA_COLOR__SIZE; i++)
 376                 OUT_RING  (chan, chan->vram->handle);
 377
 378         BEGIN_RING(chan, screen->tesla, NV50TCL_RT_CONTROL, 1);
 379         OUT_RING  (chan, 1);
 380
 381         /* activate all 32 lanes (threads) in a warp */
 382         BEGIN_RING(chan, screen->tesla, NV50TCL_WARP_HALVES, 1);
 383         OUT_RING  (chan, 2);
 384         BEGIN_RING(chan, screen->tesla, 0x1400, 1);
 385         OUT_RING  (chan, 0xf);
 386
 387         /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
 388         for (i = 0; i < 3; ++i) {
 389                 BEGIN_RING(chan, screen->tesla, NV50TCL_TEX_LIMITS(i), 1);
 390                 OUT_RING  (chan, 0x54);
 391         }
 392
 393         /* origin is top left (set to 1 for bottom left) */
 394         BEGIN_RING(chan, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1);
 395         OUT_RING  (chan, 0);
 396         BEGIN_RING(chan, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
 397         OUT_RING  (chan, 8);
 398
 399         /* constant buffers for immediates and VP/FP parameters */
 400         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (32 * 4) * 4,
 401                              &screen->constbuf_misc[0]);
 402         if (ret) {
 403                 nv50_screen_destroy(pscreen);
 404                 return NULL;
 405         }
 406         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 407         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 408         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 409         OUT_RING  (chan, (NV50_CB_PMISC << 16) | 0x0200);
 410         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 411         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 412         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 413         OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 414
 415         for (i = 0; i < 3; i++) {
 416                 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (256 * 4) * 4,
 417                                      &screen->constbuf_parm[i]);
 418                 if (ret) {
 419                         nv50_screen_destroy(pscreen);
 420                         return NULL;
 421                 }
 422                 BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 423                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 424                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 425                 OUT_RING  (chan, ((NV50_CB_PVP + i) << 16) | 0x0800);
 426         }
 427
 428         if (nouveau_resource_init(&screen->immd_heap[0], 0, 128) ||
 429             nouveau_resource_init(&screen->parm_heap[0], 0, 512) ||
 430             nouveau_resource_init(&screen->parm_heap[1], 0, 512))
 431         {
 432                 NOUVEAU_ERR("Error initialising constant buffers.\n");
 433                 nv50_screen_destroy(pscreen);
 434                 return NULL;
 435         }
 436
 437         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 438                              &screen->tic);
 439         if (ret) {
 440                 nv50_screen_destroy(pscreen);
 441                 return NULL;
 442         }
 443         BEGIN_RING(chan, screen->tesla, NV50TCL_TIC_ADDRESS_HIGH, 3);
 444         OUT_RELOCh(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 445         OUT_RELOCl(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 446         OUT_RING  (chan, 3 * 32 - 1);
 447
 448         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 449                              &screen->tsc);
 450         if (ret) {
 451                 nv50_screen_destroy(pscreen);
 452                 return NULL;
 453         }
 454         BEGIN_RING(chan, screen->tesla, NV50TCL_TSC_ADDRESS_HIGH, 3);
 455         OUT_RELOCh(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 456         OUT_RELOCl(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 457         OUT_RING  (chan, 0); /* ignored if TSC_LINKED (0x1234) == 1 */
 458
 459         /* map constant buffers:
 460          *  B = buffer ID (maybe more than 1 byte)
 461          *  N = CB index used in shader instruction
 462          *  P = program type (0 = VP, 2 = GP, 3 = FP)
 463          * SET_PROGRAM_CB = 0x000BBNP1
 464          */
 465         BEGIN_RING_NI(chan, screen->tesla, NV50TCL_SET_PROGRAM_CB, 8);
 466         /* bind immediate buffer */
 467         OUT_RING  (chan, 0x001 | (NV50_CB_PMISC << 12));
 468         OUT_RING  (chan, 0x021 | (NV50_CB_PMISC << 12));
 469         OUT_RING  (chan, 0x031 | (NV50_CB_PMISC << 12));
 470         /* bind auxiliary constbuf to immediate data bo */
 471         OUT_RING  (chan, 0x201 | (NV50_CB_AUX << 12));
 472         OUT_RING  (chan, 0x221 | (NV50_CB_AUX << 12));
 473         /* bind parameter buffers */
 474         OUT_RING  (chan, 0x101 | (NV50_CB_PVP << 12));
 475         OUT_RING  (chan, 0x121 | (NV50_CB_PGP << 12));
 476         OUT_RING  (chan, 0x131 | (NV50_CB_PFP << 12));
 477
 478         /* Vertex array limits - max them out */
 479         for (i = 0; i < 16; i++) {
 480                 BEGIN_RING(chan, screen->tesla,
 481                            NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
 482                 OUT_RING  (chan, 0x000000ff);
 483                 OUT_RING  (chan, 0xffffffff);
 484         }
 485
 486         BEGIN_RING(chan, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
 487         OUT_RINGf (chan, 0.0f);
 488         OUT_RINGf (chan, 1.0f);
 489
 490         /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
 491         BEGIN_RING(chan, screen->tesla, NV50TCL_LINKED_TSC, 1);
 492         OUT_RING  (chan, 1);
 493
 494         BEGIN_RING(chan, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
 495         OUT_RING  (chan, 1); /* default edgeflag to TRUE */
 496
 497         FIRE_RING (chan);
 498
 499         screen->force_push = debug_get_bool_option("NV50_ALWAYS_PUSH", FALSE);
 500         return pscreen;
 501 }
 502