2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_screen.h"
25 #include "nv50_context.h"
26 #include "nv50_screen.h"
27 #include "nv50_resource.h"
29 #include "nouveau/nouveau_stateobj.h"
32 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
33 enum pipe_format format
,
34 enum pipe_texture_target target
,
35 unsigned tex_usage
, unsigned geom_flags
)
37 if (tex_usage
& PIPE_BIND_RENDER_TARGET
) {
39 case PIPE_FORMAT_B8G8R8X8_UNORM
:
40 case PIPE_FORMAT_B8G8R8A8_UNORM
:
41 case PIPE_FORMAT_B5G6R5_UNORM
:
42 case PIPE_FORMAT_R16G16B16A16_SNORM
:
43 case PIPE_FORMAT_R16G16B16A16_UNORM
:
44 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
45 case PIPE_FORMAT_R16G16_SNORM
:
46 case PIPE_FORMAT_R16G16_UNORM
:
52 if (tex_usage
& PIPE_BIND_DEPTH_STENCIL
) {
54 case PIPE_FORMAT_Z32_FLOAT
:
55 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
56 case PIPE_FORMAT_Z24X8_UNORM
:
57 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
64 case PIPE_FORMAT_B8G8R8A8_UNORM
:
65 case PIPE_FORMAT_B8G8R8X8_UNORM
:
66 case PIPE_FORMAT_B8G8R8A8_SRGB
:
67 case PIPE_FORMAT_B8G8R8X8_SRGB
:
68 case PIPE_FORMAT_B5G5R5A1_UNORM
:
69 case PIPE_FORMAT_B4G4R4A4_UNORM
:
70 case PIPE_FORMAT_B5G6R5_UNORM
:
71 case PIPE_FORMAT_L8_UNORM
:
72 case PIPE_FORMAT_A8_UNORM
:
73 case PIPE_FORMAT_I8_UNORM
:
74 case PIPE_FORMAT_L8A8_UNORM
:
75 case PIPE_FORMAT_DXT1_RGB
:
76 case PIPE_FORMAT_DXT1_RGBA
:
77 case PIPE_FORMAT_DXT3_RGBA
:
78 case PIPE_FORMAT_DXT5_RGBA
:
79 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
80 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
81 case PIPE_FORMAT_Z32_FLOAT
:
82 case PIPE_FORMAT_R16G16B16A16_SNORM
:
83 case PIPE_FORMAT_R16G16B16A16_UNORM
:
84 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
85 case PIPE_FORMAT_R16G16_SNORM
:
86 case PIPE_FORMAT_R16G16_UNORM
:
97 nv50_screen_get_param(struct pipe_screen
*pscreen
, int param
)
99 struct nv50_screen
*screen
= nv50_screen(pscreen
);
102 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
104 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
106 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
108 case PIPE_CAP_NPOT_TEXTURES
:
110 case PIPE_CAP_TWO_SIDED_STENCIL
:
114 case PIPE_CAP_ANISOTROPIC_FILTER
:
116 case PIPE_CAP_POINT_SPRITE
:
118 case PIPE_CAP_MAX_RENDER_TARGETS
:
120 case PIPE_CAP_OCCLUSION_QUERY
:
122 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
124 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
126 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
128 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
130 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
131 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
133 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
135 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
137 case NOUVEAU_CAP_HW_VTXBUF
:
138 return screen
->force_push
? 0 : 1;
139 case NOUVEAU_CAP_HW_IDXBUF
:
140 return screen
->force_push
? 0 : 1;
141 case PIPE_CAP_INDEP_BLEND_ENABLE
:
143 case PIPE_CAP_INDEP_BLEND_FUNC
:
145 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
146 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
148 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
149 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
152 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
158 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
161 case PIPE_CAP_MAX_LINE_WIDTH
:
162 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
164 case PIPE_CAP_MAX_POINT_WIDTH
:
165 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
167 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
169 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
172 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
178 nv50_screen_destroy(struct pipe_screen
*pscreen
)
180 struct nv50_screen
*screen
= nv50_screen(pscreen
);
183 for (i
= 0; i
< 3; i
++) {
184 if (screen
->constbuf_parm
[i
])
185 nouveau_bo_ref(NULL
, &screen
->constbuf_parm
[i
]);
188 if (screen
->constbuf_misc
[0])
189 nouveau_bo_ref(NULL
, &screen
->constbuf_misc
[0]);
191 nouveau_bo_ref(NULL
, &screen
->tic
);
193 nouveau_bo_ref(NULL
, &screen
->tsc
);
195 nouveau_notifier_free(&screen
->sync
);
196 nouveau_grobj_free(&screen
->tesla
);
197 nouveau_grobj_free(&screen
->eng2d
);
198 nouveau_grobj_free(&screen
->m2mf
);
199 nouveau_resource_destroy(&screen
->immd_heap
[0]);
200 nouveau_resource_destroy(&screen
->parm_heap
[0]);
201 nouveau_resource_destroy(&screen
->parm_heap
[1]);
202 nouveau_screen_fini(&screen
->base
);
206 #define BGN_RELOC(ch, bo, gr, m, n, fl) \
207 OUT_RELOC(ch, bo, (n << 18) | (gr->subc << 13) | m, fl, 0, 0)
210 nv50_screen_relocs(struct nv50_screen
*screen
)
212 struct nouveau_channel
*chan
= screen
->base
.channel
;
213 struct nouveau_grobj
*tesla
= screen
->tesla
;
215 const unsigned rl
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
| NOUVEAU_BO_DUMMY
;
217 MARK_RING (chan
, 28, 26);
219 /* cause grobj autobind */
220 BEGIN_RING(chan
, tesla
, 0x0100, 1);
223 BGN_RELOC (chan
, screen
->tic
, tesla
, NV50TCL_TIC_ADDRESS_HIGH
, 2, rl
);
224 OUT_RELOCh(chan
, screen
->tic
, 0, rl
);
225 OUT_RELOCl(chan
, screen
->tic
, 0, rl
);
227 BGN_RELOC (chan
, screen
->tsc
, tesla
, NV50TCL_TSC_ADDRESS_HIGH
, 2, rl
);
228 OUT_RELOCh(chan
, screen
->tsc
, 0, rl
);
229 OUT_RELOCl(chan
, screen
->tsc
, 0, rl
);
231 BGN_RELOC (chan
, screen
->constbuf_misc
[0],
232 tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3, rl
);
233 OUT_RELOCh(chan
, screen
->constbuf_misc
[0], 0, rl
);
234 OUT_RELOCl(chan
, screen
->constbuf_misc
[0], 0, rl
);
235 OUT_RELOC (chan
, screen
->constbuf_misc
[0],
236 (NV50_CB_PMISC
<< 16) | 0x0200, rl
, 0, 0);
238 BGN_RELOC (chan
, screen
->constbuf_misc
[0],
239 tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3, rl
);
240 OUT_RELOCh(chan
, screen
->constbuf_misc
[0], 0x200, rl
);
241 OUT_RELOCl(chan
, screen
->constbuf_misc
[0], 0x200, rl
);
242 OUT_RELOC (chan
, screen
->constbuf_misc
[0],
243 (NV50_CB_AUX
<< 16) | 0x0200, rl
, 0, 0);
245 for (i
= 0; i
< 3; ++i
) {
246 BGN_RELOC (chan
, screen
->constbuf_parm
[i
],
247 tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3, rl
);
248 OUT_RELOCh(chan
, screen
->constbuf_parm
[i
], 0, rl
);
249 OUT_RELOCl(chan
, screen
->constbuf_parm
[i
], 0, rl
);
250 OUT_RELOC (chan
, screen
->constbuf_parm
[i
],
251 ((NV50_CB_PVP
+ i
) << 16) | 0x0800, rl
, 0, 0);
256 nv50_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
258 struct nv50_screen
*screen
= CALLOC_STRUCT(nv50_screen
);
259 struct nouveau_channel
*chan
;
260 struct pipe_screen
*pscreen
;
261 unsigned chipset
= dev
->chipset
;
262 unsigned tesla_class
= 0;
264 const unsigned rl
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
;
268 pscreen
= &screen
->base
.base
;
270 ret
= nouveau_screen_init(&screen
->base
, dev
);
272 nv50_screen_destroy(pscreen
);
275 chan
= screen
->base
.channel
;
277 pscreen
->winsys
= ws
;
278 pscreen
->destroy
= nv50_screen_destroy
;
279 pscreen
->get_param
= nv50_screen_get_param
;
280 pscreen
->get_paramf
= nv50_screen_get_paramf
;
281 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
282 pscreen
->context_create
= nv50_create
;
284 nv50_screen_init_resource_functions(pscreen
);
286 /* DMA engine object */
287 ret
= nouveau_grobj_alloc(chan
, 0xbeef5039,
288 NV50_MEMORY_TO_MEMORY_FORMAT
, &screen
->m2mf
);
290 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret
);
291 nv50_screen_destroy(pscreen
);
296 ret
= nouveau_grobj_alloc(chan
, 0xbeef502d, NV50_2D
, &screen
->eng2d
);
298 NOUVEAU_ERR("Error creating 2D object: %d\n", ret
);
299 nv50_screen_destroy(pscreen
);
304 switch (chipset
& 0xf0) {
306 tesla_class
= NV50TCL
;
310 tesla_class
= NV84TCL
;
317 tesla_class
= NVA0TCL
;
320 tesla_class
= NVA8TCL
;
325 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset
);
326 nv50_screen_destroy(pscreen
);
330 ret
= nouveau_grobj_alloc(chan
, 0xbeef5097, tesla_class
,
333 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
334 nv50_screen_destroy(pscreen
);
338 /* this is necessary for the new RING_3D / statebuffer code */
339 BIND_RING(chan
, screen
->tesla
, 7);
342 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
344 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
345 nv50_screen_destroy(pscreen
);
349 /* Static M2MF init */
350 BEGIN_RING(chan
, screen
->m2mf
,
351 NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY
, 3);
352 OUT_RING (chan
, screen
->sync
->handle
);
353 OUT_RING (chan
, chan
->vram
->handle
);
354 OUT_RING (chan
, chan
->vram
->handle
);
357 BEGIN_RING(chan
, screen
->eng2d
, NV50_2D_DMA_NOTIFY
, 4);
358 OUT_RING (chan
, screen
->sync
->handle
);
359 OUT_RING (chan
, chan
->vram
->handle
);
360 OUT_RING (chan
, chan
->vram
->handle
);
361 OUT_RING (chan
, chan
->vram
->handle
);
362 BEGIN_RING(chan
, screen
->eng2d
, NV50_2D_OPERATION
, 1);
363 OUT_RING (chan
, NV50_2D_OPERATION_SRCCOPY
);
364 BEGIN_RING(chan
, screen
->eng2d
, NV50_2D_CLIP_ENABLE
, 1);
366 BEGIN_RING(chan
, screen
->eng2d
, 0x0888, 1);
369 /* Static tesla init */
370 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_COND_MODE
, 1);
371 OUT_RING (chan
, NV50TCL_COND_MODE_ALWAYS
);
372 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_DMA_NOTIFY
, 1);
373 OUT_RING (chan
, screen
->sync
->handle
);
374 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_DMA_ZETA
, 11);
375 for (i
= 0; i
< 11; i
++)
376 OUT_RING (chan
, chan
->vram
->handle
);
377 BEGIN_RING(chan
, screen
->tesla
,
378 NV50TCL_DMA_COLOR(0), NV50TCL_DMA_COLOR__SIZE
);
379 for (i
= 0; i
< NV50TCL_DMA_COLOR__SIZE
; i
++)
380 OUT_RING (chan
, chan
->vram
->handle
);
382 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_RT_CONTROL
, 1);
385 /* activate all 32 lanes (threads) in a warp */
386 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_REG_MODE
, 1);
387 OUT_RING (chan
, NV50TCL_REG_MODE_STRIPED
);
388 BEGIN_RING(chan
, screen
->tesla
, 0x1400, 1);
389 OUT_RING (chan
, 0xf);
391 /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
392 for (i
= 0; i
< 3; ++i
) {
393 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_TEX_LIMITS(i
), 1);
394 OUT_RING (chan
, 0x54);
397 /* origin is top left (set to 1 for bottom left) */
398 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_Y_ORIGIN_BOTTOM
, 1);
400 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_VP_REG_ALLOC_RESULT
, 1);
403 /* constant buffers for immediates and VP/FP parameters */
404 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, (32 * 4) * 4,
405 &screen
->constbuf_misc
[0]);
407 nv50_screen_destroy(pscreen
);
410 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
411 OUT_RELOCh(chan
, screen
->constbuf_misc
[0], 0, rl
);
412 OUT_RELOCl(chan
, screen
->constbuf_misc
[0], 0, rl
);
413 OUT_RING (chan
, (NV50_CB_PMISC
<< 16) | 0x0200);
414 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
415 OUT_RELOCh(chan
, screen
->constbuf_misc
[0], 0x200, rl
);
416 OUT_RELOCl(chan
, screen
->constbuf_misc
[0], 0x200, rl
);
417 OUT_RING (chan
, (NV50_CB_AUX
<< 16) | 0x0200);
419 for (i
= 0; i
< 3; i
++) {
420 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, (256 * 4) * 4,
421 &screen
->constbuf_parm
[i
]);
423 nv50_screen_destroy(pscreen
);
426 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
427 OUT_RELOCh(chan
, screen
->constbuf_parm
[i
], 0, rl
);
428 OUT_RELOCl(chan
, screen
->constbuf_parm
[i
], 0, rl
);
429 OUT_RING (chan
, ((NV50_CB_PVP
+ i
) << 16) | 0x0800);
432 if (nouveau_resource_init(&screen
->immd_heap
[0], 0, 128) ||
433 nouveau_resource_init(&screen
->parm_heap
[0], 0, 512) ||
434 nouveau_resource_init(&screen
->parm_heap
[1], 0, 512))
436 NOUVEAU_ERR("Error initialising constant buffers.\n");
437 nv50_screen_destroy(pscreen
);
441 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, 3 * 32 * (8 * 4),
444 nv50_screen_destroy(pscreen
);
447 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_TIC_ADDRESS_HIGH
, 3);
448 OUT_RELOCh(chan
, screen
->tic
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
449 OUT_RELOCl(chan
, screen
->tic
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
450 OUT_RING (chan
, 3 * 32 - 1);
452 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, 3 * 32 * (8 * 4),
455 nv50_screen_destroy(pscreen
);
458 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_TSC_ADDRESS_HIGH
, 3);
459 OUT_RELOCh(chan
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
460 OUT_RELOCl(chan
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
461 OUT_RING (chan
, 0); /* ignored if TSC_LINKED (0x1234) == 1 */
463 /* map constant buffers:
464 * B = buffer ID (maybe more than 1 byte)
465 * N = CB index used in shader instruction
466 * P = program type (0 = VP, 2 = GP, 3 = FP)
467 * SET_PROGRAM_CB = 0x000BBNP1
469 BEGIN_RING_NI(chan
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 8);
470 /* bind immediate buffer */
471 OUT_RING (chan
, 0x001 | (NV50_CB_PMISC
<< 12));
472 OUT_RING (chan
, 0x021 | (NV50_CB_PMISC
<< 12));
473 OUT_RING (chan
, 0x031 | (NV50_CB_PMISC
<< 12));
474 /* bind auxiliary constbuf to immediate data bo */
475 OUT_RING (chan
, 0x201 | (NV50_CB_AUX
<< 12));
476 OUT_RING (chan
, 0x221 | (NV50_CB_AUX
<< 12));
477 /* bind parameter buffers */
478 OUT_RING (chan
, 0x101 | (NV50_CB_PVP
<< 12));
479 OUT_RING (chan
, 0x121 | (NV50_CB_PGP
<< 12));
480 OUT_RING (chan
, 0x131 | (NV50_CB_PFP
<< 12));
482 /* Vertex array limits - max them out */
483 for (i
= 0; i
< 16; i
++) {
484 BEGIN_RING(chan
, screen
->tesla
,
485 NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i
), 2);
486 OUT_RING (chan
, 0x000000ff);
487 OUT_RING (chan
, 0xffffffff);
490 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
491 OUT_RINGf (chan
, 0.0f
);
492 OUT_RINGf (chan
, 1.0f
);
494 /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
495 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_LINKED_TSC
, 1);
498 BEGIN_RING(chan
, screen
->tesla
, NV50TCL_EDGEFLAG_ENABLE
, 1);
499 OUT_RING (chan
, 1); /* default edgeflag to TRUE */
503 screen
->force_push
= debug_get_bool_option("NV50_ALWAYS_PUSH", FALSE
);