2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_screen.h"
25 #include "nv50_context.h"
26 #include "nv50_screen.h"
28 #include "nouveau/nouveau_stateobj.h"
31 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
32 enum pipe_format format
,
33 enum pipe_texture_target target
,
34 unsigned tex_usage
, unsigned geom_flags
)
36 if (tex_usage
& PIPE_TEXTURE_USAGE_RENDER_TARGET
) {
38 case PIPE_FORMAT_B8G8R8X8_UNORM
:
39 case PIPE_FORMAT_B8G8R8A8_UNORM
:
40 case PIPE_FORMAT_B5G6R5_UNORM
:
41 case PIPE_FORMAT_R16G16B16A16_SNORM
:
42 case PIPE_FORMAT_R16G16B16A16_UNORM
:
43 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
44 case PIPE_FORMAT_R16G16_SNORM
:
45 case PIPE_FORMAT_R16G16_UNORM
:
51 if (tex_usage
& PIPE_TEXTURE_USAGE_DEPTH_STENCIL
) {
53 case PIPE_FORMAT_Z32_FLOAT
:
54 case PIPE_FORMAT_S8Z24_UNORM
:
55 case PIPE_FORMAT_Z24X8_UNORM
:
56 case PIPE_FORMAT_Z24S8_UNORM
:
63 case PIPE_FORMAT_B8G8R8A8_UNORM
:
64 case PIPE_FORMAT_B8G8R8X8_UNORM
:
65 case PIPE_FORMAT_B8G8R8A8_SRGB
:
66 case PIPE_FORMAT_B8G8R8X8_SRGB
:
67 case PIPE_FORMAT_B5G5R5A1_UNORM
:
68 case PIPE_FORMAT_B4G4R4A4_UNORM
:
69 case PIPE_FORMAT_B5G6R5_UNORM
:
70 case PIPE_FORMAT_L8_UNORM
:
71 case PIPE_FORMAT_A8_UNORM
:
72 case PIPE_FORMAT_I8_UNORM
:
73 case PIPE_FORMAT_L8A8_UNORM
:
74 case PIPE_FORMAT_DXT1_RGB
:
75 case PIPE_FORMAT_DXT1_RGBA
:
76 case PIPE_FORMAT_DXT3_RGBA
:
77 case PIPE_FORMAT_DXT5_RGBA
:
78 case PIPE_FORMAT_S8Z24_UNORM
:
79 case PIPE_FORMAT_Z24S8_UNORM
:
80 case PIPE_FORMAT_Z32_FLOAT
:
81 case PIPE_FORMAT_R16G16B16A16_SNORM
:
82 case PIPE_FORMAT_R16G16B16A16_UNORM
:
83 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
84 case PIPE_FORMAT_R16G16_SNORM
:
85 case PIPE_FORMAT_R16G16_UNORM
:
96 nv50_screen_get_param(struct pipe_screen
*pscreen
, int param
)
98 struct nv50_screen
*screen
= nv50_screen(pscreen
);
101 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
103 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
105 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
107 case PIPE_CAP_NPOT_TEXTURES
:
109 case PIPE_CAP_TWO_SIDED_STENCIL
:
113 case PIPE_CAP_ANISOTROPIC_FILTER
:
115 case PIPE_CAP_POINT_SPRITE
:
117 case PIPE_CAP_MAX_RENDER_TARGETS
:
119 case PIPE_CAP_OCCLUSION_QUERY
:
121 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
123 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
125 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
127 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
129 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
130 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
132 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
134 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
136 case NOUVEAU_CAP_HW_VTXBUF
:
137 return screen
->force_push
? 0 : 1;
138 case NOUVEAU_CAP_HW_IDXBUF
:
139 return screen
->force_push
? 0 : 1;
140 case PIPE_CAP_INDEP_BLEND_ENABLE
:
142 case PIPE_CAP_INDEP_BLEND_FUNC
:
144 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
145 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
147 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
148 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
151 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
157 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
160 case PIPE_CAP_MAX_LINE_WIDTH
:
161 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
163 case PIPE_CAP_MAX_POINT_WIDTH
:
164 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
166 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
168 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
171 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
177 nv50_screen_destroy(struct pipe_screen
*pscreen
)
179 struct nv50_screen
*screen
= nv50_screen(pscreen
);
182 for (i
= 0; i
< 3; i
++) {
183 if (screen
->constbuf_parm
[i
])
184 nouveau_bo_ref(NULL
, &screen
->constbuf_parm
[i
]);
187 if (screen
->constbuf_misc
[0])
188 nouveau_bo_ref(NULL
, &screen
->constbuf_misc
[0]);
190 nouveau_bo_ref(NULL
, &screen
->tic
);
192 nouveau_bo_ref(NULL
, &screen
->tsc
);
193 if (screen
->static_init
)
194 so_ref(NULL
, &screen
->static_init
);
196 nouveau_notifier_free(&screen
->sync
);
197 nouveau_grobj_free(&screen
->tesla
);
198 nouveau_grobj_free(&screen
->eng2d
);
199 nouveau_grobj_free(&screen
->m2mf
);
200 nouveau_resource_destroy(&screen
->immd_heap
[0]);
201 nouveau_resource_destroy(&screen
->parm_heap
[0]);
202 nouveau_resource_destroy(&screen
->parm_heap
[1]);
203 nouveau_screen_fini(&screen
->base
);
208 nv50_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
210 struct nv50_screen
*screen
= CALLOC_STRUCT(nv50_screen
);
211 struct nouveau_channel
*chan
;
212 struct pipe_screen
*pscreen
;
213 struct nouveau_stateobj
*so
;
214 unsigned chipset
= dev
->chipset
;
215 unsigned tesla_class
= 0;
220 pscreen
= &screen
->base
.base
;
222 ret
= nouveau_screen_init(&screen
->base
, dev
);
224 nv50_screen_destroy(pscreen
);
227 chan
= screen
->base
.channel
;
229 pscreen
->winsys
= ws
;
230 pscreen
->destroy
= nv50_screen_destroy
;
231 pscreen
->get_param
= nv50_screen_get_param
;
232 pscreen
->get_paramf
= nv50_screen_get_paramf
;
233 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
234 pscreen
->context_create
= nv50_create
;
236 nv50_screen_init_miptree_functions(pscreen
);
238 /* DMA engine object */
239 ret
= nouveau_grobj_alloc(chan
, 0xbeef5039,
240 NV50_MEMORY_TO_MEMORY_FORMAT
, &screen
->m2mf
);
242 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret
);
243 nv50_screen_destroy(pscreen
);
248 ret
= nouveau_grobj_alloc(chan
, 0xbeef502d, NV50_2D
, &screen
->eng2d
);
250 NOUVEAU_ERR("Error creating 2D object: %d\n", ret
);
251 nv50_screen_destroy(pscreen
);
256 switch (chipset
& 0xf0) {
258 tesla_class
= NV50TCL
;
262 tesla_class
= NV84TCL
;
269 tesla_class
= NVA0TCL
;
272 tesla_class
= NVA8TCL
;
277 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset
);
278 nv50_screen_destroy(pscreen
);
282 ret
= nouveau_grobj_alloc(chan
, 0xbeef5097, tesla_class
,
285 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
286 nv50_screen_destroy(pscreen
);
291 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
293 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
294 nv50_screen_destroy(pscreen
);
298 /* Static M2MF init */
299 so
= so_new(1, 3, 0);
300 so_method(so
, screen
->m2mf
, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY
, 3);
301 so_data (so
, screen
->sync
->handle
);
302 so_data (so
, chan
->vram
->handle
);
303 so_data (so
, chan
->vram
->handle
);
308 so
= so_new(4, 7, 0);
309 so_method(so
, screen
->eng2d
, NV50_2D_DMA_NOTIFY
, 4);
310 so_data (so
, screen
->sync
->handle
);
311 so_data (so
, chan
->vram
->handle
);
312 so_data (so
, chan
->vram
->handle
);
313 so_data (so
, chan
->vram
->handle
);
314 so_method(so
, screen
->eng2d
, NV50_2D_OPERATION
, 1);
315 so_data (so
, NV50_2D_OPERATION_SRCCOPY
);
316 so_method(so
, screen
->eng2d
, NV50_2D_CLIP_ENABLE
, 1);
318 so_method(so
, screen
->eng2d
, 0x0888, 1);
323 /* Static tesla init */
324 so
= so_new(47, 95, 24);
326 so_method(so
, screen
->tesla
, NV50TCL_COND_MODE
, 1);
327 so_data (so
, NV50TCL_COND_MODE_ALWAYS
);
328 so_method(so
, screen
->tesla
, NV50TCL_DMA_NOTIFY
, 1);
329 so_data (so
, screen
->sync
->handle
);
330 so_method(so
, screen
->tesla
, NV50TCL_DMA_ZETA
, 11);
331 for (i
= 0; i
< 11; i
++)
332 so_data(so
, chan
->vram
->handle
);
333 so_method(so
, screen
->tesla
, NV50TCL_DMA_COLOR(0),
334 NV50TCL_DMA_COLOR__SIZE
);
335 for (i
= 0; i
< NV50TCL_DMA_COLOR__SIZE
; i
++)
336 so_data(so
, chan
->vram
->handle
);
337 so_method(so
, screen
->tesla
, NV50TCL_RT_CONTROL
, 1);
340 /* activate all 32 lanes (threads) in a warp */
341 so_method(so
, screen
->tesla
, NV50TCL_WARP_HALVES
, 1);
343 so_method(so
, screen
->tesla
, 0x1400, 1);
346 /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
347 for (i
= 0; i
< 3; ++i
) {
348 so_method(so
, screen
->tesla
, NV50TCL_TEX_LIMITS(i
), 1);
352 /* origin is top left (set to 1 for bottom left) */
353 so_method(so
, screen
->tesla
, NV50TCL_Y_ORIGIN_BOTTOM
, 1);
355 so_method(so
, screen
->tesla
, NV50TCL_VP_REG_ALLOC_RESULT
, 1);
358 /* constant buffers for immediates and VP/FP parameters */
359 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, (32 * 4) * 4,
360 &screen
->constbuf_misc
[0]);
362 nv50_screen_destroy(pscreen
);
366 for (i
= 0; i
< 3; i
++) {
367 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, (256 * 4) * 4,
368 &screen
->constbuf_parm
[i
]);
370 nv50_screen_destroy(pscreen
);
375 if (nouveau_resource_init(&screen
->immd_heap
[0], 0, 128) ||
376 nouveau_resource_init(&screen
->parm_heap
[0], 0, 512) ||
377 nouveau_resource_init(&screen
->parm_heap
[1], 0, 512))
379 NOUVEAU_ERR("Error initialising constant buffers.\n");
380 nv50_screen_destroy(pscreen
);
385 // map constant buffers:
386 // B = buffer ID (maybe more than 1 byte)
387 // N = CB index used in shader instruction
388 // P = program type (0 = VP, 2 = GP, 3 = FP)
389 so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1);
390 so_data (so, 0x000BBNP1);
393 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
394 so_reloc (so
, screen
->constbuf_misc
[0], 0, NOUVEAU_BO_VRAM
|
395 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
396 so_reloc (so
, screen
->constbuf_misc
[0], 0, NOUVEAU_BO_VRAM
|
397 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
398 so_data (so
, (NV50_CB_PMISC
<< 16) | 0x00000200);
399 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
400 so_data (so
, 0x00000001 | (NV50_CB_PMISC
<< 12));
401 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
402 so_data (so
, 0x00000021 | (NV50_CB_PMISC
<< 12));
403 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
404 so_data (so
, 0x00000031 | (NV50_CB_PMISC
<< 12));
406 /* bind auxiliary constbuf to immediate data bo */
407 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
408 so_reloc (so
, screen
->constbuf_misc
[0], (128 * 4) * 4,
409 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
410 so_reloc (so
, screen
->constbuf_misc
[0], (128 * 4) * 4,
411 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
412 so_data (so
, (NV50_CB_AUX
<< 16) | 0x00000200);
413 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
414 so_data (so
, 0x00000201 | (NV50_CB_AUX
<< 12));
415 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
416 so_data (so
, 0x00000221 | (NV50_CB_AUX
<< 12));
418 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
419 so_reloc (so
, screen
->constbuf_parm
[PIPE_SHADER_VERTEX
], 0,
420 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
421 so_reloc (so
, screen
->constbuf_parm
[PIPE_SHADER_VERTEX
], 0,
422 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
423 so_data (so
, (NV50_CB_PVP
<< 16) | 0x00000800);
424 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
425 so_data (so
, 0x00000101 | (NV50_CB_PVP
<< 12));
427 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
428 so_reloc (so
, screen
->constbuf_parm
[PIPE_SHADER_GEOMETRY
], 0,
429 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
430 so_reloc (so
, screen
->constbuf_parm
[PIPE_SHADER_GEOMETRY
], 0,
431 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
432 so_data (so
, (NV50_CB_PGP
<< 16) | 0x00000800);
433 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
434 so_data (so
, 0x00000121 | (NV50_CB_PGP
<< 12));
436 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
437 so_reloc (so
, screen
->constbuf_parm
[PIPE_SHADER_FRAGMENT
], 0,
438 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
439 so_reloc (so
, screen
->constbuf_parm
[PIPE_SHADER_FRAGMENT
], 0,
440 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
441 so_data (so
, (NV50_CB_PFP
<< 16) | 0x00000800);
442 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
443 so_data (so
, 0x00000131 | (NV50_CB_PFP
<< 12));
445 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, 3 * 32 * (8 * 4),
448 nv50_screen_destroy(pscreen
);
452 so_method(so
, screen
->tesla
, NV50TCL_TIC_ADDRESS_HIGH
, 3);
453 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
454 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
455 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
456 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
457 so_data (so
, 3 * 32 - 1);
459 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, 3 * 32 * (8 * 4),
462 nv50_screen_destroy(pscreen
);
466 so_method(so
, screen
->tesla
, NV50TCL_TSC_ADDRESS_HIGH
, 3);
467 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
468 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
469 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
470 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
471 so_data (so
, 0x00000000); /* ignored if TSC_LINKED (0x1234) = 1 */
474 /* Vertex array limits - max them out */
475 for (i
= 0; i
< 16; i
++) {
476 so_method(so
, screen
->tesla
, NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i
), 2);
477 so_data (so
, 0x000000ff);
478 so_data (so
, 0xffffffff);
481 so_method(so
, screen
->tesla
, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
482 so_data (so
, fui(0.0));
483 so_data (so
, fui(1.0));
485 /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
486 so_method(so
, screen
->tesla
, NV50TCL_LINKED_TSC
, 1);
489 so_method(so
, screen
->tesla
, NV50TCL_EDGEFLAG_ENABLE
, 1);
490 so_data (so
, 1); /* default edgeflag to TRUE */
493 so_ref (so
, &screen
->static_init
);
495 nouveau_pushbuf_flush(chan
, 0);
497 screen
->force_push
= debug_get_bool_option("NV50_ALWAYS_PUSH", FALSE
);