src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nv50_context.h"
  27 #include "nv50_screen.h"
  28 #include "nv50_resource.h"
  29
  30 #include "nouveau/nouveau_stateobj.h"
  31
  32 static boolean
  33 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  34                                 enum pipe_format format,
  35                                 enum pipe_texture_target target,
  36                                 unsigned sample_count,
  37                                 unsigned usage, unsigned geom_flags)
  38 {
  39         if (sample_count > 1)
  40                 return FALSE;
  41
  42         if (!util_format_s3tc_enabled) {
  43                 switch (format) {
  44                 case PIPE_FORMAT_DXT1_RGB:
  45                 case PIPE_FORMAT_DXT1_RGBA:
  46                 case PIPE_FORMAT_DXT3_RGBA:
  47                 case PIPE_FORMAT_DXT5_RGBA:
  48                         return FALSE;
  49                 default:
  50                         break;
  51                 }
  52         }
  53
  54         switch (format) {
  55         case PIPE_FORMAT_Z16_UNORM:
  56                 if ((nouveau_screen(pscreen)->device->chipset & 0xf0) != 0xa0)
  57                         return FALSE;
  58                 break;
  59         default:
  60                 break;
  61         }
  62
  63         /* transfers & shared are always supported */
  64         usage &= ~(PIPE_BIND_TRANSFER_READ |
  65                    PIPE_BIND_TRANSFER_WRITE |
  66                    PIPE_BIND_SHARED);
  67
  68         return (nv50_format_table[format].usage & usage) == usage;
  69 }
  70
  71 static int
  72 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  73 {
  74         switch (param) {
  75         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  76                 return 32;
  77         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  78                 return 32;
  79         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  80                 return 64;
  81         case PIPE_CAP_NPOT_TEXTURES:
  82                 return 1;
  83         case PIPE_CAP_TWO_SIDED_STENCIL:
  84                 return 1;
  85         case PIPE_CAP_GLSL:
  86                 return 1;
  87         case PIPE_CAP_GEOMETRY_SHADER4:
  88                 return 0;
  89         case PIPE_CAP_ANISOTROPIC_FILTER:
  90                 return 1;
  91         case PIPE_CAP_POINT_SPRITE:
  92                 return 1;
  93         case PIPE_CAP_MAX_RENDER_TARGETS:
  94                 return 8;
  95         case PIPE_CAP_OCCLUSION_QUERY:
  96                 return 1;
  97         case PIPE_CAP_TIMER_QUERY:
  98                 return 0;
  99         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 100                 return 1;
 101         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 102                 return 13;
 103         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 104                 return 10;
 105         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 106                 return 13;
 107         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 108         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
 109                 return 1;
 110         case PIPE_CAP_TEXTURE_SWIZZLE:
 111                 return 1;
 112         case PIPE_CAP_TGSI_CONT_SUPPORTED:
 113                 return 1;
 114         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 115                 return 1;
 116         case PIPE_CAP_INDEP_BLEND_ENABLE:
 117                 return 1;
 118         case PIPE_CAP_INDEP_BLEND_FUNC:
 119                 return 0;
 120         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 121                 return 1;
 122         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 123         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 124                 return 1;
 125         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 126         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 127                 return 0;
 128         case PIPE_CAP_MAX_VS_INSTRUCTIONS:
 129         case PIPE_CAP_MAX_FS_INSTRUCTIONS:
 130         case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS:
 131         case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS:
 132         case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS:
 133         case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS:
 134         case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS:
 135         case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: /* arbitrary limit */
 136                 return 16384;
 137         case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH:
 138         case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: /* need stack bo */
 139                 return 4;
 140         case PIPE_CAP_MAX_VS_INPUTS:
 141                 return 16;
 142         case PIPE_CAP_MAX_FS_INPUTS: /* 128 / 4 with GP */
 143                 return 64 / 4;
 144         case PIPE_CAP_MAX_VS_CONSTS:
 145         case PIPE_CAP_MAX_FS_CONSTS:
 146                 return 65536 / 16;
 147         case PIPE_CAP_MAX_VS_ADDRS:
 148         case PIPE_CAP_MAX_FS_ADDRS: /* no spilling atm */
 149                 return 1;
 150         case PIPE_CAP_MAX_VS_PREDS:
 151         case PIPE_CAP_MAX_FS_PREDS: /* not yet handled */
 152                 return 0;
 153         case PIPE_CAP_MAX_VS_TEMPS:
 154         case PIPE_CAP_MAX_FS_TEMPS: /* no spilling atm */
 155                 return 128 / 4;
 156         case PIPE_CAP_DEPTH_CLAMP:
 157                 return 1;
 158         default:
 159                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 160                 return 0;
 161         }
 162 }
 163
 164 static float
 165 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 166 {
 167         switch (param) {
 168         case PIPE_CAP_MAX_LINE_WIDTH:
 169         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 170                 return 10.0;
 171         case PIPE_CAP_MAX_POINT_WIDTH:
 172         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 173                 return 64.0;
 174         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 175                 return 16.0;
 176         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 177                 return 4.0;
 178         default:
 179                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 180                 return 0.0;
 181         }
 182 }
 183
 184 static void
 185 nv50_screen_destroy(struct pipe_screen *pscreen)
 186 {
 187         struct nv50_screen *screen = nv50_screen(pscreen);
 188         unsigned i;
 189
 190         for (i = 0; i < 3; i++) {
 191                 if (screen->constbuf_parm[i])
 192                         nouveau_bo_ref(NULL, &screen->constbuf_parm[i]);
 193         }
 194
 195         if (screen->constbuf_misc[0])
 196                 nouveau_bo_ref(NULL, &screen->constbuf_misc[0]);
 197         if (screen->tic)
 198                 nouveau_bo_ref(NULL, &screen->tic);
 199         if (screen->tsc)
 200                 nouveau_bo_ref(NULL, &screen->tsc);
 201
 202         nouveau_notifier_free(&screen->sync);
 203         nouveau_grobj_free(&screen->tesla);
 204         nouveau_grobj_free(&screen->eng2d);
 205         nouveau_grobj_free(&screen->m2mf);
 206         nouveau_resource_destroy(&screen->immd_heap);
 207         nouveau_screen_fini(&screen->base);
 208         FREE(screen);
 209 }
 210
 211 #define BGN_RELOC(ch, bo, gr, m, n, fl) \
 212    OUT_RELOC(ch, bo, (n << 18) | (gr->subc << 13) | m, fl, 0, 0)
 213
 214 void
 215 nv50_screen_relocs(struct nv50_screen *screen)
 216 {
 217         struct nouveau_channel *chan = screen->base.channel;
 218         struct nouveau_grobj *tesla = screen->tesla;
 219         unsigned i;
 220         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
 221
 222         MARK_RING (chan, 28, 26);
 223
 224         /* cause grobj autobind */
 225         BEGIN_RING(chan, tesla, 0x0100, 1);
 226         OUT_RING  (chan, 0);
 227
 228         BGN_RELOC (chan, screen->tic, tesla, NV50TCL_TIC_ADDRESS_HIGH, 2, rl);
 229         OUT_RELOCh(chan, screen->tic, 0, rl);
 230         OUT_RELOCl(chan, screen->tic, 0, rl);
 231
 232         BGN_RELOC (chan, screen->tsc, tesla, NV50TCL_TSC_ADDRESS_HIGH, 2, rl);
 233         OUT_RELOCh(chan, screen->tsc, 0, rl);
 234         OUT_RELOCl(chan, screen->tsc, 0, rl);
 235
 236         BGN_RELOC (chan, screen->constbuf_misc[0],
 237                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 238         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 239         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 240         OUT_RELOC (chan, screen->constbuf_misc[0],
 241                    (NV50_CB_PMISC << 16) | 0x0200, rl, 0, 0);
 242
 243         BGN_RELOC (chan, screen->constbuf_misc[0],
 244                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 245         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 246         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 247         OUT_RELOC (chan, screen->constbuf_misc[0],
 248                    (NV50_CB_AUX << 16) | 0x0200, rl, 0, 0);
 249
 250         for (i = 0; i < 3; ++i) {
 251                 BGN_RELOC (chan, screen->constbuf_parm[i],
 252                            tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 253                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 254                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 255                 OUT_RELOC (chan, screen->constbuf_parm[i],
 256                            ((NV50_CB_PVP + i) << 16) | 0x0000, rl, 0, 0);
 257         }
 258 }
 259
 260 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
 261 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
 262 #endif
 263
 264 extern int nouveau_device_get_param(struct nouveau_device *dev,
 265                                     uint64_t param, uint64_t *value);
 266
 267 struct pipe_screen *
 268 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 269 {
 270         struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen);
 271         struct nouveau_channel *chan;
 272         struct pipe_screen *pscreen;
 273         uint64_t value;
 274         unsigned chipset = dev->chipset;
 275         unsigned tesla_class = 0;
 276         unsigned stack_size;
 277         int ret, i;
 278         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 279
 280         if (!screen)
 281                 return NULL;
 282         pscreen = &screen->base.base;
 283
 284         ret = nouveau_screen_init(&screen->base, dev);
 285         if (ret) {
 286                 nv50_screen_destroy(pscreen);
 287                 return NULL;
 288         }
 289         chan = screen->base.channel;
 290
 291         pscreen->winsys = ws;
 292         pscreen->destroy = nv50_screen_destroy;
 293         pscreen->get_param = nv50_screen_get_param;
 294         pscreen->get_paramf = nv50_screen_get_paramf;
 295         pscreen->is_format_supported = nv50_screen_is_format_supported;
 296         pscreen->context_create = nv50_create;
 297
 298         nv50_screen_init_resource_functions(pscreen);
 299
 300         /* DMA engine object */
 301         ret = nouveau_grobj_alloc(chan, 0xbeef5039,
 302                 NV50_MEMORY_TO_MEMORY_FORMAT, &screen->m2mf);
 303         if (ret) {
 304                 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret);
 305                 nv50_screen_destroy(pscreen);
 306                 return NULL;
 307         }
 308
 309         /* 2D object */
 310         ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 311         if (ret) {
 312                 NOUVEAU_ERR("Error creating 2D object: %d\n", ret);
 313                 nv50_screen_destroy(pscreen);
 314                 return NULL;
 315         }
 316
 317         /* 3D object */
 318         switch (chipset & 0xf0) {
 319         case 0x50:
 320                 tesla_class = NV50TCL;
 321                 break;
 322         case 0x80:
 323         case 0x90:
 324                 tesla_class = NV84TCL;
 325                 break;
 326         case 0xa0:
 327                 switch (chipset) {
 328                 case 0xa0:
 329                 case 0xaa:
 330                 case 0xac:
 331                         tesla_class = NVA0TCL;
 332                         break;
 333                 default:
 334                         tesla_class = NVA8TCL;
 335                         break;
 336                 }
 337                 break;
 338         default:
 339                 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset);
 340                 nv50_screen_destroy(pscreen);
 341                 return NULL;
 342         }
 343
 344         ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class,
 345                 &screen->tesla);
 346         if (ret) {
 347                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 348                 nv50_screen_destroy(pscreen);
 349                 return NULL;
 350         }
 351
 352         /* this is necessary for the new RING_3D / statebuffer code */
 353         BIND_RING(chan, screen->tesla, 7);
 354
 355         /* Sync notifier */
 356         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 357         if (ret) {
 358                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 359                 nv50_screen_destroy(pscreen);
 360                 return NULL;
 361         }
 362
 363         /* Static M2MF init */
 364         BEGIN_RING(chan, screen->m2mf,
 365                    NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 366         OUT_RING  (chan, screen->sync->handle);
 367         OUT_RING  (chan, chan->vram->handle);
 368         OUT_RING  (chan, chan->vram->handle);
 369
 370         /* Static 2D init */
 371         BEGIN_RING(chan, screen->eng2d, NV50_2D_DMA_NOTIFY, 4);
 372         OUT_RING  (chan, screen->sync->handle);
 373         OUT_RING  (chan, chan->vram->handle);
 374         OUT_RING  (chan, chan->vram->handle);
 375         OUT_RING  (chan, chan->vram->handle);
 376         BEGIN_RING(chan, screen->eng2d, NV50_2D_OPERATION, 1);
 377         OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 378         BEGIN_RING(chan, screen->eng2d, NV50_2D_CLIP_ENABLE, 1);
 379         OUT_RING  (chan, 0);
 380         BEGIN_RING(chan, screen->eng2d, 0x0888, 1);
 381         OUT_RING  (chan, 1);
 382
 383         /* Static tesla init */
 384         BEGIN_RING(chan, screen->tesla, NV50TCL_COND_MODE, 1);
 385         OUT_RING  (chan, NV50TCL_COND_MODE_ALWAYS);
 386         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
 387         OUT_RING  (chan, screen->sync->handle);
 388         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_ZETA, 11);
 389         for (i = 0; i < 11; i++)
 390                 OUT_RING  (chan, chan->vram->handle);
 391         BEGIN_RING(chan, screen->tesla,
 392                    NV50TCL_DMA_COLOR(0), NV50TCL_DMA_COLOR__SIZE);
 393         for (i = 0; i < NV50TCL_DMA_COLOR__SIZE; i++)
 394                 OUT_RING  (chan, chan->vram->handle);
 395
 396         BEGIN_RING(chan, screen->tesla, NV50TCL_RT_CONTROL, 1);
 397         OUT_RING  (chan, 1);
 398
 399         /* activate all 32 lanes (threads) in a warp */
 400         BEGIN_RING(chan, screen->tesla, NV50TCL_REG_MODE, 1);
 401         OUT_RING  (chan, NV50TCL_REG_MODE_STRIPED);
 402         BEGIN_RING(chan, screen->tesla, 0x1400, 1);
 403         OUT_RING  (chan, 0xf);
 404
 405         /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
 406         for (i = 0; i < 3; ++i) {
 407                 BEGIN_RING(chan, screen->tesla, NV50TCL_TEX_LIMITS(i), 1);
 408                 OUT_RING  (chan, 0x54);
 409         }
 410
 411         /* origin is top left (set to 1 for bottom left) */
 412         BEGIN_RING(chan, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1);
 413         OUT_RING  (chan, 0);
 414         BEGIN_RING(chan, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
 415         OUT_RING  (chan, 8);
 416
 417         /* constant buffers for immediates and VP/FP parameters */
 418         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (32 * 4) * 4,
 419                              &screen->constbuf_misc[0]);
 420         if (ret) {
 421                 nv50_screen_destroy(pscreen);
 422                 return NULL;
 423         }
 424         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 425         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 426         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 427         OUT_RING  (chan, (NV50_CB_PMISC << 16) | 0x0200);
 428         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 429         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 430         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 431         OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 432
 433         for (i = 0; i < 3; i++) {
 434                 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (4096 * 4) * 4,
 435                                      &screen->constbuf_parm[i]);
 436                 if (ret) {
 437                         nv50_screen_destroy(pscreen);
 438                         return NULL;
 439                 }
 440                 BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 441                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 442                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 443                 /* CB_DEF_SET_SIZE value of 0x0000 means 65536 */
 444                 OUT_RING  (chan, ((NV50_CB_PVP + i) << 16) | 0x0000);
 445         }
 446
 447         if (nouveau_resource_init(&screen->immd_heap, 0, 128)) {
 448                 NOUVEAU_ERR("Error initialising shader immediates heap.\n");
 449                 nv50_screen_destroy(pscreen);
 450                 return NULL;
 451         }
 452
 453         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 454                              &screen->tic);
 455         if (ret) {
 456                 nv50_screen_destroy(pscreen);
 457                 return NULL;
 458         }
 459         BEGIN_RING(chan, screen->tesla, NV50TCL_TIC_ADDRESS_HIGH, 3);
 460         OUT_RELOCh(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 461         OUT_RELOCl(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 462         OUT_RING  (chan, 3 * 32 - 1);
 463
 464         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 465                              &screen->tsc);
 466         if (ret) {
 467                 nv50_screen_destroy(pscreen);
 468                 return NULL;
 469         }
 470         BEGIN_RING(chan, screen->tesla, NV50TCL_TSC_ADDRESS_HIGH, 3);
 471         OUT_RELOCh(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 472         OUT_RELOCl(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 473         OUT_RING  (chan, 0); /* ignored if TSC_LINKED (0x1234) == 1 */
 474
 475         /* map constant buffers:
 476          *  B = buffer ID (maybe more than 1 byte)
 477          *  N = CB index used in shader instruction
 478          *  P = program type (0 = VP, 2 = GP, 3 = FP)
 479          * SET_PROGRAM_CB = 0x000BBNP1
 480          */
 481         BEGIN_RING_NI(chan, screen->tesla, NV50TCL_SET_PROGRAM_CB, 8);
 482         /* bind immediate buffer */
 483         OUT_RING  (chan, 0x001 | (NV50_CB_PMISC << 12));
 484         OUT_RING  (chan, 0x021 | (NV50_CB_PMISC << 12));
 485         OUT_RING  (chan, 0x031 | (NV50_CB_PMISC << 12));
 486         /* bind auxiliary constbuf to immediate data bo */
 487         OUT_RING  (chan, 0x201 | (NV50_CB_AUX << 12));
 488         OUT_RING  (chan, 0x221 | (NV50_CB_AUX << 12));
 489         /* bind parameter buffers */
 490         OUT_RING  (chan, 0x101 | (NV50_CB_PVP << 12));
 491         OUT_RING  (chan, 0x121 | (NV50_CB_PGP << 12));
 492         OUT_RING  (chan, 0x131 | (NV50_CB_PFP << 12));
 493
 494         /* shader stack */
 495         nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 496
 497         stack_size  = util_bitcount(value & 0xffff);
 498         stack_size *= util_bitcount((value >> 24) & 0xf);
 499         stack_size *= 32 * 64 * 8;
 500
 501         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 502                              stack_size, &screen->stack_bo);
 503         if (ret) {
 504                 nv50_screen_destroy(pscreen);
 505                 return NULL;
 506         }
 507         BEGIN_RING(chan, screen->tesla, NV50TCL_STACK_ADDRESS_HIGH, 3);
 508         OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 509         OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 510         OUT_RING  (chan, 4);
 511
 512         /* Vertex array limits - max them out */
 513         for (i = 0; i < 16; i++) {
 514                 BEGIN_RING(chan, screen->tesla,
 515                            NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
 516                 OUT_RING  (chan, 0x000000ff);
 517                 OUT_RING  (chan, 0xffffffff);
 518         }
 519
 520         BEGIN_RING(chan, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
 521         OUT_RINGf (chan, 0.0f);
 522         OUT_RINGf (chan, 1.0f);
 523
 524         BEGIN_RING(chan, screen->tesla, NV50TCL_VIEWPORT_TRANSFORM_EN, 1);
 525         OUT_RING  (chan, 1);
 526
 527         /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
 528         BEGIN_RING(chan, screen->tesla, NV50TCL_LINKED_TSC, 1);
 529         OUT_RING  (chan, 1);
 530
 531         BEGIN_RING(chan, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
 532         OUT_RING  (chan, 1); /* default edgeflag to TRUE */
 533
 534         FIRE_RING (chan);
 535
 536         screen->force_push = debug_get_bool_option("NV50_ALWAYS_PUSH", FALSE);
 537         if(!screen->force_push)
 538                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = NOUVEAU_BO_GART;
 539         return pscreen;
 540 }
 541