55358183703583c33da22c4f8ce157083e6d7cd6
[mesa.git] / src / gallium / drivers / nv50 / nv50_tex.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "nv50_context.h"
24 #include "nv50_texture.h"
25 #include "nv50_resource.h"
26
27 #include "nouveau/nouveau_stateobj.h"
28 #include "nouveau/nouveau_reloc.h"
29
30 #include "util/u_format.h"
31
32 static INLINE uint32_t
33 nv50_tic_swizzle(uint32_t tc, unsigned swz)
34 {
35 switch (swz) {
36 case PIPE_SWIZZLE_RED:
37 return (tc & NV50TIC_0_0_MAPR_MASK) >> NV50TIC_0_0_MAPR_SHIFT;
38 case PIPE_SWIZZLE_GREEN:
39 return (tc & NV50TIC_0_0_MAPG_MASK) >> NV50TIC_0_0_MAPG_SHIFT;
40 case PIPE_SWIZZLE_BLUE:
41 return (tc & NV50TIC_0_0_MAPB_MASK) >> NV50TIC_0_0_MAPB_SHIFT;
42 case PIPE_SWIZZLE_ALPHA:
43 return (tc & NV50TIC_0_0_MAPA_MASK) >> NV50TIC_0_0_MAPA_SHIFT;
44 case PIPE_SWIZZLE_ONE:
45 return 7;
46 case PIPE_SWIZZLE_ZERO:
47 default:
48 return 0;
49 }
50 }
51
52 boolean
53 nv50_tex_construct(struct nv50_sampler_view *view)
54 {
55 const struct util_format_description *desc;
56 struct nv50_miptree *mt = nv50_miptree(view->pipe.texture);
57 uint32_t swz[4], *tic = view->tic;
58
59 tic[0] = nv50_format_table[view->pipe.format].tic;
60
61 swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r);
62 swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g);
63 swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b);
64 swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a);
65 view->tic[0] = (tic[0] & ~NV50TIC_0_0_SWIZZLE_MASK) |
66 (swz[0] << NV50TIC_0_0_MAPR_SHIFT) |
67 (swz[1] << NV50TIC_0_0_MAPG_SHIFT) |
68 (swz[2] << NV50TIC_0_0_MAPB_SHIFT) |
69 (swz[3] << NV50TIC_0_0_MAPA_SHIFT);
70
71 tic[2] = 0x50001000;
72 tic[2] |= ((mt->base.bo->tile_mode & 0x0f) << 22) |
73 ((mt->base.bo->tile_mode & 0xf0) << 21);
74
75 desc = util_format_description(mt->base.base.format);
76 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
77 tic[2] |= NV50TIC_0_2_COLORSPACE_SRGB;
78
79 switch (mt->base.base.target) {
80 case PIPE_TEXTURE_1D:
81 tic[2] |= NV50TIC_0_2_TARGET_1D;
82 break;
83 case PIPE_TEXTURE_2D:
84 tic[2] |= NV50TIC_0_2_TARGET_2D;
85 break;
86 case PIPE_TEXTURE_3D:
87 tic[2] |= NV50TIC_0_2_TARGET_3D;
88 break;
89 case PIPE_TEXTURE_CUBE:
90 tic[2] |= NV50TIC_0_2_TARGET_CUBE;
91 break;
92 default:
93 NOUVEAU_ERR("invalid texture target: %d\n",
94 mt->base.base.target);
95 return FALSE;
96 }
97
98 tic[3] = 0x00300000;
99
100 tic[4] = (1 << 31) | mt->base.base.width0;
101 tic[5] = (mt->base.base.last_level << 28) |
102 (mt->base.base.depth0 << 16) | mt->base.base.height0;
103
104 tic[6] = 0x03000000;
105
106 tic[7] = (view->pipe.last_level << 4) | view->pipe.first_level;
107
108 return TRUE;
109 }
110
111 static int
112 nv50_validate_textures(struct nv50_context *nv50, struct nouveau_stateobj *so,
113 unsigned p)
114 {
115 struct nouveau_grobj *eng2d = nv50->screen->eng2d;
116 struct nouveau_grobj *tesla = nv50->screen->tesla;
117 unsigned unit, j;
118
119 const unsigned rll = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_LOW;
120 const unsigned rlh = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH
121 | NOUVEAU_BO_OR;
122
123 nv50_so_init_sifc(nv50, so, nv50->screen->tic, NOUVEAU_BO_VRAM,
124 p * (32 * 8 * 4), nv50->sampler_view_nr[p] * 8 * 4);
125
126 for (unit = 0; unit < nv50->sampler_view_nr[p]; ++unit) {
127 struct nv50_sampler_view *view =
128 nv50_sampler_view(nv50->sampler_views[p][unit]);
129
130 so_method(so, eng2d, NV50_2D_SIFC_DATA | (2 << 29), 8);
131 if (view) {
132 uint32_t tic2 = view->tic[2];
133 struct nv50_miptree *mt =
134 nv50_miptree(view->pipe.texture);
135
136 tic2 &= ~NV50TIC_0_2_NORMALIZED_COORDS;
137 if (nv50->sampler[p][unit]->normalized)
138 tic2 |= NV50TIC_0_2_NORMALIZED_COORDS;
139 view->tic[2] = tic2;
140
141 so_data (so, view->tic[0]);
142 so_reloc (so, mt->base.bo, 0, rll, 0, 0);
143 so_reloc (so, mt->base.bo, 0, rlh, tic2, tic2);
144 so_datap (so, &view->tic[3], 5);
145
146 /* Set TEX insn $t src binding $unit in program type p
147 * to TIC, TSC entry (32 * p + unit), mark valid (1).
148 */
149 so_method(so, tesla, NV50TCL_BIND_TIC(p), 1);
150 so_data (so, ((32 * p + unit) << 9) | (unit << 1) | 1);
151 } else {
152 for (j = 0; j < 8; ++j)
153 so_data(so, 0);
154 so_method(so, tesla, NV50TCL_BIND_TIC(p), 1);
155 so_data (so, (unit << 1) | 0);
156 }
157 }
158
159 for (; unit < nv50->state.sampler_view_nr[p]; unit++) {
160 /* Make other bindings invalid. */
161 so_method(so, tesla, NV50TCL_BIND_TIC(p), 1);
162 so_data (so, (unit << 1) | 0);
163 }
164
165 nv50->state.sampler_view_nr[p] = nv50->sampler_view_nr[p];
166 return TRUE;
167 }
168
169 static void
170 nv50_emit_texture_relocs(struct nv50_context *nv50, int prog)
171 {
172 struct nouveau_channel *chan = nv50->screen->base.channel;
173 struct nouveau_bo *tic = nv50->screen->tic;
174 int unit;
175
176 for (unit = 0; unit < nv50->sampler_view_nr[prog]; unit++) {
177 struct nv50_sampler_view *view;
178 struct nv50_miptree *mt;
179 const unsigned base = ((prog * 32) + unit) * 32;
180
181 view = nv50_sampler_view(nv50->sampler_views[prog][unit]);
182 if (!view)
183 continue;
184 mt = nv50_miptree(view->pipe.texture);
185
186 nouveau_reloc_emit(chan, tic, base + 4, NULL, mt->base.bo, 0, 0,
187 NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
188 NOUVEAU_BO_LOW, 0, 0);
189 nouveau_reloc_emit(chan, tic, base + 8, NULL, mt->base.bo, 0, 0,
190 NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
191 NOUVEAU_BO_HIGH, view->tic[2], view->tic[2]);
192 }
193 }
194
195 void
196 nv50_tex_relocs(struct nv50_context *nv50)
197 {
198 nv50_emit_texture_relocs(nv50, 2); /* FP */
199 nv50_emit_texture_relocs(nv50, 0); /* VP */
200 }
201
202 struct nouveau_stateobj *
203 nv50_tex_validate(struct nv50_context *nv50)
204 {
205 struct nouveau_stateobj *so;
206 struct nouveau_grobj *tesla = nv50->screen->tesla;
207 unsigned p, m = 0, d = 0, r = 0;
208
209 for (p = 0; p < 3; ++p) {
210 unsigned nr = MAX2(nv50->sampler_view_nr[p],
211 nv50->state.sampler_view_nr[p]);
212 m += nr;
213 d += nr;
214 r += nv50->sampler_view_nr[p];
215 }
216 m = m * 2 + 3 * 4 + 1;
217 d = d * 9 + 3 * 19 + 1;
218 r = r * 2 + 3 * 2;
219
220 so = so_new(m, d, r);
221
222 if (nv50_validate_textures(nv50, so, 0) == FALSE ||
223 nv50_validate_textures(nv50, so, 2) == FALSE) {
224 so_ref(NULL, &so);
225
226 NOUVEAU_ERR("failed tex validate\n");
227 return NULL;
228 }
229
230 so_method(so, tesla, 0x1330, 1); /* flush TIC */
231 so_data (so, 0);
232
233 return so;
234 }